130 lines
4.5 KiB
VHDL
130 lines
4.5 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.dvi_package.all;
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library UNISIM;
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use UNISIM.Vcomponents.all;
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entity serdes_n_to_1 is
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generic ( SF : integer := 0 );
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port (
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ioclk : in std_logic;
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gclk : in std_logic;
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rst : in std_logic;
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serdesstrobe_i : in std_logic;
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data_i : in std_logic_vector(SF-1 downto 0);
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data_o : out std_logic
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);
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end serdes_n_to_1;
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architecture serdes_n_to_1 of serdes_n_to_1 is
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signal cascade_di : std_logic;
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signal cascade_do : std_logic;
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signal cascade_ti : std_logic;
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signal cascade_to : std_logic;
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signal mdatain : std_logic_vector(8 downto 0);
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begin
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datir: for I in 0 to SF-1 generate
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mdatain(I) <= data_i(I);
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end generate;
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dati0: for I in SF to 8 generate
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mdatain(I) <= '0';
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end generate;
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oserdes_m: OSERDES2
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generic map (
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DATA_WIDTH => SF, -- SERDES word width. This should match the setting is BUFPLL
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DATA_RATE_OQ => "SDR", -- <SDR>, DDR
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DATA_RATE_OT => "SDR", -- <SDR>, DDR
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SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
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OUTPUT_MODE => "DIFFERENTIAL"
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)
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port map (
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OQ => data_o,
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OCE => '1',
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CLK0 => ioclk,
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CLK1 => '0',
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IOCE => serdesstrobe_i,
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RST => rst,
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CLKDIV => gclk,
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D4 => mdatain(7),
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D3 => mdatain(6),
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D2 => mdatain(5),
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D1 => mdatain(4),
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TQ => open,
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T1 => '0',
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T2 => '0',
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T3 => '0',
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T4 => '0',
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TRAIN => '0',
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TCE => '1',
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SHIFTIN1 => '1', -- Dummy input in Master
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SHIFTIN2 => '1', -- Dummy input in Master
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SHIFTIN3 => cascade_do, -- Cascade output D data from slave
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SHIFTIN4 => cascade_to, -- Cascade output T data from slave
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SHIFTOUT1 => cascade_di, -- Cascade input D data to slave
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SHIFTOUT2 => cascade_ti, -- Cascade input T data to slave
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SHIFTOUT3 => open, -- Dummy output in Master
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SHIFTOUT4 => open -- Dummy output in Master
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);
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oserdes_s: OSERDES2
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generic map (
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DATA_WIDTH => SF, -- SERDES word width. This should match the setting is BUFPLL
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DATA_RATE_OQ => "SDR", -- <SDR>, DDR
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DATA_RATE_OT => "SDR", -- <SDR>, DDR
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SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
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OUTPUT_MODE => "DIFFERENTIAL"
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)
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port map (
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OQ => open,
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OCE => '1',
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CLK0 => ioclk,
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CLK1 => '0',
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IOCE => serdesstrobe_i,
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RST => rst,
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CLKDIV => gclk,
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D4 => mdatain(3),
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D3 => mdatain(2),
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D2 => mdatain(1),
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D1 => mdatain(0),
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TQ => open,
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T1 => '0',
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T2 => '0',
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T3 => '0',
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T4 => '0',
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TRAIN => '0',
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TCE => '1',
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SHIFTIN1 => cascade_di, -- Cascade input D from Master
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SHIFTIN2 => cascade_ti, -- Cascade input T from Master
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SHIFTIN3 => '1', -- Dummy input in Slave
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SHIFTIN4 => '1', -- Dummy input in Slave
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SHIFTOUT1 => open, -- Dummy output in Slave
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SHIFTOUT2 => open, -- Dummy output in Slave
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SHIFTOUT3 => cascade_do, -- Cascade output D data to Master
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SHIFTOUT4 => cascade_to -- Cascade output T data to Master
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);
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end serdes_n_to_1;
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