2013-10-02 10:43:54 +02:00
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##############################################################
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#
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2013-12-04 15:43:22 +01:00
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# PlanAhead 14.6
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# Date: Thu Nov 28 22:34:38 2013
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2013-10-02 10:43:54 +02:00
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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2013-12-04 15:43:22 +01:00
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# Xilinx IP GUI. It is strongly recommended
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2013-10-02 10:43:54 +02:00
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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# BEGIN Project Options
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2013-12-04 15:43:22 +01:00
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SET devicefamily=spartan6
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SET device=xc6slx45
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SET package=csg324
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SET speedgrade=-3
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SET verilogsim=false
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SET vhdlsim=true
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2013-10-02 10:43:54 +02:00
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# END Project Options
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# BEGIN Select
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SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
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# END Select
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# BEGIN Parameters
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CSET component_name=usb_fifo_tx_fin
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2013-12-04 15:43:22 +01:00
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CSET fifo_implementation=Independent_Clocks_Block_RAM
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CSET synchronization_stages=2
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CSET synchronization_stages_axi=2
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CSET interface_type=Native
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CSET performance_options=First_Word_Fall_Through
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CSET input_data_width=24
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CSET input_depth=1024
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CSET output_data_width=24
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CSET output_depth=1024
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CSET enable_ecc=false
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CSET use_embedded_registers=false
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CSET reset_pin=true
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CSET enable_reset_synchronization=true
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CSET reset_type=Asynchronous_Reset
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CSET full_flags_reset_value=1
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CSET use_dout_reset=true
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CSET dout_reset_value=0
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CSET almost_full_flag=false
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CSET almost_empty_flag=false
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CSET valid_flag=false
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CSET valid_sense=Active_High
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CSET underflow_flag=false
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CSET underflow_sense=Active_High
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CSET write_acknowledge_flag=false
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CSET write_acknowledge_sense=Active_High
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CSET overflow_flag=false
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CSET overflow_sense=Active_High
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CSET inject_sbit_error=false
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CSET inject_dbit_error=false
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CSET use_extra_logic=false
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2013-10-02 10:43:54 +02:00
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CSET data_count=false
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CSET data_count_width=10
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2013-12-04 15:43:22 +01:00
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CSET write_data_count=false
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CSET write_data_count_width=10
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CSET read_data_count=false
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CSET read_data_count_width=10
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2013-10-02 10:43:54 +02:00
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CSET disable_timing_violations=false
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2013-12-04 15:43:22 +01:00
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CSET read_clock_frequency=1
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CSET write_clock_frequency=1
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CSET programmable_full_type=No_Programmable_Full_Threshold
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CSET full_threshold_assert_value=1023
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CSET full_threshold_negate_value=1022
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CSET programmable_empty_type=No_Programmable_Empty_Threshold
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2013-10-02 10:43:54 +02:00
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CSET empty_threshold_assert_value=4
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CSET empty_threshold_negate_value=5
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2013-12-04 15:43:22 +01:00
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CSET axi_type=AXI4_Stream
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CSET clock_type_axi=Common_Clock
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CSET use_clock_enable=false
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CSET clock_enable_type=Slave_Interface_Clock_Enable
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CSET enable_write_channel=false
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CSET enable_read_channel=false
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CSET id_width=4
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CSET axi_address_width=32
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CSET axi_data_width=64
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2013-10-02 10:43:54 +02:00
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CSET enable_awuser=false
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2013-12-04 15:43:22 +01:00
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CSET awuser_width=1
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CSET enable_wuser=false
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CSET wuser_width=1
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2013-10-02 10:43:54 +02:00
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CSET enable_buser=false
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2013-12-04 15:43:22 +01:00
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CSET buser_width=1
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CSET enable_aruser=false
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CSET aruser_width=1
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2013-10-02 10:43:54 +02:00
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CSET enable_ruser=false
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2013-12-04 15:43:22 +01:00
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CSET ruser_width=1
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2013-10-02 10:43:54 +02:00
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CSET enable_tdata=false
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2013-12-04 15:43:22 +01:00
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CSET tdata_width=64
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2013-10-02 10:43:54 +02:00
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CSET enable_tid=false
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2013-12-04 15:43:22 +01:00
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CSET tid_width=8
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CSET enable_tdest=false
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CSET tdest_width=4
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CSET enable_tuser=false
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CSET tuser_width=4
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2013-10-02 10:43:54 +02:00
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CSET enable_tready=true
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2013-12-04 15:43:22 +01:00
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CSET enable_tlast=false
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2013-10-02 10:43:54 +02:00
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CSET enable_tstrobe=false
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2013-12-04 15:43:22 +01:00
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CSET tstrb_width=4
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CSET enable_tkeep=false
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CSET tkeep_width=4
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CSET wach_type=FIFO
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2013-10-02 10:43:54 +02:00
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CSET fifo_implementation_wach=Common_Clock_Block_RAM
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2013-12-04 15:43:22 +01:00
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CSET fifo_application_type_wach=Data_FIFO
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CSET enable_ecc_wach=false
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CSET inject_sbit_error_wach=false
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2013-10-02 10:43:54 +02:00
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CSET inject_dbit_error_wach=false
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2013-12-04 15:43:22 +01:00
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CSET input_depth_wach=16
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CSET enable_data_counts_wach=false
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CSET programmable_full_type_wach=No_Programmable_Full_Threshold
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CSET full_threshold_assert_value_wach=1023
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CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
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CSET empty_threshold_assert_value_wach=1022
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CSET wdch_type=FIFO
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CSET fifo_implementation_wdch=Common_Clock_Block_RAM
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CSET fifo_application_type_wdch=Data_FIFO
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CSET enable_ecc_wdch=false
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CSET inject_sbit_error_wdch=false
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2013-10-02 10:43:54 +02:00
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CSET inject_dbit_error_wdch=false
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2013-12-04 15:43:22 +01:00
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CSET input_depth_wdch=1024
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CSET enable_data_counts_wdch=false
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CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
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CSET full_threshold_assert_value_wdch=1023
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CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
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CSET empty_threshold_assert_value_wdch=1022
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CSET wrch_type=FIFO
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CSET fifo_implementation_wrch=Common_Clock_Block_RAM
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CSET fifo_application_type_wrch=Data_FIFO
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CSET enable_ecc_wrch=false
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CSET inject_sbit_error_wrch=false
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2013-10-02 10:43:54 +02:00
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CSET inject_dbit_error_wrch=false
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2013-12-04 15:43:22 +01:00
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CSET input_depth_wrch=16
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CSET enable_data_counts_wrch=false
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CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
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CSET full_threshold_assert_value_wrch=1023
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CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
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CSET empty_threshold_assert_value_wrch=1022
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CSET rach_type=FIFO
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CSET fifo_implementation_rach=Common_Clock_Block_RAM
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CSET fifo_application_type_rach=Data_FIFO
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CSET enable_ecc_rach=false
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2013-10-02 10:43:54 +02:00
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CSET inject_sbit_error_rach=false
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2013-12-04 15:43:22 +01:00
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CSET inject_dbit_error_rach=false
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2013-10-02 10:43:54 +02:00
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CSET input_depth_rach=16
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2013-12-04 15:43:22 +01:00
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CSET enable_data_counts_rach=false
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CSET programmable_full_type_rach=No_Programmable_Full_Threshold
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CSET full_threshold_assert_value_rach=1023
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2013-10-02 10:43:54 +02:00
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CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
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2013-12-04 15:43:22 +01:00
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CSET empty_threshold_assert_value_rach=1022
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CSET rdch_type=FIFO
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CSET fifo_implementation_rdch=Common_Clock_Block_RAM
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CSET fifo_application_type_rdch=Data_FIFO
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CSET enable_ecc_rdch=false
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CSET inject_sbit_error_rdch=false
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CSET inject_dbit_error_rdch=false
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CSET input_depth_rdch=1024
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CSET enable_data_counts_rdch=false
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CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
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CSET full_threshold_assert_value_rdch=1023
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2013-10-02 10:43:54 +02:00
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CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
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2013-12-04 15:43:22 +01:00
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CSET empty_threshold_assert_value_rdch=1022
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CSET axis_type=FIFO
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CSET fifo_implementation_axis=Common_Clock_Block_RAM
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CSET fifo_application_type_axis=Data_FIFO
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CSET enable_ecc_axis=false
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CSET inject_sbit_error_axis=false
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CSET inject_dbit_error_axis=false
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CSET input_depth_axis=1024
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CSET enable_data_counts_axis=false
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2013-10-02 10:43:54 +02:00
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CSET programmable_full_type_axis=No_Programmable_Full_Threshold
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2013-12-04 15:43:22 +01:00
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CSET full_threshold_assert_value_axis=1023
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CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
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CSET empty_threshold_assert_value_axis=1022
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2013-10-02 10:43:54 +02:00
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CSET register_slice_mode_wach=Fully_Registered
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CSET register_slice_mode_wdch=Fully_Registered
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CSET register_slice_mode_wrch=Fully_Registered
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2013-12-04 15:43:22 +01:00
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CSET register_slice_mode_rach=Fully_Registered
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CSET register_slice_mode_rdch=Fully_Registered
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CSET register_slice_mode_axis=Fully_Registered
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2013-10-02 10:43:54 +02:00
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CSET underflow_flag_axi=false
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CSET underflow_sense_axi=Active_High
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2013-12-04 15:43:22 +01:00
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CSET overflow_flag_axi=false
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CSET overflow_sense_axi=Active_High
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CSET disable_timing_violations_axi=false
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CSET add_ngc_constraint_axi=false
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CSET enable_common_underflow=false
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CSET enable_common_overflow=false
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CSET enable_read_pointer_increment_by2=false
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2013-10-02 10:43:54 +02:00
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# END Parameters
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GENERATE
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