48 lines
1.8 KiB
VHDL
48 lines
1.8 KiB
VHDL
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-- ---------------------------------------------------------------
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-- (2013) Benjamin Krill <benjamin@krll.de>
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-- ---------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- GENERAL PKT FORMAT
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-- --------------------------------------------------------
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-- Type (4bit)
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-- Plength (7bit) data length (0 = 0byte, 0x7f = 127 * 4byte)
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-- 31 16|15 0
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-- header |Type ________|___PLenght______|
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-- data |... type defined data/fields ... |
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--
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-- DDR2 WRITE TYPE FORMAT
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-- --------------------------------------------------------
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-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
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-- data | .... data .... |
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--
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-- DDR2 READ TYPE FORMAT
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-- --------------------------------------------------------
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-- header0 |0 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
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-- header1 | |_______SIZE_____| -- SIZE in 4byte to read
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package strm_package is
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constant STRM_TYPE_HIGH : integer := 31;
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constant STRM_TYPE_LOW : integer := 28;
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constant STRM_LENGTH_HIGH : integer := 23;
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constant STRM_LENGTH_LOW : integer := 0;
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-- SLAVE TYPE IDs
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constant STRM_TYPE_DDR2 : std_logic_vector(3 downto 0) := "0001";
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-- DDR2
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constant STRM_DDR2_BUS : integer := 0;
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constant STRM_DDR2_ADR_HIGH : integer := 27;
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constant STRM_DDR2_ADR_LOW : integer := 0;
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constant STRM_DDR2_ACCESS : integer := 31;
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constant STRM_DDR2_ACC_WRITE : std_logic := '1';
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constant STRM_DDR2_ACC_READ : std_logic := '0';
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constant STRM_DDR2_SIZE_HIGH : integer := 23;
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constant STRM_DDR2_SIZE_LOW : integer := 0;
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-- bus types
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type strm_dat_bus_t is array(natural range <>) of std_logic_vector(31 downto 0);
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end package;
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