fx2/fpga/f2p/strm_package.vhd

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2013-10-02 10:43:54 +02:00
-- ---------------------------------------------------------------
-- (2013) Benjamin Krill <benjamin@krll.de>
-- ---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- GENERAL PKT FORMAT
-- --------------------------------------------------------
-- Type (4bit)
-- Plength (7bit) data length (0 = 0byte, 0x7f = 127 * 4byte)
-- 31 16|15 0
-- header |Type ________|___PLenght______|
-- data |... type defined data/fields ... |
--
-- DDR2 WRITE TYPE FORMAT
-- --------------------------------------------------------
-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- data | .... data .... |
--
-- DDR2 READ TYPE FORMAT
-- --------------------------------------------------------
-- header0 |0 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- header1 | |_______SIZE_____| -- SIZE in 4byte to read
package strm_package is
constant STRM_TYPE_HIGH : integer := 31;
constant STRM_TYPE_LOW : integer := 28;
constant STRM_LENGTH_HIGH : integer := 23;
constant STRM_LENGTH_LOW : integer := 0;
-- SLAVE TYPE IDs
constant STRM_TYPE_DDR2 : std_logic_vector(3 downto 0) := "0001";
-- DDR2
constant STRM_DDR2_BUS : integer := 0;
constant STRM_DDR2_ADR_HIGH : integer := 27;
constant STRM_DDR2_ADR_LOW : integer := 0;
constant STRM_DDR2_ACCESS : integer := 31;
constant STRM_DDR2_ACC_WRITE : std_logic := '1';
constant STRM_DDR2_ACC_READ : std_logic := '0';
constant STRM_DDR2_SIZE_HIGH : integer := 23;
constant STRM_DDR2_SIZE_LOW : integer := 0;
-- bus types
type strm_dat_bus_t is array(natural range <>) of std_logic_vector(31 downto 0);
end package;