56 lines
2.0 KiB
VHDL
56 lines
2.0 KiB
VHDL
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-- ---------------------------------------------------------------------------
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-- (2009) Benjamin Krill <ben@codiert.org>
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--
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-- "THE BEER-WARE LICENSE" (Revision 42):
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-- ben@codiert.org wrote this file. As long as you retain this notice you can
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-- do whatever you want with this stuff. If we meet some day, and you think
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-- this stuff is worth it, you can buy me a beer in return Benjamin Krill
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-- ---------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity rrarbiter is
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generic ( CNT : integer := 7 );
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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req : in std_logic_vector(CNT-1 downto 0);
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ack : in std_logic;
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grant : out std_logic_vector(CNT-1 downto 0)
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);
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end;
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architecture rrarbiter of rrarbiter is
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signal grant_q : std_logic_vector(CNT-1 downto 0);
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signal pre_req : std_logic_vector(CNT-1 downto 0);
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signal sel_gnt : std_logic_vector(CNT-1 downto 0);
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signal isol_lsb : std_logic_vector(CNT-1 downto 0);
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signal mask_pre : std_logic_vector(CNT-1 downto 0);
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signal win : std_logic_vector(CNT-1 downto 0);
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begin
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grant <= grant_q;
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mask_pre <= req and not (std_logic_vector(unsigned(pre_req) - 1) or pre_req); -- Mask off previous winners
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sel_gnt <= mask_pre and std_logic_vector(unsigned(not(mask_pre)) + 1); -- Select new winner
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isol_lsb <= req and std_logic_vector(unsigned(not(req)) + 1); -- Isolate least significant set bit.
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win <= sel_gnt when mask_pre /= (CNT-1 downto 0 => '0') else isol_lsb;
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process (clk,rst_n)
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begin
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if rst_n = '0' then
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pre_req <= (others => '0');
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grant_q <= (others => '0');
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elsif rising_edge(clk) then
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grant_q <= grant_q;
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pre_req <= pre_req;
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if grant_q = (CNT-1 downto 0 => '0') or ack = '1' then
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if win /= (CNT-1 downto 0 => '0') then
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pre_req <= win;
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end if;
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grant_q <= win;
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end if;
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end if;
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end process;
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end rrarbiter;
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