diff --git a/fpga/f2p/f2p_strm_top.vhd b/fpga/f2p/f2p_strm_top.vhd index 9019542..44eb487 100644 --- a/fpga/f2p/f2p_strm_top.vhd +++ b/fpga/f2p/f2p_strm_top.vhd @@ -47,6 +47,7 @@ entity f2p_strm_top is -- streaming bus strm_in_data_o : out std_logic_vector(31 downto 0); strm_in_eop_o : out std_logic; + strm_in_sop_o : out std_logic; strm_in_en_o : out std_logic; strm_in_busy_i : in std_logic; strm_out_slv_reqs_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); @@ -61,6 +62,7 @@ architecture f2p_strm_top of f2p_strm_top is signal rp_read_cnt : unsigned(23 downto 0); signal strm_data : std_logic_vector(31 downto 0); signal strm_eop : std_logic; + signal strm_sop : std_logic; signal strm_en : std_logic; signal wp_wr : std_logic; @@ -78,6 +80,7 @@ architecture f2p_strm_top of f2p_strm_top is begin strm_in_data_o <= strm_data; strm_in_eop_o <= strm_eop; + strm_in_sop_o <= strm_sop; strm_in_en_o <= strm_en; f2p_master_0: entity work.f2p_master @@ -121,6 +124,7 @@ begin strm_data <= (others => '0'); strm_en <= '0'; strm_eop <= '0'; + strm_sop <= '0'; elsif rising_edge(clk) then -- get next packet and stream to slaves if rp_rd = '1' then @@ -134,9 +138,13 @@ begin -- stream data strm_en <= '0'; strm_eop <= '0'; + strm_sop <= '0'; if rp_rd = '1' then strm_en <= '1'; strm_data <= rp_dat; + if rp_read_cnt = x"000000" then + strm_sop <= '1'; + end if; if rp_read_cnt = x"000001" then strm_eop <= '1'; end if; diff --git a/fpga/f2p/f2p_strm_top_tb.vhd b/fpga/f2p/f2p_strm_top_tb.vhd index f20f46b..ef31074 100644 --- a/fpga/f2p/f2p_strm_top_tb.vhd +++ b/fpga/f2p/f2p_strm_top_tb.vhd @@ -34,6 +34,7 @@ ARCHITECTURE rtl OF f2p_strm_top_tb IS signal strm_in_type : std_logic_vector( 3 downto 0); signal strm_in_data : std_logic_vector(31 downto 0); signal strm_in_eop : std_logic; + signal strm_in_sop : std_logic; signal strm_in_en : std_logic; signal strm_in_busy : std_logic; constant STRM_OUT_SLV_CNT : integer := 1; @@ -116,6 +117,7 @@ BEGIN -- streaming bus strm_in_data_o => strm_in_data, strm_in_eop_o => strm_in_eop, + strm_in_sop_o => strm_in_sop, strm_in_en_o => strm_in_en, strm_in_busy_i => strm_in_busy, strm_out_slv_reqs_i => strm_out_slv_reqs, @@ -138,6 +140,7 @@ BEGIN -- streaming bus strm_in_data_i => strm_in_data, strm_in_eop_i => strm_in_eop, + strm_in_sop_i => strm_in_sop, strm_in_en_i => strm_in_en, strm_in_busy_o => strm_in_busy, strm_out_req_o => ddr2_strm_out_req, diff --git a/fpga/f2p/strm_package.vhd b/fpga/f2p/strm_package.vhd index ad3b6cb..f439642 100644 --- a/fpga/f2p/strm_package.vhd +++ b/fpga/f2p/strm_package.vhd @@ -26,11 +26,14 @@ use ieee.numeric_std.all; -- GENERAL PKT FORMAT -- -------------------------------------------------------- -- Type (4bit) +-- _Tag (4bit) -- Plength (7bit) data length (0 = 0byte, 0x7f = 127 * 4byte) -- 31 16|15 0 --- header |Type ________|___PLenght______| +-- header |Type_Tag________|___PLenght______| -- data |... type defined data/fields ... | -- +-- -------------------------------------------------------- +-- -------------------------------------------------------- -- DDR2 WRITE TYPE FORMAT -- -------------------------------------------------------- -- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned @@ -40,18 +43,34 @@ use ieee.numeric_std.all; -- -------------------------------------------------------- -- header0 |0 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned -- header1 | |_______SIZE_____| -- SIZE in 4byte to read +-- -------------------------------------------------------- +-- -------------------------------------------------------- +-- -------------------------------------------------------- +-- -------------------------------------------------------- +-- REGFILE WRITE TYPE FORMAT +-- -------------------------------------------------------- +-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned +-- data | 32 bit data | +-- +-- REGFILE READ TYPE FORMAT +-- -------------------------------------------------------- +-- header |0TAG________ADDR|ESS_____________| -- ADDRESS 4byte aligned +-- -------------------------------------------------------- +-- -------------------------------------------------------- package strm_package is constant STRM_TYPE_HIGH : integer := 31; constant STRM_TYPE_LOW : integer := 28; + constant STRM_TAG_HIGH : integer := 27; + constant STRM_TAG_LOW : integer := 24; constant STRM_LENGTH_HIGH : integer := 23; constant STRM_LENGTH_LOW : integer := 0; -- SLAVE TYPE IDs constant STRM_TYPE_DDR2 : std_logic_vector(3 downto 0) := "0001"; + constant STRM_TYPE_REGFILE : std_logic_vector(3 downto 0) := "0010"; -- DDR2 - constant STRM_DDR2_BUS : integer := 0; constant STRM_DDR2_ADR_HIGH : integer := 27; constant STRM_DDR2_ADR_LOW : integer := 0; constant STRM_DDR2_ACCESS : integer := 31; diff --git a/fpga/strm_ddr2/strm_ddr2.vhd b/fpga/strm_ddr2/strm_ddr2.vhd index d1d2ca6..5991b76 100644 --- a/fpga/strm_ddr2/strm_ddr2.vhd +++ b/fpga/strm_ddr2/strm_ddr2.vhd @@ -33,6 +33,7 @@ entity strm_ddr2 is -- streaming bus strm_in_data_i : in std_logic_vector(31 downto 0); strm_in_eop_i : in std_logic; + strm_in_sop_i : in std_logic; strm_in_en_i : in std_logic; strm_in_busy_o : out std_logic; strm_out_req_o : out std_logic; @@ -72,9 +73,11 @@ architecture strm_ddr2 of strm_ddr2 is signal rst : std_logic; signal strm_in_data : std_logic_vector(31 downto 0); signal strm_in_eop : std_logic; + signal strm_in_sop : std_logic; signal strm_in_en : std_logic; signal strm_in_busy : std_logic; signal strm_type_vld : std_logic; + signal strm_tag : std_logic_vector( 3 downto 0); signal strm_size : unsigned(23 downto 0); signal ddr2_wr_en : std_logic; signal ddr2_wr_mask : std_logic_vector( 3 downto 0); @@ -90,7 +93,7 @@ architecture strm_ddr2 of strm_ddr2 is signal strm_out_eop : std_logic; signal strm_out_hdr_en : std_logic; signal ddr2_rd_en : std_logic; - signal bla_cnt : unsigned(7 downto 0); + signal read_cnt : unsigned(7 downto 0); begin rst <= not rst_n; ddr2_rd_en_o <= ddr2_rd_en; @@ -101,15 +104,17 @@ begin ddr2_wr_data_o <= ddr2_wr_data; strm_in_data <= strm_in_data_i; strm_in_eop <= strm_in_eop_i; + strm_in_sop <= strm_in_sop_i; strm_in_en <= strm_in_en_i; strm_in_busy_o <= strm_in_busy; strm_in_busy <= ddr2_wr_full_i or ddr2_cmd_full_i; - strm_type_vld <= '1' when strm_in_data(STRM_TYPE_HIGH downto STRM_TYPE_LOW) = STRM_TYPE_DDR2 else '0'; + strm_type_vld <= strm_in_sop when strm_in_data(STRM_TYPE_HIGH downto STRM_TYPE_LOW) = STRM_TYPE_DDR2 else '0'; process (clk, rst_n) begin if rst_n = '0' then sm_strm <= IDLE; + strm_tag <= (others => '0'); strm_size <= (others => '0'); ddr2_cmd_instr <= (others => '0'); ddr2_wr_en <= '0'; @@ -120,11 +125,12 @@ begin ddr2_size <= (others => '0'); ddr2_read_size <= (others => '0'); strm_out_size <= (others => '0'); - bla_cnt <= (others => '0'); + read_cnt <= (others => '0'); strm_out_hdr_en <= '0'; elsif rising_edge(clk) then -- STRM SIZE if sm_strm = IDLE and strm_in_en = '1' then + strm_tag <= strm_in_data(STRM_TAG_HIGH downto STRM_TAG_LOW); strm_size <= unsigned(strm_in_data(STRM_LENGTH_HIGH downto STRM_LENGTH_LOW)); end if; @@ -226,7 +232,7 @@ begin sm_strm <= DDR2_READ; end if; when DDR2_READ => - if ddr2_rd_empty_i = '1' and ddr2_size /= x"000000" and bla_cnt = dw_cnt(6 downto 0) then + if ddr2_rd_empty_i = '1' and ddr2_size /= x"000000" and read_cnt = dw_cnt(6 downto 0) then sm_strm <= DDR2_RD_ADJ; elsif strm_out_eop = '1' then sm_strm <= IDLE; @@ -248,9 +254,9 @@ begin end if; if ddr2_cmd_en = '1' then - bla_cnt <= (others => '0'); + read_cnt <= (others => '0'); elsif ddr2_rd_en = '1' then - bla_cnt <= bla_cnt + "1"; + read_cnt <= read_cnt + "1"; end if; -- STRM OUT REGISTERS @@ -272,7 +278,7 @@ begin strm_out_en_o <= strm_out_hdr_en when sm_strm = DDR2_RD_WAIT and strm_out_busy_i = '0' else ddr2_rd_en; strm_out_eop <= ddr2_rd_en when ddr2_read_size >= strm_out_size and sm_strm = DDR2_READ else '0'; strm_out_eop_o <= strm_out_eop; - strm_out_data_o <= STRM_TYPE_DDR2 & (27 downto 24 => '0') & std_logic_vector(strm_out_size) + strm_out_data_o <= STRM_TYPE_DDR2 & strm_tag & std_logic_vector(strm_out_size) when strm_out_hdr_en = '1' else ddr2_rd_data_i; end strm_ddr2; diff --git a/fpga/vendor/xilinx/usb_fifo_tx.xco b/fpga/vendor/xilinx/usb_fifo_tx.xco index 02304a5..c813e57 100644 --- a/fpga/vendor/xilinx/usb_fifo_tx.xco +++ b/fpga/vendor/xilinx/usb_fifo_tx.xco @@ -1,213 +1,194 @@ ############################################################## # -# Xilinx Core Generator version 14.6 -# Date: Wed Sep 4 11:25:04 2013 +# PlanAhead 14.6 +# Date: Thu Nov 28 22:36:15 2013 + # ############################################################## # # This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended +# Xilinx IP GUI. It is strongly recommended # that you do not manually alter this file as it may cause # unexpected and unsupported behavior. # ############################################################## -# -# Generated from component: xilinx.com:ip:fifo_generator:9.3 -# -############################################################## -# # BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = false -SET vhdlsim = true +SET devicefamily=spartan6 +SET device=xc6slx45 +SET package=csg324 +SET speedgrade=-3 +SET verilogsim=false +SET vhdlsim=true # END Project Options # BEGIN Select SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 # END Select # BEGIN Parameters -CSET add_ngc_constraint_axi=false -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET aruser_width=1 -CSET awuser_width=1 -CSET axi_address_width=32 -CSET axi_data_width=64 -CSET axi_type=AXI4_Stream -CSET axis_type=FIFO -CSET buser_width=1 -CSET clock_enable_type=Slave_Interface_Clock_Enable -CSET clock_type_axi=Common_Clock CSET component_name=usb_fifo_tx -CSET data_count=false -CSET data_count_width=10 -CSET disable_timing_violations=false -CSET disable_timing_violations_axi=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_assert_value_axis=1022 -CSET empty_threshold_assert_value_rach=1022 -CSET empty_threshold_assert_value_rdch=1022 -CSET empty_threshold_assert_value_wach=1022 -CSET empty_threshold_assert_value_wdch=1022 -CSET empty_threshold_assert_value_wrch=1022 -CSET empty_threshold_negate_value=5 -CSET enable_aruser=false -CSET enable_awuser=false -CSET enable_buser=false -CSET enable_common_overflow=false -CSET enable_common_underflow=false -CSET enable_data_counts_axis=false -CSET enable_data_counts_rach=false -CSET enable_data_counts_rdch=false -CSET enable_data_counts_wach=false -CSET enable_data_counts_wdch=false -CSET enable_data_counts_wrch=false -CSET enable_ecc=false -CSET enable_ecc_axis=false -CSET enable_ecc_rach=false -CSET enable_ecc_rdch=false -CSET enable_ecc_wach=false -CSET enable_ecc_wdch=false -CSET enable_ecc_wrch=false -CSET enable_read_channel=false -CSET enable_read_pointer_increment_by2=false -CSET enable_reset_synchronization=true -CSET enable_ruser=false -CSET enable_tdata=false -CSET enable_tdest=false -CSET enable_tid=false -CSET enable_tkeep=false -CSET enable_tlast=false -CSET enable_tready=true -CSET enable_tstrobe=false -CSET enable_tuser=false -CSET enable_write_channel=false -CSET enable_wuser=false -CSET fifo_application_type_axis=Data_FIFO -CSET fifo_application_type_rach=Data_FIFO -CSET fifo_application_type_rdch=Data_FIFO -CSET fifo_application_type_wach=Data_FIFO -CSET fifo_application_type_wdch=Data_FIFO -CSET fifo_application_type_wrch=Data_FIFO CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET fifo_implementation_axis=Common_Clock_Block_RAM -CSET fifo_implementation_rach=Common_Clock_Block_RAM -CSET fifo_implementation_rdch=Common_Clock_Block_RAM -CSET fifo_implementation_wach=Common_Clock_Block_RAM -CSET fifo_implementation_wdch=Common_Clock_Block_RAM -CSET fifo_implementation_wrch=Common_Clock_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=1021 -CSET full_threshold_assert_value_axis=1023 -CSET full_threshold_assert_value_rach=1023 -CSET full_threshold_assert_value_rdch=1023 -CSET full_threshold_assert_value_wach=1023 -CSET full_threshold_assert_value_wdch=1023 -CSET full_threshold_assert_value_wrch=1023 -CSET full_threshold_negate_value=1020 -CSET id_width=4 -CSET inject_dbit_error=false -CSET inject_dbit_error_axis=false -CSET inject_dbit_error_rach=false -CSET inject_dbit_error_rdch=false -CSET inject_dbit_error_wach=false -CSET inject_dbit_error_wdch=false -CSET inject_dbit_error_wrch=false -CSET inject_sbit_error=false -CSET inject_sbit_error_axis=false -CSET inject_sbit_error_rach=false -CSET inject_sbit_error_rdch=false -CSET inject_sbit_error_wach=false -CSET inject_sbit_error_wdch=false -CSET inject_sbit_error_wrch=false +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET interface_type=Native +CSET performance_options=First_Word_Fall_Through CSET input_data_width=32 CSET input_depth=1024 -CSET input_depth_axis=1024 -CSET input_depth_rach=16 -CSET input_depth_rdch=1024 -CSET input_depth_wach=16 -CSET input_depth_wdch=1024 -CSET input_depth_wrch=16 -CSET interface_type=Native CSET output_data_width=8 CSET output_depth=4096 +CSET enable_ecc=false +CSET use_embedded_registers=false +CSET reset_pin=true +CSET enable_reset_synchronization=true +CSET reset_type=Asynchronous_Reset +CSET full_flags_reset_value=1 +CSET use_dout_reset=true +CSET dout_reset_value=0 +CSET almost_full_flag=false +CSET almost_empty_flag=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High CSET overflow_flag=false -CSET overflow_flag_axi=false CSET overflow_sense=Active_High -CSET overflow_sense_axi=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET programmable_full_type_axis=No_Programmable_Full_Threshold -CSET programmable_full_type_rach=No_Programmable_Full_Threshold -CSET programmable_full_type_rdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wach=No_Programmable_Full_Threshold -CSET programmable_full_type_wdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wrch=No_Programmable_Full_Threshold -CSET rach_type=FIFO -CSET rdch_type=FIFO -CSET read_clock_frequency=1 +CSET inject_sbit_error=false +CSET inject_dbit_error=false +CSET use_extra_logic=false +CSET data_count=false +CSET data_count_width=10 +CSET write_data_count=false +CSET write_data_count_width=10 CSET read_data_count=false CSET read_data_count_width=12 -CSET register_slice_mode_axis=Fully_Registered -CSET register_slice_mode_rach=Fully_Registered -CSET register_slice_mode_rdch=Fully_Registered +CSET disable_timing_violations=false +CSET read_clock_frequency=1 +CSET write_clock_frequency=1 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET full_threshold_assert_value=1021 +CSET full_threshold_negate_value=1020 +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET axi_type=AXI4_Stream +CSET clock_type_axi=Common_Clock +CSET use_clock_enable=false +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET enable_write_channel=false +CSET enable_read_channel=false +CSET id_width=4 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET enable_awuser=false +CSET awuser_width=1 +CSET enable_wuser=false +CSET wuser_width=1 +CSET enable_buser=false +CSET buser_width=1 +CSET enable_aruser=false +CSET aruser_width=1 +CSET enable_ruser=false +CSET ruser_width=1 +CSET enable_tdata=false +CSET tdata_width=64 +CSET enable_tid=false +CSET tid_width=8 +CSET enable_tdest=false +CSET tdest_width=4 +CSET enable_tuser=false +CSET tuser_width=4 +CSET enable_tready=true +CSET enable_tlast=false +CSET enable_tstrobe=false +CSET tstrb_width=4 +CSET enable_tkeep=false +CSET tkeep_width=4 +CSET wach_type=FIFO +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_application_type_wach=Data_FIFO +CSET enable_ecc_wach=false +CSET inject_sbit_error_wach=false +CSET inject_dbit_error_wach=false +CSET input_depth_wach=16 +CSET enable_data_counts_wach=false +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_wach=1023 +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_wach=1022 +CSET wdch_type=FIFO +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_application_type_wdch=Data_FIFO +CSET enable_ecc_wdch=false +CSET inject_sbit_error_wdch=false +CSET inject_dbit_error_wdch=false +CSET input_depth_wdch=1024 +CSET enable_data_counts_wdch=false +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_wdch=1023 +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_wdch=1022 +CSET wrch_type=FIFO +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET fifo_application_type_wrch=Data_FIFO +CSET enable_ecc_wrch=false +CSET inject_sbit_error_wrch=false +CSET inject_dbit_error_wrch=false +CSET input_depth_wrch=16 +CSET enable_data_counts_wrch=false +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_wrch=1023 +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_wrch=1022 +CSET rach_type=FIFO +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_application_type_rach=Data_FIFO +CSET enable_ecc_rach=false +CSET inject_sbit_error_rach=false +CSET inject_dbit_error_rach=false +CSET input_depth_rach=16 +CSET enable_data_counts_rach=false +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_rach=1023 +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_rach=1022 +CSET rdch_type=FIFO +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_application_type_rdch=Data_FIFO +CSET enable_ecc_rdch=false +CSET inject_sbit_error_rdch=false +CSET inject_dbit_error_rdch=false +CSET input_depth_rdch=1024 +CSET enable_data_counts_rdch=false +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_rdch=1023 +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_rdch=1022 +CSET axis_type=FIFO +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_application_type_axis=Data_FIFO +CSET enable_ecc_axis=false +CSET inject_sbit_error_axis=false +CSET inject_dbit_error_axis=false +CSET input_depth_axis=1024 +CSET enable_data_counts_axis=false +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_axis=1023 +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_axis=1022 CSET register_slice_mode_wach=Fully_Registered CSET register_slice_mode_wdch=Fully_Registered CSET register_slice_mode_wrch=Fully_Registered -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET ruser_width=1 -CSET synchronization_stages=2 -CSET synchronization_stages_axi=2 -CSET tdata_width=64 -CSET tdest_width=4 -CSET tid_width=8 -CSET tkeep_width=4 -CSET tstrb_width=4 -CSET tuser_width=4 -CSET underflow_flag=false +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_axis=Fully_Registered CSET underflow_flag_axi=false -CSET underflow_sense=Active_High CSET underflow_sense_axi=Active_High -CSET use_clock_enable=false -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET wach_type=FIFO -CSET wdch_type=FIFO -CSET wrch_type=FIFO -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=10 -CSET wuser_width=1 +CSET overflow_flag_axi=false +CSET overflow_sense_axi=Active_High +CSET disable_timing_violations_axi=false +CSET add_ngc_constraint_axi=false +CSET enable_common_underflow=false +CSET enable_common_overflow=false +CSET enable_read_pointer_increment_by2=false # END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T12:39:56Z -# END Extra information GENERATE -# CRC: e2514423 diff --git a/fpga/vendor/xilinx/usb_fifo_tx_fin.xco b/fpga/vendor/xilinx/usb_fifo_tx_fin.xco index ce5c250..2cc9321 100644 --- a/fpga/vendor/xilinx/usb_fifo_tx_fin.xco +++ b/fpga/vendor/xilinx/usb_fifo_tx_fin.xco @@ -1,213 +1,194 @@ ############################################################## # -# Xilinx Core Generator version 14.6 -# Date: Wed Sep 25 12:38:10 2013 +# PlanAhead 14.6 +# Date: Thu Nov 28 22:34:38 2013 + # ############################################################## # # This file contains the customisation parameters for a -# Xilinx CORE Generator IP GUI. It is strongly recommended +# Xilinx IP GUI. It is strongly recommended # that you do not manually alter this file as it may cause # unexpected and unsupported behavior. # ############################################################## -# -# Generated from component: xilinx.com:ip:fifo_generator:9.3 -# -############################################################## -# # BEGIN Project Options -SET addpads = false -SET asysymbol = true -SET busformat = BusFormatAngleBracketNotRipped -SET createndf = false -SET designentry = VHDL -SET device = xc6slx45 -SET devicefamily = spartan6 -SET flowvendor = Other -SET formalverification = false -SET foundationsym = false -SET implementationfiletype = Ngc -SET package = csg324 -SET removerpms = false -SET simulationfiles = Behavioral -SET speedgrade = -3 -SET verilogsim = false -SET vhdlsim = true +SET devicefamily=spartan6 +SET device=xc6slx45 +SET package=csg324 +SET speedgrade=-3 +SET verilogsim=false +SET vhdlsim=true # END Project Options # BEGIN Select SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 # END Select # BEGIN Parameters -CSET add_ngc_constraint_axi=false -CSET almost_empty_flag=false -CSET almost_full_flag=false -CSET aruser_width=1 -CSET awuser_width=1 -CSET axi_address_width=32 -CSET axi_data_width=64 -CSET axi_type=AXI4_Stream -CSET axis_type=FIFO -CSET buser_width=1 -CSET clock_enable_type=Slave_Interface_Clock_Enable -CSET clock_type_axi=Common_Clock CSET component_name=usb_fifo_tx_fin -CSET data_count=false -CSET data_count_width=10 -CSET disable_timing_violations=false -CSET disable_timing_violations_axi=false -CSET dout_reset_value=0 -CSET empty_threshold_assert_value=4 -CSET empty_threshold_assert_value_axis=1022 -CSET empty_threshold_assert_value_rach=1022 -CSET empty_threshold_assert_value_rdch=1022 -CSET empty_threshold_assert_value_wach=1022 -CSET empty_threshold_assert_value_wdch=1022 -CSET empty_threshold_assert_value_wrch=1022 -CSET empty_threshold_negate_value=5 -CSET enable_aruser=false -CSET enable_awuser=false -CSET enable_buser=false -CSET enable_common_overflow=false -CSET enable_common_underflow=false -CSET enable_data_counts_axis=false -CSET enable_data_counts_rach=false -CSET enable_data_counts_rdch=false -CSET enable_data_counts_wach=false -CSET enable_data_counts_wdch=false -CSET enable_data_counts_wrch=false -CSET enable_ecc=false -CSET enable_ecc_axis=false -CSET enable_ecc_rach=false -CSET enable_ecc_rdch=false -CSET enable_ecc_wach=false -CSET enable_ecc_wdch=false -CSET enable_ecc_wrch=false -CSET enable_read_channel=false -CSET enable_read_pointer_increment_by2=false -CSET enable_reset_synchronization=true -CSET enable_ruser=false -CSET enable_tdata=false -CSET enable_tdest=false -CSET enable_tid=false -CSET enable_tkeep=false -CSET enable_tlast=false -CSET enable_tready=true -CSET enable_tstrobe=false -CSET enable_tuser=false -CSET enable_write_channel=false -CSET enable_wuser=false -CSET fifo_application_type_axis=Data_FIFO -CSET fifo_application_type_rach=Data_FIFO -CSET fifo_application_type_rdch=Data_FIFO -CSET fifo_application_type_wach=Data_FIFO -CSET fifo_application_type_wdch=Data_FIFO -CSET fifo_application_type_wrch=Data_FIFO CSET fifo_implementation=Independent_Clocks_Block_RAM -CSET fifo_implementation_axis=Common_Clock_Block_RAM -CSET fifo_implementation_rach=Common_Clock_Block_RAM -CSET fifo_implementation_rdch=Common_Clock_Block_RAM -CSET fifo_implementation_wach=Common_Clock_Block_RAM -CSET fifo_implementation_wdch=Common_Clock_Block_RAM -CSET fifo_implementation_wrch=Common_Clock_Block_RAM -CSET full_flags_reset_value=1 -CSET full_threshold_assert_value=1023 -CSET full_threshold_assert_value_axis=1023 -CSET full_threshold_assert_value_rach=1023 -CSET full_threshold_assert_value_rdch=1023 -CSET full_threshold_assert_value_wach=1023 -CSET full_threshold_assert_value_wdch=1023 -CSET full_threshold_assert_value_wrch=1023 -CSET full_threshold_negate_value=1022 -CSET id_width=4 -CSET inject_dbit_error=false -CSET inject_dbit_error_axis=false -CSET inject_dbit_error_rach=false -CSET inject_dbit_error_rdch=false -CSET inject_dbit_error_wach=false -CSET inject_dbit_error_wdch=false -CSET inject_dbit_error_wrch=false -CSET inject_sbit_error=false -CSET inject_sbit_error_axis=false -CSET inject_sbit_error_rach=false -CSET inject_sbit_error_rdch=false -CSET inject_sbit_error_wach=false -CSET inject_sbit_error_wdch=false -CSET inject_sbit_error_wrch=false +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET interface_type=Native +CSET performance_options=First_Word_Fall_Through CSET input_data_width=24 CSET input_depth=1024 -CSET input_depth_axis=1024 -CSET input_depth_rach=16 -CSET input_depth_rdch=1024 -CSET input_depth_wach=16 -CSET input_depth_wdch=1024 -CSET input_depth_wrch=16 -CSET interface_type=Native CSET output_data_width=24 CSET output_depth=1024 +CSET enable_ecc=false +CSET use_embedded_registers=false +CSET reset_pin=true +CSET enable_reset_synchronization=true +CSET reset_type=Asynchronous_Reset +CSET full_flags_reset_value=1 +CSET use_dout_reset=true +CSET dout_reset_value=0 +CSET almost_full_flag=false +CSET almost_empty_flag=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High CSET overflow_flag=false -CSET overflow_flag_axi=false CSET overflow_sense=Active_High -CSET overflow_sense_axi=Active_High -CSET performance_options=First_Word_Fall_Through -CSET programmable_empty_type=No_Programmable_Empty_Threshold -CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold -CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold -CSET programmable_full_type=No_Programmable_Full_Threshold -CSET programmable_full_type_axis=No_Programmable_Full_Threshold -CSET programmable_full_type_rach=No_Programmable_Full_Threshold -CSET programmable_full_type_rdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wach=No_Programmable_Full_Threshold -CSET programmable_full_type_wdch=No_Programmable_Full_Threshold -CSET programmable_full_type_wrch=No_Programmable_Full_Threshold -CSET rach_type=FIFO -CSET rdch_type=FIFO -CSET read_clock_frequency=1 +CSET inject_sbit_error=false +CSET inject_dbit_error=false +CSET use_extra_logic=false +CSET data_count=false +CSET data_count_width=10 +CSET write_data_count=false +CSET write_data_count_width=10 CSET read_data_count=false CSET read_data_count_width=10 -CSET register_slice_mode_axis=Fully_Registered -CSET register_slice_mode_rach=Fully_Registered -CSET register_slice_mode_rdch=Fully_Registered +CSET disable_timing_violations=false +CSET read_clock_frequency=1 +CSET write_clock_frequency=1 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET full_threshold_assert_value=1023 +CSET full_threshold_negate_value=1022 +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET axi_type=AXI4_Stream +CSET clock_type_axi=Common_Clock +CSET use_clock_enable=false +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET enable_write_channel=false +CSET enable_read_channel=false +CSET id_width=4 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET enable_awuser=false +CSET awuser_width=1 +CSET enable_wuser=false +CSET wuser_width=1 +CSET enable_buser=false +CSET buser_width=1 +CSET enable_aruser=false +CSET aruser_width=1 +CSET enable_ruser=false +CSET ruser_width=1 +CSET enable_tdata=false +CSET tdata_width=64 +CSET enable_tid=false +CSET tid_width=8 +CSET enable_tdest=false +CSET tdest_width=4 +CSET enable_tuser=false +CSET tuser_width=4 +CSET enable_tready=true +CSET enable_tlast=false +CSET enable_tstrobe=false +CSET tstrb_width=4 +CSET enable_tkeep=false +CSET tkeep_width=4 +CSET wach_type=FIFO +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_application_type_wach=Data_FIFO +CSET enable_ecc_wach=false +CSET inject_sbit_error_wach=false +CSET inject_dbit_error_wach=false +CSET input_depth_wach=16 +CSET enable_data_counts_wach=false +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_wach=1023 +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_wach=1022 +CSET wdch_type=FIFO +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_application_type_wdch=Data_FIFO +CSET enable_ecc_wdch=false +CSET inject_sbit_error_wdch=false +CSET inject_dbit_error_wdch=false +CSET input_depth_wdch=1024 +CSET enable_data_counts_wdch=false +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_wdch=1023 +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_wdch=1022 +CSET wrch_type=FIFO +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET fifo_application_type_wrch=Data_FIFO +CSET enable_ecc_wrch=false +CSET inject_sbit_error_wrch=false +CSET inject_dbit_error_wrch=false +CSET input_depth_wrch=16 +CSET enable_data_counts_wrch=false +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_wrch=1023 +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_wrch=1022 +CSET rach_type=FIFO +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_application_type_rach=Data_FIFO +CSET enable_ecc_rach=false +CSET inject_sbit_error_rach=false +CSET inject_dbit_error_rach=false +CSET input_depth_rach=16 +CSET enable_data_counts_rach=false +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_rach=1023 +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_rach=1022 +CSET rdch_type=FIFO +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_application_type_rdch=Data_FIFO +CSET enable_ecc_rdch=false +CSET inject_sbit_error_rdch=false +CSET inject_dbit_error_rdch=false +CSET input_depth_rdch=1024 +CSET enable_data_counts_rdch=false +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_rdch=1023 +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_rdch=1022 +CSET axis_type=FIFO +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_application_type_axis=Data_FIFO +CSET enable_ecc_axis=false +CSET inject_sbit_error_axis=false +CSET inject_dbit_error_axis=false +CSET input_depth_axis=1024 +CSET enable_data_counts_axis=false +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET full_threshold_assert_value_axis=1023 +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET empty_threshold_assert_value_axis=1022 CSET register_slice_mode_wach=Fully_Registered CSET register_slice_mode_wdch=Fully_Registered CSET register_slice_mode_wrch=Fully_Registered -CSET reset_pin=true -CSET reset_type=Asynchronous_Reset -CSET ruser_width=1 -CSET synchronization_stages=2 -CSET synchronization_stages_axi=2 -CSET tdata_width=64 -CSET tdest_width=4 -CSET tid_width=8 -CSET tkeep_width=4 -CSET tstrb_width=4 -CSET tuser_width=4 -CSET underflow_flag=false +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_axis=Fully_Registered CSET underflow_flag_axi=false -CSET underflow_sense=Active_High CSET underflow_sense_axi=Active_High -CSET use_clock_enable=false -CSET use_dout_reset=true -CSET use_embedded_registers=false -CSET use_extra_logic=false -CSET valid_flag=false -CSET valid_sense=Active_High -CSET wach_type=FIFO -CSET wdch_type=FIFO -CSET wrch_type=FIFO -CSET write_acknowledge_flag=false -CSET write_acknowledge_sense=Active_High -CSET write_clock_frequency=1 -CSET write_data_count=false -CSET write_data_count_width=10 -CSET wuser_width=1 +CSET overflow_flag_axi=false +CSET overflow_sense_axi=Active_High +CSET disable_timing_violations_axi=false +CSET add_ngc_constraint_axi=false +CSET enable_common_underflow=false +CSET enable_common_overflow=false +CSET enable_read_pointer_increment_by2=false # END Parameters -# BEGIN Extra information -MISC pkg_timestamp=2012-11-19T12:39:56Z -# END Extra information GENERATE -# CRC: 7bd756aa