Merge branch 'master' of ssh://wave//srv/www/dev.krll.de/git/fx2
This commit is contained in:
commit
c6b9499af2
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-- ---------------------------------------------------------------
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-- (2013) Benjamin Krill <benjamin@krll.de>
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-- ---------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.strm_package.all;
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ENTITY f2p_strm_top_tb IS
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END f2p_strm_top_tb;
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ARCHITECTURE rtl OF f2p_strm_top_tb IS
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constant CLK_PERIOD : time := 5 ns;
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constant CLK_PERIOD2: time := 21 ns;
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signal clk : std_logic;
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signal usb_clk : std_logic;
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signal rst : std_logic;
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signal rst_n : std_logic;
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signal usb_flag_a_i : std_logic;
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signal usb_flag_full : std_logic;
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signal usb_flag_empty : std_logic;
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signal usb_cs_o : std_logic;
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signal usb_oe_o : std_logic;
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signal usb_rd_o : std_logic;
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signal usb_wr_o : std_logic;
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signal usb_pktend_o : std_logic;
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signal usb_adr_o : std_logic_vector(1 downto 0);
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signal usb_dat_io : std_logic_vector(7 downto 0);
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signal usb_dat_o : std_logic_vector(7 downto 0);
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signal usb_dat_i : std_logic_vector(7 downto 0);
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signal tmp_data : std_logic_vector(31 downto 0);
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signal tmp_data_m : std_logic_vector(31 downto 0);
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signal strm_in_type : std_logic_vector( 3 downto 0);
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signal strm_in_data : std_logic_vector(31 downto 0);
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signal strm_in_eop : std_logic;
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signal strm_in_en : std_logic;
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signal strm_in_busy : std_logic;
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constant STRM_OUT_SLV_CNT : integer := 1;
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signal strm_out_slv_reqs : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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signal strm_out_slv_busy : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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signal strm_out_data : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
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signal strm_out_eop : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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signal strm_out_en : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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signal ddr2_strm_out_req : std_logic;
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signal ddr2_strm_out_busy : std_logic;
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signal ddr2_strm_out_data : std_logic_vector(31 downto 0);
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signal ddr2_strm_out_eop : std_logic;
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signal ddr2_strm_out_en : std_logic;
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signal usb_flag_a_iq : std_logic;
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signal usb_flag_b_iq : std_logic;
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signal usb_flag_c_iq : std_logic;
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signal usb_cs_oq : std_logic;
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signal usb_oe_oq : std_logic;
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signal usb_rd_oq : std_logic;
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signal usb_wr_oq : std_logic;
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signal usb_pktend_oq : std_logic;
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signal usb_adr_oq : std_logic_vector(1 downto 0);
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signal ddr2_cmd_en_o : std_logic;
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signal ddr2_wr_full_i : std_logic;
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signal ddr2_rd_empty_i : std_logic;
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signal ddr2_rd_en_o : std_logic;
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BEGIN
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rst <= transport '1', '0' after ( 4 * CLK_PERIOD);
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rst_n <= not rst;
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clock: process
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begin
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clk <= '1', '0' after CLK_PERIOD/2;
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wait for CLK_PERIOD;
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end process;
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usb_clk_0: process
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begin
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usb_clk <= '1', '0' after CLK_PERIOD2/2;
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wait for CLK_PERIOD2;
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end process;
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reg1: process begin
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wait until rising_edge(clk);
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end process;
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reg2: process begin
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wait until rising_edge(usb_clk);
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usb_flag_a_iq <= usb_flag_a_i;
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usb_flag_b_iq <= usb_flag_full;
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usb_flag_c_iq <= usb_flag_empty;
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usb_cs_o <= usb_cs_oq;
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usb_oe_o <= usb_oe_oq;
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usb_rd_o <= usb_rd_oq;
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usb_wr_o <= usb_wr_oq;
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usb_pktend_o <= usb_pktend_oq;
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usb_adr_o <= usb_adr_oq;
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end process;
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usb_dat_io <= (others => 'Z') when usb_oe_o = '1' else usb_dat_o;
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usb_dat_i <= usb_dat_io when usb_oe_o = '0' else (others => '0');
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f2p_strm_top_0: entity work.f2p_strm_top
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generic map ( STRM_OUT_SLV_CNT => STRM_OUT_SLV_CNT )
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port map (
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clk => clk,
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rst_n => rst_n,
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-- cypress interface
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usb_clk => usb_clk,
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usb_flag_a_i => usb_flag_a_iq,
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usb_flag_b_i => usb_flag_full,
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usb_flag_c_i => usb_flag_empty,
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usb_cs_o => usb_cs_oq,
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usb_oe_o => usb_oe_oq,
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usb_rd_o => usb_rd_oq,
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usb_wr_o => usb_wr_oq,
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usb_pktend_o => usb_pktend_oq,
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usb_adr_o => usb_adr_oq,
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usb_dat_io => usb_dat_io,
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-- streaming bus
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strm_in_data_o => strm_in_data,
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strm_in_eop_o => strm_in_eop,
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strm_in_en_o => strm_in_en,
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strm_in_busy_i => strm_in_busy,
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strm_out_slv_reqs_i => strm_out_slv_reqs,
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strm_out_slv_busy_o => strm_out_slv_busy,
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strm_out_data_i => strm_out_data,
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strm_out_eop_i => strm_out_eop,
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strm_out_en_i => strm_out_en
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);
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ddr2_strm_out_busy <= strm_out_slv_busy(0);
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strm_out_slv_reqs(0) <= ddr2_strm_out_req;
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strm_out_data(0) <= ddr2_strm_out_data;
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strm_out_eop(0) <= ddr2_strm_out_eop;
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strm_out_en(0) <= ddr2_strm_out_en;
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strm_ddr2_0: entity work.strm_ddr2
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port map (
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clk => clk,
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rst_n => rst_n,
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-- streaming bus
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strm_in_data_i => strm_in_data,
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strm_in_eop_i => strm_in_eop,
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strm_in_en_i => strm_in_en,
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strm_in_busy_o => strm_in_busy,
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strm_out_req_o => ddr2_strm_out_req,
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strm_out_busy_i => ddr2_strm_out_busy,
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strm_out_data_o => ddr2_strm_out_data,
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strm_out_eop_o => ddr2_strm_out_eop,
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strm_out_en_o => ddr2_strm_out_en,
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-- memory interface
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ddr2_cmd_en_o => ddr2_cmd_en_o,
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ddr2_cmd_instr_o => open,
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ddr2_cmd_bl_o => open,
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ddr2_cmd_byte_addr_o => open,
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ddr2_cmd_empty_i => '0',
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ddr2_cmd_full_i => '0',
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ddr2_wr_en_o => open,
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ddr2_wr_mask_o => open,
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ddr2_wr_data_o => open,
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ddr2_wr_full_i => ddr2_wr_full_i,
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ddr2_wr_empty_i => '0',
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ddr2_wr_count_i => (others => '0'),
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ddr2_wr_underrun_i => '0',
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ddr2_wr_error_i => '0',
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ddr2_rd_en_o => ddr2_rd_en_o,
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ddr2_rd_data_i => (others => '0'),
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ddr2_rd_full_i => '0',
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ddr2_rd_empty_i => ddr2_rd_empty_i,
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ddr2_rd_count_i => (others => '0'),
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ddr2_rd_overflow_i => '0',
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ddr2_rd_error_i => '0'
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);
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bla: process begin
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ddr2_wr_full_i <= '0';
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-- wait for 500*CLK_PERIOD;
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-- ddr2_wr_full_i <= '1';
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-- wait for 50*CLK_PERIOD;
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-- ddr2_wr_full_i <= '0';
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wait;
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end process;
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bla2: process begin
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ddr2_rd_empty_i <= '1';
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wait for 20*CLK_PERIOD;
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wait until ddr2_cmd_en_o = '1';
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wait for 10*CLK_PERIOD;
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ddr2_rd_empty_i <= '0';
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wait until ddr2_rd_en_o = '1';
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wait for 5*CLK_PERIOD;
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ddr2_rd_empty_i <= '1';
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wait for 5*CLK_PERIOD;
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ddr2_rd_empty_i <= '0';
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wait for 5*CLK_PERIOD;
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ddr2_rd_empty_i <= '1';
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end process;
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tmp_data_m <= tmp_data(7 downto 0) & tmp_data(15 downto 8) & tmp_data(23 downto 16) & tmp_data(31 downto 24);
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usb_beh: process begin
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usb_flag_a_i <= '0';
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usb_flag_full <= '1';
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usb_flag_empty <= '0';
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usb_dat_o <= (others => '0');
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for I in 1 to 1 loop
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wait for 20*CLK_PERIOD2;
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-- do DDR read
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tmp_data <= STRM_TYPE_DDR2 & (27 downto 24 => '0') & x"000002";
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wait for 2*CLK_PERIOD2;
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usb_flag_empty <= '1';
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usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8));
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wait until usb_rd_o = '0';
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for I in 1 to 3 loop
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usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8));
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wait for CLK_PERIOD2;
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end loop;
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-- DDR2 HEADER 0
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usb_flag_empty <= '0';
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tmp_data <= x"0000100" & std_logic_vector(to_unsigned(I, 4));
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wait for 2*CLK_PERIOD2;
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usb_flag_empty <= '1';
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usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8));
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wait until usb_rd_o = '0';
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for I in 1 to 3 loop
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usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8));
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wait for CLK_PERIOD2;
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end loop;
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usb_flag_empty <= '0';
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-- DDR2 HEADER 1
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usb_flag_empty <= '0';
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tmp_data <= x"0000000a";
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wait for 2*CLK_PERIOD2;
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usb_flag_empty <= '1';
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usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8));
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wait until usb_rd_o = '0';
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for I in 1 to 3 loop
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usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8));
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wait for CLK_PERIOD2;
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end loop;
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usb_flag_empty <= '0';
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wait for 200*CLK_PERIOD2;
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end loop;
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wait;
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-- do DDR write
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-- STRM header
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tmp_data <= STRM_TYPE_DDR2 & (27 downto 24 => '0') & x"000041";
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wait for 2*CLK_PERIOD2;
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usb_flag_empty <= '1';
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usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8));
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wait until usb_rd_o = '0';
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for I in 1 to 3 loop
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usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8));
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wait for CLK_PERIOD2;
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end loop;
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-- DDR2 HEADER
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usb_flag_empty <= '0';
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tmp_data <= x"80001000";
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wait for 2*CLK_PERIOD2;
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usb_flag_empty <= '1';
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usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8));
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wait until usb_rd_o = '0';
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for I in 1 to 3 loop
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usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8));
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wait for CLK_PERIOD2;
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end loop;
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usb_flag_empty <= '0';
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-- DATA
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usb_flag_empty <= '1';
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usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8));
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wait until usb_rd_o = '0';
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for I in 2 to 4*64 loop
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usb_dat_o <= std_logic_vector(to_unsigned(I, 8));
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wait for CLK_PERIOD2;
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end loop;
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usb_flag_empty <= '0';
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usb_dat_o <= (others => '0');
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wait;
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end process;
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end rtl;
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configuration f2p_strm_top_tb_rtl_cfg of f2p_strm_top_tb is
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for rtl
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end for;
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end f2p_strm_top_tb_rtl_cfg;
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