commit f3e562f83550176711b755b5c1979cd09245f461 Author: Benjamin Krill Date: Wed Oct 2 10:43:54 2013 +0200 initial commit diff --git a/README b/README new file mode 100644 index 0000000..b3d7cdf --- /dev/null +++ b/README @@ -0,0 +1,20 @@ +-- Cypress EZ-USB FX2 -- + +- Firmware - +Library routines for creating firmware for the Cypress FX2 +(CY7C68013 and variants) with SDCC. +http://fx2lib.sourceforge.net + +Including adjustments to support the implemented FPGA VHDL +module. + +- FPGA - +The FPGA implementation consists of multiple modules. + +f2p/ - FX2 to PIPE module. (FX2 master to pipe) +strm_ddr2/ - STRM client to access DDR2 memory +misc/ - some general used modules +vendor/ - vendor specific files + +- Linux - +libusb wrapper library and ddr2 example application diff --git a/firmware/Makefile b/firmware/Makefile new file mode 100644 index 0000000..0309b7b --- /dev/null +++ b/firmware/Makefile @@ -0,0 +1,11 @@ +DIRS = lib fw + +all: + @for dir in $(DIRS); do \ + $(MAKE) -C $$dir || exit 1; \ + done + +clean: + @for dir in $(DIRS); do \ + $(MAKE) -C $$dir clean || exit 1; \ + done diff --git a/firmware/fw/.gitignore b/firmware/fw/.gitignore new file mode 100644 index 0000000..42e046d --- /dev/null +++ b/firmware/fw/.gitignore @@ -0,0 +1,9 @@ +*.asm +*.lst +*.rel +*.rst +*.sym +*.map +*.mem +*.bix +*.iic diff --git a/firmware/fw/Makefile b/firmware/fw/Makefile new file mode 100644 index 0000000..f7d4b40 --- /dev/null +++ b/firmware/fw/Makefile @@ -0,0 +1,5 @@ +SOURCES = fw.c device.c +A51_SOURCES = dscr.a51 +BASENAME = firmware + +include ../lib/fx2.mk diff --git a/firmware/fw/device.c b/firmware/fw/device.c new file mode 100644 index 0000000..9e4beac --- /dev/null +++ b/firmware/fw/device.c @@ -0,0 +1,127 @@ +#include +#include + +#ifdef DEBUG_FIRMWARE +#include +#else +#define printf(...) +#endif + +//************************** Configuration Handlers ***************************** +// change to support as many interfaces as you need +//volatile xdata BYTE interface=0; +//volatile xdata BYTE alt=0; // alt interface + +// set *alt_ifc to the current alt interface for ifc +BOOL +handle_get_interface(BYTE ifc, BYTE * alt_ifc) +{ +// *alt_ifc=alt; + return TRUE; +} + +// return TRUE if you set the interface requested +// NOTE this function should reconfigure and reset the endpoints +// according to the interface descriptors you provided. +BOOL +handle_set_interface(BYTE ifc, BYTE alt_ifc) +{ + printf("Set Interface.\n"); + //interface=ifc; + //alt=alt_ifc; + return TRUE; +} + +// handle getting and setting the configuration +// 1 is the default. If you support more than one config +// keep track of the config number and return the correct number +// config numbers are set int the dscr file. +//volatile BYTE config=1; +BYTE +handle_get_configuration() +{ + return 1; +} + +// NOTE changing config requires the device to reset all the endpoints +BOOL +handle_set_configuration(BYTE cfg) +{ + printf("Set Configuration.\n"); + //config=cfg; + return TRUE; +} + +//******************* VENDOR COMMAND HANDLERS ************************** +BOOL +handle_vendorcommand(BYTE cmd) +{ + switch (cmd) { +// case VC_EPSTAT: +// break; + default: + printf ( "Need to implement vendor command: %02x\n", cmd ); + } + + /* not handled by handlers */ + return FALSE; +} + +//******************** INIT *********************** +void +main_init() +{ + SYNCDELAY4; REVCTL = 0x03; + + /* set register default values */ + SYNCDELAY4; PINFLAGSAB = 0x00; + SYNCDELAY4; PINFLAGSCD = 0x00; + SYNCDELAY4; FIFOPINPOLAR = 0x00; + + /* SLAVE FIFO (set bmIFCLKPOL to ensure better setup times) */ + SYNCDELAY4; IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | (bmIFCFG1 | bmIFCFG0); + + /* only valid endpoints are 2/6 */ + /* EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x (HOST->DEVICE) */ + SYNCDELAY4; EP2CFG = 0xa2; + + /* slave fifo configuration 8bit, autoout */ + //SYNCDELAY4; EP2FIFOCFG &= ~bmWORDWIDE; + SYNCDELAY4; EP2FIFOCFG = bmAUTOOUT; + SYNCDELAY4; EP2AUTOINLENH = 0x00; + SYNCDELAY4; EP2AUTOINLENL = 0x00; + /* EP6 is DIR=IN, TYPE=BULK, SIZE=512, BUF=2x (DEVICE->HOST) */ + SYNCDELAY4; EP6CFG = 0xe2; + /* slave fifo configuration 8bit, autoin, zero length */ + //SYNCDELAY4; EP6FIFOCFG &= ~bmWORDWIDE; + SYNCDELAY4; EP6FIFOCFG = bmAUTOIN | bmZEROLENIN; + /* AUTOIN packet length (512byte) */ + SYNCDELAY4; EP6AUTOINLENH = 0x02; + SYNCDELAY4; EP6AUTOINLENL = 0x00; + + /* unused fifos */ + SYNCDELAY4; EP4FIFOCFG = 0; + SYNCDELAY4; EP8FIFOCFG = 0; + + /* deactive other endpoints */ + SYNCDELAY4; EP1INCFG &= ~bmVALID; + SYNCDELAY4; EP1OUTCFG &= ~bmVALID; + SYNCDELAY4; EP4CFG &= ~bmVALID; + SYNCDELAY4; EP8CFG &= ~bmVALID; + + /* Reset the FIFO */ + SYNCDELAY4; FIFORESET = 0x80; + SYNCDELAY4; FIFORESET = 0x82; + SYNCDELAY4; FIFORESET = 0x84; + SYNCDELAY4; FIFORESET = 0x86; + SYNCDELAY4; FIFORESET = 0x00; + SYNCDELAY4; + + printf("Initialization Done.\n"); +} + +void +main_loop() +{ + // do some work +} diff --git a/firmware/fw/dscr.a51 b/firmware/fw/dscr.a51 new file mode 100644 index 0000000..424d908 --- /dev/null +++ b/firmware/fw/dscr.a51 @@ -0,0 +1,186 @@ +.module DEV_DSCR + +; descriptor types +; same as setupdat.h +DSCR_DEVICE_TYPE=1 +DSCR_CONFIG_TYPE=2 +DSCR_STRING_TYPE=3 +DSCR_INTERFACE_TYPE=4 +DSCR_ENDPOINT_TYPE=5 +DSCR_DEVQUAL_TYPE=6 + +; for the repeating interfaces +DSCR_INTERFACE_LEN=9 +DSCR_ENDPOINT_LEN=7 + +; endpoint types +ENDPOINT_TYPE_CONTROL=0 +ENDPOINT_TYPE_ISO=1 +ENDPOINT_TYPE_BULK=2 +ENDPOINT_TYPE_INT=3 + + .globl _dev_dscr, _dev_qual_dscr, _highspd_dscr, _fullspd_dscr, _dev_strings, _dev_strings_end +; These need to be in code memory. If +; they aren't you'll have to manully copy them somewhere +; in code memory otherwise SUDPTRH:L don't work right + .area DSCR_AREA (CODE) + +_dev_dscr: + .db dev_dscr_end-_dev_dscr ; len + .db DSCR_DEVICE_TYPE ; type + .dw 0x0002 ; usb 2.0 + .db 0xff ; class (vendor specific) + .db 0xff ; subclass (vendor specific) + .db 0xff ; protocol (vendor specific) + .db 64 ; packet size (ep0) + .dw 0xB404 ; vendor id + .dw 0x4223 ; product id + .dw 0x0100 ; version id + .db 1 ; manufacturure str idx + .db 2 ; product str idx + .db 0 ; serial str idx + .db 1 ; n configurations +dev_dscr_end: + +_dev_qual_dscr: + .db dev_qualdscr_end-_dev_qual_dscr + .db DSCR_DEVQUAL_TYPE + .dw 0x0002 ; usb 2.0 + .db 0xff + .db 0xff + .db 0xff + .db 64 ; max packet + .db 1 ; n configs + .db 0 ; extra reserved byte +dev_qualdscr_end: + +_highspd_dscr: + .db highspd_dscr_end-_highspd_dscr ; dscr len ;; Descriptor length + .db DSCR_CONFIG_TYPE + ; can't use .dw because byte order is different + .db (highspd_dscr_realend-_highspd_dscr) % 256 ; total length of config lsb + .db (highspd_dscr_realend-_highspd_dscr) / 256 ; total length of config msb + .db 1 ; n interfaces + .db 1 ; config number + .db 0 ; config string + .db 0x80 ; attrs = bus powered, no wakeup + .db 0x32 ; max power = 100ma +highspd_dscr_end: + +; all the interfaces next +; NOTE the default TRM actually has more alt interfaces +; but you can add them back in if you need them. +; here, we just use the default alt setting 1 from the trm + .db DSCR_INTERFACE_LEN + .db DSCR_INTERFACE_TYPE + .db 0 ; index + .db 0 ; alt setting idx + .db 2 ; n endpoints + .db 0xff ; class + .db 0xff + .db 0xff + .db 0 ; string index + +; endpoint 2 out + .db DSCR_ENDPOINT_LEN + .db DSCR_ENDPOINT_TYPE + .db 0x02 ; ep2 dir=OUT and address + .db ENDPOINT_TYPE_BULK ; type + .db 0x00 ; max packet LSB + .db 0x02 ; max packet size=512 bytes + .db 0x00 ; polling interval + +; endpoint 6 in + .db DSCR_ENDPOINT_LEN + .db DSCR_ENDPOINT_TYPE + .db 0x86 ; ep6 dir=in and address + .db ENDPOINT_TYPE_BULK ; type + .db 0x00 ; max packet LSB + .db 0x02 ; max packet size=512 bytes + .db 0x00 ; polling interval + +highspd_dscr_realend: + +.even +_fullspd_dscr: + .db fullspd_dscr_end-_fullspd_dscr ; dscr len + .db DSCR_CONFIG_TYPE + ; can't use .dw because byte order is different + .db (fullspd_dscr_realend-_fullspd_dscr) % 256 ; total length of config lsb + .db (fullspd_dscr_realend-_fullspd_dscr) / 256 ; total length of config msb + .db 1 ; n interfaces + .db 1 ; config number + .db 0 ; config string + .db 0x80 ; attrs = bus powered, no wakeup + .db 0x32 ; max power = 100ma +fullspd_dscr_end: + +; all the interfaces next +; NOTE the default TRM actually has more alt interfaces +; but you can add them back in if you need them. +; here, we just use the default alt setting 1 from the trm + .db DSCR_INTERFACE_LEN + .db DSCR_INTERFACE_TYPE + .db 0 ; index + .db 0 ; alt setting idx + .db 2 ; n endpoints + .db 0xff ; class + .db 0xff + .db 0xff + .db 1 ; string index + +; endpoint 2 out + .db DSCR_ENDPOINT_LEN + .db DSCR_ENDPOINT_TYPE + .db 0x02 ; ep2 dir=OUT and address + .db ENDPOINT_TYPE_BULK ; type + .db 0x40 ; max packet LSB + .db 0x00 ; max packet size=64 bytes + .db 0x00 ; polling interval + +; endpoint 6 in + .db DSCR_ENDPOINT_LEN + .db DSCR_ENDPOINT_TYPE + .db 0x86 ; ep6 dir=in and address + .db ENDPOINT_TYPE_BULK ; type + .db 0x40 ; max packet LSB + .db 0x00 ; max packet size=64 bytes + .db 0x00 ; polling interval +fullspd_dscr_realend: + +.even +_dev_strings: +; sample string +_string0: + .db string0end-_string0 ; len + .db DSCR_STRING_TYPE + .db 0x09, 0x04 ; 0x0409 is the language code for English. Possible to add more codes after this. +string0end: +; add more strings here +_string1: + .db _string1end-_string1 ;; len + .db DSCR_STRING_TYPE + .db 'D',00 + .db 'E',00 + .db 'B',00 + .db 'U',00 + .db 'G',00 + .db ' ',00 + .db 'F',00 + .db 'W',00 +_string1end: +_string2: + .db _string2end-_string2 ;; len + .db DSCR_STRING_TYPE + .db 'T',00 + .db 'E',00 + .db 'S',00 + .db 'T',00 + .db ' ',00 + .db '1',00 + .db '2',00 + .db '3',00 +_string2end: + +_dev_strings_end: + .dw 0x0000 ; in case you wanted to look at memory between _dev_strings and _dev_strings_end diff --git a/firmware/fw/fw.c b/firmware/fw/fw.c new file mode 100644 index 0000000..dc236c5 --- /dev/null +++ b/firmware/fw/fw.c @@ -0,0 +1,119 @@ +#include +#include +#include +#include +#include + +#ifdef DEBUG_FIRMWARE +#include +#include +#else +#define printf(...) +#endif + +volatile __bit dosud = FALSE; +volatile __bit dosuspend = FALSE; + +// custom functions +extern void main_loop(); +extern void main_init(); + +void +main() +{ + +#ifdef DEBUG_FIRMWARE + SETCPUFREQ(CLK_48M); + // main_init can still set this to whatever you want. + sio0_init(57600); // needed for printf if debug defined +#endif + + main_init(); + + // set up interrupts. + USE_USB_INTS(); + + ENABLE_SUDAV(); + ENABLE_USBRESET(); + ENABLE_HISPEED(); + ENABLE_SUSPEND(); + ENABLE_RESUME(); + + /* global interrupt enable */ + EA = 1; + +// iic files (c2 load) don't need to renumerate/delay +// trm 3.6 +#ifndef NORENUM + RENUMERATE(); +#else + USBCS &= ~bmDISCON; +#endif + + while (TRUE) { + main_loop(); + + if (dosud) { + dosud = FALSE; + handle_setupdata(); + } + + if (dosuspend) { + dosuspend = FALSE; + do { + printf("I'm going to Suspend.\n"); + WAKEUPCS |= bmWU | bmWU2; // make sure ext wakeups are cleared + SUSPEND = 1; + PCON |= 1; + __asm + nop + nop + nop + nop + nop + nop + nop + __endasm; + } while (!remote_wakeup_allowed && REMOTE_WAKEUP()); + printf("I'm going to wake up.\n"); + + // resume + // trm 6.4 + if (REMOTE_WAKEUP()) { + delay(5); + USBCS |= bmSIGRESUME; + delay(15); + USBCS &= ~bmSIGRESUME; + } + } + } +} + +void +resume_isr() __interrupt RESUME_ISR { + CLEAR_RESUME(); +} + +void +sudav_isr() __interrupt SUDAV_ISR { + dosud = TRUE; + CLEAR_SUDAV(); +} + +void +usbreset_isr() __interrupt USBRESET_ISR { + handle_hispeed(FALSE); + CLEAR_USBRESET(); +} + +void +hispeed_isr() __interrupt HISPEED_ISR { + handle_hispeed(TRUE); + CLEAR_HISPEED(); +} + +void +suspend_isr() __interrupt SUSPEND_ISR { + dosuspend = TRUE; + CLEAR_SUSPEND(); +} diff --git a/firmware/include/autovector.h b/firmware/include/autovector.h new file mode 100644 index 0000000..8251e88 --- /dev/null +++ b/firmware/include/autovector.h @@ -0,0 +1,304 @@ +// Copyright (C) 2010 Ubixum, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + + + +/** \file usbjt.h + * + * To use usbjt, you must tell the linker where to put the IN2JT. + * It must lie on a page boundary or your interrupts won't work right. + * + * example: + * -Wl"-b INT2JT = 0x1A00" + * + * Make sure that INT2JT doesn't overlap your other code! + * + * Unlike the standard fx2 interrupts (\ref fx2ints.h), the autovectored + * interrupts are defined in assemply and have pre-written function names. + * Be sure to override the functions defined in this header or your + * interrupt handler will not be called. + **/ + +#ifndef USBJT_H +#define USBJT_H + +#include "fx2regs.h" + + + +// this causes usbjt to be included from the lib +// not used for anything +extern volatile BYTE INT2JT; +extern volatile BYTE INT4JT; +/** + * Enable all interrupts (EA=1) separate from this macro. + * This macro causes the autovector assembly for int2 interrupts + * to be overlayed at 0x43. In addition, the jump table for the + * interrupts will be included in the firmware. The jump table + * must lie on a page boundary. This is done by passing the linker + * arguments to sdcc. + * + * \code + * sdcc -Wl"-b INT2JT = 0xaddr" + * \endcode + **/ +#define USE_USB_INTS() {BYTE dummy=INT2JT;\ + EUSB=1;\ + INTSETUP|=bmAV2EN;} +/** This macro causes the autovector assemby for int4 to be overlayed + * at 0x53. Don't use this if you want external pin generated int4 interrupts + * and want to define your own interrupt handler. It is possible to use + * usb interrupts with autovectoring and not use GPIF interrupts but GPIF + * interrupts require the USB jump table. (You can't USE your own usb interrupt + * handler if you want to enable GPIF interrupts.) + **/ +#define USE_GPIF_INTS() {BYTE dummy=INT4JT;\ + EIEX4=1;\ + INTSETUP|=bmAV4EN|INT4IN;} + + + +#define CLEAR_USBINT() EXIF &= ~0x10 +#define CLEAR_GPIF() EXIF &= ~0x40 + +#define ENABLE_SUDAV() USBIE|=bmSUDAV +#define CLEAR_SUDAV() CLEAR_USBINT(); USBIRQ=bmSUDAV + +#define ENABLE_SUTOK() USBIE|=bmSUTOK; +#define CLEAR_SUTOK() CLEAR_USBINT(); USBIRQ=bmSUTOK + +#define ENABLE_SOF() USBIE|=bmSOF +#define CLEAR_SOF() CLEAR_USBINT(); USBIRQ=bmSOF + +#define ENABLE_SUSPEND() USBIE|=bmSUSP +#define CLEAR_SUSPEND() CLEAR_USBINT(); USBIRQ=bmSUSP + +#define ENABLE_USBRESET() USBIE|= bmURES +#define CLEAR_USBRESET() CLEAR_USBINT(); USBIRQ=bmURES + +#define ENABLE_HISPEED() USBIE|=bmHSGRANT +#define CLEAR_HISPEED() CLEAR_USBINT(); USBIRQ=bmHSGRANT + +#define ENABLE_EP0IN() EPIE|=bmEP0IN +#define CLEAR_EP0IN() CLEAR_USBINT(); EPIRQ=bmEP0IN + +#define ENABLE_EP1IN() EPIE|=bmEP1IN +#define CLEAR_EP1IN() CLEAR_USBINT(); EPIRQ=bmEP1IN + +#define ENABLE_EP2() EPIE|=bmEP2 +#define CLEAR_EP2() CLEAR_USBINT(); EPIRQ=bmEP2 + +#define ENABLE_EP6() EPIE|=bmEP6 +#define CLEAR_EP6() CLEAR_USBINT(); EPIRQ=bmEP6 + +#define ENABLE_EP2ISOERR() USBERRIE |= bmISOEP2 +#define CLEAR_EP2ISOERR() CLEAR_USBINT(); USBERRIRQ = bmISOEP2 + +#define ENABLE_EP6PF() EP6FIFOIE |= bmBIT2 +#define CLEAR_EP6PF() CLEAR_GPIF(); EP6FIFOIRQ=bmBIT2 + +#define ENABLE_EP6FF() EP6FIFOIE |= bmBIT0 +#define CLEAR_EP6FF() CLEAR_GPIF(); EP6FIFOIRQ=bmBIT0 + +#define ENABLE_GPIFDONE() GPIFIE |= 0x01; +#define CLEAR_GPIFDONE() CLEAR_GPIF(); GPIFIRQ = 0x01; + +#define ENABLE_GPIFWF() GPIFIE |= 0x02; +#define CLEAR_GPIFWF() GLEAR_GPIF(); GPIFIRQ = 0x02; + +/** + * ez-usb has 12 built in ISRs, to get + * sdcc to put these USB ISRs immediately + * after the other ISRs (and not waste space) + * we start at 13 + **/ +typedef enum { + SUDAV_ISR = 13, + SOF_ISR, + SUTOK_ISR, + SUSPEND_ISR, + USBRESET_ISR, + HISPEED_ISR, + EP0ACK_ISR, + EP0IN_ISR, + EP0OUT_ISR, + EP1IN_ISR, + EP1OUT_ISR, + EP2_ISR, + EP4_ISR, + EP6_ISR, + EP8_ISR, + IBN_ISR, + EP0PING_ISR, + EP1PING_ISR, + EP2PING_ISR, + EP4PING_ISR, + EP6PING_ISR, + EP8PING_ISR, + ERRLIMIT_ISR, + EP2ISOERR_ISR, + EP4ISOERR_ISR, + EP6ISOERR_ISR, + EP8ISOERR_ISR, + RESERVED_ISR, + EP2PF_ISR, + EP4PF_ISR, + EP6PF_ISR, + EP8PF_ISR, + EP2EF_ISR, + EP4EF_ISR, + EP6EF_ISR, + EP8EF_ISR, + EP2FF_ISR, + EP4FF_ISR, + EP6FF_ISR, + EP8FF_ISR, + GPIFDONE_ISR, + GPIFWF_ISR +} USB_ISR; + +// you must include the predef of these in the file with your main +// so lets just define them here + +void +sudav_isr() +__interrupt SUDAV_ISR; +void +sof_isr() +__interrupt SOF_ISR; +void +sutok_isr() +__interrupt SUTOK_ISR; +void +suspend_isr() +__interrupt SUSPEND_ISR; +void +usbreset_isr() +__interrupt USBRESET_ISR; +void +hispeed_isr() +__interrupt HISPEED_ISR; +void +ep0ack_isr() +__interrupt EP0ACK_ISR; +void +ep0in_isr() +__interrupt EP0IN_ISR; +void +ep0out_isr() +__interrupt EP0OUT_ISR; +void +ep1in_isr() +__interrupt EP1IN_ISR; +void +ep1out_isr() +__interrupt EP1OUT_ISR; +void +ep2_isr() +__interrupt EP2_ISR; +void +ep4_isr() +__interrupt EP4_ISR; +void +ep6_isr() +__interrupt EP6_ISR; +void +ep8_isr() +__interrupt EP8_ISR; +void +ibn_isr() +__interrupt IBN_ISR; +void +ep0ping_isr() +__interrupt EP0PING_ISR; +void +ep1ping_isr() +__interrupt EP1PING_ISR; +void +ep2ping_isr() +__interrupt EP2PING_ISR; +void +ep4ping_isr() +__interrupt EP4PING_ISR; +void +ep6ping_isr() +__interrupt EP6PING_ISR; +void +ep8ping_isr() +__interrupt EP8PING_ISR; +void +errlimit_isr() +__interrupt ERRLIMIT_ISR; +void +ep2isoerr_isr() +__interrupt EP2ISOERR_ISR; +void +ep4isoerr_isr() +__interrupt EP4ISOERR_ISR; +void +ep6isoerr_isr() +__interrupt EP6ISOERR_ISR; +void +ep8isoerr_isr() +__interrupt EP8ISOERR_ISR; +void +spare_isr() +__interrupt RESERVED_ISR; // not used +// gpif ints +void +ep2pf_isr() +__interrupt EP2PF_ISR; +void +ep4pf_isr() +__interrupt EP4PF_ISR; +void +ep6pf_isr() +__interrupt EP6PF_ISR; +void +ep8pf_isr() +__interrupt EP8PF_ISR; +void +ep2ef_isr() +__interrupt EP2EF_ISR; +void +ep4ef_isr() +__interrupt EP4EF_ISR; +void +ep6ef_isr() +__interrupt EP6EF_ISR; +void +ep8ef_isr() +__interrupt EP8EF_ISR; +void +ep2ff_isr() +__interrupt EP2FF_ISR; +void +ep4ff_isr() +__interrupt EP4FF_ISR; +void +ep6ff_isr() +__interrupt EP6FF_ISR; +void +ep8ff_isr() +__interrupt EP8FF_ISR; +void +gpifdone_isr() +__interrupt GPIFDONE_ISR; +void +gpifwf_isr() +__interrupt GPIFWF_ISR; + +#endif diff --git a/firmware/include/delay.h b/firmware/include/delay.h new file mode 100644 index 0000000..ed0600d --- /dev/null +++ b/firmware/include/delay.h @@ -0,0 +1,90 @@ +// Copyright (C) 2009 Ubixum, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/*! \file + * Functions for causing delays. + * */ + + +#ifndef DELAY_H +#define DELAY_H + +#include "fx2types.h" + +/** + * 0-65536 millis + **/ +void delay(WORD millis); + +/** + * See TRM 15-14,15-15 + * some registers (r/w) require syncdelay after + * + * up to the programmer to determine which sync is needed. + * for standard 48mhz clock w/ 48mhz IFCONFIG 3 nops is sufficient. + * + * slower clock and faster ifclock require more delay + * + * min delay = roof ( 1.5 x (ifclock/clkout + 1) ) + * + * Minimum IFCLOCK is 5mhz but you have to use an + * external clock source to go below 30mhz + * + * IFCLKSRC 1 = internal, 0=external + * 3048mhz 0 = 30mhz, 1 = 48mzh + * + * Figure your own sync delay out if IFCLKSRC=0. + **/ + +#define NOP __asm nop __endasm + +/** + * SYNCDELAY2 can work for the following clock speeds + * + * ifclk/clk + * \li 48/12 + * + * ceil(1.5 * (20.8 / 83.3 + 1)) = 2 + * + * \see NOP + * + **/ +#define SYNCDELAY2 NOP; NOP + +/** + * SYNCDELAY3 can work for the following clock speeds + * + * ifcfg/clk + * \li 48/24 + * \li 48/48 + * \li 30/12 + * \li 30/24 + * + * \see NOP + **/ +#define SYNCDELAY3 NOP; NOP; NOP + +/** + * SYNCDELAY4 should be used for the following speeds + * + * ifcfg/clk + * \li 30/48 + * + * \see NOP + **/ +#define SYNCDELAY4 NOP; NOP; NOP; NOP + +#endif diff --git a/firmware/include/eputils.h b/firmware/include/eputils.h new file mode 100644 index 0000000..5ebf19b --- /dev/null +++ b/firmware/include/eputils.h @@ -0,0 +1,86 @@ +// Copyright (C) 2009 Ubixum, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/*! \file + * Functions and macros for working with endpoints. + * */ + +#ifndef EPUTILS_H +#define EPUTILS_H + +#include "fx2types.h" + +/** + * NOTE you can't use these unless you define SYNCDELAY + * as a macro or function. The reason is that SYNCDELAY + * needs to be longer or shorter depending on your IFCONFIG + * settings. + * See delay.h + * + * Example: + * \code + * #define SYNCDELAY SYNCDELAY4 // SYNCDELAY4 from delay.h + * \endcode + * + * + **/ + +/** + * Stalls EP0. + **/ +#define STALLEP0() EP0CS |= bmEPSTALL + +/** + * \brief Reset the toggle on an endpoint. + * To use this, the endpoint needs bit 8 to be IN=1,OUT=0 + **/ +#define RESETTOGGLE(ep) TOGCTL = (ep&0x0F) + ((ep&0x80)>>3); TOGCTL |= bmRESETTOGGLE + + +/** + * RESETFIFO should not use 0x80|epnum for IN endpoints + * Only use 0x02, 0x04, 0x06, 0x06 for ep value + **/ +#define RESETFIFO(ep) {FIFORESET=0x80; SYNCDELAY;\ + FIFORESET=ep; SYNCDELAY;\ + FIFORESET=0x00; SYNCDELAY;} +/** + * Quickly reset all endpoint FIFOS. + **/ +#define RESETFIFOS() {FIFORESET=0x80; SYNCDELAY;\ + FIFORESET=0x02; SYNCDELAY;\ + FIFORESET=0x04; SYNCDELAY;\ + FIFORESET=0x06; SYNCDELAY;\ + FIFORESET=0x08; SYNCDELAY;\ + FIFORESET=0x00; SYNCDELAY;} + +/** + * Continually read available bytes from endpoint0 into dst, wait + * until more bytes are available, and loop until len bytes have + * been read. + **/ +void readep0(BYTE * dst, WORD len); + + +/** + * Write bytes from src to ep0, allowing host to transfer data + * between 64 byte blocks. + **/ +void writeep0(BYTE * src, WORD len); + + + +#endif diff --git a/firmware/include/fx2ints.h b/firmware/include/fx2ints.h new file mode 100644 index 0000000..b4b1adb --- /dev/null +++ b/firmware/include/fx2ints.h @@ -0,0 +1,115 @@ +// Copyright (C) 2010 Ubixum, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/*! \file + * Define the standard fx2 interrupts. For int2 and int4 autovector + * interrupts see \ref autovector.h + * + * To enable an interrupt, simply define an interrupt handler function + * and use the appropriate ENABLE_* macro. Interrupt enable macros + * do not enable interrupts globally. Use EA=1 to enable interrupts. + * + * \code + * void main() { + * ENABLE_RESUME(); + * EA=1; + * ... + * } + * + * void handle_resume() interrupt RESUME_ISR { + * CLEAR_RESUME(); + * } + * \endcode + * + * */ + + +/** + * \brief interrupt numbers for standard fx2 interrupts + + **/ +typedef enum { + IE0_ISR = 0, ///< External interrupt 0 + TF0_ISR, ///< Timer 0 interrupt + IE1_ISR, ///< External interrupt 1 + TF1_ISR, ///< Timer 1 interrupt + TI_0_ISR, ///< Serial port 0 transmit or receive interrupt + TF2_ISR, ///< Timer 2 interrupt + RESUME_ISR, ///< Resume interrupt + TI_1_ISR, ///< Serial port 1 transmit or receive interrupt + USBINT_ISR, ///< Usb Interrupt. An interrupt handler for this should only be used if not using auto vectored interrupts with int2 + I2CINT_ISR, ///< I2C Bus interrupt + IE4_ISR, ///< External interrupt 4. An interrupt handler for this should only be used if not using auto vectored interrupts with int4 + IE5_ISR, ///< External interrupt 5 + IE6_ISR, ///< External interrupt 6 +} FX2_ISR; + + +/** + * \brief Enable the timer 0 interrupt. + * + * There is not CLEAR_TIMER0 because the timer interrupt flag + * is automatically cleared when the isr is called. + **/ +#define ENABLE_TIMER0() ET0=1 + +/** + * \brief Enable timer 1 interrupt + * There is no CLEAR_TIMER1 because the timer interrupt flag + * is automatically cleared when the isr is called. + **/ +#define ENABLE_TIMER1() ET1=1 + + +/** + * \brief Enable timer 2 interrupt + * + * This is the same interrupt whether timer 2 overflowed or + * for the external EXF2 flag. + **/ +#define ENABLE_TIMER2() ET2=1 +/** + * \brief Clear timer 2 interrupt + * + * Clears both the TF2 AND EXF2 flag + **/ +#define CLEAR_TIMER2() TF2=0;EXF2=0; + +/** + * \brief Enable the Resume Interrupt. Requires EA=1 separately. + **/ +#define ENABLE_RESUME() ERESI = 1 + +/** + * \brief Clear the resume interrupt. Use within the resume + * interrupt handler. + **/ +#define CLEAR_RESUME() RESI=0 + + +#define ENABLE_INT4() + +/** + * \brief + * Enable external interupt for int5# + **/ +#define ENABLE_INT5() EIEX5=1 + +/** + * \brief + * Clear int5# interrupt + **/ +#define CLEAR_INT5() EXIF &= ~0x80 diff --git a/firmware/include/fx2macros.h b/firmware/include/fx2macros.h new file mode 100644 index 0000000..0383ede --- /dev/null +++ b/firmware/include/fx2macros.h @@ -0,0 +1,127 @@ +// Copyright (C) 2009 Ubixum, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/*! \file + * Macros for simple common tasks in fx2 firmware. + * */ + +#ifndef FX2MACROS_H +#define FX2MACROS_H + +#include "fx2regs.h" +#include "fx2types.h" + +#define MSB(addr) (BYTE)(((WORD)(addr) >> 8) & 0xff) +#define LSB(addr) (BYTE)((WORD)(addr) & 0xff) +#define MAKEWORD(msb,lsb) (((WORD)msb << 8) | lsb) + +#define MSW(dword) (WORD)((dword >> 16) & 0xffff) +#define LSW(dword) (WORD)(dword & 0xffff) +#define MAKEDWORD(msw,lsw) (((DWORD)msw << 16) | lsw) + +// clock stuff + +/** + * \brief Used for getting and setting the CPU clock speed. + **/ +typedef enum { CLK_12M = 0, CLK_24M, CLK_48M } CLK_SPD; + +/** + * \brief Evaluates to a CLK_SPD enum. + **/ +#define CPUFREQ (CLK_SPD)((CPUCS & bmCLKSPD) >> 3) +/** + * \brief Sets the cpu to operate at a specific + * clock speed. + **/ +#define SETCPUFREQ(SPD) CPUCS = (CPUCS & ~bmCLKSPD) | (SPD << 3) + +/** + * \brief Evaluates to a DWORD value representing + * the clock speed in cycles per second. + * + * Speeds: + * + * \li 12000000L + * \li 24000000L + * \li 48000000L + * + **/ +#define XTAL (CPUFREQ==CLK_12M ? 12000000L :\ + CPUFREQ==CLK_24M ? 24000000L : 48000000L) + + +/** + * \brief Evaluates to the i2c bus frequency in cyles per + * second. + * + * Speeds: + * + * \li 400000L + * \li 100000L + * + **/ +#define I2CFREQ ((I2CTL & bm400KHZ) ? 400000L : 100000L) + + +#define IFFREQ (IFCONFIG & bm3048MHZ ? 48000000L : 30000000L) +#define SETIF30MHZ() IFCONFIG &= ~bm3048MHZ +#define SETIF48MHZ() IFCONFIG |= bm3048MHZ + + +// eeprom stuff +#define EEPROM_TWO_BYTE (I2CS & bmBIT4) + +/** + * \brief Cause the device to disconnect and reconnect to USB. This macro + * unconditionally renumerates the device no matter how the firmware is loaded. + * + * NOTE Windows really doesn't like this if the firmware is loaded + * from an eeprom. You'll see information messages about the device not + * working properly. On the other hand, if you are changing the device + * descriptor, e.g., the vendor and product id, when downloading firmware to the device, + * you'll need to use this macro instead of the + * standard RENUMERATE macro. + **/ +#define RENUMERATE_UNCOND() USBCS|=bmDISCON|bmRENUM;delay(1500);USBCS&=~bmDISCON +/** + * \brief Cause the device to disconnect and reconnect to the USB bus. This macro + * doesn't do anything if the firmware is loaded from an eeprom. + **/ +#define RENUMERATE() if(!(USBCS&bmRENUM)) {USBCS|=bmDISCON|bmRENUM;delay(1500);USBCS &= ~bmDISCON;} + + +// interrupts +// USB interrupts are in usbjt.h + + + + +/** + * \brief TRUE if the FX2 has transitioned to high speed on the USB bus.. + **/ +#define HISPEED (USBCS&bmHSM) + + + + +/** + * \brief Evaluates to TRUE if a remote wakeup event has occurred. + **/ +#define REMOTE_WAKEUP() (((WAKEUPCS & bmWU) && (WAKEUPCS & bmWUEN)) || ((WAKEUPCS & bmWU2) && (WAKEUPCS & bmWU2EN))) + + +#endif diff --git a/firmware/include/fx2regs.h b/firmware/include/fx2regs.h new file mode 100644 index 0000000..905221d --- /dev/null +++ b/firmware/include/fx2regs.h @@ -0,0 +1,638 @@ +// Copyright (C) 2009 Ubixum, Inc. +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2.1 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +/*! \file + * + * This is the basic header/register file for working with the cypress fx2 + * (cyc768013) and variants 8051 chipset. It contains the special function + * register definitions as well as the special configuration registers + * addresses. + * + * The TRM for the fx2 chip contains the full documentation for what each of + * these registers do. + * + * */ + + +/** \mainpage FX2LIB Documentation + * \verbinclude README + **/ + +/** \example fw.c + * The firmware framework allows for easily beginning a new firware project. + **/ + +#ifndef FX2REGS_H +#define FX2REGS_H + +#include "fx2types.h" + +__xdata __at 0xE400 volatile BYTE GPIF_WAVE_DATA; +__xdata __at 0xE480 volatile BYTE RES_WAVEDATA_END; + +// General Configuration + +__xdata __at 0xE600 volatile BYTE CPUCS; ///< Control & Status +__xdata __at 0xE601 volatile BYTE IFCONFIG; ///< Interface Configuration +__xdata __at 0xE602 volatile BYTE PINFLAGSAB; ///< FIFO FLAGA and FLAGB Assignments +__xdata __at 0xE603 volatile BYTE PINFLAGSCD; ///< FIFO FLAGC and FLAGD Assignments +__xdata __at 0xE604 volatile BYTE FIFORESET; ///< Restore FIFOS to default state +__xdata __at 0xE605 volatile BYTE BREAKPT; ///< Breakpoint +__xdata __at 0xE606 volatile BYTE BPADDRH; ///< Breakpoint Address H +__xdata __at 0xE607 volatile BYTE BPADDRL; ///< Breakpoint Address L +__xdata __at 0xE608 volatile BYTE UART230; ///< 230 Kbaud clock for T0,T1,T2 +__xdata __at 0xE609 volatile BYTE FIFOPINPOLAR; ///< FIFO polarities +__xdata __at 0xE60A volatile BYTE REVID; ///< Chip Revision +__xdata __at 0xE60B volatile BYTE REVCTL; ///< Chip Revision Control + +// Endpoint Configuration + +__xdata __at 0xE610 volatile BYTE EP1OUTCFG; ///< Endpoint 1-OUT Configuration +__xdata __at 0xE611 volatile BYTE EP1INCFG; ///< Endpoint 1-IN Configuration +__xdata __at 0xE612 volatile BYTE EP2CFG; ///< Endpoint 2 Configuration +__xdata __at 0xE613 volatile BYTE EP4CFG; ///< Endpoint 4 Configuration +__xdata __at 0xE614 volatile BYTE EP6CFG; ///< Endpoint 6 Configuration +__xdata __at 0xE615 volatile BYTE EP8CFG; ///< Endpoint 8 Configuration +__xdata __at 0xE618 volatile BYTE EP2FIFOCFG; ///< Endpoint 2 FIFO configuration +__xdata __at 0xE619 volatile BYTE EP4FIFOCFG; ///< Endpoint 4 FIFO configuration +__xdata __at 0xE61A volatile BYTE EP6FIFOCFG; ///< Endpoint 6 FIFO configuration +__xdata __at 0xE61B volatile BYTE EP8FIFOCFG; ///< Endpoint 8 FIFO configuration +__xdata __at 0xE620 volatile BYTE EP2AUTOINLENH; ///< Endpoint 2 Packet Length H (IN only) +__xdata __at 0xE621 volatile BYTE EP2AUTOINLENL; ///< Endpoint 2 Packet Length L (IN only) +__xdata __at 0xE622 volatile BYTE EP4AUTOINLENH; ///< Endpoint 4 Packet Length H (IN only) +__xdata __at 0xE623 volatile BYTE EP4AUTOINLENL; ///< Endpoint 4 Packet Length L (IN only) +__xdata __at 0xE624 volatile BYTE EP6AUTOINLENH; ///< Endpoint 6 Packet Length H (IN only) +__xdata __at 0xE625 volatile BYTE EP6AUTOINLENL; ///< Endpoint 6 Packet Length L (IN only) +__xdata __at 0xE626 volatile BYTE EP8AUTOINLENH; ///< Endpoint 8 Packet Length H (IN only) +__xdata __at 0xE627 volatile BYTE EP8AUTOINLENL; ///< Endpoint 8 Packet Length L (IN only) +__xdata __at 0xE630 volatile BYTE EP2FIFOPFH; ///< EP2 Programmable Flag trigger H +__xdata __at 0xE631 volatile BYTE EP2FIFOPFL; ///< EP2 Programmable Flag trigger L +__xdata __at 0xE632 volatile BYTE EP4FIFOPFH; ///< EP4 Programmable Flag trigger H +__xdata __at 0xE633 volatile BYTE EP4FIFOPFL; ///< EP4 Programmable Flag trigger L +__xdata __at 0xE634 volatile BYTE EP6FIFOPFH; ///< EP6 Programmable Flag trigger H +__xdata __at 0xE635 volatile BYTE EP6FIFOPFL; ///< EP6 Programmable Flag trigger L +__xdata __at 0xE636 volatile BYTE EP8FIFOPFH; ///< EP8 Programmable Flag trigger H +__xdata __at 0xE637 volatile BYTE EP8FIFOPFL; ///< EP8 Programmable Flag trigger L +__xdata __at 0xE640 volatile BYTE EP2ISOINPKTS; ///< EP2 (if ISO) IN Packets per frame (1-3) +__xdata __at 0xE641 volatile BYTE EP4ISOINPKTS; ///< EP4 (if ISO) IN Packets per frame (1-3) +__xdata __at 0xE642 volatile BYTE EP6ISOINPKTS; ///< EP6 (if ISO) IN Packets per frame (1-3) +__xdata __at 0xE643 volatile BYTE EP8ISOINPKTS; ///< EP8 (if ISO) IN Packets per frame (1-3) +__xdata __at 0xE648 volatile BYTE INPKTEND; ///< Force IN Packet End +__xdata __at 0xE649 volatile BYTE OUTPKTEND; ///< Force OUT Packet End + +// Interrupts + +__xdata __at 0xE650 volatile BYTE EP2FIFOIE; ///< Endpoint 2 Flag Interrupt Enable +__xdata __at 0xE651 volatile BYTE EP2FIFOIRQ; ///< Endpoint 2 Flag Interrupt Request +__xdata __at 0xE652 volatile BYTE EP4FIFOIE; ///< Endpoint 4 Flag Interrupt Enable +__xdata __at 0xE653 volatile BYTE EP4FIFOIRQ; ///< Endpoint 4 Flag Interrupt Request +__xdata __at 0xE654 volatile BYTE EP6FIFOIE; ///< Endpoint 6 Flag Interrupt Enable +__xdata __at 0xE655 volatile BYTE EP6FIFOIRQ; ///< Endpoint 6 Flag Interrupt Request +__xdata __at 0xE656 volatile BYTE EP8FIFOIE; ///< Endpoint 8 Flag Interrupt Enable +__xdata __at 0xE657 volatile BYTE EP8FIFOIRQ; ///< Endpoint 8 Flag Interrupt Request +__xdata __at 0xE658 volatile BYTE IBNIE; ///< IN-BULK-NAK Interrupt Enable +__xdata __at 0xE659 volatile BYTE IBNIRQ; ///< IN-BULK-NAK interrupt Request +__xdata __at 0xE65A volatile BYTE NAKIE; ///< Endpoint Ping NAK interrupt Enable +__xdata __at 0xE65B volatile BYTE NAKIRQ; ///< Endpoint Ping NAK interrupt Request +__xdata __at 0xE65C volatile BYTE USBIE; ///< USB Int Enables +__xdata __at 0xE65D volatile BYTE USBIRQ; ///< USB Interrupt Requests +__xdata __at 0xE65E volatile BYTE EPIE; ///< Endpoint Interrupt Enables +__xdata __at 0xE65F volatile BYTE EPIRQ; ///< Endpoint Interrupt Requests +__xdata __at 0xE660 volatile BYTE GPIFIE; ///< GPIF Interrupt Enable +__xdata __at 0xE661 volatile BYTE GPIFIRQ; ///< GPIF Interrupt Request +__xdata __at 0xE662 volatile BYTE USBERRIE; ///< USB Error Interrupt Enables +__xdata __at 0xE663 volatile BYTE USBERRIRQ; ///< USB Error Interrupt Requests +__xdata __at 0xE664 volatile BYTE ERRCNTLIM; ///< USB Error counter and limit +__xdata __at 0xE665 volatile BYTE CLRERRCNT; ///< Clear Error Counter EC[3..0] +__xdata __at 0xE666 volatile BYTE INT2IVEC; ///< Interupt 2 (USB) Autovector +__xdata __at 0xE667 volatile BYTE INT4IVEC; ///< Interupt 4 (FIFOS & GPIF) Autovector +__xdata __at 0xE668 volatile BYTE INTSETUP; ///< Interrupt 2&4 Setup + +// Input/Output + +__xdata __at 0xE670 volatile BYTE PORTACFG; ///< I/O PORTA Alternate Configuration +__xdata __at 0xE671 volatile BYTE PORTCCFG; ///< I/O PORTC Alternate Configuration +__xdata __at 0xE672 volatile BYTE PORTECFG; ///< I/O PORTE Alternate Configuration +__xdata __at 0xE678 volatile BYTE I2CS; ///< Control & Status +__xdata __at 0xE679 volatile BYTE I2DAT; ///< Data +__xdata __at 0xE67A volatile BYTE I2CTL; ///< I2C Control +__xdata __at 0xE67B volatile BYTE XAUTODAT1; ///< Autoptr1 MOVX access +__xdata __at 0xE67C volatile BYTE XAUTODAT2; ///< Autoptr2 MOVX access + +#define EXTAUTODAT1 XAUTODAT1 +#define EXTAUTODAT2 XAUTODAT2 + +// USB Control + +__xdata __at 0xE680 volatile BYTE USBCS; ///< USB Control & Status +__xdata __at 0xE681 volatile BYTE SUSPEND; ///< Put chip into suspend +__xdata __at 0xE682 volatile BYTE WAKEUPCS; ///< Wakeup source and polarity +__xdata __at 0xE683 volatile BYTE TOGCTL; ///< Toggle Control +__xdata __at 0xE684 volatile BYTE USBFRAMEH; ///< USB Frame count H +__xdata __at 0xE685 volatile BYTE USBFRAMEL; ///< USB Frame count L +__xdata __at 0xE686 volatile BYTE MICROFRAME; ///< Microframe count, 0-7 +__xdata __at 0xE687 volatile BYTE FNADDR; ///< USB Function address + +// Endpoints + +__xdata __at 0xE68A volatile BYTE EP0BCH; ///< Endpoint 0 Byte Count H +__xdata __at 0xE68B volatile BYTE EP0BCL; ///< Endpoint 0 Byte Count L +__xdata __at 0xE68D volatile BYTE EP1OUTBC; ///< Endpoint 1 OUT Byte Count +__xdata __at 0xE68F volatile BYTE EP1INBC; ///< Endpoint 1 IN Byte Count +__xdata __at 0xE690 volatile BYTE EP2BCH; ///< Endpoint 2 Byte Count H +__xdata __at 0xE691 volatile BYTE EP2BCL; ///< Endpoint 2 Byte Count L +__xdata __at 0xE694 volatile BYTE EP4BCH; ///< Endpoint 4 Byte Count H +__xdata __at 0xE695 volatile BYTE EP4BCL; ///< Endpoint 4 Byte Count L +__xdata __at 0xE698 volatile BYTE EP6BCH; ///< Endpoint 6 Byte Count H +__xdata __at 0xE699 volatile BYTE EP6BCL; ///< Endpoint 6 Byte Count L +__xdata __at 0xE69C volatile BYTE EP8BCH; ///< Endpoint 8 Byte Count H +__xdata __at 0xE69D volatile BYTE EP8BCL; ///< Endpoint 8 Byte Count L +__xdata __at 0xE6A0 volatile BYTE EP0CS; ///< Endpoint Control and Status +__xdata __at 0xE6A1 volatile BYTE EP1OUTCS; ///< Endpoint 1 OUT Control and Status +__xdata __at 0xE6A2 volatile BYTE EP1INCS; ///< Endpoint 1 IN Control and Status +__xdata __at 0xE6A3 volatile BYTE EP2CS; ///< Endpoint 2 Control and Status +__xdata __at 0xE6A4 volatile BYTE EP4CS; ///< Endpoint 4 Control and Status +__xdata __at 0xE6A5 volatile BYTE EP6CS; ///< Endpoint 6 Control and Status +__xdata __at 0xE6A6 volatile BYTE EP8CS; ///< Endpoint 8 Control and Status +__xdata __at 0xE6A7 volatile BYTE EP2FIFOFLGS; ///< Endpoint 2 Flags +__xdata __at 0xE6A8 volatile BYTE EP4FIFOFLGS; ///< Endpoint 4 Flags +__xdata __at 0xE6A9 volatile BYTE EP6FIFOFLGS; ///< Endpoint 6 Flags +__xdata __at 0xE6AA volatile BYTE EP8FIFOFLGS; ///< Endpoint 8 Flags +__xdata __at 0xE6AB volatile BYTE EP2FIFOBCH; ///< EP2 FIFO total byte count H +__xdata __at 0xE6AC volatile BYTE EP2FIFOBCL; ///< EP2 FIFO total byte count L +__xdata __at 0xE6AD volatile BYTE EP4FIFOBCH; ///< EP4 FIFO total byte count H +__xdata __at 0xE6AE volatile BYTE EP4FIFOBCL; ///< EP4 FIFO total byte count L +__xdata __at 0xE6AF volatile BYTE EP6FIFOBCH; ///< EP6 FIFO total byte count H +__xdata __at 0xE6B0 volatile BYTE EP6FIFOBCL; ///< EP6 FIFO total byte count L +__xdata __at 0xE6B1 volatile BYTE EP8FIFOBCH; ///< EP8 FIFO total byte count H +__xdata __at 0xE6B2 volatile BYTE EP8FIFOBCL; ///< EP8 FIFO total byte count L +__xdata __at 0xE6B3 volatile BYTE SUDPTRH; ///< Setup Data Pointer high address byte +__xdata __at 0xE6B4 volatile BYTE SUDPTRL; ///< Setup Data Pointer low address byte +__xdata __at 0xE6B5 volatile BYTE SUDPTRCTL; ///< Setup Data Pointer Auto Mode +__xdata __at 0xE6B8 volatile BYTE SETUPDAT[8]; ///< 8 bytes of SETUP data + +// GPIF + +__xdata __at 0xE6C0 volatile BYTE GPIFWFSELECT; ///< Waveform Selector +__xdata __at 0xE6C1 volatile BYTE GPIFIDLECS; ///< GPIF Done, GPIF IDLE drive mode +__xdata __at 0xE6C2 volatile BYTE GPIFIDLECTL; ///< Inactive Bus, CTL states +__xdata __at 0xE6C3 volatile BYTE GPIFCTLCFG; ///< CTL OUT pin drive +__xdata __at 0xE6C4 volatile BYTE GPIFADRH; ///< GPIF Address H +__xdata __at 0xE6C5 volatile BYTE GPIFADRL; ///< GPIF Address L + +__xdata __at 0xE6CE volatile BYTE GPIFTCB3; ///< GPIF Transaction Count Byte 3 +__xdata __at 0xE6CF volatile BYTE GPIFTCB2; ///< GPIF Transaction Count Byte 2 +__xdata __at 0xE6D0 volatile BYTE GPIFTCB1; ///< GPIF Transaction Count Byte 1 +__xdata __at 0xE6D1 volatile BYTE GPIFTCB0; ///< GPIF Transaction Count Byte 0 + +__xdata __at 0xE6D2 volatile BYTE EP2GPIFFLGSEL; ///< EP2 GPIF Flag select +__xdata __at 0xE6D3 volatile BYTE EP2GPIFPFSTOP; ///< Stop GPIF EP2 transaction on prog. flag +__xdata __at 0xE6D4 volatile BYTE EP2GPIFTRIG; ///< EP2 FIFO Trigger +__xdata __at 0xE6DA volatile BYTE EP4GPIFFLGSEL; ///< EP4 GPIF Flag select +__xdata __at 0xE6DB volatile BYTE EP4GPIFPFSTOP; ///< Stop GPIF EP4 transaction on prog. flag +__xdata __at 0xE6DC volatile BYTE EP4GPIFTRIG; ///< EP4 FIFO Trigger +__xdata __at 0xE6E2 volatile BYTE EP6GPIFFLGSEL; ///< EP6 GPIF Flag select +__xdata __at 0xE6E3 volatile BYTE EP6GPIFPFSTOP; ///< Stop GPIF EP6 transaction on prog. flag +__xdata __at 0xE6E4 volatile BYTE EP6GPIFTRIG; ///< EP6 FIFO Trigger +__xdata __at 0xE6EA volatile BYTE EP8GPIFFLGSEL; ///< EP8 GPIF Flag select +__xdata __at 0xE6EB volatile BYTE EP8GPIFPFSTOP; ///< Stop GPIF EP8 transaction on prog. flag +__xdata __at 0xE6EC volatile BYTE EP8GPIFTRIG; ///< EP8 FIFO Trigger +__xdata __at 0xE6F0 volatile BYTE XGPIFSGLDATH; ///< GPIF Data H (16-bit mode only) +__xdata __at 0xE6F1 volatile BYTE XGPIFSGLDATLX; ///< Read/Write GPIF Data L & trigger transac +__xdata __at 0xE6F2 volatile BYTE XGPIFSGLDATLNOX; ///< Read GPIF Data L, no transac trigger +__xdata __at 0xE6F3 volatile BYTE GPIFREADYCFG; ///< Internal RDY,Sync/Async, RDY5CFG +__xdata __at 0xE6F4 volatile BYTE GPIFREADYSTAT; ///< RDY pin states +__xdata __at 0xE6F5 volatile BYTE GPIFABORT; ///< Abort GPIF cycles + +// UDMA + +__xdata __at 0xE6C6 volatile BYTE FLOWSTATE; /// +#include +#include + +void +delay(WORD millis) +{ + /** + * It takes 12 crystal pulses to make 1 machine cycle (8051.com) + * ez-usb trm 1.13 + * 83.3 ns at 48mhz per instruction cycle + * (assume 166.6ns at 24mhz) + * (assume 333.3ns at 12mhz) + * ez-usb trm 12.1 + * Includes the cycles for each instruction + **/ + WORD loop_count; + volatile WORD count; // NOTE perhaps use different solutions w/ out volatile + + + // set count to the number of times we need to + // go around a loop for 1 millisecond + + // then do that loop millis times. (1000 us=1ms) + + // 48mhz: 1000 us / (17 cycles * 83.3 ns / cycle / 1000 ns/us) = 706 + // 24mhz: 353 + // 12mhz: 177 + // recalculate if the number of cycles changes + // like if you change the loop below + loop_count = CPUFREQ == CLK_12M ? 177 : CPUFREQ == CLK_24M ? 353 : 706; + + // sdcc generated assembly + /* cycles code + ; delay.c:31: do { + 00101$: + ; delay.c:32: } while ( --count ); + 2 dec _delay_count_1_1 + 2 mov a,#0xff + 4 cjne a,_delay_count_1_1,00121$ + 2 dec (_delay_count_1_1 + 1) + 00121$: + 2 mov a,_delay_count_1_1 + 2 orl a,(_delay_count_1_1 + 1) + 3 jnz 00101$ + + Total 17 + */ + + do { + count = loop_count; + do { + } while (--count); + } while (--millis); + +} diff --git a/firmware/lib/eputils.c b/firmware/lib/eputils.c new file mode 100644 index 0000000..ef94488 --- /dev/null +++ b/firmware/lib/eputils.c @@ -0,0 +1,64 @@ +/** + * Copyright (C) 2009 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + + + + +#include + +#include + +#ifdef DEBUG_EPUTILS +#include +#else +#define printf(...) +#endif + +void +readep0(BYTE * dst, WORD len) +{ + WORD read = 0; // n bytes read + BYTE c, avail; + while (read < len) { + EP0BCH = 0; + // NOTE need syncdelay? + EP0BCL = 0; // re-arm ep so host can send more + while (EP0CS & bmEPBUSY); + avail = EP0BCL; // max size fits in one byte (64 bytes) + for (c = 0; c < avail; ++c) + dst[read + c] = EP0BUF[c]; + read += avail; + } +} + + +void +writeep0(BYTE * src, WORD len) +{ + WORD written = 0; + BYTE c; + while (written < len) { + while (EP0CS & bmEPBUSY); // wait + for (c = 0; c < 64 && written < len; ++c) { + EP0BUF[c] = src[written++]; + } + EP0BCH = 0; + EP0BCL = c; + printf("Write %d bytes\n", c); + } +} diff --git a/firmware/lib/fx2.mk b/firmware/lib/fx2.mk new file mode 100644 index 0000000..bb0c78d --- /dev/null +++ b/firmware/lib/fx2.mk @@ -0,0 +1,94 @@ +# common make targets for compiling fx2 firmware +# +# In your Makefile, define: +# SOURCES: list of c files to compile +# A51_SOURCES: list of any a51 files. +# DEPS: list of any depedancies (like auto-generated header files) that need +# generated prior to compiling. You must provide the target definition +# for any DEPS you define. +# BASENAME: name of your firmware file, i.e., myfirmware, but not myfirmware.c +# +# Leave these alone or redefine as necessary to customize firmware. +# (Redefine after including this makefile) +# VID vendor id +# PID product id +# LIBS optional additional libraries to link with the firmware. +# SDCC build/link options +# CODE_SIZE: Default --code-size 0x3c00 +# XRAM_SIZE: Default --xram-size 0x0200 +# XRAM_LOC: Default --xram-loc 0x3c00 +# BUILDDIR: build directory (default build) +# These two can be changed to be blank if no device descriptor is being used. +# DSCR_AREA: Default -Wl"-b DSCR_AREA=0x3e00" +# INT2JT: Default -Wl"-b INT2JT=0x3f00" +# +# Provided targets: +# +# default target: creates $(BASENAME).ihx +# bix: creates $(BASENAME).bix +# iic: creates $(BASENAME).iic +# load: uses fx2load to load firmware.bix onto the development board +# (You can customize VID/PID if you need to load the firmware onto a device that has different vendor and product id +# The default is 0x04b4, 0x8613 +# clean: delete all the temp files. + +ASM = sdcc-sdas8051 +CC = sdcc-sdcc +VID ?= 0x04b4 +PID ?= 0x2342 + +DSCR_AREA ?= -Wl"-b DSCR_AREA=0x3e00" +INT2JT ?= -Wl"-b INT2JT=0x3f00" +CODE_SIZE ?= --code-size 0x3c00 +XRAM_SIZE ?= --xram-size 0x0200 +XRAM_LOC ?= --xram-loc 0x3c00 +BUILDDIR ?= build +CFLAGS = -mmcs51 $(CODE_SIZE) $(XRAM_SIZE) $(XRAM_LOC) $(DSCR_AREA) $(INT2JT) + +FX2LIBDIR?=$(dir $(lastword $(MAKEFILE_LIST)))../ + +RELS=$(addprefix $(BUILDDIR)/, $(addsuffix .rel, $(notdir $(basename $(SOURCES) $(A51_SOURCES))))) + + +.PHONY: all ihx iic bix load clean clean-all + +all: ihx +ihx: $(BUILDDIR)/$(BASENAME).ihx +bix: $(BUILDDIR)/$(BASENAME).bix +iic: $(BUILDDIR)/$(BASENAME).iic + +$(FX2LIBDIR)/lib/fx2.lib: $(FX2LIBDIR)/lib/*.c $(FX2LIBDIR)/lib/*.a51 + $(MAKE) -C $(FX2LIBDIR)/lib + +$(BUILDDIR): + mkdir -p $(BUILDDIR) + +# can't use default target %.rel because there is no way +# to differentiate the dependency. (Is it %.rel: %.c or %.a51) +$(BUILDDIR)/$(BASENAME).ihx: $(BUILDDIR) $(SOURCES) $(A51_SOURCES) $(FX2LIBDIR)/lib/fx2.lib $(DEPS) + for a in $(A51_SOURCES); do \ + cp $$a $(BUILDDIR)/; \ + cd $(BUILDDIR) && $(ASM) -logs `basename $$a` && cd ..; \ + done + for s in $(SOURCES); do \ + THISREL=$$(basename `echo "$$s" | sed -e 's/\.c$$/\.rel/'`); \ + $(CC) $(CFLAGS) -c -I $(FX2LIBDIR)/include $$s -o $(BUILDDIR)/$$THISREL ; \ + done + $(CC) $(CFLAGS) -o $@ $(RELS) fx2.lib -L $(FX2LIBDIR)/lib $(LIBS) + +$(BUILDDIR)/$(BASENAME).bix: $(BUILDDIR)/$(BASENAME).ihx + objcopy -I ihex -O binary $< $@ +$(BUILDDIR)/$(BASENAME).iic: $(BUILDDIR)/$(BASENAME).ihx + $(FX2LIBDIR)/utils/ihx2iic.py -v $(VID) -p $(PID) $< $@ + +load: $(BUILDDIR)/$(BASENAME).bix + #fx2load -v $(VID) -p $(PID) $(BUILDDIR)/$(BASENAME).bix + fx2load -v 0x1443 -p 0x0007 $(BUILDDIR)/$(BASENAME).bix + #fxload -vvv -t fx2 -D /dev/bus/usb/002/003 -I $(BUILDDIR)/$(BASENAME).bix + #fxload -vvv -t fx2 -D /dev/bus/usb/002/003 -I build/firmware.ihx + +clean: + rm -f $(BUILDDIR)/*.{asm,ihx,lnk,lst,map,mem,rel,rst,sym,adb,cdb,bix} + +clean-all: clean + $(MAKE) -C $(FX2LIBDIR)/lib clean diff --git a/firmware/lib/gpif.c b/firmware/lib/gpif.c new file mode 100644 index 0000000..6c3baef --- /dev/null +++ b/firmware/lib/gpif.c @@ -0,0 +1,198 @@ +/** + * Copyright (C) 2009 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + + +#include +#include +#include + +#include + +#define SYNCDELAY SYNCDELAY4 + +void +gpif_init(BYTE * wavedata, BYTE * initdata) +{ + + BYTE i; + + // Registers which require a synchronization delay, see section 15.14 + // FIFORESET FIFOPINPOLAR + // INPKTEND OUTPKTEND + // EPxBCH:L REVCTL + // GPIFTCB3 GPIFTCB2 + // GPIFTCB1 GPIFTCB0 + // EPxFIFOPFH:L EPxAUTOINLENH:L + // EPxFIFOCFG EPxGPIFFLGSEL + // PINFLAGSxx EPxFIFOIRQ + // EPxFIFOIE GPIFIRQ + // GPIFIE GPIFADRH:L + // UDMACRCH:L EPxGPIFTRIG + // GPIFTRIG + + // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well... + // ...these have been replaced by GPIFTC[B3:B0] registers + + // 8051 doesn't have access to waveform memories 'til + // the part is in GPIF mode. + + // IFCLKSRC=1 , FIFOs executes on internal clk source + // xMHz=1 , 48MHz internal clk rate + // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz + // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk + // ASYNC=1 , master samples asynchronous + // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF + // IFCFG[1:0]=10, FX2 in GPIF master mode IFCONFIG + IFCONFIG &= ~0x03; // turn off IFCFG[1:0] + IFCONFIG |= 0x02; // set's IFCFG[1:0] to 10 to put in GPIF master mode. + + + GPIFABORT = 0xFF; // abort any waveforms pending + + GPIFREADYCFG = initdata[0]; + GPIFCTLCFG = initdata[1]; + GPIFIDLECS = initdata[2]; + GPIFIDLECTL = initdata[3]; + GPIFWFSELECT = initdata[5]; + GPIFREADYSTAT = initdata[6]; + + // use dual autopointer feature... + AUTOPTRSETUP = 0x07; // inc both pointers, + // ...warning: this introduces pdata hole(s) + // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2) + + // source + AUTOPTRH1 = MSB((WORD) wavedata); + AUTOPTRL1 = LSB((WORD) wavedata); + + // destination + AUTOPTRH2 = 0xE4; + AUTOPTRL2 = 0x00; + + // transfer + for (i = 0x00; i < 128; i++) { + EXTAUTODAT2 = EXTAUTODAT1; + } + +// Configure GPIF Address pins, output initial value, +// these instructions don't do anything on the +// smaller chips (e.g., 56 pin model only has ports a,b,d) + PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0] + OEC = 0xFF; // and as outputs + PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8] + OEE |= 0x80; // and as output + +// ...OR... tri-state GPIFADR[8:0] pins +// PORTCCFG = 0x00; // [7:0] as port I/O +// OEC = 0x00; // and as inputs +// PORTECFG &= 0x7F; // [8] as port I/O +// OEE &= 0x7F; // and as input + +// GPIF address pins update when GPIFADRH/L written + SYNCDELAY; // + GPIFADRH = 0x00; // bits[7:1] always 0 + SYNCDELAY; // + GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000 + +// set the initial flowstates to be all 0 in case flow states are not used + + FLOWSTATE = 0; + FLOWLOGIC = 0; + FLOWEQ0CTL = 0; + FLOWEQ1CTL = 0; + FLOWHOLDOFF = 0; + FLOWSTB = 0; + FLOWSTBEDGE = 0; + FLOWSTBHPERIOD = 0; +} + +void +gpif_setflowstate(BYTE * flowstates, BYTE bank) +{ + BYTE base = 9 * bank; + FLOWSTATE = flowstates[base]; + FLOWLOGIC = flowstates[base + 1]; + FLOWEQ0CTL = flowstates[base + 2]; + FLOWEQ1CTL = flowstates[base + 3]; + FLOWHOLDOFF = flowstates[base + 4]; + FLOWSTB = flowstates[base + 5]; + FLOWSTBEDGE = flowstates[base + 6]; + FLOWSTBHPERIOD = flowstates[base + 7]; +} + +void +gpif_set_tc32(DWORD tc) +{ + GPIFTCB3 = MSB(MSW(tc)); + SYNCDELAY; + GPIFTCB2 = LSB(MSW(tc)); + SYNCDELAY; + GPIFTCB1 = MSB(LSW(tc)); + SYNCDELAY; + GPIFTCB0 = LSB(LSW(tc)); +} + +void +gpif_set_tc16(WORD tc) +{ + GPIFTCB1 = MSB(tc); + SYNCDELAY; + GPIFTCB0 = LSB(tc); +} + + +void +gpif_single_read16(WORD * res, WORD len) +{ + BYTE c; + while (!(GPIFTRIG & 0x80)); // wait done + // dummy read to trigger real read + res[0] = XGPIFSGLDATLX; + for (c = 0; c < len; ++c) { + while (!(GPIFTRIG & 0x80)); // wait done + // real read + res[c] = GPIFSGLDATH << 8; + // whether or not to do another transfer is controlled by GPIFSGLDATLNOX or ..DATLX + res[c] |= c == len - 1 ? GPIFSGLDATLNOX : GPIFSGLDATLX; + } +} + +void +gpif_single_write16(WORD * dat, WORD len) +{ + BYTE c; + for (c = 0; c < len; ++c) { + while (!(GPIFTRIG & 0x80)); + XGPIFSGLDATH = MSB(dat[c]); + XGPIFSGLDATLX = LSB(dat[c]); + } +} + +void +gpif_fifo_read(GPIF_EP_NUM ep_num) +{ + while (!(GPIFTRIG & 0x80)); // wait until things are finished + GPIFTRIG = GPIFTRGRD | ep_num; +} + +void +gpif_fifo_write(GPIF_EP_NUM ep_num) +{ + while (!(GPIFTRIG & 0x80)); // wait until things are finished + GPIFTRIG = ep_num; // R/W=0, E[1:0] = ep_num +} diff --git a/firmware/lib/i2c.c b/firmware/lib/i2c.c new file mode 100644 index 0000000..97ceb6b --- /dev/null +++ b/firmware/lib/i2c.c @@ -0,0 +1,313 @@ +/** + * Copyright (C) 2009 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include // NOTE this needs deleted + +#include +#include +#include +#include + + +//#define DEBUG_I2C 1 + +#ifdef DEBUG_I2C +#define i2c_printf(...) printf(__VA_ARGS__) +#else +#define i2c_printf(...) +#endif + + +volatile __xdata BOOL cancel_i2c_trans; +#define CHECK_I2C_CANCEL() if (cancel_i2c_trans) return FALSE + +/** + * + 1. Set START=1. If BERR=1, start timer*. + 2. Write the 7-bit peripheral address and the direction bit (0 for a write) to I2DAT. + 3. Wait for DONE=1 or for timer to expire*. If BERR=1, go to step 1. + 4. If ACK=0, go to step 9. + 5. Load I2DAT with a data byte. + 6. Wait for DONE=1*. If BERR=1, go to step 1. + 7. If ACK=0, go to step 9. + 8. Repeat steps 5-7 for each byte until all bytes have been transferred. + 9. Set STOP=1. Wait for STOP = 0 before initiating another transfer. + **/ +BOOL +i2c_write(BYTE addr, WORD len, BYTE * addr_buf, WORD len2, BYTE * data_buf) +{ + + WORD cur_byte; + WORD total_bytes = len + len2; // NOTE overflow error? + BYTE retry_count = 2; // two tries to write address/read ack + cancel_i2c_trans = FALSE; + //BOOL wait=FALSE; // use timer if needed + + // 1. Set START=1. If BERR=1, start timer*. + step1: + CHECK_I2C_CANCEL(); + cur_byte = 0; + I2CS |= bmSTART; + if (I2CS & bmBERR) { + i2c_printf("Woops.. need to do the timer\n"); + delay(10); // way too long probably + goto step1; + } + + // 2. Write the 7-bit peripheral address and the direction bit (0 for a write) to I2DAT. + I2DAT = addr << 1; + + // 3. Wait for DONE=1 or for timer to expire*. If BERR=1, go to step 1. + while (!(I2CS & bmDONE) && !cancel_i2c_trans); + CHECK_I2C_CANCEL(); + if (I2CS & bmBERR) { + i2c_printf("bmBERR, going to step 1\n"); + goto step1; + } + + // 4. If ACK=0, go to step 9. + if (!(I2CS & bmACK)) { + I2CS |= bmSTOP; + while ((I2CS & bmSTOP) && !cancel_i2c_trans); + CHECK_I2C_CANCEL(); + --retry_count; + if (!retry_count) { + i2c_printf("No ack after writing address.! Fail\n"); + return FALSE; + } + delay(10); + goto step1; + } + // 8. Repeat steps 5-7 for each byte until all bytes have been transferred. + while (cur_byte < total_bytes) { + // 5. Load I2DAT with a data byte. + I2DAT = + cur_byte < + len ? addr_buf[cur_byte] : data_buf[cur_byte - len]; + ++cur_byte; + // 6. Wait for DONE=1*. If BERR=1, go to step 1. + while (!(I2CS & bmDONE) && !cancel_i2c_trans); + CHECK_I2C_CANCEL(); + if (I2CS & bmBERR) { + i2c_printf("bmBERR on byte %d. Going to step 1\n", + cur_byte - 1); + goto step1; + //return FALSE; + } + // 7. If ACK=0, go to step 9. + if (!(I2CS & bmACK)) { + I2CS |= bmSTOP; + while ((I2CS & bmSTOP) && !cancel_i2c_trans); + i2c_printf("No Ack after byte %d. Fail\n", cur_byte - 1); + return FALSE; + } + } + + + // 9. Set STOP=1. Wait for STOP = 0 before initiating another transfer. + //real step 9 + I2CS |= bmSTOP; + while ((I2CS & bmSTOP) && !cancel_i2c_trans); + CHECK_I2C_CANCEL(); + + return TRUE; + +} + +/* + trm 13.4.4 + + 1. Set START=1. If BERR = 1, start timer*. + 2. Write the 7-bit peripheral address and the direction bit (1 for a read) to I2DAT. + 3. Wait for DONE=1 or for timer to expire*. If BERR=1, go to step 1. + 4. If ACK=0, set STOP=1 and go to step 15. + 5. Read I2DAT to initiate the first burst of nine SCL pulses to clock in the first byte from the slave. + Discard the value that was read from I2DAT. + 6. Wait for DONE=1. If BERR=1, go to step 1. + 7. Read the just-received byte of data from I2DAT. This read also initiates the next read transfer. + 8. Repeat steps 6 and 7 for each byte until ready to read the second-to-last byte. + 9. Wait for DONE=1. If BERR=1, go to step 1. + 10. Before reading the second-to-last I2DAT byte, set LASTRD=1. + 11. Read the second-to-last byte from I2DAT. With LASTRD=1, this initiates the final byte read on + the bus. + 12. Wait for DONE=1. If BERR=1, go to step 1. + 13. Set STOP=1. + 14. Read the final byte from I2DAT immediately (the next instruction) after setting the STOP bit. By + reading I2DAT while the "stop" condition is being generated, the just-received data byte will be + retrieved without initiating an extra read transaction (nine more SCL pulses) on the I²Cbus. + 15. Wait for STOP = 0 before initiating another transfer +*/ + +/* + * timer should be at least as long as longest start-stop interval on the bus + serial clock for i2c bus runs at 100khz by default and can run at 400khz for devices that support it + start-stop interval is about 9 serial clock cycles + 400KHZ bit 0=100khz, 1=400khz + + how many cycles at XTAL cycles/second = 9 cycles at 400k (or 100k) cycles/second + + timeout = n i2c cycles / I2C cycles/sec = timeout seconds + timeout seconds * XTAL cycles/sec = XTAL cycles + 9 / 400 (or 100) * (XTAL) + +*/ +BOOL +i2c_read(BYTE addr, WORD len, BYTE * buf) +{ + + + BYTE tmp; + WORD cur_byte; + cancel_i2c_trans = FALSE; + //WORD timeout_cycles = (WORD)(9.0 * XTAL / I2CFREQ ); + + // 1. Set START=1. If BERR = 1, start timer*. + start: + CHECK_I2C_CANCEL(); + cur_byte = 0; + + I2CS |= bmSTART; + if (I2CS & bmBERR) { + i2c_printf("Woops, step1 BERR, need to do timeout\n"); + delay(10); // NOTE way too long + goto start; + } + // 2. Write the 7-bit peripheral address and the direction bit (1 for a read) to I2DAT. + I2DAT = (addr << 1) | 1; // last 1 for read + + // 3. Wait for DONE=1 or for timer to expire*. If BERR=1, go to step 1. + + while (!(I2CS & bmDONE) && !cancel_i2c_trans); + CHECK_I2C_CANCEL(); + if (I2CS & bmBERR) + goto start; + + // 4. If ACK=0, set STOP=1 and go to step 15. + if (!(I2CS & bmACK)) { + I2CS |= bmSTOP; + while ((I2CS & bmSTOP) && !cancel_i2c_trans); + return FALSE; + } + // with only one byte to read, this needs set here. + // (In this case, the tmp read is the 2nd to last read) + if (len == 1) + I2CS |= bmLASTRD; + + // 5. Read I2DAT to initiate the first burst of nine SCL pulses to clock in the first byte from the slave. + // Discard the value that was read from I2DAT. + tmp = I2DAT; // discard read + + while (len > cur_byte + 1) { // reserve last byte read for after the loop + + // 6. Wait for DONE=1. If BERR=1, go to step 1. + // 9. Wait for DONE=1. If BERR=1, go to step 1. + while (!(I2CS & bmDONE) && !cancel_i2c_trans); + CHECK_I2C_CANCEL(); + if (I2CS & bmBERR) + goto start; + + // 10. Before reading the second-to-last I2DAT byte, set LASTRD=1. + if (len == cur_byte + 2) // 2nd to last byte + I2CS |= bmLASTRD; + + // 7. Read the just-received byte of data from I2DAT. This read also initiates the next read transfer. + // 11. Read the second-to-last byte from I2DAT. With LASTRD=1, this initiates the final byte read on + // the bus. + buf[cur_byte++] = I2DAT; + + // 8. Repeat steps 6 and 7 for each byte until ready to read the second-to-last byte. + } + + //12. Wait for DONE=1. If BERR=1, go to step 1. + while (!(I2CS & bmDONE) && !cancel_i2c_trans); + CHECK_I2C_CANCEL(); + if (I2CS & bmBERR) + goto start; + // 13. Set STOP=1. + I2CS |= bmSTOP; + // 14. Read the final byte from I2DAT immediately (the next instruction) after setting the STOP bit. By + // reading I2DAT while the "stop" condition is being generated, the just-received data byte will be + // retrieved without initiating an extra read transaction (nine more SCL pulses) on the I²Cbus. + buf[cur_byte] = I2DAT; // use instead of buffer addressing so next instruction reads I2DAT + + while ((I2CS & bmSTOP) && !cancel_i2c_trans); + CHECK_I2C_CANCEL(); + + return TRUE; +} + + + +BOOL +eeprom_write(BYTE prom_addr, WORD addr, WORD length, BYTE * buf) +{ + BYTE addr_len = 0; + // 1st bytes of buffer are address and next byte is value + BYTE data_buffer[3]; + WORD cur_byte = 0; + +#ifdef DEBUG_I2C + if (EEPROM_TWO_BYTE) { + i2c_printf("Two Byte EEProm Address detected.\n"); + } else { + i2c_printf("Single Byte EEProm address detected.\n"); + } +#endif + + while (cur_byte < length) { + addr_len = 0; + if (EEPROM_TWO_BYTE) { + data_buffer[addr_len++] = MSB(addr); + } + data_buffer[addr_len++] = LSB(addr); + data_buffer[addr_len++] = buf[cur_byte++]; + + i2c_printf("%02x ", data_buffer[addr_len - 1]); + + if (!i2c_write(prom_addr, addr_len, data_buffer, 0, NULL)) + return FALSE; + ++addr; // next byte goes to next address + } + + return TRUE; + +} + + +BOOL +eeprom_read(BYTE prom_addr, WORD addr, WORD length, BYTE * buf) +{ + + BYTE eeprom_addr[2]; + BYTE addr_len = 0; + if (EEPROM_TWO_BYTE) + eeprom_addr[addr_len++] = MSB(addr); + + eeprom_addr[addr_len++] = LSB(addr); + + // write the address we want to read to the prom + //printf ("Starting Addr Write with addr len %d\n", addr_len); + if (!i2c_write(prom_addr, addr_len, eeprom_addr, 0, NULL)) + return FALSE; + //printf ( "Starting read\n" ); + if (!i2c_read(prom_addr, length, buf)) + return FALSE; + + return TRUE; + +} diff --git a/firmware/lib/int4av.a51 b/firmware/lib/int4av.a51 new file mode 100644 index 0000000..85bce78 --- /dev/null +++ b/firmware/lib/int4av.a51 @@ -0,0 +1,28 @@ +; Copyright (C) 2010 Ubixum, Inc. +; +; This library is free software; you can redistribute it and/or +; modify it under the terms of the GNU Lesser General Public +; License as published by the Free Software Foundation; either +; version 2.1 of the License, or (at your option) any later version. +; +; This library is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +; Lesser General Public License for more details. +; +; You should have received a copy of the GNU Lesser General Public +; License along with this library; if not, write to the Free Software +; Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +.module INT4AV ; jump table for int4AV (GPIF & endpoint interrupts) + +.globl _INT4JT + +.area INT4AV (ABS,OVR) +.org 0x53 ; where INT4 jumps to +_INT4AV = #. + 2 + ljmp _INT2JT ; the addr gets replaced so this really goes to int4jt locations + + +.area INT4JT ( CODE ) +_INT4JT: ; doesn't do anything but forces this module to be linked in if gpif macro used. diff --git a/firmware/lib/interrupts/ep0ack_isr.c b/firmware/lib/interrupts/ep0ack_isr.c new file mode 100644 index 0000000..d901d5c --- /dev/null +++ b/firmware/lib/interrupts/ep0ack_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep0ack_isr() +__interrupt EP0ACK_ISR { +} diff --git a/firmware/lib/interrupts/ep0in_isr.c b/firmware/lib/interrupts/ep0in_isr.c new file mode 100644 index 0000000..942d70c --- /dev/null +++ b/firmware/lib/interrupts/ep0in_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep0in_isr() +__interrupt EP0IN_ISR { +} diff --git a/firmware/lib/interrupts/ep0out_isr.c b/firmware/lib/interrupts/ep0out_isr.c new file mode 100644 index 0000000..69b5827 --- /dev/null +++ b/firmware/lib/interrupts/ep0out_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep0out_isr() +__interrupt EP0OUT_ISR { +} diff --git a/firmware/lib/interrupts/ep0ping_isr.c b/firmware/lib/interrupts/ep0ping_isr.c new file mode 100644 index 0000000..dee59a1 --- /dev/null +++ b/firmware/lib/interrupts/ep0ping_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep0ping_isr() +__interrupt EP0PING_ISR { +} diff --git a/firmware/lib/interrupts/ep1in_isr.c b/firmware/lib/interrupts/ep1in_isr.c new file mode 100644 index 0000000..f3918fa --- /dev/null +++ b/firmware/lib/interrupts/ep1in_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep1in_isr() +__interrupt EP1IN_ISR { +} diff --git a/firmware/lib/interrupts/ep1out_isr.c b/firmware/lib/interrupts/ep1out_isr.c new file mode 100644 index 0000000..074992f --- /dev/null +++ b/firmware/lib/interrupts/ep1out_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep1out_isr() +__interrupt EP1OUT_ISR { +} diff --git a/firmware/lib/interrupts/ep1ping_isr.c b/firmware/lib/interrupts/ep1ping_isr.c new file mode 100644 index 0000000..561c082 --- /dev/null +++ b/firmware/lib/interrupts/ep1ping_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep1ping_isr() +__interrupt EP1PING_ISR { +} diff --git a/firmware/lib/interrupts/ep2_isr.c b/firmware/lib/interrupts/ep2_isr.c new file mode 100644 index 0000000..4318eb7 --- /dev/null +++ b/firmware/lib/interrupts/ep2_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep2_isr() +__interrupt EP2_ISR { +} diff --git a/firmware/lib/interrupts/ep2ef_isr.c b/firmware/lib/interrupts/ep2ef_isr.c new file mode 100644 index 0000000..9101981 --- /dev/null +++ b/firmware/lib/interrupts/ep2ef_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep2ef_isr() +__interrupt EP2EF_ISR { +} diff --git a/firmware/lib/interrupts/ep2ff_isr.c b/firmware/lib/interrupts/ep2ff_isr.c new file mode 100644 index 0000000..8d57e5a --- /dev/null +++ b/firmware/lib/interrupts/ep2ff_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep2ff_isr() +__interrupt EP2FF_ISR { +} diff --git a/firmware/lib/interrupts/ep2isoerr_isr.c b/firmware/lib/interrupts/ep2isoerr_isr.c new file mode 100644 index 0000000..2fa1f93 --- /dev/null +++ b/firmware/lib/interrupts/ep2isoerr_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep2isoerr_isr() +__interrupt EP2ISOERR_ISR { +} diff --git a/firmware/lib/interrupts/ep2pf_isr.c b/firmware/lib/interrupts/ep2pf_isr.c new file mode 100644 index 0000000..2472a10 --- /dev/null +++ b/firmware/lib/interrupts/ep2pf_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep2pf_isr() +__interrupt EP2PF_ISR { +} diff --git a/firmware/lib/interrupts/ep2ping_isr.c b/firmware/lib/interrupts/ep2ping_isr.c new file mode 100644 index 0000000..1ab173b --- /dev/null +++ b/firmware/lib/interrupts/ep2ping_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep2ping_isr() +__interrupt EP2PING_ISR { +} diff --git a/firmware/lib/interrupts/ep4_isr.c b/firmware/lib/interrupts/ep4_isr.c new file mode 100644 index 0000000..8ef4100 --- /dev/null +++ b/firmware/lib/interrupts/ep4_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep4_isr() +__interrupt EP4_ISR { +} diff --git a/firmware/lib/interrupts/ep4ef_isr.c b/firmware/lib/interrupts/ep4ef_isr.c new file mode 100644 index 0000000..e8fc383 --- /dev/null +++ b/firmware/lib/interrupts/ep4ef_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep4ef_isr() +__interrupt EP4EF_ISR { +} diff --git a/firmware/lib/interrupts/ep4ff_isr.c b/firmware/lib/interrupts/ep4ff_isr.c new file mode 100644 index 0000000..6f82662 --- /dev/null +++ b/firmware/lib/interrupts/ep4ff_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep4ff_isr() +__interrupt EP4FF_ISR { +} diff --git a/firmware/lib/interrupts/ep4isoerr_isr.c b/firmware/lib/interrupts/ep4isoerr_isr.c new file mode 100644 index 0000000..ec936fd --- /dev/null +++ b/firmware/lib/interrupts/ep4isoerr_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep4isoerr_isr() +__interrupt EP4ISOERR_ISR { +} diff --git a/firmware/lib/interrupts/ep4pf_isr.c b/firmware/lib/interrupts/ep4pf_isr.c new file mode 100644 index 0000000..4c31ebc --- /dev/null +++ b/firmware/lib/interrupts/ep4pf_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep4pf_isr() +__interrupt EP4PF_ISR { +} diff --git a/firmware/lib/interrupts/ep4ping_isr.c b/firmware/lib/interrupts/ep4ping_isr.c new file mode 100644 index 0000000..dc127f6 --- /dev/null +++ b/firmware/lib/interrupts/ep4ping_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep4ping_isr() +__interrupt EP4PING_ISR { +} diff --git a/firmware/lib/interrupts/ep6_isr.c b/firmware/lib/interrupts/ep6_isr.c new file mode 100644 index 0000000..6989f4a --- /dev/null +++ b/firmware/lib/interrupts/ep6_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep6_isr() +__interrupt EP6_ISR { +} diff --git a/firmware/lib/interrupts/ep6ef_isr.c b/firmware/lib/interrupts/ep6ef_isr.c new file mode 100644 index 0000000..0c26b3c --- /dev/null +++ b/firmware/lib/interrupts/ep6ef_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep6ef_isr() +__interrupt EP6EF_ISR { +} diff --git a/firmware/lib/interrupts/ep6ff_isr.c b/firmware/lib/interrupts/ep6ff_isr.c new file mode 100644 index 0000000..dfa27f4 --- /dev/null +++ b/firmware/lib/interrupts/ep6ff_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep6ff_isr() +__interrupt EP6FF_ISR { +} diff --git a/firmware/lib/interrupts/ep6isoerr_isr.c b/firmware/lib/interrupts/ep6isoerr_isr.c new file mode 100644 index 0000000..c1bc859 --- /dev/null +++ b/firmware/lib/interrupts/ep6isoerr_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep6isoerr_isr() +__interrupt EP6ISOERR_ISR { +} diff --git a/firmware/lib/interrupts/ep6pf_isr.c b/firmware/lib/interrupts/ep6pf_isr.c new file mode 100644 index 0000000..098b83c --- /dev/null +++ b/firmware/lib/interrupts/ep6pf_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep6pf_isr() +__interrupt EP6PF_ISR { +} diff --git a/firmware/lib/interrupts/ep6ping_isr.c b/firmware/lib/interrupts/ep6ping_isr.c new file mode 100644 index 0000000..c8c8d0f --- /dev/null +++ b/firmware/lib/interrupts/ep6ping_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep6ping_isr() +__interrupt EP6PING_ISR { +} diff --git a/firmware/lib/interrupts/ep8_isr.c b/firmware/lib/interrupts/ep8_isr.c new file mode 100644 index 0000000..01360d1 --- /dev/null +++ b/firmware/lib/interrupts/ep8_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep8_isr() +__interrupt EP8_ISR { +} diff --git a/firmware/lib/interrupts/ep8ef_isr.c b/firmware/lib/interrupts/ep8ef_isr.c new file mode 100644 index 0000000..943b915 --- /dev/null +++ b/firmware/lib/interrupts/ep8ef_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep8ef_isr() +__interrupt EP8EF_ISR { +} diff --git a/firmware/lib/interrupts/ep8ff_isr.c b/firmware/lib/interrupts/ep8ff_isr.c new file mode 100644 index 0000000..83a7708 --- /dev/null +++ b/firmware/lib/interrupts/ep8ff_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep8ff_isr() +__interrupt EP8FF_ISR { +} diff --git a/firmware/lib/interrupts/ep8isoerr_isr.c b/firmware/lib/interrupts/ep8isoerr_isr.c new file mode 100644 index 0000000..4246fa3 --- /dev/null +++ b/firmware/lib/interrupts/ep8isoerr_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep8isoerr_isr() +__interrupt EP8ISOERR_ISR { +} diff --git a/firmware/lib/interrupts/ep8pf_isr.c b/firmware/lib/interrupts/ep8pf_isr.c new file mode 100644 index 0000000..6d95af7 --- /dev/null +++ b/firmware/lib/interrupts/ep8pf_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep8pf_isr() +__interrupt EP8PF_ISR { +} diff --git a/firmware/lib/interrupts/ep8ping_isr.c b/firmware/lib/interrupts/ep8ping_isr.c new file mode 100644 index 0000000..ddc5c88 --- /dev/null +++ b/firmware/lib/interrupts/ep8ping_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ep8ping_isr() +__interrupt EP8PING_ISR { +} diff --git a/firmware/lib/interrupts/errlimit_isr.c b/firmware/lib/interrupts/errlimit_isr.c new file mode 100644 index 0000000..8ae5671 --- /dev/null +++ b/firmware/lib/interrupts/errlimit_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +errlimit_isr() +__interrupt ERRLIMIT_ISR { +} diff --git a/firmware/lib/interrupts/gpifdone_isr.c b/firmware/lib/interrupts/gpifdone_isr.c new file mode 100644 index 0000000..f131ec0 --- /dev/null +++ b/firmware/lib/interrupts/gpifdone_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +gpifdone_isr() +__interrupt GPIFDONE_ISR { +} diff --git a/firmware/lib/interrupts/gpifwf_isr.c b/firmware/lib/interrupts/gpifwf_isr.c new file mode 100644 index 0000000..a3ebda3 --- /dev/null +++ b/firmware/lib/interrupts/gpifwf_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +gpifwf_isr() +__interrupt GPIFWF_ISR { +} diff --git a/firmware/lib/interrupts/hispeed_isr.c b/firmware/lib/interrupts/hispeed_isr.c new file mode 100644 index 0000000..8183976 --- /dev/null +++ b/firmware/lib/interrupts/hispeed_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +hispeed_isr() +__interrupt HISPEED_ISR { +} diff --git a/firmware/lib/interrupts/ibn_isr.c b/firmware/lib/interrupts/ibn_isr.c new file mode 100644 index 0000000..96208a3 --- /dev/null +++ b/firmware/lib/interrupts/ibn_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +ibn_isr() +__interrupt IBN_ISR { +} diff --git a/firmware/lib/interrupts/sof_isr.c b/firmware/lib/interrupts/sof_isr.c new file mode 100644 index 0000000..e2bfe26 --- /dev/null +++ b/firmware/lib/interrupts/sof_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +sof_isr() +__interrupt SOF_ISR { +} diff --git a/firmware/lib/interrupts/spare_isr.c b/firmware/lib/interrupts/spare_isr.c new file mode 100644 index 0000000..bcd280a --- /dev/null +++ b/firmware/lib/interrupts/spare_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +spare_isr() +__interrupt RESERVED_ISR { +} diff --git a/firmware/lib/interrupts/sudav_isr.c b/firmware/lib/interrupts/sudav_isr.c new file mode 100644 index 0000000..26b3e6e --- /dev/null +++ b/firmware/lib/interrupts/sudav_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +sudav_isr() +__interrupt SUDAV_ISR { +} diff --git a/firmware/lib/interrupts/suspend_isr.c b/firmware/lib/interrupts/suspend_isr.c new file mode 100644 index 0000000..22e92d0 --- /dev/null +++ b/firmware/lib/interrupts/suspend_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +suspend_isr() +__interrupt SUSPEND_ISR { +} diff --git a/firmware/lib/interrupts/sutok_isr.c b/firmware/lib/interrupts/sutok_isr.c new file mode 100644 index 0000000..d1cd788 --- /dev/null +++ b/firmware/lib/interrupts/sutok_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +sutok_isr() +__interrupt SUTOK_ISR { +} diff --git a/firmware/lib/interrupts/usbreset_isr.c b/firmware/lib/interrupts/usbreset_isr.c new file mode 100644 index 0000000..df5addb --- /dev/null +++ b/firmware/lib/interrupts/usbreset_isr.c @@ -0,0 +1,24 @@ +/** + * Copyright (C) 2010 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +#include + +void +usbreset_isr() +__interrupt USBRESET_ISR { +} diff --git a/firmware/lib/serial.c b/firmware/lib/serial.c new file mode 100644 index 0000000..bcc8e77 --- /dev/null +++ b/firmware/lib/serial.c @@ -0,0 +1,102 @@ +/** + * Copyright (C) 2009 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + + +#include +#include +#include + + +/** + * using the comp port implies that timer 2 will be used as + * a baud rate generator. (Don't use timer 2) + **/ +void +sio0_init(WORD baud_rate) + __critical +{ // baud_rate max should be 57600 since int=2 bytes + + WORD hl; // hl value for reload + BYTE mult; // multiplier for clock speed + DWORD tmp; // scratch for mult/divide + + // 0 = 12mhz, 1=24mhz, 2=48mhz + mult = CPUFREQ == CLK_12M ? 1 : CPUFREQ == CLK_24M ? 2 : 4; // since only 3 clock speeds, fast switch instead of doing 2^clock speed pow(2,clkspd) + + // set the clock rate + // use clock 2 + RCLK = 1; + TCLK = 1; + +// RCAP2H:L = 0xFFFF - CLKOUT / 32 x baud_rate + + // in order to round to nearest value.. + // tmp * 2 // double + // tmp / rate // do the divide + // tmp + 1 // add one (which is like adding 1/2) + // tmp / 2 // back to original rounded + tmp = mult * 375000L * 2; + tmp /= baud_rate; + tmp += 1; + tmp /= 2; + + hl = 0xFFFF - (WORD) tmp; + + RCAP2H = MSB(hl); + // seems that the 24/48mhz calculations are always one less than suggested values + // trm table 14-16 + RCAP2L = LSB(hl) + (mult > 0 ? 1 : 0); + TR2 = 1; // start the timer + + // set up the serial port + SM0 = 0; + SM1 = 1; // serial mode 1 (asyncronous) + SM2 = 0; // has to do with receiving + REN = 1; // to enable receiving + PCON |= 0x80; // SET SMOD0, baud rate doubler + TI = 1; // we send initial byte + +} + +char +getchar() +{ + char c; + while (!RI); + c = SBUF0; + RI = 0; + return c; +} + +void +_transchar(char c) +{ + while (!TI); // wait for TI=1 + TI = 0; + SBUF0 = c; +} + +void +putchar(char c) +{ + if (c == '\n') + _transchar('\r'); // transmit \r\n + _transchar(c); + if (c == '\r') + _transchar('\n'); // transmit \r\n +} diff --git a/firmware/lib/setupdat.c b/firmware/lib/setupdat.c new file mode 100644 index 0000000..a6dc690 --- /dev/null +++ b/firmware/lib/setupdat.c @@ -0,0 +1,396 @@ +/** + * Copyright (C) 2009 Ubixum, Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + **/ + +//#define DEBUG_SETUPDAT + +#ifdef DEBUG_SETUPDAT +#include // NOTE this needs deleted +#else +#define printf(...) +#define NULL (void*)0; +#endif + +#include +#include +#include +#include + + +extern BOOL handle_vendorcommand(BYTE cmd); +extern BOOL handle_set_configuration(BYTE cfg); +extern BOOL handle_get_interface(BYTE ifc, BYTE * alt_ifc); +extern BOOL handle_set_interface(BYTE ifc, BYTE alt_ifc); +extern BYTE handle_get_configuration(); +extern BOOL handle_set_configuration(BYTE cfg); +extern void handle_reset_ep(BYTE ep); + +/** + * Predefs for handlers + **/ + + +// GET_STATUS, +BOOL handle_get_status(); +// CLEAR_FEATURE, +BOOL handle_clear_feature(); + // 0x02 is reserved +// SET_FEATURE=0x03, +BOOL handle_set_feature(); + // 0x04 is reserved +// SET_ADDRESS=0x05, // this is handled by EZ-USB core unless RENUM=0 +// GET_DESCRIPTOR, +void handle_get_descriptor(); +// SET_DESCRIPTOR, +// GET_CONFIGURATION, // handled by callback +// SET_CONFIGURATION, // handled by callback +// GET_INTERFACE, // handled by callback +// SET_INTERFACE, // handled by callback +// SYNC_FRAME // not yet implemented + +/* + TRM 2.2 + Setup Token -> + data transfer -> + handshake +*/ + +void +handle_setupdata() +{ + //printf ( "Handle setupdat: %02x\n", SETUPDAT[1] ); + + switch (SETUPDAT[1]) { + + case GET_STATUS: + if (!handle_get_status()) + STALLEP0(); + break; + case CLEAR_FEATURE: + if (!handle_clear_feature()) { + STALLEP0(); + } + break; + case SET_FEATURE: + if (!handle_set_feature()) { + STALLEP0(); + } + break; + case GET_DESCRIPTOR: + handle_get_descriptor(); + break; + case GET_CONFIGURATION: + EP0BUF[0] = handle_get_configuration(); + EP0BCH = 0; + EP0BCL = 1; + break; + case SET_CONFIGURATION: + // user callback + if (!handle_set_configuration(SETUPDAT[2])) { + STALLEP0(); + } + break; + case GET_INTERFACE: + { + BYTE alt_ifc; + if (!handle_get_interface(SETUPDAT[4], &alt_ifc)) { + STALLEP0(); + } else { + EP0BUF[0] = alt_ifc; + EP0BCH = 0; + EP0BCL = 1; + } + } + break; + case SET_INTERFACE: + // user callback + if (!handle_set_interface(SETUPDAT[4], SETUPDAT[2])) { + STALLEP0(); + } + break; + default: + if (!handle_vendorcommand(SETUPDAT[1])) { + printf("Unhandled Vendor Command: %02x\n", SETUPDAT[1]); + STALLEP0(); + } + + + } + + // do the handshake + EP0CS |= bmHSNAK; + +} + +__xdata BYTE * +ep_addr(BYTE ep) +{ // bit 8 of ep_num is the direction + BYTE ep_num = ep & ~0x80; // mask the direction + switch (ep_num) { + case 0: + return &EP0CS; + case 1: + return ep & 0x80 ? &EP1INCS : &EP1OUTCS; + case 2: + return &EP2CS; + case 4: + return &EP4CS; + case 6: + return &EP6CS; + case 8: + return &EP8CS; + default: + return NULL; + } +} + + +// Get status has three request types +#define GS_DEVICE 0x80 +#define GS_INTERFACE 0x81 +#define GS_ENDPOINT 0x82 + + +volatile BOOL self_powered = FALSE; +volatile BOOL remote_wakeup_allowed = FALSE; + +BOOL +handle_get_status() +{ + + switch (SETUPDAT[0]) { + +// case 0: // sometimes we get a 0 status too + case GS_INTERFACE: + EP0BUF[0] = 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + case GS_DEVICE: + + // two byte response + // byte 0 bit 0 = self powered bit 1 = remote wakeup + EP0BUF[0] = (remote_wakeup_allowed << 1) | self_powered; + // byte 1 = 0 + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + break; + case GS_ENDPOINT: + { + __xdata BYTE *pep = ep_addr(SETUPDAT[4]); + if (!pep) + return FALSE; + // byte 0 bit 0 = stall bit + EP0BUF[0] = *pep & bmEPSTALL ? 1 : 0; + EP0BUF[1] = 0; + EP0BCH = 0; + EP0BCL = 2; + } + break; + default: + printf("Unexpected Get Status: %02x\n", SETUPDAT[0]); + return FALSE; + + + } + return TRUE; +} + + +#define GF_DEVICE 0 +#define GF_ENDPOINT 2 + +BOOL +handle_clear_feature() +{ + //printf ( "Clear Feature\n" ); + switch (SETUPDAT[0]) { + case GF_DEVICE: + if (SETUPDAT[2] == 1) { + remote_wakeup_allowed = FALSE; + break; + } + return FALSE; + case GF_ENDPOINT: + if (SETUPDAT[2] == 0) { // ep stall feature + __xdata BYTE *pep = ep_addr(SETUPDAT[4]); + printf("unstall endpoint %02X\n", SETUPDAT[4]); + *pep &= ~bmEPSTALL; + RESETTOGGLE(SETUPDAT[4]); + } else { + printf("unsupported ep feature %02x", SETUPDAT[2]); + return FALSE; + } + + break; + default: + return handle_vendorcommand(SETUPDAT[1]); + } + return TRUE; +} + +BOOL +handle_set_feature() +{ + printf("Set Feature %02x\n", SETUPDAT[0]); + switch (SETUPDAT[0]) { + case GF_DEVICE: + if (SETUPDAT[2] == 2) + break; // this is TEST_MODE and we simply need to return the handshake + if (SETUPDAT[2] == 1) { + remote_wakeup_allowed = TRUE; + break; + } + return FALSE; + case GF_ENDPOINT: + if (SETUPDAT[2] == 0) { // ep stall feature + // set TRM 2.3.2 + // stall and endpoint + __xdata BYTE *pep = ep_addr(SETUPDAT[4]); + printf("Stall ep %d\n", SETUPDAT[4]); + if (!pep) { + return FALSE; + } + + *pep |= bmEPSTALL; + // should now reset data toggles + // write ep+dir to TOGCTL + RESETTOGGLE(SETUPDAT[4]); + // restore stalled ep to default condition + // NOTE + //handle_reset_ep(SETUPDAT[4]); + + } else { + printf("unsupported ep feature %02x\n", SETUPDAT[2]); + return FALSE; + } + break; + default: + return handle_vendorcommand(SETUPDAT[1]); + } + return TRUE; +} + +/* these are devined in dscr.asm + and need to be customized then + linked in by the firmware manually */ +extern __code WORD dev_dscr; +extern __code WORD dev_qual_dscr; +extern __code WORD highspd_dscr; +extern __code WORD fullspd_dscr; +extern __code WORD dev_strings; + +WORD pDevConfig = (WORD) & fullspd_dscr; +WORD pOtherConfig = (WORD) & highspd_dscr; + +void +handle_hispeed(BOOL highspeed) +{ + __critical { + printf("Hi Speed or reset Interrupt\n"); + if (highspeed) { + pDevConfig = (WORD) & highspd_dscr; + pOtherConfig = (WORD) & fullspd_dscr; + } else { + pDevConfig = (WORD) & fullspd_dscr; + pOtherConfig = (WORD) & highspd_dscr; + } + } +} + +/** + * Handle: + * Device Descriptor + * Device Qualifier + * Configuration + * String + * Other-Speed + **/ +void +handle_get_descriptor() +{ + //printf ( "Get Descriptor\n" ); + + switch (SETUPDAT[3]) { + case DSCR_DEVICE_TYPE: + printf("Get Device Config\n"); + SUDPTRH = MSB((WORD) & dev_dscr); + SUDPTRL = LSB((WORD) & dev_dscr); + break; + case DSCR_CONFIG_TYPE: + // get the config descriptor + printf("Get Config Descriptor\n"); + SUDPTRH = MSB(pDevConfig); + SUDPTRL = LSB(pDevConfig); + break; + case DSCR_STRING_TYPE: + //printf ( "Get String Descriptor idx: %d\n", SETUPDAT[2] ); + { + STRING_DSCR *pStr = (STRING_DSCR *) & dev_strings; + // pStr points to string 0 + BYTE idx = SETUPDAT[2]; + BYTE cur = 0; // current check + do { + if (idx == cur++) + break; + //printf ( "Length of pStr: %d\n", pStr->dsc_len ); + //printf ( "pstr: %04x to ", pStr ); + pStr = + (STRING_DSCR *) ((BYTE *) pStr + + pStr->dsc_len); + //printf ( "%04x\n" , pStr ); + if (pStr->dsc_type != DSCR_STRING_TYPE) + pStr = NULL; + } while (pStr && cur <= idx); + + if (pStr) { + /* BYTE i; + //printf ( "found str: '"); + for (i=0;idsc_len-2;++i) { + printf ( i%2==0?"%c":"%02x", *((BYTE*)(&pStr->pstr)+i)); + } printf ( "\n"); */ + + SUDPTRH = MSB((WORD) pStr); + SUDPTRL = LSB((WORD) pStr); + //SUDPTRH = MSB((WORD)&dev_strings); + //SUDPTRL = LSB((WORD)&dev_strings); + } else { + STALLEP0(); + } + + } + + break; + case DSCR_DEVQUAL_TYPE: + printf("Get Device Qualifier Descriptor\n"); + // assumes this is a high speed capable device + SUDPTRH = MSB((WORD) & dev_qual_dscr); + SUDPTRL = LSB((WORD) & dev_qual_dscr); + break; + case DSCR_OTHERSPD_TYPE: + printf("Other Speed Descriptor\n"); + SUDPTRH = MSB(pOtherConfig); + SUDPTRL = LSB(pOtherConfig); + break; + default: + printf("Unhandled Get Descriptor: %02x\n", SETUPDAT[3]); + STALLEP0(); + } + +} diff --git a/firmware/lib/usbav.a51 b/firmware/lib/usbav.a51 new file mode 100644 index 0000000..ce956d9 --- /dev/null +++ b/firmware/lib/usbav.a51 @@ -0,0 +1,125 @@ +; Copyright (C) 2010 Ubixum, Inc. +; +; This library is free software; you can redistribute it and/or +; modify it under the terms of the GNU Lesser General Public +; License as published by the Free Software Foundation; either +; version 2.1 of the License, or (at your option) any later version. +; +; This library is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +; Lesser General Public License for more details. +; +; You should have received a copy of the GNU Lesser General Public +; License along with this library; if not, write to the Free Software +; Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + +.module INT2AV ; jump table for usb auto vector + +.globl _INT2JT ; defined as global so this assembly gets included in project + +.area INT2AV (ABS,OVR) +.org 0x43 ; this is where USBINT ( interrupt 8 ) jumps to +_INT2AV = #. + 2 ; two bytes for ljmp (auto set by INT2IVEC) + ljmp _INT2JT + +; INT2 Jump Table + +.area INT2JT ( CODE ) +;.org 0x1A00 ; needs to be on a page boundary + +_INT2JT: + ljmp _sudav_isr + .db 0 + ljmp _sof_isr + .db 0 + ljmp _sutok_isr + .db 0 + ljmp _suspend_isr + .db 0 + ljmp _usbreset_isr + .db 0 + ljmp _hispeed_isr + .db 0 + ljmp _ep0ack_isr + .db 0 + ljmp _spare_isr + .db 0 + ljmp _ep0in_isr + .db 0 + ljmp _ep0out_isr + .db 0 + ljmp _ep1in_isr + .db 0 + ljmp _ep1out_isr + .db 0 + ljmp _ep2_isr + .db 0 + ljmp _ep4_isr + .db 0 + ljmp _ep6_isr + .db 0 + ljmp _ep8_isr + .db 0 + ljmp _ibn_isr + .db 0 + ljmp _spare_isr + .db 0 + ljmp _ep0ping_isr + .db 0 + ljmp _ep1ping_isr + .db 0 + ljmp _ep2ping_isr + .db 0 + ljmp _ep4ping_isr + .db 0 + ljmp _ep6ping_isr + .db 0 + ljmp _ep8ping_isr + .db 0 + ljmp _errlimit_isr + .db 0 + ljmp _spare_isr + .db 0 + ljmp _spare_isr + .db 0 + ljmp _spare_isr + .db 0 + ljmp _ep2isoerr_isr + .db 0 + ljmp _ep4isoerr_isr + .db 0 + ljmp _ep6isoerr_isr + .db 0 + ljmp _ep8isoerr_isr + .db 0 +; INT4JT + ljmp _ep2pf_isr + .db 0 + ljmp _ep4pf_isr + .db 0 + ljmp _ep6pf_isr + .db 0 + ljmp _ep8pf_isr + .db 0 + ljmp _ep2ef_isr + .db 0 + ljmp _ep4ef_isr + .db 0 + ljmp _ep6ef_isr + .db 0 + ljmp _ep8ef_isr + .db 0 + ljmp _ep2ff_isr + .db 0 + ljmp _ep4ff_isr + .db 0 + ljmp _ep6ff_isr + .db 0 + ljmp _ep8ff_isr + .db 0 + ljmp _gpifdone_isr + .db 0 + ljmp _gpifwf_isr + .db 0 + diff --git a/fpga/f2p/f2p_master.vhd b/fpga/f2p/f2p_master.vhd new file mode 100644 index 0000000..e593ef2 --- /dev/null +++ b/fpga/f2p/f2p_master.vhd @@ -0,0 +1,220 @@ +-- --------------------------------------------------------------- +-- (2013) Benjamin Krill +-- --------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity f2p_master is + port ( + clk : in std_logic; + rst_n : in std_logic; + debug : out std_logic_vector(7 downto 0); + + -- cypress interface + usb_clk : in std_logic; + usb_flag_a_i : in std_logic; -- programmable flag + usb_flag_b_i : in std_logic; -- full flag + usb_flag_c_i : in std_logic; -- empty flag + usb_cs_o : out std_logic; -- put to GND, not need for this application + usb_oe_o : out std_logic; -- active_low + usb_rd_o : out std_logic; -- active_low + usb_wr_o : out std_logic; -- active_low + usb_pktend_o : out std_logic; -- active_low + usb_adr_o : out std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8 + usb_dat_io : inout std_logic_vector(7 downto 0); + + -- write/read pipe + wp_wr_i : in std_logic; + wp_full_o : out std_logic; + wp_eop_i : in std_logic; + wp_dat_i : in std_logic_vector(31 downto 0); + rp_rd_i : in std_logic; + rp_empty_o : out std_logic; + rp_dat_o : out std_logic_vector(31 downto 0) + ); +end f2p_master; + +architecture f2p_master of f2p_master is + constant EP2 : std_logic_vector(1 downto 0) := "00"; + constant EP4 : std_logic_vector(1 downto 0) := "01"; + constant EP6 : std_logic_vector(1 downto 0) := "10"; + constant EP8 : std_logic_vector(1 downto 0) := "11"; + signal rst : std_logic; + + type sm_usb_t is (IDLE, RD_ADDRESS, RD_READ, WR_ADDRESS, WR_WRITE); + signal sm_usb : sm_usb_t; + signal usb_oe : std_logic; + signal usb_rd : std_logic; + signal usb_wr : std_logic; + signal usb_wr_cnt : unsigned(25 downto 0); + signal usb_pktend : std_logic; + signal usb_dat_out : std_logic_vector(7 downto 0); + signal usb_dat_in : std_logic_vector(7 downto 0); + + signal usb_adr : std_logic; + signal uftx_din : std_logic_vector(31 downto 0); + signal uftx_wren : std_logic; + signal uftx_rden : std_logic; + signal uftx_dout : std_logic_vector( 7 downto 0); + signal uftx_full : std_logic; + signal uftx_empty : std_logic; + signal ufrx_din : std_logic_vector( 7 downto 0); + signal ufrx_wren : std_logic; + signal ufrx_rden : std_logic; + signal ufrx_dout : std_logic_vector(31 downto 0); + signal ufrx_full : std_logic; + signal ufrx_empty : std_logic; + signal uftxfin_cnt : unsigned(23 downto 0); + signal uftxfin_din : std_logic_vector(23 downto 0); + signal uftxfin_wren : std_logic; + signal uftxfin_rden : std_logic; + signal uftxfin_dout : std_logic_vector(23 downto 0); + signal uftxfin_full : std_logic; + signal uftxfin_empty : std_logic; +begin + rst <= not rst_n; + -- EP2 from host, EP6 to host + -- during IDLE monitor EF and read data from fifo + usb_adr_o <= EP2 when (usb_adr = '0' or sm_usb = RD_ADDRESS) and sm_usb /= WR_ADDRESS else EP6; + usb_cs_o <= '0'; + usb_oe_o <= not usb_oe; + usb_rd_o <= not usb_rd; + usb_wr_o <= not usb_wr; + usb_pktend_o <= not usb_pktend; + + usb_dat_io <= (others => 'Z') when usb_oe = '1' else usb_dat_out; + usb_dat_in <= usb_dat_io when usb_oe = '1' else (others => '0'); + usb_oe <= '1' when (usb_adr = '0' or sm_usb = RD_ADDRESS) and sm_usb /= WR_ADDRESS else '0'; + usb_rd <= '1' when sm_usb = RD_READ and usb_flag_c_i = '1' else '0'; + usb_wr <= '1' when sm_usb = WR_WRITE and usb_flag_b_i = '1' and uftx_empty = '0' else '0'; + usb_pktend <= '1' when sm_usb = WR_WRITE and uftxfin_empty = '0' + and to_integer(usb_wr_cnt(25 downto 2)) = to_integer(unsigned(uftxfin_dout)) else '0'; + + process (usb_clk, rst_n) + begin + if rst_n = '0' then + sm_usb <= IDLE; + usb_adr <= '0'; + usb_wr_cnt <= "00" & x"000001"; + elsif rising_edge(usb_clk) then + if usb_pktend = '1' then + usb_wr_cnt <= "00" & x"000001"; + elsif usb_wr = '1' then + usb_wr_cnt <= usb_wr_cnt + "1"; + end if; + + -- EP address switch + if sm_usb = RD_ADDRESS then + usb_adr <= '0'; + elsif sm_usb = WR_ADDRESS then + usb_adr <= '1'; + end if; + + case sm_usb is + when IDLE => + if uftx_empty = '0' then + sm_usb <= WR_ADDRESS; + elsif ufrx_full = '0' then + sm_usb <= RD_ADDRESS; + end if; + + when RD_ADDRESS => + sm_usb <= RD_READ; + + when RD_READ => + sm_usb <= IDLE; + if usb_flag_c_i = '1' and ufrx_full = '0' then -- fifo not empty + sm_usb <= RD_READ; + end if; + + when WR_ADDRESS => + sm_usb <= WR_WRITE; + + when WR_WRITE => + if usb_pktend = '1' then + sm_usb <= IDLE; + end if; + + end case; + end if; + end process; + + -- -------------------------------------------------------------------- + -- USB RX FIFO + -- -------------------------------------------------------------------- + rp_dat_o <= ufrx_dout(7 downto 0) & ufrx_dout(15 downto 8) & ufrx_dout(23 downto 16) & ufrx_dout(31 downto 24); + rp_empty_o <= ufrx_empty; + ufrx_rden <= rp_rd_i; + ufrx_din <= usb_dat_in; + ufrx_wren <= usb_rd; + usb_fifo_rx_0: entity work.usb_fifo_rx + port map ( + rst => rst, + + wr_clk => usb_clk, + wr_en => ufrx_wren, + din => ufrx_din, + full => ufrx_full, + + rd_clk => clk, + rd_en => ufrx_rden, + dout => ufrx_dout, + empty => ufrx_empty + ); + + -- -------------------------------------------------------------------- + -- USB TX FIFO + -- -------------------------------------------------------------------- + uftx_din <= wp_dat_i; + uftx_wren <= wp_wr_i; + wp_full_o <= uftx_full; + uftx_rden <= usb_wr; + usb_dat_out <= uftx_dout; + usb_fifo_tx_0: entity work.usb_fifo_tx + port map ( + rst => rst, + + wr_clk => clk, + wr_en => uftx_wren, + din => uftx_din, + full => uftx_full, + + rd_clk => usb_clk, + rd_en => uftx_rden, + dout => uftx_dout, + empty => uftx_empty + ); + + process (clk, rst_n) + begin + if rst_n = '0' then + uftxfin_cnt <= x"000001"; + elsif rising_edge(clk) then + if uftxfin_wren = '1' then + uftxfin_cnt <= x"000001"; + elsif wp_wr_i = '1' then + uftxfin_cnt <= uftxfin_cnt + "1"; + end if; + end if; + end process; + + uftxfin_wren <= wp_wr_i and wp_eop_i and not uftxfin_full; + uftxfin_din <= std_logic_vector(uftxfin_cnt); + uftxfin_rden <= usb_pktend and not uftxfin_empty; + usb_fifo_txfin_0: entity work.usb_fifo_tx_fin + port map ( + rst => rst, + + wr_clk => clk, + wr_en => uftxfin_wren, + din => uftxfin_din, + full => uftxfin_full, + + rd_clk => usb_clk, + rd_en => uftxfin_rden, + dout => uftxfin_dout, + empty => uftxfin_empty + ); + +end f2p_master; diff --git a/fpga/f2p/f2p_strm_top.vhd b/fpga/f2p/f2p_strm_top.vhd new file mode 100644 index 0000000..232618e --- /dev/null +++ b/fpga/f2p/f2p_strm_top.vhd @@ -0,0 +1,151 @@ +-- --------------------------------------------------------------- +-- (2013) Benjamin Krill +-- --------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.strm_package.all; + +entity f2p_strm_top is + generic ( STRM_OUT_SLV_CNT : integer := 1 ); + port ( + clk : in std_logic; + rst_n : in std_logic; + debug : out std_logic_vector(7 downto 0); + + -- cypress interface + usb_clk : in std_logic; + usb_flag_a_i : in std_logic; -- programmable flag + usb_flag_b_i : in std_logic; -- full flag + usb_flag_c_i : in std_logic; -- empty flag + usb_cs_o : out std_logic; -- put to GND, not need for this application + usb_oe_o : out std_logic; -- active_low + usb_rd_o : out std_logic; -- active_low + usb_wr_o : out std_logic; -- active_low + usb_pktend_o : out std_logic; -- active_low + usb_adr_o : out std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8 + usb_dat_io : inout std_logic_vector(7 downto 0); + + -- streaming bus + strm_in_data_o : out std_logic_vector(31 downto 0); + strm_in_eop_o : out std_logic; + strm_in_en_o : out std_logic; + strm_in_busy_i : in std_logic; + strm_out_slv_reqs_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); + strm_out_slv_busy_o : out std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); + strm_out_data_i : in strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0); + strm_out_eop_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); + strm_out_en_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0) + ); +end f2p_strm_top; + +architecture f2p_strm_top of f2p_strm_top is + signal rp_read_cnt : unsigned(23 downto 0); + signal strm_data : std_logic_vector(31 downto 0); + signal strm_eop : std_logic; + signal strm_en : std_logic; + + signal wp_wr : std_logic; + signal wp_full : std_logic; + signal wp_eop : std_logic; + signal wp_dat : std_logic_vector(31 downto 0); + signal rp_rd : std_logic; + signal rp_empty : std_logic; + signal rp_dat : std_logic_vector(31 downto 0); + + signal rrarb_req : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); + signal rrarb_ack : std_logic; + signal rrarb_grant : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); + signal strm_out_data_mux : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0); +begin + strm_in_data_o <= strm_data; + strm_in_eop_o <= strm_eop; + strm_in_en_o <= strm_en; + + f2p_master_0: entity work.f2p_master + port map ( + clk => clk, + rst_n => rst_n, + debug => debug, + + -- cypress interface + usb_clk => usb_clk, + usb_flag_a_i => usb_flag_a_i, + usb_flag_b_i => usb_flag_b_i, + usb_flag_c_i => usb_flag_c_i, + usb_cs_o => usb_cs_o, + usb_oe_o => usb_oe_o, + usb_rd_o => usb_rd_o, + usb_wr_o => usb_wr_o, + usb_pktend_o => usb_pktend_o, + usb_adr_o => usb_adr_o, + usb_dat_io => usb_dat_io, + + -- write/read pipe + wp_wr_i => wp_wr, + wp_full_o => wp_full, + wp_dat_i => wp_dat, + wp_eop_i => wp_eop, + rp_rd_i => rp_rd, + rp_empty_o => rp_empty, + rp_dat_o => rp_dat + ); + + -- ------------------------------------------------------------------ + -- USB FIFO SLAVES + -- ------------------------------------------------------------------ + -- FROM USB + rp_rd <= not rp_empty and not strm_in_busy_i; + process (clk, rst_n) + begin + if rst_n = '0' then + rp_read_cnt <= (others => '0'); + strm_data <= (others => '0'); + strm_en <= '0'; + strm_eop <= '0'; + elsif rising_edge(clk) then + -- get next packet and stream to slaves + if rp_rd = '1' then + if rp_read_cnt /= x"000000" then + rp_read_cnt <= rp_read_cnt - "1"; + else + rp_read_cnt <= unsigned(rp_dat(STRM_LENGTH_HIGH downto STRM_LENGTH_LOW)); + end if; + end if; + + -- stream data + strm_en <= '0'; + strm_eop <= '0'; + if rp_rd = '1' then + strm_en <= '1'; + strm_data <= rp_dat; + if rp_read_cnt = x"000001" then + strm_eop <= '1'; + end if; + end if; + end if; + end process; + + -- TO USB - strm arbiter + rrarb_req <= strm_out_slv_reqs_i and not rrarb_grant; + rrarb_ack <= '1' when (strm_out_eop_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0'; + rrarb_strm_out_0: entity work.rrarbiter + generic map ( CNT => STRM_OUT_SLV_CNT ) + port map ( + clk => clk, + rst_n => rst_n, + req => rrarb_req, + ack => rrarb_ack, + grant => rrarb_grant + ); + strm_out_slv_busy_o <= not rrarb_grant or (STRM_OUT_SLV_CNT-1 downto 0 => wp_full); + + strm_out_data_mux(0) <= strm_out_data_i(0) and (31 downto 0 => rrarb_grant(0)); + dc: for I in 1 to STRM_OUT_SLV_CNT-1 generate + strm_out_data_mux(I) <= strm_out_data_mux(I-1) or (strm_out_data_i(I) and (31 downto 0 => rrarb_grant(I))); + end generate dc; + wp_dat <= strm_out_data_mux(STRM_OUT_SLV_CNT-1); + wp_wr <= '1' when (strm_out_en_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0'; + wp_eop <= '1' when (strm_out_eop_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0'; + +end f2p_strm_top; diff --git a/fpga/f2p/strm_package.vhd b/fpga/f2p/strm_package.vhd new file mode 100644 index 0000000..a755135 --- /dev/null +++ b/fpga/f2p/strm_package.vhd @@ -0,0 +1,47 @@ +-- --------------------------------------------------------------- +-- (2013) Benjamin Krill +-- --------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- GENERAL PKT FORMAT +-- -------------------------------------------------------- +-- Type (4bit) +-- Plength (7bit) data length (0 = 0byte, 0x7f = 127 * 4byte) +-- 31 16|15 0 +-- header |Type ________|___PLenght______| +-- data |... type defined data/fields ... | +-- +-- DDR2 WRITE TYPE FORMAT +-- -------------------------------------------------------- +-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned +-- data | .... data .... | +-- +-- DDR2 READ TYPE FORMAT +-- -------------------------------------------------------- +-- header0 |0 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned +-- header1 | |_______SIZE_____| -- SIZE in 4byte to read + +package strm_package is + constant STRM_TYPE_HIGH : integer := 31; + constant STRM_TYPE_LOW : integer := 28; + constant STRM_LENGTH_HIGH : integer := 23; + constant STRM_LENGTH_LOW : integer := 0; + + -- SLAVE TYPE IDs + constant STRM_TYPE_DDR2 : std_logic_vector(3 downto 0) := "0001"; + + -- DDR2 + constant STRM_DDR2_BUS : integer := 0; + constant STRM_DDR2_ADR_HIGH : integer := 27; + constant STRM_DDR2_ADR_LOW : integer := 0; + constant STRM_DDR2_ACCESS : integer := 31; + constant STRM_DDR2_ACC_WRITE : std_logic := '1'; + constant STRM_DDR2_ACC_READ : std_logic := '0'; + constant STRM_DDR2_SIZE_HIGH : integer := 23; + constant STRM_DDR2_SIZE_LOW : integer := 0; + + -- bus types + type strm_dat_bus_t is array(natural range <>) of std_logic_vector(31 downto 0); +end package; diff --git a/fpga/misc/rrarbiter.vhd b/fpga/misc/rrarbiter.vhd new file mode 100644 index 0000000..4331d12 --- /dev/null +++ b/fpga/misc/rrarbiter.vhd @@ -0,0 +1,55 @@ +-- --------------------------------------------------------------------------- +-- (2009) Benjamin Krill +-- +-- "THE BEER-WARE LICENSE" (Revision 42): +-- ben@codiert.org wrote this file. As long as you retain this notice you can +-- do whatever you want with this stuff. If we meet some day, and you think +-- this stuff is worth it, you can buy me a beer in return Benjamin Krill +-- --------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity rrarbiter is + generic ( CNT : integer := 7 ); + port ( + clk : in std_logic; + rst_n : in std_logic; + + req : in std_logic_vector(CNT-1 downto 0); + ack : in std_logic; + grant : out std_logic_vector(CNT-1 downto 0) + ); +end; + +architecture rrarbiter of rrarbiter is + signal grant_q : std_logic_vector(CNT-1 downto 0); + signal pre_req : std_logic_vector(CNT-1 downto 0); + signal sel_gnt : std_logic_vector(CNT-1 downto 0); + signal isol_lsb : std_logic_vector(CNT-1 downto 0); + signal mask_pre : std_logic_vector(CNT-1 downto 0); + signal win : std_logic_vector(CNT-1 downto 0); +begin + grant <= grant_q; + mask_pre <= req and not (std_logic_vector(unsigned(pre_req) - 1) or pre_req); -- Mask off previous winners + sel_gnt <= mask_pre and std_logic_vector(unsigned(not(mask_pre)) + 1); -- Select new winner + isol_lsb <= req and std_logic_vector(unsigned(not(req)) + 1); -- Isolate least significant set bit. + win <= sel_gnt when mask_pre /= (CNT-1 downto 0 => '0') else isol_lsb; + + process (clk,rst_n) + begin + if rst_n = '0' then + pre_req <= (others => '0'); + grant_q <= (others => '0'); + elsif rising_edge(clk) then + grant_q <= grant_q; + pre_req <= pre_req; + if grant_q = (CNT-1 downto 0 => '0') or ack = '1' then + if win /= (CNT-1 downto 0 => '0') then + pre_req <= win; + end if; + grant_q <= win; + end if; + end if; + end process; +end rrarbiter; diff --git a/fpga/strm_ddr2/strm_ddr2.vhd b/fpga/strm_ddr2/strm_ddr2.vhd new file mode 100644 index 0000000..827f819 --- /dev/null +++ b/fpga/strm_ddr2/strm_ddr2.vhd @@ -0,0 +1,260 @@ +-- --------------------------------------------------------------- +-- (2013) Benjamin Krill +-- --------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.strm_package.all; + +entity strm_ddr2 is + port ( + clk : in std_logic; + rst_n : in std_logic; + debug : out std_logic_vector( 7 downto 0); + + -- streaming bus + strm_in_data_i : in std_logic_vector(31 downto 0); + strm_in_eop_i : in std_logic; + strm_in_en_i : in std_logic; + strm_in_busy_o : out std_logic; + strm_out_req_o : out std_logic; + strm_out_busy_i : in std_logic; + strm_out_data_o : out std_logic_vector(31 downto 0); + strm_out_eop_o : out std_logic; + strm_out_en_o : out std_logic; + + -- memory interface + ddr2_cmd_en_o : out std_logic; + ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0); + ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0); + ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0); + ddr2_cmd_empty_i : in std_logic; + ddr2_cmd_full_i : in std_logic; + ddr2_wr_en_o : out std_logic; + ddr2_wr_mask_o : out std_logic_vector( 3 downto 0); + ddr2_wr_data_o : out std_logic_vector(31 downto 0); + ddr2_wr_full_i : in std_logic; + ddr2_wr_empty_i : in std_logic; + ddr2_wr_count_i : in std_logic_vector( 6 downto 0); + ddr2_wr_underrun_i : in std_logic; + ddr2_wr_error_i : in std_logic; + ddr2_rd_en_o : out std_logic; + ddr2_rd_data_i : in std_logic_vector(31 downto 0); + ddr2_rd_full_i : in std_logic; + ddr2_rd_empty_i : in std_logic; + ddr2_rd_count_i : in std_logic_vector( 6 downto 0); + ddr2_rd_overflow_i : in std_logic; + ddr2_rd_error_i : in std_logic + ); +end strm_ddr2; + +architecture strm_ddr2 of strm_ddr2 is + type sm_strm_t is (IDLE, DDR2_ADDRESS, RECV, DDR2_READ, DDR2_RD_SIZE, DDR2_RD_WAIT, DDR2_RD_ADJ, DDR2_RD_REQ, IGNORE); + signal sm_strm : sm_strm_t; + signal rst : std_logic; + signal strm_in_data : std_logic_vector(31 downto 0); + signal strm_in_eop : std_logic; + signal strm_in_en : std_logic; + signal strm_in_busy : std_logic; + signal strm_type_vld : std_logic; + signal strm_size : unsigned(23 downto 0); + signal ddr2_wr_en : std_logic; + signal ddr2_wr_mask : std_logic_vector( 3 downto 0); + signal ddr2_wr_data : std_logic_vector(31 downto 0); + signal dw_cnt : unsigned( 7 downto 0); + signal dw_cnt_dec : unsigned( 7 downto 0); + signal ddr2_adr : unsigned(27 downto 0); + signal ddr2_size : unsigned(23 downto 0); + signal ddr2_read_size : unsigned(23 downto 0); + signal ddr2_cmd_en : std_logic; + signal ddr2_cmd_instr : std_logic_vector( 2 downto 0); + signal strm_out_size : unsigned(23 downto 0); + signal strm_out_eop : std_logic; + signal strm_out_hdr_en : std_logic; + signal ddr2_rd_en : std_logic; + signal bla_cnt : unsigned(7 downto 0); +begin + rst <= not rst_n; + ddr2_rd_en_o <= ddr2_rd_en; + ddr2_cmd_en_o <= ddr2_cmd_en; + ddr2_cmd_instr_o <= ddr2_cmd_instr; + ddr2_wr_en_o <= ddr2_wr_en; + ddr2_wr_mask_o <= ddr2_wr_mask; + ddr2_wr_data_o <= ddr2_wr_data; + strm_in_data <= strm_in_data_i; + strm_in_eop <= strm_in_eop_i; + strm_in_en <= strm_in_en_i; + strm_in_busy_o <= strm_in_busy; + + strm_in_busy <= ddr2_wr_full_i or ddr2_cmd_full_i; + strm_type_vld <= '1' when strm_in_data(STRM_TYPE_HIGH downto STRM_TYPE_LOW) = STRM_TYPE_DDR2 else '0'; + process (clk, rst_n) + begin + if rst_n = '0' then + sm_strm <= IDLE; + strm_size <= (others => '0'); + ddr2_cmd_instr <= (others => '0'); + ddr2_wr_en <= '0'; + ddr2_wr_mask <= (others => '0'); + ddr2_wr_data <= (others => '0'); + dw_cnt <= (others => '0'); + ddr2_adr <= (others => '0'); + ddr2_size <= (others => '0'); + ddr2_read_size <= (others => '0'); + strm_out_size <= (others => '0'); + bla_cnt <= (others => '0'); + strm_out_hdr_en <= '0'; + elsif rising_edge(clk) then + -- STRM SIZE + if sm_strm = IDLE and strm_in_en = '1' then + strm_size <= unsigned(strm_in_data(STRM_LENGTH_HIGH downto STRM_LENGTH_LOW)); + end if; + + -- SAVE DDR2 ADDRESS + if sm_strm = DDR2_ADDRESS and strm_in_en = '1' then + ddr2_adr <= unsigned(strm_in_data(STRM_DDR2_ADR_HIGH downto STRM_DDR2_ADR_LOW)); + elsif ddr2_cmd_en = '1' then + ddr2_adr <= ddr2_adr + x"040"; + end if; + + -- SAVE DDR2 READ SIZE + if sm_strm = DDR2_RD_SIZE and strm_in_en = '1' then + ddr2_size <= unsigned(strm_in_data(STRM_DDR2_SIZE_HIGH downto STRM_DDR2_SIZE_LOW)); + strm_out_size <= unsigned(strm_in_data(STRM_DDR2_SIZE_HIGH downto STRM_DDR2_SIZE_LOW)); + elsif sm_strm = DDR2_RD_REQ and ddr2_cmd_full_i = '0' then + if ddr2_size > x"000040" then + ddr2_size <= ddr2_size - x"40"; + else + ddr2_size <= (others => '0'); + end if; + end if; + + -- DDR2 DW COUNT + if sm_strm = RECV or sm_strm = IDLE then + if strm_in_en = '1' and ddr2_cmd_en = '1' then + dw_cnt <= x"01"; + elsif ddr2_cmd_en = '1' then + dw_cnt <= (others => '0'); + elsif strm_in_en = '1' then + dw_cnt <= dw_cnt + "1"; + end if; + elsif sm_strm = DDR2_RD_ADJ and ddr2_cmd_full_i = '0' then + if ddr2_size > x"000040" then + dw_cnt <= x"40"; + else + dw_cnt <= ddr2_size(7 downto 0); + end if; + elsif strm_out_eop = '1' then + dw_cnt <= (others => '0'); + end if; + + -- DDR2 instruction + if sm_strm = DDR2_ADDRESS and strm_in_en = '1' then + if strm_in_data(STRM_DDR2_ACCESS) = STRM_DDR2_ACC_WRITE then + ddr2_cmd_instr <= "000"; + else + ddr2_cmd_instr <= "001"; + end if; + end if; + + if sm_strm = IDLE then + strm_out_hdr_en <= '1'; + elsif sm_strm = DDR2_RD_WAIT and strm_out_busy_i = '0' then + strm_out_hdr_en <= '0'; + end if; + + -- RECV STATES + case sm_strm is + when IDLE => + if strm_in_en = '1' then + if strm_type_vld = '1' then + sm_strm <= DDR2_ADDRESS; + else + sm_strm <= IGNORE; + end if; + end if; + when DDR2_ADDRESS => + if strm_in_en = '1' then + if strm_in_data(STRM_DDR2_ACCESS) = STRM_DDR2_ACC_WRITE then + sm_strm <= RECV; + else + sm_strm <= DDR2_RD_SIZE; + end if; + end if; + + -- DDR WRITE + when RECV => + if strm_in_eop = '1' and strm_in_en = '1' then + sm_strm <= IDLE; + end if; + + -- DDR READ + when DDR2_RD_SIZE => + if strm_in_en = '1' then + if strm_in_eop = '1' then + sm_strm <= DDR2_RD_ADJ; + else + sm_strm <= IGNORE; + end if; + end if; + when DDR2_RD_ADJ => + if ddr2_cmd_full_i = '0' then + sm_strm <= DDR2_RD_REQ; + end if; + when DDR2_RD_REQ => + sm_strm <= DDR2_RD_WAIT; + when DDR2_RD_WAIT => + if ddr2_rd_empty_i = '0' and strm_out_busy_i = '0' then + sm_strm <= DDR2_READ; + end if; + when DDR2_READ => + if ddr2_rd_empty_i = '1' and ddr2_size /= x"000000" and bla_cnt = dw_cnt(6 downto 0) then + sm_strm <= DDR2_RD_ADJ; + elsif strm_out_eop = '1' then + sm_strm <= IDLE; + end if; + + -- COMMON IGNORE + when IGNORE => + if strm_in_eop = '1' and strm_in_en = '1' then + sm_strm <= IDLE; + end if; + end case; + + -- DDR REGISTERS + ddr2_wr_en <= '0'; + if strm_in_en = '1' and sm_strm = RECV then + ddr2_wr_en <= '1'; + ddr2_wr_mask <= (others => '0'); + ddr2_wr_data <= strm_in_data; + end if; + + if ddr2_cmd_en = '1' then + bla_cnt <= (others => '0'); + elsif ddr2_rd_en = '1' then + bla_cnt <= bla_cnt + "1"; + end if; + + -- STRM OUT REGISTERS + if sm_strm = DDR2_RD_SIZE then + ddr2_read_size <= x"000001"; + elsif ddr2_rd_en = '1' then + ddr2_read_size <= ddr2_read_size + "1"; + end if; + end if; + end process; + + ddr2_cmd_en <= '1' when (sm_strm = RECV and dw_cnt = x"40") or ((sm_strm = DDR2_RD_REQ or sm_strm = IDLE) and dw_cnt /= x"00") else '0'; + dw_cnt_dec <= dw_cnt - "1"; + ddr2_cmd_bl_o <= std_logic_vector(dw_cnt_dec(5 downto 0)); + ddr2_cmd_byte_addr_o <= std_logic_vector(ddr2_adr) & "00"; + + ddr2_rd_en <= not ddr2_rd_empty_i when sm_strm = DDR2_READ else '0'; + strm_out_req_o <= not ddr2_rd_empty_i and strm_out_busy_i when sm_strm = DDR2_RD_WAIT else '0'; + strm_out_en_o <= strm_out_hdr_en when sm_strm = DDR2_RD_WAIT and strm_out_busy_i = '0' else ddr2_rd_en; + strm_out_eop <= ddr2_rd_en when ddr2_read_size >= strm_out_size and sm_strm = DDR2_READ else '0'; + strm_out_eop_o <= strm_out_eop; + strm_out_data_o <= STRM_TYPE_DDR2 & (27 downto 24 => '0') & std_logic_vector(strm_out_size) + when strm_out_hdr_en = '1' else ddr2_rd_data_i; + +end strm_ddr2; diff --git a/fpga/vendor/xilinx/usb_fifo_rx.ngc b/fpga/vendor/xilinx/usb_fifo_rx.ngc new file mode 100644 index 0000000..c6a23f6 --- /dev/null +++ b/fpga/vendor/xilinx/usb_fifo_rx.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/vendor/xilinx/usb_fifo_rx.vhd b/fpga/vendor/xilinx/usb_fifo_rx.vhd new file mode 100644 index 0000000..2369dd0 --- /dev/null +++ b/fpga/vendor/xilinx/usb_fifo_rx.vhd @@ -0,0 +1,283 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2013 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file usb_fifo_rx.vhd when simulating +-- the core, usb_fifo_rx. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY usb_fifo_rx IS + PORT ( + rst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC + ); +END usb_fifo_rx; + +ARCHITECTURE usb_fifo_rx_a OF usb_fifo_rx IS +-- synthesis translate_off +COMPONENT wrapped_usb_fifo_rx + PORT ( + rst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_usb_fifo_rx USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral) + GENERIC MAP ( + c_add_ngc_constraint => 0, + c_application_type_axis => 0, + c_application_type_rach => 0, + c_application_type_rdch => 0, + c_application_type_wach => 0, + c_application_type_wdch => 0, + c_application_type_wrch => 0, + c_axi_addr_width => 32, + c_axi_aruser_width => 1, + c_axi_awuser_width => 1, + c_axi_buser_width => 1, + c_axi_data_width => 64, + c_axi_id_width => 4, + c_axi_ruser_width => 1, + c_axi_type => 0, + c_axi_wuser_width => 1, + c_axis_tdata_width => 64, + c_axis_tdest_width => 4, + c_axis_tid_width => 8, + c_axis_tkeep_width => 4, + c_axis_tstrb_width => 4, + c_axis_tuser_width => 4, + c_axis_type => 0, + c_common_clock => 0, + c_count_type => 0, + c_data_count_width => 12, + c_default_value => "BlankString", + c_din_width => 8, + c_din_width_axis => 1, + c_din_width_rach => 32, + c_din_width_rdch => 64, + c_din_width_wach => 32, + c_din_width_wdch => 64, + c_din_width_wrch => 2, + c_dout_rst_val => "0", + c_dout_width => 32, + c_enable_rlocs => 0, + c_enable_rst_sync => 1, + c_error_injection_type => 0, + c_error_injection_type_axis => 0, + c_error_injection_type_rach => 0, + c_error_injection_type_rdch => 0, + c_error_injection_type_wach => 0, + c_error_injection_type_wdch => 0, + c_error_injection_type_wrch => 0, + c_family => "spartan6", + c_full_flags_rst_val => 1, + c_has_almost_empty => 0, + c_has_almost_full => 0, + c_has_axi_aruser => 0, + c_has_axi_awuser => 0, + c_has_axi_buser => 0, + c_has_axi_rd_channel => 0, + c_has_axi_ruser => 0, + c_has_axi_wr_channel => 0, + c_has_axi_wuser => 0, + c_has_axis_tdata => 0, + c_has_axis_tdest => 0, + c_has_axis_tid => 0, + c_has_axis_tkeep => 0, + c_has_axis_tlast => 0, + c_has_axis_tready => 1, + c_has_axis_tstrb => 0, + c_has_axis_tuser => 0, + c_has_backup => 0, + c_has_data_count => 0, + c_has_data_counts_axis => 0, + c_has_data_counts_rach => 0, + c_has_data_counts_rdch => 0, + c_has_data_counts_wach => 0, + c_has_data_counts_wdch => 0, + c_has_data_counts_wrch => 0, + c_has_int_clk => 0, + c_has_master_ce => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_has_prog_flags_axis => 0, + c_has_prog_flags_rach => 0, + c_has_prog_flags_rdch => 0, + c_has_prog_flags_wach => 0, + c_has_prog_flags_wdch => 0, + c_has_prog_flags_wrch => 0, + c_has_rd_data_count => 0, + c_has_rd_rst => 0, + c_has_rst => 1, + c_has_slave_ce => 0, + c_has_srst => 0, + c_has_underflow => 0, + c_has_valid => 0, + c_has_wr_ack => 0, + c_has_wr_data_count => 0, + c_has_wr_rst => 0, + c_implementation_type => 2, + c_implementation_type_axis => 1, + c_implementation_type_rach => 1, + c_implementation_type_rdch => 1, + c_implementation_type_wach => 1, + c_implementation_type_wdch => 1, + c_implementation_type_wrch => 1, + c_init_wr_pntr_val => 0, + c_interface_type => 0, + c_memory_type => 1, + c_mif_file_name => "BlankString", + c_msgon_val => 0, + c_optimization_mode => 0, + c_overflow_low => 0, + c_preload_latency => 0, + c_preload_regs => 1, + c_prim_fifo_type => "4kx9", + c_prog_empty_thresh_assert_val => 4, + c_prog_empty_thresh_assert_val_axis => 1022, + c_prog_empty_thresh_assert_val_rach => 1022, + c_prog_empty_thresh_assert_val_rdch => 1022, + c_prog_empty_thresh_assert_val_wach => 1022, + c_prog_empty_thresh_assert_val_wdch => 1022, + c_prog_empty_thresh_assert_val_wrch => 1022, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_type => 0, + c_prog_empty_type_axis => 0, + c_prog_empty_type_rach => 0, + c_prog_empty_type_rdch => 0, + c_prog_empty_type_wach => 0, + c_prog_empty_type_wdch => 0, + c_prog_empty_type_wrch => 0, + c_prog_full_thresh_assert_val => 4095, + c_prog_full_thresh_assert_val_axis => 1023, + c_prog_full_thresh_assert_val_rach => 1023, + c_prog_full_thresh_assert_val_rdch => 1023, + c_prog_full_thresh_assert_val_wach => 1023, + c_prog_full_thresh_assert_val_wdch => 1023, + c_prog_full_thresh_assert_val_wrch => 1023, + c_prog_full_thresh_negate_val => 4094, + c_prog_full_type => 0, + c_prog_full_type_axis => 0, + c_prog_full_type_rach => 0, + c_prog_full_type_rdch => 0, + c_prog_full_type_wach => 0, + c_prog_full_type_wdch => 0, + c_prog_full_type_wrch => 0, + c_rach_type => 0, + c_rd_data_count_width => 10, + c_rd_depth => 1024, + c_rd_freq => 1, + c_rd_pntr_width => 10, + c_rdch_type => 0, + c_reg_slice_mode_axis => 0, + c_reg_slice_mode_rach => 0, + c_reg_slice_mode_rdch => 0, + c_reg_slice_mode_wach => 0, + c_reg_slice_mode_wdch => 0, + c_reg_slice_mode_wrch => 0, + c_synchronizer_stage => 2, + c_underflow_low => 0, + c_use_common_overflow => 0, + c_use_common_underflow => 0, + c_use_default_settings => 0, + c_use_dout_rst => 0, + c_use_ecc => 0, + c_use_ecc_axis => 0, + c_use_ecc_rach => 0, + c_use_ecc_rdch => 0, + c_use_ecc_wach => 0, + c_use_ecc_wdch => 0, + c_use_ecc_wrch => 0, + c_use_embedded_reg => 0, + c_use_fifo16_flags => 0, + c_use_fwft_data_count => 0, + c_valid_low => 0, + c_wach_type => 0, + c_wdch_type => 0, + c_wr_ack_low => 0, + c_wr_data_count_width => 12, + c_wr_depth => 4096, + c_wr_depth_axis => 1024, + c_wr_depth_rach => 16, + c_wr_depth_rdch => 1024, + c_wr_depth_wach => 16, + c_wr_depth_wdch => 1024, + c_wr_depth_wrch => 16, + c_wr_freq => 1, + c_wr_pntr_width => 12, + c_wr_pntr_width_axis => 10, + c_wr_pntr_width_rach => 4, + c_wr_pntr_width_rdch => 10, + c_wr_pntr_width_wach => 4, + c_wr_pntr_width_wdch => 10, + c_wr_pntr_width_wrch => 4, + c_wr_response_latency => 1, + c_wrch_type => 0 + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_usb_fifo_rx + PORT MAP ( + rst => rst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty + ); +-- synthesis translate_on + +END usb_fifo_rx_a; diff --git a/fpga/vendor/xilinx/usb_fifo_rx.xco b/fpga/vendor/xilinx/usb_fifo_rx.xco new file mode 100644 index 0000000..56a834f --- /dev/null +++ b/fpga/vendor/xilinx/usb_fifo_rx.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.6 +# Date: Thu Sep 5 11:31:02 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=usb_fifo_rx +CSET data_count=false +CSET data_count_width=12 +CSET disable_timing_violations=true +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=4095 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=4094 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=8 +CSET input_depth=4096 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=32 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=false +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=12 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: cfe320cf diff --git a/fpga/vendor/xilinx/usb_fifo_tx.ngc b/fpga/vendor/xilinx/usb_fifo_tx.ngc new file mode 100644 index 0000000..94d4bc6 --- /dev/null +++ b/fpga/vendor/xilinx/usb_fifo_tx.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/vendor/xilinx/usb_fifo_tx.vhd b/fpga/vendor/xilinx/usb_fifo_tx.vhd new file mode 100644 index 0000000..5d17660 --- /dev/null +++ b/fpga/vendor/xilinx/usb_fifo_tx.vhd @@ -0,0 +1,283 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2013 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file usb_fifo_tx.vhd when simulating +-- the core, usb_fifo_tx. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY usb_fifo_tx IS + PORT ( + rst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC + ); +END usb_fifo_tx; + +ARCHITECTURE usb_fifo_tx_a OF usb_fifo_tx IS +-- synthesis translate_off +COMPONENT wrapped_usb_fifo_tx + PORT ( + rst : IN STD_LOGIC; + wr_clk : IN STD_LOGIC; + rd_clk : IN STD_LOGIC; + din : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + wr_en : IN STD_LOGIC; + rd_en : IN STD_LOGIC; + dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + full : OUT STD_LOGIC; + empty : OUT STD_LOGIC + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_usb_fifo_tx USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral) + GENERIC MAP ( + c_add_ngc_constraint => 0, + c_application_type_axis => 0, + c_application_type_rach => 0, + c_application_type_rdch => 0, + c_application_type_wach => 0, + c_application_type_wdch => 0, + c_application_type_wrch => 0, + c_axi_addr_width => 32, + c_axi_aruser_width => 1, + c_axi_awuser_width => 1, + c_axi_buser_width => 1, + c_axi_data_width => 64, + c_axi_id_width => 4, + c_axi_ruser_width => 1, + c_axi_type => 0, + c_axi_wuser_width => 1, + c_axis_tdata_width => 64, + c_axis_tdest_width => 4, + c_axis_tid_width => 8, + c_axis_tkeep_width => 4, + c_axis_tstrb_width => 4, + c_axis_tuser_width => 4, + c_axis_type => 0, + c_common_clock => 0, + c_count_type => 0, + c_data_count_width => 10, + c_default_value => "BlankString", + c_din_width => 32, + c_din_width_axis => 1, + c_din_width_rach => 32, + c_din_width_rdch => 64, + c_din_width_wach => 32, + c_din_width_wdch => 64, + c_din_width_wrch => 2, + c_dout_rst_val => "0", + c_dout_width => 8, + c_enable_rlocs => 0, + c_enable_rst_sync => 1, + c_error_injection_type => 0, + c_error_injection_type_axis => 0, + c_error_injection_type_rach => 0, + c_error_injection_type_rdch => 0, + c_error_injection_type_wach => 0, + c_error_injection_type_wdch => 0, + c_error_injection_type_wrch => 0, + c_family => "spartan6", + c_full_flags_rst_val => 1, + c_has_almost_empty => 0, + c_has_almost_full => 0, + c_has_axi_aruser => 0, + c_has_axi_awuser => 0, + c_has_axi_buser => 0, + c_has_axi_rd_channel => 0, + c_has_axi_ruser => 0, + c_has_axi_wr_channel => 0, + c_has_axi_wuser => 0, + c_has_axis_tdata => 0, + c_has_axis_tdest => 0, + c_has_axis_tid => 0, + c_has_axis_tkeep => 0, + c_has_axis_tlast => 0, + c_has_axis_tready => 1, + c_has_axis_tstrb => 0, + c_has_axis_tuser => 0, + c_has_backup => 0, + c_has_data_count => 0, + c_has_data_counts_axis => 0, + c_has_data_counts_rach => 0, + c_has_data_counts_rdch => 0, + c_has_data_counts_wach => 0, + c_has_data_counts_wdch => 0, + c_has_data_counts_wrch => 0, + c_has_int_clk => 0, + c_has_master_ce => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_has_prog_flags_axis => 0, + c_has_prog_flags_rach => 0, + c_has_prog_flags_rdch => 0, + c_has_prog_flags_wach => 0, + c_has_prog_flags_wdch => 0, + c_has_prog_flags_wrch => 0, + c_has_rd_data_count => 0, + c_has_rd_rst => 0, + c_has_rst => 1, + c_has_slave_ce => 0, + c_has_srst => 0, + c_has_underflow => 0, + c_has_valid => 0, + c_has_wr_ack => 0, + c_has_wr_data_count => 0, + c_has_wr_rst => 0, + c_implementation_type => 2, + c_implementation_type_axis => 1, + c_implementation_type_rach => 1, + c_implementation_type_rdch => 1, + c_implementation_type_wach => 1, + c_implementation_type_wdch => 1, + c_implementation_type_wrch => 1, + c_init_wr_pntr_val => 0, + c_interface_type => 0, + c_memory_type => 1, + c_mif_file_name => "BlankString", + c_msgon_val => 1, + c_optimization_mode => 0, + c_overflow_low => 0, + c_preload_latency => 0, + c_preload_regs => 1, + c_prim_fifo_type => "1kx36", + c_prog_empty_thresh_assert_val => 4, + c_prog_empty_thresh_assert_val_axis => 1022, + c_prog_empty_thresh_assert_val_rach => 1022, + c_prog_empty_thresh_assert_val_rdch => 1022, + c_prog_empty_thresh_assert_val_wach => 1022, + c_prog_empty_thresh_assert_val_wdch => 1022, + c_prog_empty_thresh_assert_val_wrch => 1022, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_type => 0, + c_prog_empty_type_axis => 0, + c_prog_empty_type_rach => 0, + c_prog_empty_type_rdch => 0, + c_prog_empty_type_wach => 0, + c_prog_empty_type_wdch => 0, + c_prog_empty_type_wrch => 0, + c_prog_full_thresh_assert_val => 1021, + c_prog_full_thresh_assert_val_axis => 1023, + c_prog_full_thresh_assert_val_rach => 1023, + c_prog_full_thresh_assert_val_rdch => 1023, + c_prog_full_thresh_assert_val_wach => 1023, + c_prog_full_thresh_assert_val_wdch => 1023, + c_prog_full_thresh_assert_val_wrch => 1023, + c_prog_full_thresh_negate_val => 1020, + c_prog_full_type => 0, + c_prog_full_type_axis => 0, + c_prog_full_type_rach => 0, + c_prog_full_type_rdch => 0, + c_prog_full_type_wach => 0, + c_prog_full_type_wdch => 0, + c_prog_full_type_wrch => 0, + c_rach_type => 0, + c_rd_data_count_width => 12, + c_rd_depth => 4096, + c_rd_freq => 1, + c_rd_pntr_width => 12, + c_rdch_type => 0, + c_reg_slice_mode_axis => 0, + c_reg_slice_mode_rach => 0, + c_reg_slice_mode_rdch => 0, + c_reg_slice_mode_wach => 0, + c_reg_slice_mode_wdch => 0, + c_reg_slice_mode_wrch => 0, + c_synchronizer_stage => 2, + c_underflow_low => 0, + c_use_common_overflow => 0, + c_use_common_underflow => 0, + c_use_default_settings => 0, + c_use_dout_rst => 1, + c_use_ecc => 0, + c_use_ecc_axis => 0, + c_use_ecc_rach => 0, + c_use_ecc_rdch => 0, + c_use_ecc_wach => 0, + c_use_ecc_wdch => 0, + c_use_ecc_wrch => 0, + c_use_embedded_reg => 0, + c_use_fifo16_flags => 0, + c_use_fwft_data_count => 0, + c_valid_low => 0, + c_wach_type => 0, + c_wdch_type => 0, + c_wr_ack_low => 0, + c_wr_data_count_width => 10, + c_wr_depth => 1024, + c_wr_depth_axis => 1024, + c_wr_depth_rach => 16, + c_wr_depth_rdch => 1024, + c_wr_depth_wach => 16, + c_wr_depth_wdch => 1024, + c_wr_depth_wrch => 16, + c_wr_freq => 1, + c_wr_pntr_width => 10, + c_wr_pntr_width_axis => 10, + c_wr_pntr_width_rach => 4, + c_wr_pntr_width_rdch => 10, + c_wr_pntr_width_wach => 4, + c_wr_pntr_width_wdch => 10, + c_wr_pntr_width_wrch => 4, + c_wr_response_latency => 1, + c_wrch_type => 0 + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_usb_fifo_tx + PORT MAP ( + rst => rst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty + ); +-- synthesis translate_on + +END usb_fifo_tx_a; diff --git a/fpga/vendor/xilinx/usb_fifo_tx.xco b/fpga/vendor/xilinx/usb_fifo_tx.xco new file mode 100644 index 0000000..02304a5 --- /dev/null +++ b/fpga/vendor/xilinx/usb_fifo_tx.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.6 +# Date: Wed Sep 4 11:25:04 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=usb_fifo_tx +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1021 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=1020 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=32 +CSET input_depth=1024 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=8 +CSET output_depth=4096 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=12 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=10 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: e2514423 diff --git a/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc b/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc new file mode 100644 index 0000000..bbc219a --- /dev/null +++ b/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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0, + c_application_type_axis => 0, + c_application_type_rach => 0, + c_application_type_rdch => 0, + c_application_type_wach => 0, + c_application_type_wdch => 0, + c_application_type_wrch => 0, + c_axi_addr_width => 32, + c_axi_aruser_width => 1, + c_axi_awuser_width => 1, + c_axi_buser_width => 1, + c_axi_data_width => 64, + c_axi_id_width => 4, + c_axi_ruser_width => 1, + c_axi_type => 0, + c_axi_wuser_width => 1, + c_axis_tdata_width => 64, + c_axis_tdest_width => 4, + c_axis_tid_width => 8, + c_axis_tkeep_width => 4, + c_axis_tstrb_width => 4, + c_axis_tuser_width => 4, + c_axis_type => 0, + c_common_clock => 0, + c_count_type => 0, + c_data_count_width => 10, + c_default_value => "BlankString", + c_din_width => 24, + c_din_width_axis => 1, + c_din_width_rach => 32, + c_din_width_rdch => 64, + c_din_width_wach => 32, + c_din_width_wdch => 64, + c_din_width_wrch => 2, + c_dout_rst_val => "0", + c_dout_width => 24, + c_enable_rlocs => 0, + c_enable_rst_sync => 1, + c_error_injection_type => 0, + c_error_injection_type_axis => 0, + c_error_injection_type_rach => 0, + c_error_injection_type_rdch => 0, + c_error_injection_type_wach => 0, + c_error_injection_type_wdch => 0, + c_error_injection_type_wrch => 0, + c_family => "spartan6", + c_full_flags_rst_val => 1, + c_has_almost_empty => 0, + c_has_almost_full => 0, + c_has_axi_aruser => 0, + c_has_axi_awuser => 0, + c_has_axi_buser => 0, + c_has_axi_rd_channel => 0, + c_has_axi_ruser => 0, + c_has_axi_wr_channel => 0, + c_has_axi_wuser => 0, + c_has_axis_tdata => 0, + c_has_axis_tdest => 0, + c_has_axis_tid => 0, + c_has_axis_tkeep => 0, + c_has_axis_tlast => 0, + c_has_axis_tready => 1, + c_has_axis_tstrb => 0, + c_has_axis_tuser => 0, + c_has_backup => 0, + c_has_data_count => 0, + c_has_data_counts_axis => 0, + c_has_data_counts_rach => 0, + c_has_data_counts_rdch => 0, + c_has_data_counts_wach => 0, + c_has_data_counts_wdch => 0, + c_has_data_counts_wrch => 0, + c_has_int_clk => 0, + c_has_master_ce => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_has_prog_flags_axis => 0, + c_has_prog_flags_rach => 0, + c_has_prog_flags_rdch => 0, + c_has_prog_flags_wach => 0, + c_has_prog_flags_wdch => 0, + c_has_prog_flags_wrch => 0, + c_has_rd_data_count => 0, + c_has_rd_rst => 0, + c_has_rst => 1, + c_has_slave_ce => 0, + c_has_srst => 0, + c_has_underflow => 0, + c_has_valid => 0, + c_has_wr_ack => 0, + c_has_wr_data_count => 0, + c_has_wr_rst => 0, + c_implementation_type => 2, + c_implementation_type_axis => 1, + c_implementation_type_rach => 1, + c_implementation_type_rdch => 1, + c_implementation_type_wach => 1, + c_implementation_type_wdch => 1, + c_implementation_type_wrch => 1, + c_init_wr_pntr_val => 0, + c_interface_type => 0, + c_memory_type => 1, + c_mif_file_name => "BlankString", + c_msgon_val => 1, + c_optimization_mode => 0, + c_overflow_low => 0, + c_preload_latency => 0, + c_preload_regs => 1, + c_prim_fifo_type => "1kx36", + c_prog_empty_thresh_assert_val => 4, + c_prog_empty_thresh_assert_val_axis => 1022, + c_prog_empty_thresh_assert_val_rach => 1022, + c_prog_empty_thresh_assert_val_rdch => 1022, + c_prog_empty_thresh_assert_val_wach => 1022, + c_prog_empty_thresh_assert_val_wdch => 1022, + c_prog_empty_thresh_assert_val_wrch => 1022, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_type => 0, + c_prog_empty_type_axis => 0, + c_prog_empty_type_rach => 0, + c_prog_empty_type_rdch => 0, + c_prog_empty_type_wach => 0, + c_prog_empty_type_wdch => 0, + c_prog_empty_type_wrch => 0, + c_prog_full_thresh_assert_val => 1023, + c_prog_full_thresh_assert_val_axis => 1023, + c_prog_full_thresh_assert_val_rach => 1023, + c_prog_full_thresh_assert_val_rdch => 1023, + c_prog_full_thresh_assert_val_wach => 1023, + c_prog_full_thresh_assert_val_wdch => 1023, + c_prog_full_thresh_assert_val_wrch => 1023, + c_prog_full_thresh_negate_val => 1022, + c_prog_full_type => 0, + c_prog_full_type_axis => 0, + c_prog_full_type_rach => 0, + c_prog_full_type_rdch => 0, + c_prog_full_type_wach => 0, + c_prog_full_type_wdch => 0, + c_prog_full_type_wrch => 0, + c_rach_type => 0, + c_rd_data_count_width => 10, + c_rd_depth => 1024, + c_rd_freq => 1, + c_rd_pntr_width => 10, + c_rdch_type => 0, + c_reg_slice_mode_axis => 0, + c_reg_slice_mode_rach => 0, + c_reg_slice_mode_rdch => 0, + c_reg_slice_mode_wach => 0, + c_reg_slice_mode_wdch => 0, + c_reg_slice_mode_wrch => 0, + c_synchronizer_stage => 2, + c_underflow_low => 0, + c_use_common_overflow => 0, + c_use_common_underflow => 0, + c_use_default_settings => 0, + c_use_dout_rst => 1, + c_use_ecc => 0, + c_use_ecc_axis => 0, + c_use_ecc_rach => 0, + c_use_ecc_rdch => 0, + c_use_ecc_wach => 0, + c_use_ecc_wdch => 0, + c_use_ecc_wrch => 0, + c_use_embedded_reg => 0, + c_use_fifo16_flags => 0, + c_use_fwft_data_count => 0, + c_valid_low => 0, + c_wach_type => 0, + c_wdch_type => 0, + c_wr_ack_low => 0, + c_wr_data_count_width => 10, + c_wr_depth => 1024, + c_wr_depth_axis => 1024, + c_wr_depth_rach => 16, + c_wr_depth_rdch => 1024, + c_wr_depth_wach => 16, + c_wr_depth_wdch => 1024, + c_wr_depth_wrch => 16, + c_wr_freq => 1, + c_wr_pntr_width => 10, + c_wr_pntr_width_axis => 10, + c_wr_pntr_width_rach => 4, + c_wr_pntr_width_rdch => 10, + c_wr_pntr_width_wach => 4, + c_wr_pntr_width_wdch => 10, + c_wr_pntr_width_wrch => 4, + c_wr_response_latency => 1, + c_wrch_type => 0 + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_usb_fifo_tx_fin + PORT MAP ( + rst => rst, + wr_clk => wr_clk, + rd_clk => rd_clk, + din => din, + wr_en => wr_en, + rd_en => rd_en, + dout => dout, + full => full, + empty => empty + ); +-- synthesis translate_on + +END usb_fifo_tx_fin_a; diff --git a/fpga/vendor/xilinx/usb_fifo_tx_fin.xco b/fpga/vendor/xilinx/usb_fifo_tx_fin.xco new file mode 100644 index 0000000..ce5c250 --- /dev/null +++ b/fpga/vendor/xilinx/usb_fifo_tx_fin.xco @@ -0,0 +1,213 @@ +############################################################## +# +# Xilinx Core Generator version 14.6 +# Date: Wed Sep 25 12:38:10 2013 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:fifo_generator:9.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = VHDL +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = false +SET vhdlsim = true +# END Project Options +# BEGIN Select +SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3 +# END Select +# BEGIN Parameters +CSET add_ngc_constraint_axi=false +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET aruser_width=1 +CSET awuser_width=1 +CSET axi_address_width=32 +CSET axi_data_width=64 +CSET axi_type=AXI4_Stream +CSET axis_type=FIFO +CSET buser_width=1 +CSET clock_enable_type=Slave_Interface_Clock_Enable +CSET clock_type_axi=Common_Clock +CSET component_name=usb_fifo_tx_fin +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET disable_timing_violations_axi=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_assert_value_axis=1022 +CSET empty_threshold_assert_value_rach=1022 +CSET empty_threshold_assert_value_rdch=1022 +CSET empty_threshold_assert_value_wach=1022 +CSET empty_threshold_assert_value_wdch=1022 +CSET empty_threshold_assert_value_wrch=1022 +CSET empty_threshold_negate_value=5 +CSET enable_aruser=false +CSET enable_awuser=false +CSET enable_buser=false +CSET enable_common_overflow=false +CSET enable_common_underflow=false +CSET enable_data_counts_axis=false +CSET enable_data_counts_rach=false +CSET enable_data_counts_rdch=false +CSET enable_data_counts_wach=false +CSET enable_data_counts_wdch=false +CSET enable_data_counts_wrch=false +CSET enable_ecc=false +CSET enable_ecc_axis=false +CSET enable_ecc_rach=false +CSET enable_ecc_rdch=false +CSET enable_ecc_wach=false +CSET enable_ecc_wdch=false +CSET enable_ecc_wrch=false +CSET enable_read_channel=false +CSET enable_read_pointer_increment_by2=false +CSET enable_reset_synchronization=true +CSET enable_ruser=false +CSET enable_tdata=false +CSET enable_tdest=false +CSET enable_tid=false +CSET enable_tkeep=false +CSET enable_tlast=false +CSET enable_tready=true +CSET enable_tstrobe=false +CSET enable_tuser=false +CSET enable_write_channel=false +CSET enable_wuser=false +CSET fifo_application_type_axis=Data_FIFO +CSET fifo_application_type_rach=Data_FIFO +CSET fifo_application_type_rdch=Data_FIFO +CSET fifo_application_type_wach=Data_FIFO +CSET fifo_application_type_wdch=Data_FIFO +CSET fifo_application_type_wrch=Data_FIFO +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET fifo_implementation_axis=Common_Clock_Block_RAM +CSET fifo_implementation_rach=Common_Clock_Block_RAM +CSET fifo_implementation_rdch=Common_Clock_Block_RAM +CSET fifo_implementation_wach=Common_Clock_Block_RAM +CSET fifo_implementation_wdch=Common_Clock_Block_RAM +CSET fifo_implementation_wrch=Common_Clock_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1023 +CSET full_threshold_assert_value_axis=1023 +CSET full_threshold_assert_value_rach=1023 +CSET full_threshold_assert_value_rdch=1023 +CSET full_threshold_assert_value_wach=1023 +CSET full_threshold_assert_value_wdch=1023 +CSET full_threshold_assert_value_wrch=1023 +CSET full_threshold_negate_value=1022 +CSET id_width=4 +CSET inject_dbit_error=false +CSET inject_dbit_error_axis=false +CSET inject_dbit_error_rach=false +CSET inject_dbit_error_rdch=false +CSET inject_dbit_error_wach=false +CSET inject_dbit_error_wdch=false +CSET inject_dbit_error_wrch=false +CSET inject_sbit_error=false +CSET inject_sbit_error_axis=false +CSET inject_sbit_error_rach=false +CSET inject_sbit_error_rdch=false +CSET inject_sbit_error_wach=false +CSET inject_sbit_error_wdch=false +CSET inject_sbit_error_wrch=false +CSET input_data_width=24 +CSET input_depth=1024 +CSET input_depth_axis=1024 +CSET input_depth_rach=16 +CSET input_depth_rdch=1024 +CSET input_depth_wach=16 +CSET input_depth_wdch=1024 +CSET input_depth_wrch=16 +CSET interface_type=Native +CSET output_data_width=24 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_flag_axi=false +CSET overflow_sense=Active_High +CSET overflow_sense_axi=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold +CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET programmable_full_type_axis=No_Programmable_Full_Threshold +CSET programmable_full_type_rach=No_Programmable_Full_Threshold +CSET programmable_full_type_rdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wach=No_Programmable_Full_Threshold +CSET programmable_full_type_wdch=No_Programmable_Full_Threshold +CSET programmable_full_type_wrch=No_Programmable_Full_Threshold +CSET rach_type=FIFO +CSET rdch_type=FIFO +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET register_slice_mode_axis=Fully_Registered +CSET register_slice_mode_rach=Fully_Registered +CSET register_slice_mode_rdch=Fully_Registered +CSET register_slice_mode_wach=Fully_Registered +CSET register_slice_mode_wdch=Fully_Registered +CSET register_slice_mode_wrch=Fully_Registered +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET ruser_width=1 +CSET synchronization_stages=2 +CSET synchronization_stages_axi=2 +CSET tdata_width=64 +CSET tdest_width=4 +CSET tid_width=8 +CSET tkeep_width=4 +CSET tstrb_width=4 +CSET tuser_width=4 +CSET underflow_flag=false +CSET underflow_flag_axi=false +CSET underflow_sense=Active_High +CSET underflow_sense_axi=Active_High +CSET use_clock_enable=false +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET wach_type=FIFO +CSET wdch_type=FIFO +CSET wrch_type=FIFO +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=false +CSET write_data_count_width=10 +CSET wuser_width=1 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T12:39:56Z +# END Extra information +GENERATE +# CRC: 7bd756aa diff --git a/linux/Makefile b/linux/Makefile new file mode 100644 index 0000000..9210a41 --- /dev/null +++ b/linux/Makefile @@ -0,0 +1,11 @@ +DIRS = libstrm apps + +all: + @for dir in $(DIRS); do \ + $(MAKE) -C $$dir || exit 1; \ + done + +clean: + @for dir in $(DIRS); do \ + $(MAKE) -C $$dir clean || exit 1; \ + done diff --git a/linux/apps/Makefile b/linux/apps/Makefile new file mode 100644 index 0000000..917e219 --- /dev/null +++ b/linux/apps/Makefile @@ -0,0 +1,17 @@ +CC = gcc +LD = gcc +CFLAGS = -Wall -Werror -c -I../libstrm -O2 +LDFLAGS = -L../libstrm +LDFLAGS_POST = -lstrm -lusb + +BIN_STRM_DDR2 = strm_ddr2 +SRC_STRM_DDR2 = strm_ddr2.c +OBJ_STRM_DDR2 = $(SRC_STRM_DDR2:%.c=%.o) + +all: ${BIN_STRM_DDR2} + +${BIN_STRM_DDR2}: ${OBJ_STRM_DDR2} + ${LD} ${LDFLAGS} $^ -o $@ ${LDFLAGS_POST} + +clean: + rm -f *.o ${BIN_STRM_DDR2} diff --git a/linux/apps/strm_ddr2.c b/linux/apps/strm_ddr2.c new file mode 100644 index 0000000..f39a261 --- /dev/null +++ b/linux/apps/strm_ddr2.c @@ -0,0 +1,119 @@ +/********************************************* + * (2013) Benjamin Krill + *********************************************/ +#include +#include +#include +#include +#include +#include +#include + +static void +show_usage(char *name) +{ + printf("USAGE: %s

[]\n" + "\tw - write needs address, size, pattern\n" + "\tr - read needs address, size\n" + "\t\tsize in DW (4bytes)\n" + , name); + return; +} + +int +main(int argc, char **argv) +{ + uint32_t *buf, pattern; + int address, size, size_dw, i; + clock_t start, end; + int ret = -1; + usb_dev_handle *hd; + + if (argc < 3 || (strncmp(argv[1], "w", 1) == 0 && argc < 5)) { + show_usage(argv[0]); + exit(1); + } + + if ((hd = strm_init(0x04b4, 0x2342)) == NULL) { + perror("cannot init usb2strm interface"); + exit(1); + } + + address = strtoull(argv[2], NULL, 0); + size_dw = strtoull(argv[3], NULL, 0); + size = size_dw*4; + + if (size_dw > 0xffffff) { + perror("size cannot larger than 0xffffff DW"); + goto out; + } + + buf = (uint32_t*)malloc(size+8); + if (buf == NULL) { + perror("cannot allocate memory\n"); + goto out; + } + + if (strncmp(argv[1], "w", 1) == 0) { + pattern = strtoull(argv[4], NULL, 0); + + for (i=0; i < size_dw; i++) { + buf[i+2] = pattern; + } + + buf[0] = STRM_TYPE_DDR2 << 28 | ((size_dw+1) & 0xffffff); + buf[1] = STRM_DDR2_WRITE_HDR_INIT(address >> 2); + + printf("address=0x%x size=%d pattern=0x%06x - ", address, size, pattern); + + start = clock(); + if ((ret = usb_bulk_write(hd, 2, (const char *)buf, size+8, 1000)) < 0) { + fprintf(stderr, "\nFAILED: write bulk transfer (%d) [%s].\n\t%s\n", ret, + __func__, usb_strerror()); + } else { + printf("wrote: %d bytes\n", ret); + } + end = clock(); + printf("Number of seconds: %f\n", (end-start)/(double)CLOCKS_PER_SEC); + + } else if (strncmp(argv[1], "r", 1) == 0) { + + buf[0] = STRM_TYPE_DDR2 << 28 | 2; + buf[1] = STRM_DDR2_READ_HDR_INIT(address >> 2); + buf[2] = ((size_dw) & 0xffffff); + + printf("address=0x%x size=%d - ", address, size); + + if ((ret = usb_bulk_write(hd, 2, (const char *)buf, 12, 1000)) < 0) { + fprintf(stderr, "\nFAILED: write bulk transfer (%d) [%s].\n\t%s\n", ret, + __func__, usb_strerror()); + goto free; + } else { + printf("wrote: %d bytes\n", ret); + } + + if ((ret = usb_bulk_read(hd, 6, (char *)buf, size+4, 6000000)) < 0) { + fprintf(stderr, "\nFAILED: read bulk transfer (%d) [%s].\n\t%s\n", ret, + __func__, usb_strerror()); + goto free; + } else { + printf("read: %d bytes\n", ret); + } + + for (i=0; i < size+4; i++) { + if (!(i%0x10)) + printf("\n"); + printf("%02x ", ((uint8_t*)buf)[i]); + } + printf("\n"); + } else { + printf("Unknown argument.\n"); + return -1; + } + +free: + free(buf); +out: + strm_fini(); + return 0; +} diff --git a/linux/libstrm/Makefile b/linux/libstrm/Makefile new file mode 100644 index 0000000..71f02ab --- /dev/null +++ b/linux/libstrm/Makefile @@ -0,0 +1,13 @@ +CC = gcc +CFLAGS=-Wall -Werror -O2 -I. -c -fPIC + +SRCS = usb2strm.c +OBJS = $(SRCS:%.c=%.o) + +libstrm: ${OBJS} + ${CC} -shared -Wl,-soname,$@.so.1 -o $@.so.1.0.1 $^ -lusb + @if [ ! -e $@.so ]; then ln -s $@.so.1.0.1 $@.so; fi + @if [ ! -e $@.so.1 ]; then ln -s $@.so.1.0.1 $@.so.1; fi + +clean: + rm -f *.o *.so.* *.so diff --git a/linux/libstrm/strm.h b/linux/libstrm/strm.h new file mode 100644 index 0000000..deb5d0c --- /dev/null +++ b/linux/libstrm/strm.h @@ -0,0 +1,17 @@ +#ifndef _STRM_H +#define _STRM_H + +#include +#include + +#define STRM_TYPE_DDR2 0x1 +#define STRM_DDR2_WRITE_HDR_INIT(addr) \ + (uint32_t)(0x80000000 | (addr & 0x0fffffff)) +#define STRM_DDR2_READ_HDR_INIT(addr) \ + (uint32_t)(~(0x1 << 31) & (addr & 0x0fffffff)) + +/* prototypes */ +usb_dev_handle *strm_init(int vendor, int product); +int strm_fini(void); + +#endif /* _STRM_H */ diff --git a/linux/libstrm/usb2strm.c b/linux/libstrm/usb2strm.c new file mode 100644 index 0000000..c6c2b65 --- /dev/null +++ b/linux/libstrm/usb2strm.c @@ -0,0 +1,77 @@ +/********************************************* + * (2013) Benjamin Krill + *********************************************/ +#include +#include +#include +#include +#include +#include + +#define DEBUG 0 + +#if defined(DEBUG) && DEBUG == 1 + #define printf_dbg(fmt, args...) printf(fmt, ## args) +#else + #define printf_dbg(args...) +#endif + +static usb_dev_handle *hd = NULL; + +/* TODO: extend to support multiple USB device on one host! */ +static struct usb_device * +find_device(struct usb_bus* busses, int vendor, int product) +{ + struct usb_bus *bus; + struct usb_device *dev; + + for (bus = busses; bus; bus = bus->next) { + printf_dbg("scanning bus %s\n", bus->dirname); + + for (dev = bus->devices; dev; dev=dev->next) { + /* compare device vendor and product */ + if ((dev->descriptor.idVendor == vendor) && + (dev->descriptor.idProduct == product)) { + /* print device information */ + printf_dbg("\tfound device %s bus %s (idVendor 0x%04x idProduct 0x%04x)\n", + dev->filename, dev->bus->dirname, dev->descriptor.idVendor, + dev->descriptor.idProduct); + return dev; + } else { + printf_dbg("\tdevice %s does not match\n", dev->filename); + } + } + } + return NULL; +} + +usb_dev_handle * +strm_init(int vendor, int product) +{ + struct usb_device *dev; + + usb_init(); + usb_find_busses(); + usb_find_devices(); + if ((dev = find_device(usb_get_busses(), vendor, product)) == NULL) + return NULL; + + if (!(hd = usb_open(dev))) { + printf("FAILED: cannot open device.\n"); + return NULL; + } + /* reset usb device */ + usb_reset(hd); + printf_dbg("Lets do the magic (%p) ...\n", hd); + + return hd; +} + +int +strm_fini(void) +{ + if (hd) + usb_close(hd); + hd = NULL; + return 0; +}