-- --------------------------------------------------------------- -- (2013) Benjamin Krill -- --------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.strm_package.all; ENTITY f2p_strm_top_tb IS END f2p_strm_top_tb; ARCHITECTURE rtl OF f2p_strm_top_tb IS constant CLK_PERIOD : time := 5 ns; constant CLK_PERIOD2: time := 21 ns; signal clk : std_logic; signal usb_clk : std_logic; signal rst : std_logic; signal rst_n : std_logic; signal usb_flag_a_i : std_logic; signal usb_flag_full : std_logic; signal usb_flag_empty : std_logic; signal usb_cs_o : std_logic; signal usb_oe_o : std_logic; signal usb_rd_o : std_logic; signal usb_wr_o : std_logic; signal usb_pktend_o : std_logic; signal usb_adr_o : std_logic_vector(1 downto 0); signal usb_dat_io : std_logic_vector(7 downto 0); signal usb_dat_o : std_logic_vector(7 downto 0); signal usb_dat_i : std_logic_vector(7 downto 0); signal tmp_data : std_logic_vector(31 downto 0); signal tmp_data_m : std_logic_vector(31 downto 0); signal strm_in_type : std_logic_vector( 3 downto 0); signal strm_in_data : std_logic_vector(31 downto 0); signal strm_in_eop : std_logic; signal strm_in_sop : std_logic; signal strm_in_en : std_logic; signal strm_in_busy : std_logic; constant STRM_OUT_SLV_CNT : integer := 1; signal strm_out_slv_reqs : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); signal strm_out_slv_busy : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); signal strm_out_data : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0); signal strm_out_eop : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); signal strm_out_en : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0); signal ddr2_strm_out_req : std_logic; signal ddr2_strm_out_busy : std_logic; signal ddr2_strm_out_data : std_logic_vector(31 downto 0); signal ddr2_strm_out_eop : std_logic; signal ddr2_strm_out_en : std_logic; signal usb_flag_a_iq : std_logic; signal usb_flag_b_iq : std_logic; signal usb_flag_c_iq : std_logic; signal usb_cs_oq : std_logic; signal usb_oe_oq : std_logic; signal usb_rd_oq : std_logic; signal usb_wr_oq : std_logic; signal usb_pktend_oq : std_logic; signal usb_adr_oq : std_logic_vector(1 downto 0); signal ddr2_cmd_en_o : std_logic; signal ddr2_wr_full_i : std_logic; signal ddr2_rd_empty_i : std_logic; signal ddr2_rd_en_o : std_logic; BEGIN rst <= transport '1', '0' after ( 4 * CLK_PERIOD); rst_n <= not rst; clock: process begin clk <= '1', '0' after CLK_PERIOD/2; wait for CLK_PERIOD; end process; usb_clk_0: process begin usb_clk <= '1', '0' after CLK_PERIOD2/2; wait for CLK_PERIOD2; end process; reg1: process begin wait until rising_edge(clk); end process; reg2: process begin wait until rising_edge(usb_clk); usb_flag_a_iq <= usb_flag_a_i; usb_flag_b_iq <= usb_flag_full; usb_flag_c_iq <= usb_flag_empty; usb_cs_o <= usb_cs_oq; usb_oe_o <= usb_oe_oq; usb_rd_o <= usb_rd_oq; usb_wr_o <= usb_wr_oq; usb_pktend_o <= usb_pktend_oq; usb_adr_o <= usb_adr_oq; end process; usb_dat_io <= (others => 'Z') when usb_oe_o = '1' else usb_dat_o; usb_dat_i <= usb_dat_io when usb_oe_o = '0' else (others => '0'); f2p_strm_top_0: entity work.f2p_strm_top generic map ( STRM_OUT_SLV_CNT => STRM_OUT_SLV_CNT ) port map ( clk => clk, rst_n => rst_n, -- cypress interface usb_clk => usb_clk, usb_flag_a_i => usb_flag_a_iq, usb_flag_b_i => usb_flag_full, usb_flag_c_i => usb_flag_empty, usb_cs_o => usb_cs_oq, usb_oe_o => usb_oe_oq, usb_rd_o => usb_rd_oq, usb_wr_o => usb_wr_oq, usb_pktend_o => usb_pktend_oq, usb_adr_o => usb_adr_oq, usb_dat_io => usb_dat_io, -- streaming bus strm_in_data_o => strm_in_data, strm_in_eop_o => strm_in_eop, strm_in_sop_o => strm_in_sop, strm_in_en_o => strm_in_en, strm_in_busy_i => strm_in_busy, strm_out_slv_reqs_i => strm_out_slv_reqs, strm_out_slv_busy_o => strm_out_slv_busy, strm_out_data_i => strm_out_data, strm_out_eop_i => strm_out_eop, strm_out_en_i => strm_out_en ); ddr2_strm_out_busy <= strm_out_slv_busy(0); strm_out_slv_reqs(0) <= ddr2_strm_out_req; strm_out_data(0) <= ddr2_strm_out_data; strm_out_eop(0) <= ddr2_strm_out_eop; strm_out_en(0) <= ddr2_strm_out_en; strm_ddr2_0: entity work.strm_ddr2 port map ( clk => clk, rst_n => rst_n, -- streaming bus strm_in_data_i => strm_in_data, strm_in_eop_i => strm_in_eop, strm_in_sop_i => strm_in_sop, strm_in_en_i => strm_in_en, strm_in_busy_o => strm_in_busy, strm_out_req_o => ddr2_strm_out_req, strm_out_busy_i => ddr2_strm_out_busy, strm_out_data_o => ddr2_strm_out_data, strm_out_eop_o => ddr2_strm_out_eop, strm_out_en_o => ddr2_strm_out_en, -- memory interface ddr2_cmd_en_o => ddr2_cmd_en_o, ddr2_cmd_instr_o => open, ddr2_cmd_bl_o => open, ddr2_cmd_byte_addr_o => open, ddr2_cmd_empty_i => '0', ddr2_cmd_full_i => '0', ddr2_wr_en_o => open, ddr2_wr_mask_o => open, ddr2_wr_data_o => open, ddr2_wr_full_i => ddr2_wr_full_i, ddr2_wr_empty_i => '0', ddr2_wr_count_i => (others => '0'), ddr2_wr_underrun_i => '0', ddr2_wr_error_i => '0', ddr2_rd_en_o => ddr2_rd_en_o, ddr2_rd_data_i => (others => '0'), ddr2_rd_full_i => '0', ddr2_rd_empty_i => ddr2_rd_empty_i, ddr2_rd_count_i => (others => '0'), ddr2_rd_overflow_i => '0', ddr2_rd_error_i => '0' ); bla: process begin ddr2_wr_full_i <= '0'; -- wait for 500*CLK_PERIOD; -- ddr2_wr_full_i <= '1'; -- wait for 50*CLK_PERIOD; -- ddr2_wr_full_i <= '0'; wait; end process; bla2: process begin ddr2_rd_empty_i <= '1'; wait for 20*CLK_PERIOD; wait until ddr2_cmd_en_o = '1'; wait for 10*CLK_PERIOD; ddr2_rd_empty_i <= '0'; wait until ddr2_rd_en_o = '1'; wait for 5*CLK_PERIOD; ddr2_rd_empty_i <= '1'; wait for 5*CLK_PERIOD; ddr2_rd_empty_i <= '0'; wait for 5*CLK_PERIOD; ddr2_rd_empty_i <= '1'; end process; tmp_data_m <= tmp_data(7 downto 0) & tmp_data(15 downto 8) & tmp_data(23 downto 16) & tmp_data(31 downto 24); usb_beh: process begin usb_flag_a_i <= '0'; usb_flag_full <= '1'; usb_flag_empty <= '0'; usb_dat_o <= (others => '0'); for I in 1 to 1 loop wait for 20*CLK_PERIOD2; -- do DDR read tmp_data <= STRM_TYPE_DDR2 & (27 downto 24 => '0') & x"000002"; wait for 2*CLK_PERIOD2; usb_flag_empty <= '1'; usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8)); wait until usb_rd_o = '0'; for I in 1 to 3 loop usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8)); wait for CLK_PERIOD2; end loop; -- DDR2 HEADER 0 usb_flag_empty <= '0'; tmp_data <= x"0000100" & std_logic_vector(to_unsigned(I, 4)); wait for 2*CLK_PERIOD2; usb_flag_empty <= '1'; usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8)); wait until usb_rd_o = '0'; for I in 1 to 3 loop usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8)); wait for CLK_PERIOD2; end loop; usb_flag_empty <= '0'; -- DDR2 HEADER 1 usb_flag_empty <= '0'; tmp_data <= x"0000000a"; wait for 2*CLK_PERIOD2; usb_flag_empty <= '1'; usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8)); wait until usb_rd_o = '0'; for I in 1 to 3 loop usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8)); wait for CLK_PERIOD2; end loop; usb_flag_empty <= '0'; wait for 200*CLK_PERIOD2; end loop; wait; -- do DDR write -- STRM header tmp_data <= STRM_TYPE_DDR2 & (27 downto 24 => '0') & x"000041"; wait for 2*CLK_PERIOD2; usb_flag_empty <= '1'; usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8)); wait until usb_rd_o = '0'; for I in 1 to 3 loop usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8)); wait for CLK_PERIOD2; end loop; -- DDR2 HEADER usb_flag_empty <= '0'; tmp_data <= x"80001000"; wait for 2*CLK_PERIOD2; usb_flag_empty <= '1'; usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8)); wait until usb_rd_o = '0'; for I in 1 to 3 loop usb_dat_o <= tmp_data_m(((4-I)*8)-1 downto ((4-I-1)*8)); wait for CLK_PERIOD2; end loop; usb_flag_empty <= '0'; -- DATA usb_flag_empty <= '1'; usb_dat_o <= tmp_data_m(((4-0)*8)-1 downto ((4-0-1)*8)); wait until usb_rd_o = '0'; for I in 2 to 4*64 loop usb_dat_o <= std_logic_vector(to_unsigned(I, 8)); wait for CLK_PERIOD2; end loop; usb_flag_empty <= '0'; usb_dat_o <= (others => '0'); wait; end process; end rtl; configuration f2p_strm_top_tb_rtl_cfg of f2p_strm_top_tb is for rtl end for; end f2p_strm_top_tb_rtl_cfg;