##############################################################
#
# PlanAhead 14.6
# Date: Thu Nov 28 22:36:15 2013

#
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#
#  This file contains the customisation parameters for a
#  Xilinx IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
# BEGIN Project Options
SET devicefamily=spartan6
SET device=xc6slx45
SET package=csg324
SET speedgrade=-3
SET verilogsim=false
SET vhdlsim=true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET component_name=usb_fifo_tx
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET interface_type=Native
CSET performance_options=First_Word_Fall_Through
CSET input_data_width=32
CSET input_depth=1024
CSET output_data_width=8
CSET output_depth=4096
CSET enable_ecc=false
CSET use_embedded_registers=false
CSET reset_pin=true
CSET enable_reset_synchronization=true
CSET reset_type=Asynchronous_Reset
CSET full_flags_reset_value=1
CSET use_dout_reset=true
CSET dout_reset_value=0
CSET almost_full_flag=false
CSET almost_empty_flag=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET inject_sbit_error=false
CSET inject_dbit_error=false
CSET use_extra_logic=false
CSET data_count=false
CSET data_count_width=10
CSET write_data_count=false
CSET write_data_count_width=10
CSET read_data_count=false
CSET read_data_count_width=12
CSET disable_timing_violations=false
CSET read_clock_frequency=1
CSET write_clock_frequency=1
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET full_threshold_assert_value=1021
CSET full_threshold_negate_value=1020
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET empty_threshold_assert_value=4
CSET empty_threshold_negate_value=5
CSET axi_type=AXI4_Stream
CSET clock_type_axi=Common_Clock
CSET use_clock_enable=false
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET enable_write_channel=false
CSET enable_read_channel=false
CSET id_width=4
CSET axi_address_width=32
CSET axi_data_width=64
CSET enable_awuser=false
CSET awuser_width=1
CSET enable_wuser=false
CSET wuser_width=1
CSET enable_buser=false
CSET buser_width=1
CSET enable_aruser=false
CSET aruser_width=1
CSET enable_ruser=false
CSET ruser_width=1
CSET enable_tdata=false
CSET tdata_width=64
CSET enable_tid=false
CSET tid_width=8
CSET enable_tdest=false
CSET tdest_width=4
CSET enable_tuser=false
CSET tuser_width=4
CSET enable_tready=true
CSET enable_tlast=false
CSET enable_tstrobe=false
CSET tstrb_width=4
CSET enable_tkeep=false
CSET tkeep_width=4
CSET wach_type=FIFO
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_application_type_wach=Data_FIFO
CSET enable_ecc_wach=false
CSET inject_sbit_error_wach=false
CSET inject_dbit_error_wach=false
CSET input_depth_wach=16
CSET enable_data_counts_wach=false
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET full_threshold_assert_value_wach=1023
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET empty_threshold_assert_value_wach=1022
CSET wdch_type=FIFO
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_application_type_wdch=Data_FIFO
CSET enable_ecc_wdch=false
CSET inject_sbit_error_wdch=false
CSET inject_dbit_error_wdch=false
CSET input_depth_wdch=1024
CSET enable_data_counts_wdch=false
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET full_threshold_assert_value_wdch=1023
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET empty_threshold_assert_value_wdch=1022
CSET wrch_type=FIFO
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET fifo_application_type_wrch=Data_FIFO
CSET enable_ecc_wrch=false
CSET inject_sbit_error_wrch=false
CSET inject_dbit_error_wrch=false
CSET input_depth_wrch=16
CSET enable_data_counts_wrch=false
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET full_threshold_assert_value_wrch=1023
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET empty_threshold_assert_value_wrch=1022
CSET rach_type=FIFO
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_application_type_rach=Data_FIFO
CSET enable_ecc_rach=false
CSET inject_sbit_error_rach=false
CSET inject_dbit_error_rach=false
CSET input_depth_rach=16
CSET enable_data_counts_rach=false
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET full_threshold_assert_value_rach=1023
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET empty_threshold_assert_value_rach=1022
CSET rdch_type=FIFO
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_application_type_rdch=Data_FIFO
CSET enable_ecc_rdch=false
CSET inject_sbit_error_rdch=false
CSET inject_dbit_error_rdch=false
CSET input_depth_rdch=1024
CSET enable_data_counts_rdch=false
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET full_threshold_assert_value_rdch=1023
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET empty_threshold_assert_value_rdch=1022
CSET axis_type=FIFO
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_application_type_axis=Data_FIFO
CSET enable_ecc_axis=false
CSET inject_sbit_error_axis=false
CSET inject_dbit_error_axis=false
CSET input_depth_axis=1024
CSET enable_data_counts_axis=false
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET full_threshold_assert_value_axis=1023
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET empty_threshold_assert_value_axis=1022
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_axis=Fully_Registered
CSET underflow_flag_axi=false
CSET underflow_sense_axi=Active_High
CSET overflow_flag_axi=false
CSET overflow_sense_axi=Active_High
CSET disable_timing_violations_axi=false
CSET add_ngc_constraint_axi=false
CSET enable_common_underflow=false
CSET enable_common_overflow=false
CSET enable_read_pointer_increment_by2=false
# END Parameters
GENERATE