178 lines
6.7 KiB
VHDL
178 lines
6.7 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.strm_package.all;
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entity f2p_strm_top is
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generic ( STRM_OUT_SLV_CNT : integer := 1 );
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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debug : out std_logic_vector(7 downto 0);
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-- cypress interface
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usb_clk : in std_logic;
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usb_flag_a_i : in std_logic; -- programmable flag
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usb_flag_b_i : in std_logic; -- full flag
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usb_flag_c_i : in std_logic; -- empty flag
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usb_cs_o : out std_logic; -- put to GND, not need for this application
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usb_oe_o : out std_logic; -- active_low
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usb_rd_o : out std_logic; -- active_low
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usb_wr_o : out std_logic; -- active_low
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usb_pktend_o : out std_logic; -- active_low
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usb_adr_o : out std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8
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usb_dat_io : inout std_logic_vector(7 downto 0);
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-- streaming bus
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strm_in_data_o : out std_logic_vector(31 downto 0);
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strm_in_eop_o : out std_logic;
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strm_in_sop_o : out std_logic;
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strm_in_en_o : out std_logic;
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strm_in_busy_i : in std_logic;
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strm_out_slv_reqs_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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strm_out_slv_busy_o : out std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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strm_out_data_i : in strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
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strm_out_eop_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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strm_out_en_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0)
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);
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end f2p_strm_top;
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architecture f2p_strm_top of f2p_strm_top is
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signal rp_read_cnt : unsigned(23 downto 0);
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signal strm_data : std_logic_vector(31 downto 0);
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signal strm_eop : std_logic;
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signal strm_sop : std_logic;
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signal strm_en : std_logic;
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signal wp_wr : std_logic;
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signal wp_full : std_logic;
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signal wp_eop : std_logic;
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signal wp_dat : std_logic_vector(31 downto 0);
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signal rp_rd : std_logic;
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signal rp_empty : std_logic;
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signal rp_dat : std_logic_vector(31 downto 0);
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signal rrarb_req : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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signal rrarb_ack : std_logic;
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signal rrarb_grant : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
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signal strm_out_data_mux : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
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begin
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strm_in_data_o <= strm_data;
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strm_in_eop_o <= strm_eop;
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strm_in_sop_o <= strm_sop;
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strm_in_en_o <= strm_en;
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f2p_master_0: entity work.f2p_master
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port map (
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clk => clk,
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rst_n => rst_n,
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debug => debug,
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-- cypress interface
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usb_clk => usb_clk,
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usb_flag_a_i => usb_flag_a_i,
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usb_flag_b_i => usb_flag_b_i,
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usb_flag_c_i => usb_flag_c_i,
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usb_cs_o => usb_cs_o,
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usb_oe_o => usb_oe_o,
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usb_rd_o => usb_rd_o,
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usb_wr_o => usb_wr_o,
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usb_pktend_o => usb_pktend_o,
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usb_adr_o => usb_adr_o,
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usb_dat_io => usb_dat_io,
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-- write/read pipe
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wp_wr_i => wp_wr,
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wp_full_o => wp_full,
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wp_dat_i => wp_dat,
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wp_eop_i => wp_eop,
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rp_rd_i => rp_rd,
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rp_empty_o => rp_empty,
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rp_dat_o => rp_dat
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);
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-- ------------------------------------------------------------------
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-- USB FIFO SLAVES
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-- ------------------------------------------------------------------
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-- FROM USB
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rp_rd <= not rp_empty and not strm_in_busy_i;
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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rp_read_cnt <= (others => '0');
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strm_data <= (others => '0');
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strm_en <= '0';
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strm_eop <= '0';
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strm_sop <= '0';
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elsif rising_edge(clk) then
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-- get next packet and stream to slaves
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if rp_rd = '1' then
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if rp_read_cnt /= x"000000" then
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rp_read_cnt <= rp_read_cnt - "1";
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else
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rp_read_cnt <= unsigned(rp_dat(STRM_LENGTH_HIGH downto STRM_LENGTH_LOW));
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end if;
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end if;
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-- stream data
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strm_en <= '0';
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strm_eop <= '0';
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strm_sop <= '0';
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if rp_rd = '1' then
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strm_en <= '1';
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strm_data <= rp_dat;
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if rp_read_cnt = x"000000" then
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strm_sop <= '1';
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end if;
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if rp_read_cnt = x"000001" then
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strm_eop <= '1';
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end if;
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end if;
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end if;
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end process;
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-- TO USB - strm arbiter
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rrarb_req <= strm_out_slv_reqs_i and not rrarb_grant;
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rrarb_ack <= '1' when (strm_out_eop_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0';
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rrarb_strm_out_0: entity work.rrarbiter
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generic map ( CNT => STRM_OUT_SLV_CNT )
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port map (
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clk => clk,
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rst_n => rst_n,
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req => rrarb_req,
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ack => rrarb_ack,
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grant => rrarb_grant
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);
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strm_out_slv_busy_o <= not rrarb_grant or (STRM_OUT_SLV_CNT-1 downto 0 => wp_full);
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strm_out_data_mux(0) <= strm_out_data_i(0) and (31 downto 0 => rrarb_grant(0));
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dc: for I in 1 to STRM_OUT_SLV_CNT-1 generate
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strm_out_data_mux(I) <= strm_out_data_mux(I-1) or (strm_out_data_i(I) and (31 downto 0 => rrarb_grant(I)));
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end generate dc;
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wp_dat <= strm_out_data_mux(STRM_OUT_SLV_CNT-1);
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wp_wr <= '1' when (strm_out_en_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0';
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wp_eop <= '1' when (strm_out_eop_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0';
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end f2p_strm_top;
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