85 lines
3.9 KiB
VHDL
85 lines
3.9 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- GENERAL PKT FORMAT
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-- --------------------------------------------------------
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-- Type (4bit)
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-- _Tag (4bit)
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-- Plength (7bit) data length (0 = 0byte, 0x7f = 127 * 4byte)
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-- 31 16|15 0
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-- header |Type_Tag________|___PLenght______|
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-- data |... type defined data/fields ... |
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--
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-- --------------------------------------------------------
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-- --------------------------------------------------------
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-- DDR2 WRITE TYPE FORMAT
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-- --------------------------------------------------------
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-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
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-- data | .... data .... |
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--
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-- DDR2 READ TYPE FORMAT
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-- --------------------------------------------------------
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-- header0 |0 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
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-- header1 | |_______SIZE_____| -- SIZE in 4byte to read
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-- --------------------------------------------------------
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-- --------------------------------------------------------
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-- --------------------------------------------------------
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-- --------------------------------------------------------
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-- REGFILE WRITE TYPE FORMAT
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-- --------------------------------------------------------
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-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
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-- data | 32 bit data |
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--
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-- REGFILE READ TYPE FORMAT
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-- --------------------------------------------------------
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-- header |0TAG________ADDR|ESS_____________| -- ADDRESS 4byte aligned
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-- --------------------------------------------------------
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-- --------------------------------------------------------
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package strm_package is
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constant STRM_TYPE_HIGH : integer := 31;
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constant STRM_TYPE_LOW : integer := 28;
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constant STRM_TAG_HIGH : integer := 27;
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constant STRM_TAG_LOW : integer := 24;
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constant STRM_LENGTH_HIGH : integer := 23;
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constant STRM_LENGTH_LOW : integer := 0;
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-- SLAVE TYPE IDs
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constant STRM_TYPE_DDR2 : std_logic_vector(3 downto 0) := "0001";
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constant STRM_TYPE_REGFILE : std_logic_vector(3 downto 0) := "0010";
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-- DDR2
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constant STRM_DDR2_ADR_HIGH : integer := 27;
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constant STRM_DDR2_ADR_LOW : integer := 0;
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constant STRM_DDR2_ACCESS : integer := 31;
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constant STRM_DDR2_ACC_WRITE : std_logic := '1';
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constant STRM_DDR2_ACC_READ : std_logic := '0';
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constant STRM_DDR2_SIZE_HIGH : integer := 23;
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constant STRM_DDR2_SIZE_LOW : integer := 0;
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-- bus types
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type strm_dat_bus_t is array(natural range <>) of std_logic_vector(31 downto 0);
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end package;
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