285 lines
9.9 KiB
VHDL
285 lines
9.9 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.strm_package.all;
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entity strm_ddr2 is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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debug : out std_logic_vector( 7 downto 0);
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-- streaming bus
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strm_in_data_i : in std_logic_vector(31 downto 0);
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strm_in_eop_i : in std_logic;
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strm_in_sop_i : in std_logic;
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strm_in_en_i : in std_logic;
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strm_in_busy_o : out std_logic;
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strm_out_req_o : out std_logic;
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strm_out_busy_i : in std_logic;
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strm_out_data_o : out std_logic_vector(31 downto 0);
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strm_out_eop_o : out std_logic;
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strm_out_en_o : out std_logic;
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-- memory interface
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ddr2_cmd_en_o : out std_logic;
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ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0);
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ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0);
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ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0);
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ddr2_cmd_empty_i : in std_logic;
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ddr2_cmd_full_i : in std_logic;
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ddr2_wr_en_o : out std_logic;
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ddr2_wr_mask_o : out std_logic_vector( 3 downto 0);
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ddr2_wr_data_o : out std_logic_vector(31 downto 0);
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ddr2_wr_full_i : in std_logic;
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ddr2_wr_empty_i : in std_logic;
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ddr2_wr_count_i : in std_logic_vector( 6 downto 0);
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ddr2_wr_underrun_i : in std_logic;
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ddr2_wr_error_i : in std_logic;
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ddr2_rd_en_o : out std_logic;
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ddr2_rd_data_i : in std_logic_vector(31 downto 0);
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ddr2_rd_full_i : in std_logic;
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ddr2_rd_empty_i : in std_logic;
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ddr2_rd_count_i : in std_logic_vector( 6 downto 0);
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ddr2_rd_overflow_i : in std_logic;
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ddr2_rd_error_i : in std_logic
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);
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end strm_ddr2;
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architecture strm_ddr2 of strm_ddr2 is
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type sm_strm_t is (IDLE, DDR2_ADDRESS, RECV, DDR2_READ, DDR2_RD_SIZE, DDR2_RD_WAIT, DDR2_RD_ADJ, DDR2_RD_REQ, IGNORE);
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signal sm_strm : sm_strm_t;
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signal rst : std_logic;
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signal strm_in_data : std_logic_vector(31 downto 0);
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signal strm_in_eop : std_logic;
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signal strm_in_sop : std_logic;
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signal strm_in_en : std_logic;
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signal strm_in_busy : std_logic;
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signal strm_type_vld : std_logic;
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signal strm_tag : std_logic_vector( 3 downto 0);
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signal strm_size : unsigned(23 downto 0);
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signal ddr2_wr_en : std_logic;
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signal ddr2_wr_mask : std_logic_vector( 3 downto 0);
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signal ddr2_wr_data : std_logic_vector(31 downto 0);
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signal dw_cnt : unsigned( 7 downto 0);
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signal dw_cnt_dec : unsigned( 7 downto 0);
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signal ddr2_adr : unsigned(27 downto 0);
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signal ddr2_size : unsigned(23 downto 0);
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signal ddr2_read_size : unsigned(23 downto 0);
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signal ddr2_cmd_en : std_logic;
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signal ddr2_cmd_instr : std_logic_vector( 2 downto 0);
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signal strm_out_size : unsigned(23 downto 0);
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signal strm_out_eop : std_logic;
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signal strm_out_hdr_en : std_logic;
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signal ddr2_rd_en : std_logic;
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signal read_cnt : unsigned(7 downto 0);
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begin
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rst <= not rst_n;
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ddr2_rd_en_o <= ddr2_rd_en;
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ddr2_cmd_en_o <= ddr2_cmd_en;
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ddr2_cmd_instr_o <= ddr2_cmd_instr;
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ddr2_wr_en_o <= ddr2_wr_en;
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ddr2_wr_mask_o <= ddr2_wr_mask;
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ddr2_wr_data_o <= ddr2_wr_data;
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strm_in_data <= strm_in_data_i;
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strm_in_eop <= strm_in_eop_i;
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strm_in_sop <= strm_in_sop_i;
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strm_in_en <= strm_in_en_i;
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strm_in_busy_o <= strm_in_busy;
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strm_in_busy <= ddr2_wr_full_i or ddr2_cmd_full_i;
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strm_type_vld <= strm_in_sop when strm_in_data(STRM_TYPE_HIGH downto STRM_TYPE_LOW) = STRM_TYPE_DDR2 else '0';
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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sm_strm <= IDLE;
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strm_tag <= (others => '0');
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strm_size <= (others => '0');
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ddr2_cmd_instr <= (others => '0');
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ddr2_wr_en <= '0';
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ddr2_wr_mask <= (others => '0');
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ddr2_wr_data <= (others => '0');
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dw_cnt <= (others => '0');
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ddr2_adr <= (others => '0');
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ddr2_size <= (others => '0');
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ddr2_read_size <= (others => '0');
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strm_out_size <= (others => '0');
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read_cnt <= (others => '0');
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strm_out_hdr_en <= '0';
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elsif rising_edge(clk) then
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-- STRM SIZE
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if sm_strm = IDLE and strm_in_en = '1' then
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strm_tag <= strm_in_data(STRM_TAG_HIGH downto STRM_TAG_LOW);
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strm_size <= unsigned(strm_in_data(STRM_LENGTH_HIGH downto STRM_LENGTH_LOW));
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end if;
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-- SAVE DDR2 ADDRESS
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if sm_strm = DDR2_ADDRESS and strm_in_en = '1' then
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ddr2_adr <= unsigned(strm_in_data(STRM_DDR2_ADR_HIGH downto STRM_DDR2_ADR_LOW));
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elsif ddr2_cmd_en = '1' then
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ddr2_adr <= ddr2_adr + x"040";
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end if;
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-- SAVE DDR2 READ SIZE
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if sm_strm = DDR2_RD_SIZE and strm_in_en = '1' then
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ddr2_size <= unsigned(strm_in_data(STRM_DDR2_SIZE_HIGH downto STRM_DDR2_SIZE_LOW));
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strm_out_size <= unsigned(strm_in_data(STRM_DDR2_SIZE_HIGH downto STRM_DDR2_SIZE_LOW));
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elsif sm_strm = DDR2_RD_REQ and ddr2_cmd_full_i = '0' then
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if ddr2_size > x"000040" then
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ddr2_size <= ddr2_size - x"40";
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else
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ddr2_size <= (others => '0');
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end if;
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end if;
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-- DDR2 DW COUNT
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if sm_strm = RECV or sm_strm = IDLE then
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if strm_in_en = '1' and ddr2_cmd_en = '1' then
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dw_cnt <= x"01";
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elsif ddr2_cmd_en = '1' then
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dw_cnt <= (others => '0');
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elsif strm_in_en = '1' then
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dw_cnt <= dw_cnt + "1";
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end if;
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elsif sm_strm = DDR2_RD_ADJ and ddr2_cmd_full_i = '0' then
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if ddr2_size > x"000040" then
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dw_cnt <= x"40";
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else
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dw_cnt <= ddr2_size(7 downto 0);
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end if;
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elsif strm_out_eop = '1' then
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dw_cnt <= (others => '0');
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end if;
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-- DDR2 instruction
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if sm_strm = DDR2_ADDRESS and strm_in_en = '1' then
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if strm_in_data(STRM_DDR2_ACCESS) = STRM_DDR2_ACC_WRITE then
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ddr2_cmd_instr <= "000";
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else
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ddr2_cmd_instr <= "001";
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end if;
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end if;
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if sm_strm = IDLE then
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strm_out_hdr_en <= '1';
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elsif sm_strm = DDR2_RD_WAIT and strm_out_busy_i = '0' then
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strm_out_hdr_en <= '0';
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end if;
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-- RECV STATES
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case sm_strm is
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when IDLE =>
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if strm_in_en = '1' then
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if strm_type_vld = '1' then
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sm_strm <= DDR2_ADDRESS;
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else
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sm_strm <= IGNORE;
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end if;
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end if;
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when DDR2_ADDRESS =>
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if strm_in_en = '1' then
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if strm_in_data(STRM_DDR2_ACCESS) = STRM_DDR2_ACC_WRITE then
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sm_strm <= RECV;
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else
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sm_strm <= DDR2_RD_SIZE;
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end if;
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end if;
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-- DDR WRITE
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when RECV =>
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if strm_in_eop = '1' and strm_in_en = '1' then
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sm_strm <= IDLE;
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end if;
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-- DDR READ
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when DDR2_RD_SIZE =>
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if strm_in_en = '1' then
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if strm_in_eop = '1' then
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sm_strm <= DDR2_RD_ADJ;
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else
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sm_strm <= IGNORE;
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end if;
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end if;
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when DDR2_RD_ADJ =>
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if ddr2_cmd_full_i = '0' then
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sm_strm <= DDR2_RD_REQ;
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end if;
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when DDR2_RD_REQ =>
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sm_strm <= DDR2_RD_WAIT;
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when DDR2_RD_WAIT =>
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if ddr2_rd_empty_i = '0' and strm_out_busy_i = '0' then
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sm_strm <= DDR2_READ;
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end if;
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when DDR2_READ =>
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if ddr2_rd_empty_i = '1' and ddr2_size /= x"000000" and read_cnt = dw_cnt(6 downto 0) then
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sm_strm <= DDR2_RD_ADJ;
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elsif strm_out_eop = '1' then
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sm_strm <= IDLE;
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end if;
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-- COMMON IGNORE
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when IGNORE =>
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if strm_in_eop = '1' and strm_in_en = '1' then
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sm_strm <= IDLE;
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end if;
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end case;
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-- DDR REGISTERS
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ddr2_wr_en <= '0';
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if strm_in_en = '1' and sm_strm = RECV then
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ddr2_wr_en <= '1';
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ddr2_wr_mask <= (others => '0');
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ddr2_wr_data <= strm_in_data;
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end if;
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if ddr2_cmd_en = '1' then
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read_cnt <= (others => '0');
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elsif ddr2_rd_en = '1' then
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read_cnt <= read_cnt + "1";
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end if;
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-- STRM OUT REGISTERS
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if sm_strm = DDR2_RD_SIZE then
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ddr2_read_size <= x"000001";
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elsif ddr2_rd_en = '1' then
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ddr2_read_size <= ddr2_read_size + "1";
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end if;
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end if;
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end process;
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ddr2_cmd_en <= '1' when (sm_strm = RECV and dw_cnt = x"40") or ((sm_strm = DDR2_RD_REQ or sm_strm = IDLE) and dw_cnt /= x"00") else '0';
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dw_cnt_dec <= dw_cnt - "1";
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ddr2_cmd_bl_o <= std_logic_vector(dw_cnt_dec(5 downto 0));
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ddr2_cmd_byte_addr_o <= std_logic_vector(ddr2_adr) & "00";
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ddr2_rd_en <= not ddr2_rd_empty_i when sm_strm = DDR2_READ else '0';
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strm_out_req_o <= not ddr2_rd_empty_i and strm_out_busy_i when sm_strm = DDR2_RD_WAIT else '0';
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strm_out_en_o <= strm_out_hdr_en when sm_strm = DDR2_RD_WAIT and strm_out_busy_i = '0' else ddr2_rd_en;
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strm_out_eop <= ddr2_rd_en when ddr2_read_size >= strm_out_size and sm_strm = DDR2_READ else '0';
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strm_out_eop_o <= strm_out_eop;
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strm_out_data_o <= STRM_TYPE_DDR2 & strm_tag & std_logic_vector(strm_out_size)
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when strm_out_hdr_en = '1' else ddr2_rd_data_i;
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end strm_ddr2;
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