#FPGA_PART=xc6slx45-3-csg324
CONFIG VCCAUX = 3.3;

##############################################################################
# SYSCLK Input
##############################################################################
NET "clk100" LOC = "L15" | IOSTANDARD = LVCMOS33 | TNM_NET = clk100;
TIMESPEC TS_clk100 = PERIOD "clk100" 100 MHz HIGH 50%;

# Constraint for RX0
NET "dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;

##############################################################################
# Mechanical Switches (SW)
##############################################################################
#NET "switch<0>"         LOC = "A10" |IOSTANDARD = LVCMOS33 ;
#NET "switch<1>"         LOC = "D14" |IOSTANDARD = LVCMOS33 ;
#NET "switch<2>"         LOC = "C14" | IOSTANDARD = LVCMOS33 ;
#NET "switch<3>"         LOC = "P15" | IOSTANDARD = LVCMOS33 ;

#############################################
## TMDS pairs for Atlys top OUT: J2 - Bank 0
#############################################
NET "tx0_tmds(3)"   LOC = "B6" |IOSTANDARD = TMDS_33 ; # Clock
NET "tx0_tmds_n(3)" LOC = "A6" |IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(2)"   LOC = "B8" |IOSTANDARD = TMDS_33 ; # Red
NET "tx0_tmds_n(2)" LOC = "A8" |IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(1)"   LOC = "C7" |IOSTANDARD = TMDS_33 ; # Green
NET "tx0_tmds_n(1)" LOC = "A7" |IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(0)"   LOC = "D8" |IOSTANDARD = TMDS_33 ; # Blue
NET "tx0_tmds_n(0)" LOC = "C8" |IOSTANDARD = TMDS_33 ;
#
###############################################
## TMDS pairs for Atlys top OUT: JA - Bank 2
## Use TML_33 to add output series termination
###############################################
#NET "tx1_tmds(3)"   LOC = "T9" |IOSTANDARD = TML_33; #TMDS_33 ; ## Clock
#NET "tx1_tmds_n(3)" LOC = "V9" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(2)"   LOC = "N5" |IOSTANDARD = TML_33; #TMDS_33 ; ## Red
#NET "tx1_tmds_n(2)" LOC = "P6" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(1)"   LOC = "T4" |IOSTANDARD = TML_33; #TMDS_33 ; ## Green
#NET "tx1_tmds_n(1)" LOC = "V4" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(0)"   LOC = "R3" |IOSTANDARD = TML_33; #TMDS_33 ; ## Blue
#NET "tx1_tmds_n(0)" LOC = "T3" |IOSTANDARD = TML_33; #TMDS_33 ; #
#
###################################################
## TMDS pairs for Atlys IN (FPGA Bank 1): J3
###################################################
#NET "rx1_tmds(3)"   LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
#NET "rx1_tmds_n(3)" LOC = "H18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(2)"   LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
#NET "rx1_tmds_n(2)" LOC = "J18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(1)"   LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green
#NET "rx1_tmds_n(1)" LOC = "L18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(0)"   LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue
#NET "rx1_tmds_n(0)" LOC = "K18" |IOSTANDARD = TMDS_33 ;
#
###############################################
## TMDS pairs for Atlys IN (FPGA Bank 0): J1
###############################################
NET "rx0_tmds(3)"   LOC = "D11" |IOSTANDARD = TMDS_33 ; # CLK
NET "rx0_tmds_n(3)" LOC = "C11" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(2)"   LOC = "B12" |IOSTANDARD = TMDS_33 ; # Red
NET "rx0_tmds_n(2)" LOC = "A12" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(1)"   LOC = "B11" |IOSTANDARD = TMDS_33 ; # Green
NET "rx0_tmds_n(1)" LOC = "A11" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(0)"   LOC = "G9"  |IOSTANDARD = TMDS_33 ; # Blue
NET "rx0_tmds_n(0)" LOC = "F9"  |IOSTANDARD = TMDS_33 ;
NET "rx0_scl"       LOC = "C13" |IOSTANDARD = LVCMOS33 ;
NET "rx0_sda"       LOC = "A13" |IOSTANDARD = LVCMOS33 ;


########################################
# Reset button and LEDs and Mechanical Switches (SW)
########################################
NET "rstbtn_n" LOC = "T15" |IOSTANDARD = LVCMOS33;
NET "led<0>"   LOC = "U18" |IOSTANDARD = LVCMOS33;
NET "led<1>"   LOC = "M14" |IOSTANDARD = LVCMOS33;
NET "led<2>"   LOC = "N14" |IOSTANDARD = LVCMOS33;
NET "led<3>"   LOC = "L14" |IOSTANDARD = LVCMOS33;
NET "led<4>"   LOC = "M13" |IOSTANDARD = LVCMOS33;
NET "led<5>"   LOC = "D4"  |IOSTANDARD = LVCMOS33;
NET "led<6>"   LOC = "P16" |IOSTANDARD = LVCMOS33;
NET "led<7>"   LOC = "N12" |IOSTANDARD = LVCMOS33;

# Multi-cycle paths for TX0 / encoder_0
#TIMEGRP "bramgrp_0" = RAMS(dvi_encoder_0/pixel2x/data_i<*>);
#TIMEGRP "fddbgrp_0" = FFS(dvi_encoder_0/pixel2x/db<*>);
#TIMEGRP "bramra_0"  = FFS(dvi_encoder_0/pixel2x/ra<*>);
#
#TIMESPEC "TS_ramdo_0" = FROM "bramgrp_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
#TIMESPEC "TS_ramra_0" = FROM "bramra_0"  TO "fddbgrp_0" TS_DVI_CLOCK0;
