236 lines
9.0 KiB
Makefile
236 lines
9.0 KiB
Makefile
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# #############################################################################
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# Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# #############################################################################
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PROJECT_DEFAULT = atlys_sig
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PROJECT_NAME ?= $(PROJECT_DEFAULT)
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PROJECT_DIR = $(PROJECT_NAME)_build
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PROJECT_SRC = ../src
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PROJECT_SRC_TOP = $(PROJECT_SRC)/top
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PROJECT_UCF = $(PROJECT_SRC_TOP)/$(PROJECT_NAME).ucf
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##### BUILD FLAGS #############################
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FPGA_PART = $(shell grep FPGA_PART $(PROJECT_UCF) | cut -d'=' -f2)
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XST_FLAGS = -intstyle silent
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NGDBUILD_FLAGS = -intstyle silent -dd _ngo
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NGDBUILD_FLAGS += $(if $(PROJECT_UCF),-uc ../,)$(PROJECT_UCF)
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MAP_FLAGS = -intstyle silent -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 \
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-global_opt off -mt off -ir off -pr off -lc off -power off
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PAR_FLAGS = -w -intstyle silent -ol high -mt off
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TRCE_FLAGS = -intstyle silent -v 3 -s 3 -n 3 -fastpaths
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BITGEN_FLAGS = -intstyle silent
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##### SOURCE FILES ############################
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COMMON_SRCS = $(PROJECT_SRC)/snippets/vhdl/rrarbiter.vhd
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FX2_TOP_DIR = ../../fx2/fpga
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USB_NGCS = $(FX2_TOP_DIR)/vendor/xilinx/usb_fifo_tx.ngc $(FX2_TOP_DIR)/vendor/xilinx/usb_fifo_rx.ngc \
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$(FX2_TOP_DIR)/vendor/xilinx/usb_fifo_tx_fin.ngc
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USB_SRCS = $(FX2_TOP_DIR)/f2p/strm_package.vhd $(FX2_TOP_DIR)/f2p/f2p_master.vhd \
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$(FX2_TOP_DIR)/f2p/f2p_strm_top.vhd $(FX2_TOP_DIR)/strm_ddr2/strm_ddr2.vhd \
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$(FX2_TOP_DIR)/strm_regfile/strm_regfile.vhd
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DVI_TOP_DIR = $(PROJECT_SRC)/dvi
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DVI_SRCS = $(DVI_TOP_DIR)/dvi_package.vhd $(DVI_TOP_DIR)/serdes_1_to_5_diff_data.vhd $(DVI_TOP_DIR)/DRAM16XN.vhd \
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$(DVI_TOP_DIR)/phsaligner.vhd $(DVI_TOP_DIR)/chnlbond.vhd $(DVI_TOP_DIR)/serdes_n_to_1.vhd \
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$(DVI_TOP_DIR)/encoder.vhd $(DVI_TOP_DIR)/decoder.vhd $(DVI_TOP_DIR)/convert_30to15_fifo.vhd \
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$(DVI_TOP_DIR)/dvi_encoder.vhd $(DVI_TOP_DIR)/dvi_decoder.vhd
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I2C_TOP_DIR = $(PROJECT_SRC)/i2c
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I2C_SRCS = $(I2C_TOP_DIR)/slave/i2c_slave.vhd $(I2C_TOP_DIR)/slave/i2c_rom.vhd
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DDR2_TOP_DIR = $(PROJECT_SRC)/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/
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DDR2_SRCS = $(DDR2_TOP_DIR)/iodrp_controller.vhd $(DDR2_TOP_DIR)/mcb_raw_wrapper.vhd \
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$(DDR2_TOP_DIR)/iodrp_mcb_controller.vhd $(DDR2_TOP_DIR)/mcb_soft_calibration_top.vhd \
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$(DDR2_TOP_DIR)/mcb_soft_calibration.vhd $(DDR2_TOP_DIR)/memc3_infrastructure.vhd \
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$(DDR2_TOP_DIR)/memc3_wrapper.vhd $(DDR2_TOP_DIR)/ddr2.vhd
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SIG_TOP_DIR = $(PROJECT_SRC)/sig
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SIG_NGCS = $(PROJECT_SRC)/vendor/xilinx/px_fifo.ngc
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SIG_SRCS = $(SIG_TOP_DIR)/sig_read.vhd $(SIG_TOP_DIR)/sig_write.vhd $(SIG_TOP_DIR)/sig.vhd \
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$(SIG_TOP_DIR)/ddr2dvi.vhd $(SIG_TOP_DIR)/dvi2ddr.vhd
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NGCS = $(USB_NGCS) $(SIG_NGCS)
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SRCS = $(NGCS:%.ngc=%.vhd) \
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$(COMMON_SRCS) \
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$(DVI_SRCS) \
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$(I2C_SRCS) \
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$(DDR2_SRCS) \
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$(USB_SRCS) \
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$(SIG_SRCS) \
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$(PROJECT_SRC_TOP)/$(PROJECT_NAME).vhd
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##### RUN SCRIPTS #############################
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define XST_SCRIPT
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set -tmpdir "tmp"
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set -xsthdpdir "xst"
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run
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-ifn $(PROJECT_NAME).prj
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-ofn $(PROJECT_NAME)
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-ofmt NGC
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-p $(FPGA_PART)
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-top $(PROJECT_NAME)
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-opt_mode Speed
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-opt_level 1
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-power NO
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-iuc NO
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-keep_hierarchy No
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-netlist_hierarchy As_Optimized
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-rtlview Yes
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-glob_opt AllClockNets
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-read_cores YES
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-write_timing_constraints NO
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-cross_clock_analysis NO
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-hierarchy_separator /
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-bus_delimiter <>
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-case Maintain
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-slice_utilization_ratio 100
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-bram_utilization_ratio 100
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-dsp_utilization_ratio 100
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-lc Auto
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-reduce_control_sets Auto
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-fsm_extract YES -fsm_encoding Auto
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-safe_implementation No
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-fsm_style LUT
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-ram_extract Yes
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-ram_style Auto
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-rom_extract Yes
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-shreg_extract YES
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-rom_style Auto
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-auto_bram_packing NO
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-resource_sharing YES
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-async_to_sync NO
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-shreg_min_size 2
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-use_dsp48 Auto
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-iobuf YES
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-max_fanout 100000
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-bufg 16
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-register_duplication YES
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-register_balancing NO
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-optimize_primitives NO
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-use_clock_enable Auto
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-use_sync_set Auto
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-use_sync_reset Auto
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-iob Auto
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-equivalent_register_removal YES
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-slice_utilization_ratio_maxmargin 5
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endef
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export XST_SCRIPT
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define BITGEN_FILE
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-w
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-g DebugBitstream:No
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-g Binary:no
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-g CRC:Enable
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-g Reset_on_err:No
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-g ConfigRate:2
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-g ProgPin:PullUp
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-g TckPin:PullUp
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-g TdiPin:PullUp
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-g TdoPin:PullUp
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-g TmsPin:PullUp
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-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
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-g ExtMasterCclk_en:No
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-g SPI_buswidth:1
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-g TIMER_CFG:0xFFFF
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-g multipin_wakeup:No
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-g StartUpClk:CClk
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-g DONE_cycle:4
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-g GTS_cycle:5
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-g GWE_cycle:6
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-g LCK_cycle:NoWait
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-g Security:None
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-g DonePipe:Yes
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-g DriveDone:No
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-g en_sw_gsr:No
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-g drive_awake:No
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-g sw_clk:Startupclk
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-g sw_gwe_cycle:5
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-g sw_gts_cycle:4
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endef
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export BITGEN_FILE
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##### PRINT ###################################
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PW=\033[1m\033[0m
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GR=\E[40;32m
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WH=\E[40;37m
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B=\033[1m
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pr_info = "$(B) $(GR)[$(1)]\t $(WH)$(2)$(PW)"
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TARGETS = build help prep syn ngd map par trce bit flash clean
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VAR_TARGETS = $(PROJECT_DIR)/tmp $(PROJECT_DIR)/$(PROJECT_NAME).ngc $(PROJECT_DIR)/$(PROJECT_NAME).ngd \
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$(PROJECT_DIR)/$(PROJECT_NAME)_map.ncd $(PROJECT_DIR)/$(PROJECT_NAME).pcf \
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$(PROJECT_DIR)/$(PROJECT_NAME).ncd $(PROJECT_DIR)/$(PROJECT_NAME).twr \
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$(PROJECT_DIR)/$(PROJECT_NAME).bit
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##### BUILD RULES #############################
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.SILENT: help $(if $(V),,$(TARGETS) $(VAR_TARGETS))
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.PHONY: $(TARGETS)
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help:
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echo -e "$$ make PROJECT_NAME=<top-file> <rule> [V=1]"
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echo -e "\tprojects (*=default) .. : $(subst $(PROJECT_DEFAULT),*$(PROJECT_DEFAULT),$(subst $(PROJECT_SRC_TOP)/,,$(subst .ucf,,$(wildcard $(PROJECT_SRC_TOP)/*.ucf))))"
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echo -e "\trule .................. : $(TARGETS)"
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echo -e "\tV ..................... : verbose"
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prep $(PROJECT_DIR)/tmp: $(SRCS)
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echo -e $(call pr_info,PREP,Build ENV for $(PROJECT_NAME))
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mkdir -p $(PROJECT_DIR)/tmp
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rm -f $(PROJECT_DIR)/$(PROJECT_NAME).prj
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for s in $(SRCS); do \
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if [ "$${s##*.}" = "vhd" ]; then echo "vhdl work \"../$$s\"" >> $(PROJECT_DIR)/$(PROJECT_NAME).prj; fi; \
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if [ "$${s##*.}" = "v" ]; then echo "verilog work \"../$$s\"" >> $(PROJECT_DIR)/$(PROJECT_NAME).prj; fi; \
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done
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echo "$$XST_SCRIPT" > $(PROJECT_DIR)/$(PROJECT_NAME).xst
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syn $(PROJECT_DIR)/$(PROJECT_NAME).ngc: $(PROJECT_DIR)/tmp
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echo -e $(call pr_info,NGC,Link prebuild IP Cores)
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for n in $(NGCS); do ln -sf ../$$n $(PROJECT_DIR)/${n##*/}; done
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echo -e $(call pr_info,XST,Synthesis)
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cd $(PROJECT_DIR) && xst $(XST_FLAGS) -ifn $(PROJECT_NAME).xst -ofn $(PROJECT_NAME).syr
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ngd $(PROJECT_DIR)/$(PROJECT_NAME).ngd: $(PROJECT_DIR)/$(PROJECT_NAME).ngc $(PROJECT_UCF)
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echo -e $(call pr_info,NGD,Native Generic Database)
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cd $(PROJECT_DIR) && ngdbuild $(NGDBUILD_FLAGS) -p $(FPGA_PART) $(PROJECT_NAME).ngc $(PROJECT_NAME).ngd
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map $(PROJECT_DIR)/$(PROJECT_NAME)_map.ncd $(PROJECT_DIR)/$(PROJECT_NAME).pcf: $(PROJECT_DIR)/$(PROJECT_NAME).ngd
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echo -e $(call pr_info,MAP,Mapping Logic)
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cd $(PROJECT_DIR) && map $(MAP_FLAGS) -p $(FPGA_PART) -o $(PROJECT_NAME)_map.ncd $(PROJECT_NAME).ngd $(PROJECT_NAME).pcf
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par $(PROJECT_DIR)/$(PROJECT_NAME).ncd: $(PROJECT_DIR)/$(PROJECT_NAME)_map.ncd $(PROJECT_DIR)/$(PROJECT_NAME).pcf
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echo -e $(call pr_info,PAR,Place and Route)
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cd $(PROJECT_DIR) && par $(PAR_FLAGS) $(PROJECT_NAME)_map.ncd $(PROJECT_NAME).ncd $(PROJECT_NAME).pcf
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trce $(PROJECT_DIR)/$(PROJECT_NAME).twr: $(PROJECT_DIR)/$(PROJECT_NAME).ncd
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echo -e $(call pr_info,TRCE,Timing analyzes)
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cd $(PROJECT_DIR) && trce $(TRCE_FLAGS) -xml $(PROJECT_NAME).twx $(PROJECT_NAME).ncd -o $(PROJECT_NAME).twr $(PROJECT_NAME).pcf
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bit build $(PROJECT_DIR)/$(PROJECT_NAME).bit: $(PROJECT_DIR)/$(PROJECT_NAME).ncd $(PROJECT_DIR)/$(PROJECT_NAME).twr
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echo -e $(call pr_info,BITG,Bitfile Generation)
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echo "$$BITGEN_FILE" > $(PROJECT_DIR)/$(PROJECT_NAME).ut
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cd $(PROJECT_DIR) && bitgen $(BITGEN_FLAGS) -f $(PROJECT_NAME).ut $(PROJECT_NAME).ncd
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flash: $(PROJECT_DIR)/$(PROJECT_NAME).bit
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echo -e "setmode -bs\nsetCable -p auto\nIdentify -inferir\nidentifyMPM\nassignFile -p 1 -file "$$PWD/$(PROJECT_DIR)/$(PROJECT_NAME).bit"\nprogram -p 1\nquit\n" | impact -batch
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clean:
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echo -e $(call pr_info,RM,delete project directory)
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rm -rf $(PROJECT_DIR)
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