public/hdet
1
0
Fork 0
Code Pull Requests Releases Activity
4e27d11176
hdet/fpga/syn/syn.gise

259 lines
18 KiB
Plaintext
Raw Normal View History

initial HDET design
2014-02-17 13:33:46 +01:00
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="syn.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_LOG" xil_pn:name="../../fx2/fpga/vendor/xilinx/coregen.log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.ngc" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.vhd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.ngc" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.vhd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="../src/ddr2/coregen.log"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="../src/vendor/xilinx/px_fifo.asy" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/px_fifo.ngc" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../src/vendor/xilinx/px_fifo.sym" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/px_fifo.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="../src/vendor/xilinx/px_fifo.vho" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/usb_fifo_rx.ngc" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/usb_fifo_rx.vhd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/usb_fifo_tx.ngc" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/usb_fifo_tx.vhd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="atlys_sig.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="atlys_sig.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="atlys_sig.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="atlys_sig.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="atlys_sig.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="atlys_sig.lso"/>
<file xil_pn:fileType="FILE_MSK" xil_pn:name="atlys_sig.msk"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="atlys_sig.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="atlys_sig.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="atlys_sig.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="atlys_sig.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="atlys_sig.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="atlys_sig.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="atlys_sig.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="atlys_sig.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="atlys_sig.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="atlys_sig.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="atlys_sig.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="atlys_sig.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="atlys_sig.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="atlys_sig.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="atlys_sig.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="atlys_sig.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="atlys_sig_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="atlys_sig_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="atlys_sig_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="atlys_sig_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_PSR" xil_pn:name="atlys_sig_map.psr"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="atlys_sig_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="atlys_sig_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="atlys_sig_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="atlys_sig_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="atlys_sig_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6498325036265346234" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381750723" xil_pn:in_ck="-4990497755435147446" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8579041901420796151" xil_pn:start_ts="1381750722">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.ngc"/>
<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.vhd"/>
<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.ngc"/>
<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.vhd"/>
<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc"/>
<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_controller.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_mcb_controller.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_raw_wrapper.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration_top.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_infrastructure.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_wrapper.vhd"/>
<outfile xil_pn:name="../src/vendor/xilinx/px_fifo.ngc"/>
<outfile xil_pn:name="../src/vendor/xilinx/px_fifo.vhd"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:in_ck="-3266226745153874044" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7532054547514773688" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:in_ck="-3266226745153874044" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-616900325625012223" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381750752" xil_pn:in_ck="-5754007203490239776" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3327302063185124304" xil_pn:start_ts="1381750723">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="atlys_sig.lso"/>
<outfile xil_pn:name="atlys_sig.ngc"/>
<outfile xil_pn:name="atlys_sig.ngr"/>
<outfile xil_pn:name="atlys_sig.prj"/>
<outfile xil_pn:name="atlys_sig.stx"/>
<outfile xil_pn:name="atlys_sig.syr"/>
<outfile xil_pn:name="atlys_sig.xst"/>
<outfile xil_pn:name="atlys_sig_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1379695258" xil_pn:in_ck="-2812728212376607396" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4408915874172682627" xil_pn:start_ts="1379695258">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1381750764" xil_pn:in_ck="-5271234473535174591" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7713896191513598818" xil_pn:start_ts="1381750752">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="atlys_sig.bld"/>
<outfile xil_pn:name="atlys_sig.ngd"/>
<outfile xil_pn:name="atlys_sig_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1381750841" xil_pn:in_ck="-2821415870385197163" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-8360921270489510961" xil_pn:start_ts="1381750764">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="atlys_sig.pcf"/>
<outfile xil_pn:name="atlys_sig_map.map"/>
<outfile xil_pn:name="atlys_sig_map.mrp"/>
<outfile xil_pn:name="atlys_sig_map.ncd"/>
<outfile xil_pn:name="atlys_sig_map.ngm"/>
<outfile xil_pn:name="atlys_sig_map.psr"/>
<outfile xil_pn:name="atlys_sig_map.xrpt"/>
<outfile xil_pn:name="atlys_sig_summary.xml"/>
<outfile xil_pn:name="atlys_sig_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1381750888" xil_pn:in_ck="4790132884118110510" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1381750841">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="atlys_sig.ncd"/>
<outfile xil_pn:name="atlys_sig.pad"/>
<outfile xil_pn:name="atlys_sig.par"/>
<outfile xil_pn:name="atlys_sig.ptwx"/>
<outfile xil_pn:name="atlys_sig.unroutes"/>
<outfile xil_pn:name="atlys_sig.xpi"/>
<outfile xil_pn:name="atlys_sig_pad.csv"/>
<outfile xil_pn:name="atlys_sig_pad.txt"/>
<outfile xil_pn:name="atlys_sig_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1379698920" xil_pn:in_ck="1798662901162223602" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-7216915341624083389" xil_pn:start_ts="1379698874">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1379693527" xil_pn:in_ck="1798662901162210748" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1379693525">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1375166772" xil_pn:in_ck="-2821415870385197295" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1375166762">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1381750888" xil_pn:in_ck="-2821415870385197295" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381750879">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="atlys_sig.twr"/>
<outfile xil_pn:name="atlys_sig.twx"/>
</transform>
<transform xil_pn:end_ts="1375175447" xil_pn:in_ck="4790132884118110510" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791353" xil_pn:start_ts="1375175447">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1377159094" xil_pn:in_ck="-2821415870385197163" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1377159094">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
</transforms>
</generated_project>
Copy Permalink