From d94a97b112dfe52a01daeefdc02bdbb53dd87e59 Mon Sep 17 00:00:00 2001
From: Benjamin Krill <ben@codiert.org>
Date: Mon, 17 Feb 2014 13:33:46 +0100
Subject: [PATCH] initial HDET design

---
 .gitmodules                                   |    9 +
 README                                        |   12 +
 fpga/src/dvi                                  |    1 +
 fpga/src/i2c/master/i2c_master_bit_ctrl.vhd   |  496 ++
 fpga/src/i2c/master/i2c_master_byte_ctrl.vhd  |  371 +
 fpga/src/i2c/master/i2c_master_top.vhd        |  366 +
 fpga/src/i2c/master/i2c_specs.pdf             |  Bin 0 -> 211471 bytes
 fpga/src/i2c/master/i2c_wrapper.vhdl          |  193 +
 fpga/src/i2c/sim/sim_tb.vhd                   |  131 +
 fpga/src/i2c/slave/hdmi_in.dat                |  256 +
 fpga/src/i2c/slave/hdmi_in_syncmaster191t.dat |  128 +
 fpga/src/i2c/slave/hdmi_in_syncmaster940t.dat |  256 +
 fpga/src/i2c/slave/i2c_rom.vhd                |   80 +
 fpga/src/i2c/slave/i2c_slave.vhd              |  282 +
 fpga/src/sig/ddr2dvi.vhd                      |  194 +
 fpga/src/sig/dvi2ddr.vhd                      |  112 +
 fpga/src/sig/sig.vhd                          |  127 +
 fpga/src/sig/sig_read.vhd                     |  281 +
 fpga/src/sig/sig_read_tb.vhd                  |  263 +
 fpga/src/sig/sig_tb.vhd                       |  112 +
 fpga/src/sig/sig_write.vhd                    |  171 +
 fpga/src/snippets                             |    1 +
 fpga/src/top/atlys.ucf                        |   93 +
 fpga/src/top/atlys.vhd                        |  275 +
 fpga/src/top/atlys_sig.ucf                    |  196 +
 fpga/src/top/atlys_sig.vhd                    |  466 ++
 fpga/src/top/dmb.ucf                          |   98 +
 fpga/src/top/dmb.vhd                          |  345 +
 fpga/src/vendor/xilinx/atlys_ddr2/coregen.cgp |    9 +
 .../vendor/xilinx/atlys_ddr2/create_ddr2.tcl  |   37 +
 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.gise   |   49 +
 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.ncf    |  164 +
 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.vho    |  365 +
 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xco    |   49 +
 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xise   |  123 +
 .../xilinx/atlys_ddr2/ddr2/docs/ug388.pdf     |  Bin 0 -> 2172724 bytes
 .../xilinx/atlys_ddr2/ddr2/docs/ug416.pdf     |  Bin 0 -> 80254 bytes
 .../ddr2/example_design/datasheet.txt         |   72 +
 .../ddr2/example_design/par/create_ise.sh     |   72 +
 .../ddr2/example_design/par/example_top.ucf   |  172 +
 .../ddr2/example_design/par/icon_coregen.xco  |   48 +
 .../ddr2/example_design/par/ila_coregen.xco   |  131 +
 .../ddr2/example_design/par/ise_flow.sh       |   86 +
 .../ddr2/example_design/par/ise_run.txt       |   58 +
 .../ddr2/example_design/par/makeproj.sh       |    2 +
 .../example_design/par/mem_interface_top.ut   |   22 +
 .../ddr2/example_design/par/readme.txt        |  146 +
 .../ddr2/example_design/par/rem_files.sh      |  169 +
 .../ddr2/example_design/par/set_ise_prop.tcl  |  106 +
 .../ddr2/example_design/par/vio_coregen.xco   |   51 +
 .../ddr2/example_design/rtl/example_top.vhd   | 1059 +++
 .../example_design/rtl/iodrp_controller.vhd   |  372 +
 .../rtl/iodrp_mcb_controller.vhd              |  517 ++
 .../example_design/rtl/mcb_raw_wrapper.vhd    | 7117 +++++++++++++++++
 .../rtl/mcb_soft_calibration.vhd              | 1774 ++++
 .../rtl/mcb_soft_calibration_top.vhd          |  428 +
 .../rtl/memc3_infrastructure.vhd              |  334 +
 .../ddr2/example_design/rtl/memc3_tb_top.vhd  | 1070 +++
 .../ddr2/example_design/rtl/memc3_wrapper.vhd | 1013 +++
 .../example_design/rtl/traffic_gen/afifo.vhd  |  280 +
 .../rtl/traffic_gen/cmd_gen.vhd               | 1077 +++
 .../rtl/traffic_gen/cmd_prbs_gen.vhd          |  247 +
 .../rtl/traffic_gen/data_prbs_gen.vhd         |  135 +
 .../rtl/traffic_gen/init_mem_pattern_ctr.vhd  |  620 ++
 .../rtl/traffic_gen/mcb_flow_control.vhd      |  539 ++
 .../rtl/traffic_gen/mcb_traffic_gen.vhd       | 1001 +++
 .../rtl/traffic_gen/rd_data_gen.vhd           |  434 +
 .../rtl/traffic_gen/read_data_path.vhd        |  638 ++
 .../rtl/traffic_gen/read_posted_fifo.vhd      |  339 +
 .../rtl/traffic_gen/sp6_data_gen.vhd          |  793 ++
 .../rtl/traffic_gen/tg_status.vhd             |  142 +
 .../rtl/traffic_gen/v6_data_gen.vhd           | 3276 ++++++++
 .../rtl/traffic_gen/wr_data_gen.vhd           |  511 ++
 .../rtl/traffic_gen/write_data_path.vhd       |  210 +
 .../sim/functional/ddr2_model_c3.v            | 2031 +++++
 .../functional/ddr2_model_parameters_c3.vh    | 1394 ++++
 .../example_design/sim/functional/isim.sh     |   70 +
 .../example_design/sim/functional/isim.tcl    |   72 +
 .../example_design/sim/functional/readme.txt  |  131 +
 .../ddr2/example_design/sim/functional/sim.do |  144 +
 .../sim/functional/sim_tb_top.vhd             |  445 ++
 .../sim/functional/timing_sim.sh              |   72 +
 .../synth/mem_interface_top_synp.sdc          |   36 +
 .../ddr2/example_design/synth/script_synp.tcl |   56 +
 .../atlys_ddr2/ddr2/user_design/datasheet.txt |   72 +
 .../ddr2/user_design/par/create_ise.sh        |   72 +
 .../atlys_ddr2/ddr2/user_design/par/ddr2.ucf  |  163 +
 .../ddr2/user_design/par/icon_coregen.xco     |   48 +
 .../ddr2/user_design/par/ila_coregen.xco      |  131 +
 .../ddr2/user_design/par/ise_flow.sh          |   86 +
 .../ddr2/user_design/par/ise_run.txt          |   58 +
 .../ddr2/user_design/par/makeproj.sh          |    2 +
 .../ddr2/user_design/par/mem_interface_top.ut |   22 +
 .../ddr2/user_design/par/readme.txt           |  146 +
 .../ddr2/user_design/par/rem_files.sh         |  169 +
 .../ddr2/user_design/par/set_ise_prop.tcl     |   90 +
 .../ddr2/user_design/par/vio_coregen.xco      |   51 +
 .../atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd  |  822 ++
 .../ddr2/user_design/rtl/iodrp_controller.vhd |  372 +
 .../user_design/rtl/iodrp_mcb_controller.vhd  |  517 ++
 .../ddr2/user_design/rtl/mcb_raw_wrapper.vhd  | 7117 +++++++++++++++++
 .../user_design/rtl/mcb_soft_calibration.vhd  | 1774 ++++
 .../rtl/mcb_soft_calibration_top.vhd          |  428 +
 .../user_design/rtl/memc3_infrastructure.vhd  |  334 +
 .../ddr2/user_design/rtl/memc3_wrapper.vhd    | 1013 +++
 .../atlys_ddr2/ddr2/user_design/sim/afifo.vhd |  280 +
 .../ddr2/user_design/sim/cmd_gen.vhd          | 1077 +++
 .../ddr2/user_design/sim/cmd_prbs_gen.vhd     |  247 +
 .../ddr2/user_design/sim/data_prbs_gen.vhd    |  135 +
 .../ddr2/user_design/sim/ddr2_model_c3.v      | 2031 +++++
 .../sim/ddr2_model_parameters_c3.vh           | 1394 ++++
 .../user_design/sim/init_mem_pattern_ctr.vhd  |  620 ++
 .../atlys_ddr2/ddr2/user_design/sim/isim.sh   |   70 +
 .../atlys_ddr2/ddr2/user_design/sim/isim.tcl  |   72 +
 .../ddr2/user_design/sim/mcb_flow_control.vhd |  539 ++
 .../ddr2/user_design/sim/mcb_traffic_gen.vhd  | 1001 +++
 .../ddr2/user_design/sim/memc3_tb_top.vhd     | 1070 +++
 .../ddr2/user_design/sim/rd_data_gen.vhd      |  434 +
 .../ddr2/user_design/sim/read_data_path.vhd   |  638 ++
 .../ddr2/user_design/sim/read_posted_fifo.vhd |  339 +
 .../ddr2/user_design/sim/readme.txt           |  131 +
 .../atlys_ddr2/ddr2/user_design/sim/sim.do    |  141 +
 .../ddr2/user_design/sim/sim_tb_top.vhd       |  975 +++
 .../ddr2/user_design/sim/sp6_data_gen.vhd     |  793 ++
 .../ddr2/user_design/sim/tg_status.vhd        |  142 +
 .../ddr2/user_design/sim/v6_data_gen.vhd      | 3276 ++++++++
 .../ddr2/user_design/sim/wr_data_gen.vhd      |  511 ++
 .../ddr2/user_design/sim/write_data_path.vhd  |  210 +
 .../synth/mem_interface_top_synp.sdc          |   20 +
 .../ddr2/user_design/synth/script_synp.tcl    |   40 +
 .../vendor/xilinx/atlys_ddr2/ddr2_flist.txt   |  112 +
 .../vendor/xilinx/atlys_ddr2/ddr2_readme.txt  |   45 +
 .../vendor/xilinx/atlys_ddr2/ddr2_xmdf.tcl    |   78 +
 .../vendor/xilinx/atlys_ddr2/edit_ddr2.tcl    |   37 +
 fpga/src/vendor/xilinx/px_fifo.ngc            |    3 +
 fpga/src/vendor/xilinx/px_fifo.vhd            |  286 +
 fpga/src/vendor/xilinx/px_fifo.xco            |  213 +
 fpga/syn/Makefile                             |  235 +
 fpga/syn/syn.gise                             |  258 +
 fpga/syn/syn.xise                             |  513 ++
 fpga/tools/edid2dat.sh                        |   31 +
 fpga/tools/edid_extract_timing.sh             |   61 +
 fx2                                           |    1 +
 143 files changed, 67169 insertions(+)
 create mode 100644 .gitmodules
 create mode 100644 README
 create mode 160000 fpga/src/dvi
 create mode 100644 fpga/src/i2c/master/i2c_master_bit_ctrl.vhd
 create mode 100644 fpga/src/i2c/master/i2c_master_byte_ctrl.vhd
 create mode 100644 fpga/src/i2c/master/i2c_master_top.vhd
 create mode 100644 fpga/src/i2c/master/i2c_specs.pdf
 create mode 100644 fpga/src/i2c/master/i2c_wrapper.vhdl
 create mode 100644 fpga/src/i2c/sim/sim_tb.vhd
 create mode 100644 fpga/src/i2c/slave/hdmi_in.dat
 create mode 100644 fpga/src/i2c/slave/hdmi_in_syncmaster191t.dat
 create mode 100644 fpga/src/i2c/slave/hdmi_in_syncmaster940t.dat
 create mode 100644 fpga/src/i2c/slave/i2c_rom.vhd
 create mode 100644 fpga/src/i2c/slave/i2c_slave.vhd
 create mode 100644 fpga/src/sig/ddr2dvi.vhd
 create mode 100644 fpga/src/sig/dvi2ddr.vhd
 create mode 100644 fpga/src/sig/sig.vhd
 create mode 100644 fpga/src/sig/sig_read.vhd
 create mode 100644 fpga/src/sig/sig_read_tb.vhd
 create mode 100644 fpga/src/sig/sig_tb.vhd
 create mode 100644 fpga/src/sig/sig_write.vhd
 create mode 160000 fpga/src/snippets
 create mode 100644 fpga/src/top/atlys.ucf
 create mode 100644 fpga/src/top/atlys.vhd
 create mode 100644 fpga/src/top/atlys_sig.ucf
 create mode 100644 fpga/src/top/atlys_sig.vhd
 create mode 100644 fpga/src/top/dmb.ucf
 create mode 100644 fpga/src/top/dmb.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/coregen.cgp
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/create_ddr2.tcl
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.gise
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.ncf
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.vho
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xco
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xise
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/docs/ug388.pdf
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/docs/ug416.pdf
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/datasheet.txt
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/create_ise.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/example_top.ucf
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/icon_coregen.xco
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ila_coregen.xco
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ise_flow.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ise_run.txt
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/makeproj.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/mem_interface_top.ut
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/readme.txt
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/rem_files.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/set_ise_prop.tcl
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/vio_coregen.xco
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/example_top.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_controller.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_mcb_controller.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_raw_wrapper.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_soft_calibration.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_soft_calibration_top.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_infrastructure.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_tb_top.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_wrapper.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/afifo.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/cmd_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/cmd_prbs_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/data_prbs_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/init_mem_pattern_ctr.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_flow_control.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/rd_data_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_data_path.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_posted_fifo.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/sp6_data_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/tg_status.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/v6_data_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/wr_data_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/write_data_path.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/ddr2_model_c3.v
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/ddr2_model_parameters_c3.vh
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.sh
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.tcl
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/readme.txt
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim.do
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim_tb_top.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/timing_sim.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/mem_interface_top_synp.sdc
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/script_synp.tcl
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/datasheet.txt
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/create_ise.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ddr2.ucf
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/icon_coregen.xco
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ila_coregen.xco
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_flow.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_run.txt
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/makeproj.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/mem_interface_top.ut
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/readme.txt
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/rem_files.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/set_ise_prop.tcl
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/vio_coregen.xco
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_controller.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_mcb_controller.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_raw_wrapper.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration_top.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_infrastructure.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_wrapper.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/afifo.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/cmd_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/cmd_prbs_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/data_prbs_gen.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/ddr2_model_c3.v
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/ddr2_model_parameters_c3.vh
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/init_mem_pattern_ctr.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/isim.sh
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/isim.tcl
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/mcb_flow_control.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/mcb_traffic_gen.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/memc3_tb_top.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/rd_data_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/read_data_path.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/read_posted_fifo.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/readme.txt
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sim.do
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sim_tb_top.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sp6_data_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/tg_status.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/v6_data_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/wr_data_gen.vhd
 create mode 100755 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/write_data_path.vhd
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/synth/mem_interface_top_synp.sdc
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/synth/script_synp.tcl
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2_flist.txt
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2_readme.txt
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/ddr2_xmdf.tcl
 create mode 100644 fpga/src/vendor/xilinx/atlys_ddr2/edit_ddr2.tcl
 create mode 100644 fpga/src/vendor/xilinx/px_fifo.ngc
 create mode 100644 fpga/src/vendor/xilinx/px_fifo.vhd
 create mode 100644 fpga/src/vendor/xilinx/px_fifo.xco
 create mode 100644 fpga/syn/Makefile
 create mode 100644 fpga/syn/syn.gise
 create mode 100644 fpga/syn/syn.xise
 create mode 100755 fpga/tools/edid2dat.sh
 create mode 100755 fpga/tools/edid_extract_timing.sh
 create mode 160000 fx2

diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..335ddf8
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,9 @@
+[submodule "fpga/src/dvi"]
+	path = fpga/src/dvi
+	url = http://dev.krll.de/git/hdmi
+[submodule "fx2"]
+	path = fx2
+	url = http://dev.krll.de/git/fx2
+[submodule "fpga/src/snippets"]
+	path = fpga/src/snippets
+	url = http://dev.krll.de/git/snippets
diff --git a/README b/README
new file mode 100644
index 0000000..84cf448
--- /dev/null
+++ b/README
@@ -0,0 +1,12 @@
+HDMI Experimental Toolkit
+
+-- SOURCE CODE --------------------------------------------
+- git submodules:
+http://dev.krll.de/git/hdmi
+http://dev.krll.de/git/fx2
+http://dev.krll.de/git/snippets
+
+- clone:
+git clone ssh://dev.krll.de//home/shared/dev/hmb.git/
+git submodule init
+git submodule update
diff --git a/fpga/src/dvi b/fpga/src/dvi
new file mode 160000
index 0000000..6a2d616
--- /dev/null
+++ b/fpga/src/dvi
@@ -0,0 +1 @@
+Subproject commit 6a2d616d8aed15ba241dd9ea65518ecf6f128961
diff --git a/fpga/src/i2c/master/i2c_master_bit_ctrl.vhd b/fpga/src/i2c/master/i2c_master_bit_ctrl.vhd
new file mode 100644
index 0000000..0f786b4
--- /dev/null
+++ b/fpga/src/i2c/master/i2c_master_bit_ctrl.vhd
@@ -0,0 +1,496 @@
+---------------------------------------------------------------------
+----                                                             ----
+----  WISHBONE revB2 I2C Master Core; bit-controller             ----
+----                                                             ----
+----                                                             ----
+----  Author: Richard Herveille                                  ----
+----          richard@asics.ws                                   ----
+----          www.asics.ws                                       ----
+----                                                             ----
+----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
+----                                                             ----
+---------------------------------------------------------------------
+----                                                             ----
+---- Copyright (C) 2000 Richard Herveille                        ----
+----                    richard@asics.ws                         ----
+----                                                             ----
+---- This source file may be used and distributed without        ----
+---- restriction provided that this copyright statement is not   ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer.----
+----                                                             ----
+----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
+---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
+---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
+---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
+---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
+---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
+---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
+---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
+---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
+---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
+---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
+---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
+---- POSSIBILITY OF SUCH DAMAGE.                                 ----
+----                                                             ----
+---------------------------------------------------------------------
+
+--  CVS Log
+--
+--  $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
+--
+--  $Date: 2006/10/11 12:10:13 $
+--  $Revision: 1.14 $
+--  $Author: rherveille $
+--  $Locker:  $
+--  $State: Exp $
+--
+-- Change History:
+--               $Log: i2c_master_bit_ctrl.vhd,v $
+--               Revision 1.14  2006/10/11 12:10:13  rherveille
+--               Added missing semicolons ';' on endif
+--
+--               Revision 1.13  2006/10/06 10:48:24  rherveille
+--               fixed short scl high pulse after clock stretch
+--
+--               Revision 1.12  2004/05/07 11:53:31  rherveille
+--               Fixed previous fix :) Made a variable vs signal mistake.
+--
+--               Revision 1.11  2004/05/07 11:04:00  rherveille
+--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
+--
+--               Revision 1.10  2004/02/27 07:49:43  rherveille
+--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
+--
+--               Revision 1.9  2003/08/12 14:48:37  rherveille
+--               Forgot an 'end if' :-/
+--
+--               Revision 1.8  2003/08/09 07:01:13  rherveille
+--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+--               Fixed a potential bug in the byte controller's host-acknowledge generation.
+--
+--               Revision 1.7  2003/02/05 00:06:02  rherveille
+--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
+--
+--               Revision 1.6  2003/02/01 02:03:06  rherveille
+--               Fixed a few 'arbitration lost' bugs. VHDL version only.
+--
+--               Revision 1.5  2002/12/26 16:05:47  rherveille
+--               Core is now a Multimaster I2C controller.
+--
+--               Revision 1.4  2002/11/30 22:24:37  rherveille
+--               Cleaned up code
+--
+--               Revision 1.3  2002/10/30 18:09:53  rherveille
+--               Fixed some reported minor start/stop generation timing issuess.
+--
+--               Revision 1.2  2002/06/15 07:37:04  rherveille
+--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
+--
+--               Revision 1.1  2001/11/05 12:02:33  rherveille
+--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
+--               Code updated, is now up-to-date to doc. rev.0.4.
+--               Added headers.
+--
+
+
+--
+-------------------------------------
+-- Bit controller section
+------------------------------------
+--
+-- Translate simple commands into SCL/SDA transitions
+-- Each command has 5 states, A/B/C/D/idle
+--
+-- start:    SCL  ~~~~~~~~~~~~~~\____
+--	     SDA  XX/~~~~~~~\______
+--	          x | A | B | C | D | i
+--
+-- repstart  SCL  ______/~~~~~~~\___
+--	     SDA  __/~~~~~~~\______
+--	          x | A | B | C | D | i
+--
+-- stop      SCL  _______/~~~~~~~~~~~
+--	     SDA  ==\___________/~~~~~
+--	          x | A | B | C | D | i
+--
+--- write    SCL  ______/~~~~~~~\____
+--	     SDA  XXX===============XX
+--	          x | A | B | C | D | i
+--
+--- read     SCL  ______/~~~~~~~\____
+--	     SDA  XXXXXXX=XXXXXXXXXXX
+--	          x | A | B | C | D | i
+--
+
+-- Timing:      Normal mode     Fast mode
+-----------------------------------------------------------------
+-- Fscl         100KHz          400KHz
+-- Th_scl       4.0us           0.6us   High period of SCL
+-- Tl_scl       4.7us           1.3us   Low period of SCL
+-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
+-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
+-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_Logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity i2c_master_bit_ctrl is
+	port (
+		clk    : in std_logic;
+		rst    : in std_logic;
+		nReset : in std_logic;
+		ena    : in std_logic;				-- core enable signal
+
+		clk_cnt : in unsigned(15 downto 0);		-- clock prescale value
+
+		cmd     : in std_logic_vector(3 downto 0);
+		cmd_ack : out std_logic; -- command completed
+		busy    : out std_logic; -- i2c bus busy
+		al      : out std_logic; -- arbitration lost
+
+		din  : in std_logic;
+		dout : out std_logic;
+
+		-- i2c lines
+		scl_i   : in std_logic;  -- i2c clock line input
+		scl_o   : out std_logic; -- i2c clock line output
+		scl_oen : out std_logic; -- i2c clock line output enable, active low
+		sda_i   : in std_logic;  -- i2c data line input
+		sda_o   : out std_logic; -- i2c data line output
+		sda_oen : out std_logic  -- i2c data line output enable, active low
+	);
+end entity i2c_master_bit_ctrl;
+
+architecture structural of i2c_master_bit_ctrl is
+	constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
+	constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
+	constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
+	constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
+	constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
+
+	type states is (idle, start_a, start_b, start_c, start_d, start_e,
+	                stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
+	signal c_state : states;
+
+	signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
+	signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
+	signal dscl_oen           : std_logic;          -- delayed scl_oen signals
+	signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
+	signal clk_en, slave_wait : std_logic;          -- clock generation signals
+	signal ial                : std_logic;          -- internal arbitration lost signal
+--	signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
+	signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
+
+begin
+	-- whenever the slave is not ready it can delay the cycle by pulling SCL low
+	-- delay scl_oen
+	process (clk)
+	begin
+	    if (clk'event and clk = '1') then
+	      dscl_oen <= iscl_oen;
+	    end if;
+	end process;
+	slave_wait <= dscl_oen and not sSCL;
+
+	-- generate clk enable signal
+	gen_clken: process(clk, nReset)
+	begin
+	    if (nReset = '0') then
+	      cnt    <= (others => '0');
+	      clk_en <= '1';
+	    elsif (clk'event and clk = '1') then
+	      if (rst = '1') then
+	        cnt    <= (others => '0');
+	        clk_en <= '1';
+	      elsif ( (cnt = 0) or (ena = '0') ) then
+	        cnt    <= clk_cnt;
+	        clk_en <= '1';
+	      elsif (slave_wait = '1') then
+	        cnt    <= cnt;
+	        clk_en <= '0';
+	      else
+	        cnt    <= cnt -1;
+	        clk_en <= '0';
+	      end if;
+	    end if;
+	end process gen_clken;
+
+
+	-- generate bus status controller
+	bus_status_ctrl: block
+	  signal dSCL, dSDA          : std_logic;  -- delayes sSCL and sSDA
+	  signal sta_condition       : std_logic;  -- start detected
+	  signal sto_condition       : std_logic;  -- stop detected
+	  signal cmd_stop            : std_logic;  -- STOP command
+	  signal ibusy               : std_logic;  -- internal busy signal
+	begin
+	    -- synchronize SCL and SDA inputs
+	    synch_scl_sda: process(clk, nReset)
+	    begin
+	        if (nReset = '0') then
+	          sSCL <= '1';
+	          sSDA <= '1';
+
+	          dSCL <= '1';
+	          dSDA <= '1';
+	        elsif (clk'event and clk = '1') then
+	          if (rst = '1') then
+	            sSCL <= '1';
+	            sSDA <= '1';
+
+	            dSCL <= '1';
+	            dSDA <= '1';
+	          else
+	            sSCL <= scl_i;
+	            sSDA <= sda_i;
+
+	            dSCL <= sSCL;
+	            dSDA <= sSDA;
+	          end if;
+	        end if;
+	    end process synch_SCL_SDA;
+
+	    -- detect start condition => detect falling edge on SDA while SCL is high
+	    -- detect stop condition  => detect rising edge on SDA while SCL is high
+	    detect_sta_sto: process(clk, nReset)
+	    begin
+	        if (nReset = '0') then
+	          sta_condition <= '0';
+	          sto_condition <= '0';
+	        elsif (clk'event and clk = '1') then
+	          if (rst = '1') then
+	            sta_condition <= '0';
+	            sto_condition <= '0';
+	          else
+	            sta_condition <= (not sSDA and dSDA) and sSCL;
+	            sto_condition <= (sSDA and not dSDA) and sSCL;
+	          end if;
+	        end if;
+	    end process detect_sta_sto;
+
+	    -- generate i2c-bus busy signal
+	    gen_busy: process(clk, nReset)
+	    begin
+	        if (nReset = '0') then
+	          ibusy <= '0';
+	        elsif (clk'event and clk = '1') then
+	          if (rst = '1') then
+	            ibusy <= '0';
+	          else
+	            ibusy <= (sta_condition or ibusy) and not sto_condition;
+	          end if;
+	        end if;
+	    end process gen_busy;
+	    busy <= ibusy;
+
+
+	    -- generate arbitration lost signal
+	    -- aribitration lost when:
+	    -- 1) master drives SDA high, but the i2c bus is low
+	    -- 2) stop detected while not requested (detect during 'idle' state)
+	    gen_al: process(clk, nReset)
+	    begin
+	      if (nReset = '0') then
+	        cmd_stop  <= '0';
+	        ial       <= '0';
+	      elsif (clk'event and clk = '1') then
+	        if (rst = '1') then
+	          cmd_stop  <= '0';
+	          ial       <= '0';
+	        else
+	          if (clk_en = '1') then
+	            if (cmd = I2C_CMD_STOP) then
+	              cmd_stop <= '1';
+	            else
+	              cmd_stop <= '0';
+	            end if;
+	          end if;
+
+	          if (c_state = idle) then
+	            ial <= (sda_chk and not sSDA and isda_oen);
+	          else
+	            ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
+	          end if;
+
+	        end if;
+	      end if;
+	    end process gen_al;
+	    al <= ial;
+
+	    -- generate dout signal, store dout on rising edge of SCL
+	    gen_dout: process(clk)
+	    begin
+	      if (clk'event and clk = '1') then
+	        if (sSCL = '1' and dSCL = '0') then
+	          dout <= sSDA;
+	        end if;
+	      end if;
+	    end process gen_dout;
+	end block bus_status_ctrl;
+
+
+	-- generate statemachine
+	nxt_state_decoder : process (clk, nReset, c_state, cmd)
+	begin
+	    if (nReset = '0') then
+	      c_state  <= idle;
+	      cmd_ack  <= '0';
+	      iscl_oen <= '1';
+	      isda_oen <= '1';
+	      sda_chk  <= '0';
+	    elsif (clk'event and clk = '1') then
+	      if (rst = '1' or ial = '1') then
+	        c_state  <= idle;
+	        cmd_ack  <= '0';
+	        iscl_oen <= '1';
+	        isda_oen <= '1';
+	        sda_chk  <= '0';
+	      else
+	        cmd_ack <= '0'; -- default no acknowledge
+
+	        if (clk_en = '1') then
+	          case (c_state) is
+	             -- idle
+	             when idle =>
+	                case cmd is
+	                  when I2C_CMD_START => c_state <= start_a;
+	                  when I2C_CMD_STOP  => c_state <= stop_a;
+	                  when I2C_CMD_WRITE => c_state <= wr_a;
+	                  when I2C_CMD_READ  => c_state <= rd_a;
+	                  when others        => c_state <= idle; -- NOP command
+	                end case;
+
+	                iscl_oen <= iscl_oen; -- keep SCL in same state
+	                isda_oen <= isda_oen; -- keep SDA in same state
+	                sda_chk  <= '0';      -- don't check SDA
+
+	             -- start
+	             when start_a =>
+	                c_state  <= start_b;
+	                iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
+	                isda_oen <= '1';      -- set SDA high
+	                sda_chk  <= '0';      -- don't check SDA
+
+	             when start_b =>
+	                c_state  <= start_c;
+	                iscl_oen <= '1'; -- set SCL high
+	                isda_oen <= '1'; -- keep SDA high
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when start_c =>
+	                c_state  <= start_d;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '0'; -- set SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when start_d =>
+	                c_state  <= start_e;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '0'; -- keep SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when start_e =>
+	                c_state  <= idle;
+	                cmd_ack  <= '1'; -- command completed
+	                iscl_oen <= '0'; -- set SCL low
+	                isda_oen <= '0'; -- keep SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             -- stop
+	             when stop_a =>
+	                c_state  <= stop_b;
+	                iscl_oen <= '0'; -- keep SCL low
+	                isda_oen <= '0'; -- set SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when stop_b =>
+	                c_state  <= stop_c;
+	                iscl_oen <= '1'; -- set SCL high
+	                isda_oen <= '0'; -- keep SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when stop_c =>
+	                c_state  <= stop_d;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '0'; -- keep SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when stop_d =>
+	                c_state  <= idle;
+	                cmd_ack  <= '1'; -- command completed
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '1'; -- set SDA high
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             -- read
+	             when rd_a =>
+	                c_state  <= rd_b;
+	                iscl_oen <= '0'; -- keep SCL low
+	                isda_oen <= '1'; -- tri-state SDA
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when rd_b =>
+	                c_state  <= rd_c;
+	                iscl_oen <= '1'; -- set SCL high
+	                isda_oen <= '1'; -- tri-state SDA
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when rd_c =>
+	                c_state  <= rd_d;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '1'; -- tri-state SDA
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when rd_d =>
+	                c_state  <= idle;
+	                cmd_ack  <= '1'; -- command completed
+	                iscl_oen <= '0'; -- set SCL low
+	                isda_oen <= '1'; -- tri-state SDA
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             -- write
+	             when wr_a =>
+	                c_state  <= wr_b;
+	                iscl_oen <= '0'; -- keep SCL low
+	                isda_oen <= din; -- set SDA
+	                sda_chk  <= '0'; -- don't check SDA (SCL low)
+
+	             when wr_b =>
+	                c_state  <= wr_c;
+	                iscl_oen <= '1'; -- set SCL high
+	                isda_oen <= din; -- keep SDA
+	                sda_chk  <= '1'; -- check SDA
+
+	             when wr_c =>
+	                c_state  <= wr_d;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= din; -- keep SDA
+	                sda_chk  <= '1'; -- check SDA
+
+	             when wr_d =>
+	                c_state  <= idle;
+	                cmd_ack  <= '1'; -- command completed
+	                iscl_oen <= '0'; -- set SCL low
+	                isda_oen <= din; -- keep SDA
+	                sda_chk  <= '0'; -- don't check SDA (SCL low)
+
+	             when others =>
+
+	          end case;
+	        end if;
+	      end if;
+	    end if;
+	end process nxt_state_decoder;
+
+
+	-- assign outputs
+	scl_o   <= '0';
+	scl_oen <= iscl_oen;
+	sda_o   <= '0';
+	sda_oen <= isda_oen;
+end architecture structural;
+
diff --git a/fpga/src/i2c/master/i2c_master_byte_ctrl.vhd b/fpga/src/i2c/master/i2c_master_byte_ctrl.vhd
new file mode 100644
index 0000000..97d0c9f
--- /dev/null
+++ b/fpga/src/i2c/master/i2c_master_byte_ctrl.vhd
@@ -0,0 +1,371 @@
+---------------------------------------------------------------------
+----                                                             ----
+----  WISHBONE revB2 compl. I2C Master Core; byte-controller     ----
+----                                                             ----
+----                                                             ----
+----  Author: Richard Herveille                                  ----
+----          richard@asics.ws                                   ----
+----          www.asics.ws                                       ----
+----                                                             ----
+----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
+----                                                             ----
+---------------------------------------------------------------------
+----                                                             ----
+---- Copyright (C) 2000 Richard Herveille                        ----
+----                    richard@asics.ws                         ----
+----                                                             ----
+---- This source file may be used and distributed without        ----
+---- restriction provided that this copyright statement is not   ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer.----
+----                                                             ----
+----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
+---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
+---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
+---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
+---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
+---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
+---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
+---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
+---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
+---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
+---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
+---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
+---- POSSIBILITY OF SUCH DAMAGE.                                 ----
+----                                                             ----
+---------------------------------------------------------------------
+
+--  CVS Log
+--
+--  $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
+--
+--  $Date: 2004/02/18 11:41:48 $
+--  $Revision: 1.5 $
+--  $Author: rherveille $
+--  $Locker:  $
+--  $State: Exp $
+--
+-- Change History:
+--               $Log: i2c_master_byte_ctrl.vhd,v $
+--               Revision 1.5  2004/02/18 11:41:48  rherveille
+--               Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
+--
+--               Revision 1.4  2003/08/09 07:01:13  rherveille
+--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+--               Fixed a potential bug in the byte controller's host-acknowledge generation.
+--
+--               Revision 1.3  2002/12/26 16:05:47  rherveille
+--               Core is now a Multimaster I2C controller.
+--
+--               Revision 1.2  2002/11/30 22:24:37  rherveille
+--               Cleaned up code
+--
+--               Revision 1.1  2001/11/05 12:02:33  rherveille
+--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
+--               Code updated, is now up-to-date to doc. rev.0.4.
+--               Added headers.
+--
+
+
+
+
+--
+------------------------------------------
+-- Byte controller section
+------------------------------------------
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_Logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity i2c_master_byte_ctrl is
+	port (
+		clk    : in std_logic;
+		rst    : in std_logic; -- synchronous active high reset (WISHBONE compatible)
+		nReset : in std_logic;	-- asynchornous active low reset (FPGA compatible)
+		ena    : in std_logic; -- core enable signal
+
+		clk_cnt : in unsigned(15 downto 0);	-- 4x SCL
+
+		-- input signals
+		start,
+		stop,
+		read,
+		write,
+		ack_in : std_logic;
+		din    : in std_logic_vector(7 downto 0);
+
+		-- output signals
+		cmd_ack  : out std_logic; -- command done
+		ack_out  : out std_logic;
+		i2c_busy : out std_logic; -- arbitration lost
+		i2c_al   : out std_logic; -- i2c bus busy
+		dout     : out std_logic_vector(7 downto 0);
+
+		-- i2c lines
+		scl_i   : in std_logic;  -- i2c clock line input
+		scl_o   : out std_logic; -- i2c clock line output
+		scl_oen : out std_logic; -- i2c clock line output enable, active low
+		sda_i   : in std_logic;  -- i2c data line input
+		sda_o   : out std_logic; -- i2c data line output
+		sda_oen : out std_logic  -- i2c data line output enable, active low
+	);
+end entity i2c_master_byte_ctrl;
+
+architecture structural of i2c_master_byte_ctrl is
+	component i2c_master_bit_ctrl is
+	port (
+		clk    : in std_logic;
+		rst    : in std_logic;
+		nReset : in std_logic;
+		ena    : in std_logic;				-- core enable signal
+
+		clk_cnt : in unsigned(15 downto 0);		-- clock prescale value
+
+		cmd     : in std_logic_vector(3 downto 0);
+		cmd_ack : out std_logic; -- command done
+		busy    : out std_logic; -- i2c bus busy
+		al      : out std_logic; -- arbitration lost
+
+		din  : in std_logic;
+		dout : out std_logic;
+
+		-- i2c lines
+		scl_i   : in std_logic;  -- i2c clock line input
+		scl_o   : out std_logic; -- i2c clock line output
+		scl_oen : out std_logic; -- i2c clock line output enable, active low
+		sda_i   : in std_logic;  -- i2c data line input
+		sda_o   : out std_logic; -- i2c data line output
+		sda_oen : out std_logic  -- i2c data line output enable, active low
+	);
+	end component i2c_master_bit_ctrl;
+
+	-- commands for bit_controller block
+	constant I2C_CMD_NOP  	: std_logic_vector(3 downto 0) := "0000";
+	constant I2C_CMD_START	: std_logic_vector(3 downto 0) := "0001";
+	constant I2C_CMD_STOP	 : std_logic_vector(3 downto 0) := "0010";
+	constant I2C_CMD_READ	 : std_logic_vector(3 downto 0) := "0100";
+	constant I2C_CMD_WRITE	: std_logic_vector(3 downto 0) := "1000";
+
+	-- signals for bit_controller
+	signal core_cmd : std_logic_vector(3 downto 0);
+	signal core_ack, core_txd, core_rxd : std_logic;
+	signal al : std_logic;
+
+	-- signals for shift register
+	signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
+	signal shift, ld : std_logic;
+
+	-- signals for state machine
+	signal go, host_ack : std_logic;
+	signal dcnt : unsigned(2 downto 0); -- data counter
+	signal cnt_done : std_logic;
+
+begin
+	-- hookup bit_controller
+	bit_ctrl: i2c_master_bit_ctrl port map(
+		clk     => clk,
+		rst     => rst,
+		nReset  => nReset,
+		ena     => ena,
+		clk_cnt => clk_cnt,
+		cmd     => core_cmd,
+		cmd_ack => core_ack,
+		busy    => i2c_busy,
+		al      => al,
+		din     => core_txd,
+		dout    => core_rxd,
+		scl_i   => scl_i,
+		scl_o   => scl_o,
+		scl_oen => scl_oen,
+		sda_i   => sda_i,
+		sda_o   => sda_o,
+		sda_oen => sda_oen
+	);
+	i2c_al <= al;
+
+	-- generate host-command-acknowledge
+	cmd_ack <= host_ack;
+
+	-- generate go-signal
+	go <= (read or write or stop) and not host_ack;
+
+	-- assign Dout output to shift-register
+	dout <= sr;
+
+	-- generate shift register
+	shift_register: process(clk, nReset)
+	begin
+	    if (nReset = '0') then
+	      sr <= (others => '0');
+	    elsif (clk'event and clk = '1') then
+	      if (rst = '1') then
+	        sr <= (others => '0');
+	      elsif (ld = '1') then
+	        sr <= din;
+	      elsif (shift = '1') then
+	        sr <= (sr(6 downto 0) & core_rxd);
+	      end if;
+	    end if;
+	end process shift_register;
+
+	-- generate data-counter
+	data_cnt: process(clk, nReset)
+	begin
+	    if (nReset = '0') then
+	      dcnt <= (others => '0');
+	    elsif (clk'event and clk = '1') then
+	      if (rst = '1') then
+	        dcnt <= (others => '0');
+	      elsif (ld = '1') then
+	        dcnt <= (others => '1');  -- load counter with 7
+	      elsif (shift = '1') then
+	        dcnt <= dcnt -1;
+	      end if;
+	    end if;
+	end process data_cnt;
+
+	cnt_done <= '1' when (dcnt = 0) else '0';
+
+	--
+	-- state machine
+	--
+	statemachine : block
+	    type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
+	    signal c_state : states;
+	begin
+	    --
+	    -- command interpreter, translate complex commands into simpler I2C commands
+	    --
+	    nxt_state_decoder: process(clk, nReset)
+	    begin
+	        if (nReset = '0') then
+	          core_cmd <= I2C_CMD_NOP;
+	          core_txd <= '0';
+	          shift    <= '0';
+	          ld       <= '0';
+	          host_ack <= '0';
+	          c_state  <= st_idle;
+	          ack_out  <= '0';
+	        elsif (clk'event and clk = '1') then
+	          if (rst = '1' or al = '1') then
+	            core_cmd <= I2C_CMD_NOP;
+	            core_txd <= '0';
+	            shift    <= '0';
+	            ld       <= '0';
+	            host_ack <= '0';
+	            c_state  <= st_idle;
+	            ack_out  <= '0';
+	          else
+	            -- initialy reset all signal
+	            core_txd <= sr(7);
+	            shift    <= '0';
+	            ld       <= '0';
+	            host_ack <= '0';
+
+	            case c_state is
+	              when st_idle =>
+	                 if (go = '1') then
+	                   if (start = '1') then
+	                     c_state  <= st_start;
+	                     core_cmd <= I2C_CMD_START;
+	                   elsif (read = '1') then
+	                     c_state  <= st_read;
+	                     core_cmd <= I2C_CMD_READ;
+	                   elsif (write = '1') then
+	                     c_state  <= st_write;
+	                     core_cmd <= I2C_CMD_WRITE;
+	                   else -- stop
+	                     c_state  <= st_stop;
+	                     core_cmd <= I2C_CMD_STOP;
+	                   end if;
+
+	                   ld <= '1';
+	                 end if;
+
+	              when st_start =>
+	                 if (core_ack = '1') then
+	                   if (read = '1') then
+	                     c_state  <= st_read;
+	                     core_cmd <= I2C_CMD_READ;
+	                   else
+	                     c_state  <= st_write;
+	                     core_cmd <= I2C_CMD_WRITE;
+	                   end if;
+
+	                   ld <= '1';
+	                 end if;
+
+	              when st_write =>
+	                 if (core_ack = '1') then
+	                   if (cnt_done = '1') then
+	                     c_state  <= st_ack;
+	                     core_cmd <= I2C_CMD_READ;
+	                   else
+	                     c_state  <= st_write;       -- stay in same state
+	                     core_cmd <= I2C_CMD_WRITE;  -- write next bit
+	                     shift    <= '1';
+	                   end if;
+	                 end if;
+
+	              when st_read =>
+	                 if (core_ack = '1') then
+	                   if (cnt_done = '1') then
+	                     c_state  <= st_ack;
+	                     core_cmd <= I2C_CMD_WRITE;
+	                   else
+	                     c_state  <= st_read;      -- stay in same state
+	                     core_cmd <= I2C_CMD_READ; -- read next bit
+	                   end if;
+
+	                   shift    <= '1';
+	                   core_txd <= ack_in;
+	                 end if;
+
+	              when st_ack =>
+	                 if (core_ack = '1') then
+	                   -- check for stop; Should a STOP command be generated ?
+	                   if (stop = '1') then
+	                     c_state  <= st_stop;
+	                     core_cmd <= I2C_CMD_STOP;
+	                   else
+	                     c_state  <= st_idle;
+	                     core_cmd <= I2C_CMD_NOP;
+
+	                     -- generate command acknowledge signal
+	                     host_ack <= '1';
+	                   end if;
+
+	                   -- assign ack_out output to core_rxd (contains last received bit)
+	                   ack_out  <= core_rxd;
+
+	                   core_txd <= '1';
+	                 else
+	                   core_txd <= ack_in;
+	                 end if;
+
+	              when st_stop =>
+	                 if (core_ack = '1') then
+	                   c_state  <= st_idle;
+	                   core_cmd <= I2C_CMD_NOP;
+
+	                   -- generate command acknowledge signal
+	                   host_ack <= '1';
+	                 end if;
+
+	              when others => -- illegal states
+	                 c_state  <= st_idle;
+	                 core_cmd <= I2C_CMD_NOP;
+	                 report ("Byte controller entered illegal state.");
+
+	            end case;
+
+	          end if;
+	        end if;
+	    end process nxt_state_decoder;
+
+	end block statemachine;
+
+end architecture structural;
+
diff --git a/fpga/src/i2c/master/i2c_master_top.vhd b/fpga/src/i2c/master/i2c_master_top.vhd
new file mode 100644
index 0000000..a990ef3
--- /dev/null
+++ b/fpga/src/i2c/master/i2c_master_top.vhd
@@ -0,0 +1,366 @@
+---------------------------------------------------------------------
+----                                                             ----
+----  WISHBONE revB2 compl. I2C Master Core; top level           ----
+----                                                             ----
+----                                                             ----
+----  Author: Richard Herveille                                  ----
+----          richard@asics.ws                                   ----
+----          www.asics.ws                                       ----
+----                                                             ----
+----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
+----                                                             ----
+---------------------------------------------------------------------
+----                                                             ----
+---- Copyright (C) 2000 Richard Herveille                        ----
+----                    richard@asics.ws                         ----
+----                                                             ----
+---- This source file may be used and distributed without        ----
+---- restriction provided that this copyright statement is not   ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer.----
+----                                                             ----
+----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
+---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
+---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
+---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
+---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
+---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
+---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
+---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
+---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
+---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
+---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
+---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
+---- POSSIBILITY OF SUCH DAMAGE.                                 ----
+----                                                             ----
+---------------------------------------------------------------------
+
+--  CVS Log
+--
+--  $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $
+--
+--  $Date: 2004/03/14 10:17:03 $
+--  $Revision: 1.7 $
+--  $Author: rherveille $
+--  $Locker:  $
+--  $State: Exp $
+--
+-- Change History:
+--               $Log: i2c_master_top.vhd,v $
+--               Revision 1.7  2004/03/14 10:17:03  rherveille
+--               Fixed simulation issue when writing to CR register
+--
+--               Revision 1.6  2003/08/09 07:01:13  rherveille
+--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+--               Fixed a potential bug in the byte controller's host-acknowledge generation.
+--
+--               Revision 1.5  2003/02/01 02:03:06  rherveille
+--               Fixed a few 'arbitration lost' bugs. VHDL version only.
+--
+--               Revision 1.4  2002/12/26 16:05:47  rherveille
+--               Core is now a Multimaster I2C controller.
+--
+--               Revision 1.3  2002/11/30 22:24:37  rherveille
+--               Cleaned up code
+--
+--               Revision 1.2  2001/11/10 10:52:44  rherveille
+--               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
+--
+
+
+--library ieee;
+--use ieee.std_logic_1164.all;
+--use ieee.std_logic_arith.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use IEEE.STD_Logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity i2c_master_top is
+	generic(
+		ARST_LVL : std_logic := '0'                   -- asynchronous reset level
+	);
+	port (
+		-- wishbone signals
+		wb_clk_i  : in  std_logic;                    -- master clock input
+		wb_rst_i  : in  std_logic := '0';             -- synchronous active high reset
+		arst_i    : in  std_logic := not ARST_LVL;    -- asynchronous reset
+--		wb_adr_i  : in  unsigned(2 downto 0);         -- lower address bits
+		wb_adr_i  : in  std_logic_vector(2 downto 0); -- lower address bits
+		wb_dat_i  : in  std_logic_vector(7 downto 0); -- Databus input
+		wb_dat_o  : out std_logic_vector(7 downto 0); -- Databus output
+		wb_we_i   : in  std_logic;	              -- Write enable input
+		wb_stb_i  : in  std_logic;                    -- Strobe signals / core select signal
+		wb_cyc_i  : in  std_logic;	              -- Valid bus cycle input
+		wb_ack_o  : out std_logic;                    -- Bus cycle acknowledge output
+		wb_inta_o : out std_logic;                    -- interrupt request output signal
+
+		-- i2c lines
+		scl_pad_i     : in  std_logic;                -- i2c clock line input
+		scl_pad_o     : out std_logic;                -- i2c clock line output
+		scl_padoen_o  : out std_logic;                -- i2c clock line output enable, active low
+		sda_pad_i     : in  std_logic;                -- i2c data line input
+		sda_pad_o     : out std_logic;                -- i2c data line output
+		sda_padoen_o  : out std_logic                 -- i2c data line output enable, active low
+	);
+end entity i2c_master_top;
+
+architecture structural of i2c_master_top is
+--	component i2c_master_byte_ctrl is
+--	port (
+--		clk    : in std_logic;
+--		rst    : in std_logic; -- synchronous active high reset (WISHBONE compatible)
+--		nReset : in std_logic;	-- asynchornous active low reset (FPGA compatible)
+--		ena    : in std_logic; -- core enable signal
+--
+--		clk_cnt : in unsigned(15 downto 0);	-- 4x SCL
+--
+--		-- input signals
+--		start,
+--		stop,
+--		read,
+--		write,
+--		ack_in : std_logic;
+--		din    : in std_logic_vector(7 downto 0);
+--
+--		-- output signals
+--		cmd_ack  : out std_logic;
+--		ack_out  : out std_logic;
+--		i2c_busy : out std_logic;
+--		i2c_al   : out std_logic;
+--		dout     : out std_logic_vector(7 downto 0);
+--
+--		-- i2c lines
+--		scl_i   : in std_logic;  -- i2c clock line input
+--		scl_o   : out std_logic; -- i2c clock line output
+--		scl_oen : out std_logic; -- i2c clock line output enable, active low
+--		sda_i   : in std_logic;  -- i2c data line input
+--		sda_o   : out std_logic; -- i2c data line output
+--		sda_oen : out std_logic  -- i2c data line output enable, active low
+--	);
+--	end component i2c_master_byte_ctrl;
+
+	-- registers
+	signal prer : unsigned(15 downto 0);             -- clock prescale register
+	signal ctr  : std_logic_vector(7 downto 0);      -- control register
+	signal txr  : std_logic_vector(7 downto 0);      -- transmit register
+	signal rxr  : std_logic_vector(7 downto 0);      -- receive register
+	signal cr   : std_logic_vector(7 downto 0);      -- command register
+	signal sr   : std_logic_vector(7 downto 0);      -- status register
+
+	-- internal reset signal
+	signal rst_i : std_logic;
+
+	-- wishbone write access
+	signal wb_wacc : std_logic;
+
+	-- internal acknowledge signal
+	signal iack_o : std_logic;
+
+	-- done signal: command completed, clear command register
+	signal done : std_logic;
+
+	-- command register signals
+	signal sta, sto, rd, wr, ack, iack : std_logic;
+
+	signal core_en : std_logic;                      -- core enable signal
+	signal ien     : std_logic;                      -- interrupt enable signal
+
+	-- status register signals
+	signal irxack, rxack : std_logic;                -- received aknowledge from slave
+	signal tip           : std_logic;                -- transfer in progress
+	signal irq_flag      : std_logic;                -- interrupt pending flag
+	signal i2c_busy      : std_logic;                -- i2c bus busy (start signal detected)
+	signal i2c_al, al    : std_logic;                -- arbitration lost
+
+begin
+	-- generate internal reset signal
+	rst_i <= arst_i xor ARST_LVL;
+
+	-- generate acknowledge output signal
+	gen_ack_o : process(wb_clk_i)
+	begin
+	    if (wb_clk_i'event and wb_clk_i = '1') then
+	      iack_o <= wb_cyc_i and wb_stb_i and not iack_o;         -- because timing is always honored
+	    end if;
+	end process gen_ack_o;
+	wb_ack_o <= iack_o;
+
+	-- generate wishbone write access signal
+	wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
+
+	-- assign wb_dat_o
+	assign_dato : process(wb_clk_i)
+	begin
+	    if (wb_clk_i'event and wb_clk_i = '1') then
+	      if (wb_stb_i = '1' and wb_we_i = '0') then
+	      case wb_adr_i is
+	        when "000"  => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
+	        when "001"  => wb_dat_o <= std_logic_vector(prer(15 downto 8));
+	        when "010"  => wb_dat_o <= ctr;
+	        when "011"  => wb_dat_o <= rxr; -- write is transmit register TxR
+	        when "100"  => wb_dat_o <= sr;  -- write is command register CR
+
+	        -- Debugging registers:
+	        -- These registers are not documented.
+	        -- Functionality could change in future releases
+	        when "101"  => wb_dat_o <= txr;
+	        when "110"  => wb_dat_o <= cr;
+	        when "111"  => wb_dat_o <= x"23"; --(others => '0');
+	        when others => wb_dat_o <= (others => 'X');	-- for simulation only
+	      end case;
+	      else
+	      wb_dat_o <= (others => '0');
+	      end if;
+	    end if;
+	end process assign_dato;
+
+	-- generate registers (CR, SR see below)
+	gen_regs: process(rst_i, wb_clk_i)
+	begin
+	    if (rst_i = '0') then
+	      prer <= (others => '1');
+	      ctr  <= (others => '0');
+	      txr  <= (others => '0');
+	    elsif (wb_clk_i'event and wb_clk_i = '1') then
+	      if (wb_rst_i = '1') then
+	        prer <= (others => '1');
+	        ctr  <= (others => '0');
+	        txr  <= (others => '0');
+	      elsif (wb_wacc = '1') then
+	        case wb_adr_i is
+	           when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
+	           when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
+	           when "010" => ctr               <= wb_dat_i;
+	           when "011" => txr               <= wb_dat_i;
+	           when "100" => null; --write to CR, avoid executing the others clause
+
+	           -- illegal cases, for simulation only
+	           when others =>
+	              report ("Illegal write address, setting all registers to unknown.");
+	              prer <= (others => 'X');
+	              ctr  <= (others => 'X');
+	              txr  <= (others => 'X');
+	        end case;
+	      end if;
+	    end if;
+	end process gen_regs;
+
+
+	-- generate command register
+	gen_cr: process(rst_i, wb_clk_i)
+	begin
+	    if (rst_i = '0') then
+	        cr <= (others => '0');
+	    elsif (wb_clk_i'event and wb_clk_i = '1') then
+	        if (wb_rst_i = '1') then
+	            cr <= (others => '0');
+	        elsif (wb_wacc = '1') then
+	            if ( (core_en = '1') and (wb_adr_i = 4) ) then
+	                -- only take new commands when i2c core enabled
+	                -- pending commands are finished
+	                cr <= wb_dat_i;
+	            end if;
+	        else
+	            if (done = '1' or i2c_al = '1') then
+	                cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
+	            end if;
+
+	            cr(2 downto 1) <= (others => '0');   -- reserved bits, always '0'
+	            cr(0) <= '0';                        -- clear IRQ_ACK bit
+	        end if;
+	    end if;
+	end process gen_cr;
+
+	-- decode command register
+	sta  <= cr(7);
+	sto  <= cr(6);
+	rd   <= cr(5);
+	wr   <= cr(4);
+	ack  <= cr(3);
+	iack <= cr(0);
+
+	-- decode control register
+	core_en <= ctr(7);
+	ien     <= ctr(6);
+
+	-- hookup byte controller block
+	byte_ctrl: entity work.i2c_master_byte_ctrl port map (
+		clk      => wb_clk_i,
+		rst      => wb_rst_i,
+		nReset   => rst_i,
+		ena      => core_en,
+		clk_cnt  => prer,
+		start    => sta,
+		stop     => sto,
+		read     => rd,
+		write    => wr,
+		ack_in   => ack,
+		i2c_busy => i2c_busy,
+		i2c_al   => i2c_al,
+		din      => txr,
+		cmd_ack  => done,
+		ack_out  => irxack,
+		dout     => rxr,
+		scl_i    => scl_pad_i,
+		scl_o    => scl_pad_o,
+		scl_oen  => scl_padoen_o,
+		sda_i    => sda_pad_i,
+		sda_o    => sda_pad_o,
+		sda_oen  => sda_padoen_o
+	);
+
+
+	-- status register block + interrupt request signal
+	st_irq_block : block
+	begin
+	    -- generate status register bits
+	    gen_sr_bits: process (wb_clk_i, rst_i)
+	    begin
+	        if (rst_i = '0') then
+	          al       <= '0';
+	          rxack    <= '0';
+	          tip      <= '0';
+	          irq_flag <= '0';
+	        elsif (wb_clk_i'event and wb_clk_i = '1') then
+	          if (wb_rst_i = '1') then
+	            al       <= '0';
+	            rxack    <= '0';
+	            tip      <= '0';
+	            irq_flag <= '0';
+	          else
+	            al       <= i2c_al or (al and not sta);
+	            rxack    <= irxack;
+	            tip      <= (rd or wr);
+
+	            -- interrupt request flag is always generated
+	            irq_flag <= (done or i2c_al or irq_flag) and not iack;
+	          end if;
+	        end if;
+	    end process gen_sr_bits;
+
+	    -- generate interrupt request signals
+	    gen_irq: process (wb_clk_i, rst_i)
+	    begin
+	        if (rst_i = '0') then
+	          wb_inta_o <= '0';
+	        elsif (wb_clk_i'event and wb_clk_i = '1') then
+	          if (wb_rst_i = '1') then
+	            wb_inta_o <= '0';
+	          else
+	            -- interrupt signal is only generated when IEN (interrupt enable bit) is set
+	            wb_inta_o <= irq_flag and ien;
+	          end if;
+	        end if;
+	    end process gen_irq;
+
+	    -- assign status register bits
+	    sr(7)          <= rxack;
+	    sr(6)          <= i2c_busy;
+	    sr(5)          <= al;
+	    sr(4 downto 2) <= (others => '0'); -- reserved
+	    sr(1)          <= tip;
+	    sr(0)          <= irq_flag;
+	end block;
+
+end architecture structural;
diff --git a/fpga/src/i2c/master/i2c_specs.pdf b/fpga/src/i2c/master/i2c_specs.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..72021df117397a4c324ee17a0515db6f04af5a93
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diff --git a/fpga/src/i2c/master/i2c_wrapper.vhdl b/fpga/src/i2c/master/i2c_wrapper.vhdl
new file mode 100644
index 0000000..ff9381e
--- /dev/null
+++ b/fpga/src/i2c/master/i2c_wrapper.vhdl
@@ -0,0 +1,193 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity i2c_wrapper is
+	generic ( prescale : std_logic_vector(15 downto 0) := x"00c8");
+	port (
+	wb_clk_i  : in    std_logic;
+	wb_rst_i  : in    std_logic;
+	wb_adr_i  : in    std_logic_vector(15 downto 0);
+	wb_dat_i  : in    std_logic_vector(7 downto 0);
+	wb_dat_o  : out   std_logic_vector(7 downto 0);
+	wb_we_i   : in    std_logic;
+	wb_stb_i  : in    std_logic;
+	wb_ack_o  : out   std_logic;
+	scl_i     : in    std_logic;
+	scl_o     : out   std_logic;
+	sda_i     : in    std_logic;
+	sda_o     : out   std_logic;
+	debug     : out   std_logic_vector(3 downto 0)
+	);
+end;
+
+architecture i2c_wrapper of i2c_wrapper is
+
+	signal wb_adr      : unsigned(2 downto 0);
+	signal wb_dati     : std_logic_vector(7 downto 0);
+	signal wb_dato     : std_logic_vector(7 downto 0);
+	signal wb_we       : std_logic;
+	signal wb_stb      : std_logic;
+	signal wb_cyc      : std_logic;
+	signal wb_ack      : std_logic;
+	signal wb_inta     : std_logic;
+	signal wb_dat_oq   : std_logic_vector(7 downto 0);
+	signal cnt         : unsigned(3 downto 0);
+	signal wb_dowrite  : std_logic;
+	signal wb_doread   : std_logic;
+	signal end_cnt     : integer range 0 to 11;
+
+	type i2c_rec is record
+		adr   : unsigned(2 downto 0);
+		dat   : std_logic_vector(7 downto 0);
+		int   : std_logic;
+	end record;
+
+	type i2c_mem is ARRAY(0 to 11) of i2c_rec;
+	signal dat : i2c_mem;
+	type   i2c_states is (IDLE, I2C_GO, I2C_WAIT_INT, I2C_GET_RXDAT, I2C_WB_ACK);
+	signal i2c_sm : i2c_states;
+
+	signal scl           : std_logic;
+	signal sda           : std_logic;
+	signal scl_oen       : std_logic;
+	signal sda_oen       : std_logic;
+	signal i2c_init_done : std_logic;
+begin
+	scl_o    <= scl when scl_oen = '0' else '1';
+	sda_o    <= sda when sda_oen = '0' else '1';
+	wb_dat_o <= wb_dat_oq;
+
+	i2c_master : entity work.i2c_master_top
+	generic map( ARST_LVL => '1' )
+	port map (
+		-- wishbone signals
+		wb_clk_i  => wb_clk_i,
+		wb_rst_i  => wb_rst_i,
+		arst_i    => wb_rst_i,
+		wb_adr_i  => std_logic_vector(wb_adr),
+		wb_dat_i  => wb_dati,
+		wb_dat_o  => wb_dato,
+		wb_we_i   => wb_we,
+		wb_stb_i  => wb_stb,
+		wb_cyc_i  => wb_cyc,
+		wb_ack_o  => wb_ack,
+		wb_inta_o => wb_inta,
+
+		-- i2c lines
+		scl_pad_i    => scl_i,
+		scl_pad_o    => scl,
+		scl_padoen_o => scl_oen,
+		sda_pad_i    => sda_i,
+		sda_pad_o    => sda,
+		sda_padoen_o => sda_oen
+	);
+
+	i2c_write: process (wb_clk_i, wb_rst_i)
+	begin
+	if rising_edge(wb_clk_i) then
+	if wb_rst_i = '1' then
+		wb_dat_oq     <= (others => '0');
+		cnt           <= (others => '0');
+		i2c_init_done <= '0';
+		wb_dowrite    <= '0';
+		wb_doread     <= '0';
+		end_cnt       <= 0;
+	else
+		dat <= dat;
+
+		if wb_ack = '1' and i2c_sm = I2C_GO then
+			cnt <= cnt + "1";
+		elsif i2c_sm = IDLE and i2c_init_done = '1' then
+			cnt <= "0011";
+		elsif i2c_sm = IDLE and i2c_init_done = '0' then
+			cnt <= "0000";
+		end if;
+
+		if i2c_sm = IDLE and wb_stb_i = '1' then
+	       		if wb_we_i = '1' then
+				      --         PRESCALE Register                                            enable core and interrupt
+				dat  <= (("000", prescale(7 downto 0),'0'), ("001", prescale(15 downto 8),'0'), ("010", x"c0",'0'),
+				      --     ADDRESS           STA and WR bit           DATA/REG           STA and WR
+					 ("011", x"EC", '0'), ("100", x"90",'1'), ("011", x"ff", '0'), ("100", x"90",'1'), 
+				      --       DATA              STO and WR
+					 ("011", x"ff",'0'), ("100", x"50", '1'));
+				dat(3).dat <= wb_adr_i(15 downto 0);
+				dat(5).dat <= wb_adr_i( 7 downto 0);
+				dat(8).dat <= wb_dat_i;
+				end_cnt    <= 9;
+			else
+				dat  <= (("000", prescale(7 downto 0),'0'), ("001", prescale(15 downto 8),'0'), ("010", x"c0",'0'),
+				      --     ADDRESS           STA and WR bit           DATA/REG             WR           
+					 ("011", x"EC", '0'), ("100", x"91",'1'), ("011", x"ff", '0'), ("100", x"11", '1'),
+				      --     ADDRESS                STA,WR             STO, RD, NACK
+				         ("011", x"ED", '0'), ("100", x"91",'1'), ("100", x"69", '1'), ("111", x"00", '0'), ("111", x"00", '0'));
+				dat(3).dat <= wb_adr_i(15 downto 9) & '0'; -- address write
+				dat(5).dat <= wb_adr_i( 7 downto 0);       -- memory location
+				dat(7).dat <= wb_adr_i(15 downto 9) & '1'; -- address read
+				end_cnt    <= 10;
+			end if;
+		end if;
+
+		i2c_init_done <= i2c_init_done;
+		if i2c_sm = I2C_GO and cnt = "0010" then
+			i2c_init_done <= '1';
+		end if;
+
+		if i2c_sm = I2C_GET_RXDAT and wb_ack = '1' then
+			wb_dat_oq <= wb_dato;
+		end if;
+
+		case i2c_sm is
+		when IDLE =>
+			if (wb_stb_i = '1') then
+				i2c_sm <= I2C_GO;
+			end if;
+		when I2C_GO =>
+			wb_dowrite <= '1';
+
+			if wb_ack = '1' and dat(to_integer(cnt)).int = '1' then
+				i2c_sm  <= I2C_WAIT_INT;
+				wb_dowrite <= '0';
+			elsif wb_ack = '1' and dat(to_integer(cnt)).int = '0' then
+				if to_integer(cnt) = end_cnt then
+					i2c_sm <= I2C_GET_RXDAT;
+				end if;
+				wb_dowrite <= '0';
+			end if;
+		when I2C_WAIT_INT =>
+			wb_doread <= '1';
+
+			if wb_ack = '1' and wb_dato(1) = '0' then
+				wb_doread <= '0';
+				if to_integer(cnt) = end_cnt then
+					i2c_sm <= I2C_GET_RXDAT;
+				else
+					i2c_sm <= I2C_GO;
+				end if;
+			end if;
+		when I2C_GET_RXDAT =>
+			wb_doread <= '1';
+			if wb_ack = '1' then
+				wb_doread <= '0';
+				i2c_sm <= I2C_WB_ACK;
+			end if;
+		when I2C_WB_ACK =>
+			i2c_sm <= IDLE;
+		end case;
+	end if;
+	end if;
+	end process;
+
+	wb_ack_o <= '1' when i2c_sm = I2C_WB_ACK else '0';
+	wb_dati <= dat(to_integer(cnt)).dat;
+	wb_adr  <= dat(to_integer(cnt)).adr when wb_dowrite = '1'       else
+	                              "011" when i2c_sm = I2C_GET_RXDAT else
+	                              "100";
+	wb_cyc  <= wb_stb;
+	wb_stb  <= '1' when (wb_dowrite = '1' or wb_doread = '1') and wb_ack = '0' else '0';
+	wb_we   <= wb_dowrite;
+
+	debug(3 downto 0) <= std_logic_vector(cnt);
+
+end i2c_wrapper;
diff --git a/fpga/src/i2c/sim/sim_tb.vhd b/fpga/src/i2c/sim/sim_tb.vhd
new file mode 100644
index 0000000..e3a6ccb
--- /dev/null
+++ b/fpga/src/i2c/sim/sim_tb.vhd
@@ -0,0 +1,131 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sim_tb is
+end sim_tb;
+
+architecture rtl of sim_tb is
+	constant CLK_PERIOD     : time := 10 ns;
+	signal clk              : std_logic;
+	signal rst              : std_logic;
+	signal rst_n            : std_logic;
+
+	component i2c_wrapper is
+	generic ( prescale : std_logic_vector(15 downto 0) := x"00c8");
+	port (
+		wb_clk_i  : in    std_logic;
+		wb_rst_i  : in    std_logic;
+		wb_adr_i  : in    std_logic_vector(15 downto 0);
+		wb_dat_i  : in    std_logic_vector(7 downto 0);
+		wb_dat_o  : out   std_logic_vector(7 downto 0);
+		wb_we_i   : in    std_logic;
+		wb_stb_i  : in    std_logic;
+		wb_ack_o  : out   std_logic;
+		scl_i     : in    std_logic;
+		scl_o     : out   std_logic;
+		sda_i     : in    std_logic;
+		sda_o     : out   std_logic;
+		debug     : out   std_logic_vector(3 downto 0)
+	);
+	end component;
+
+	component i2c_rom is
+	port (
+		clk    : in    std_logic;
+		rst_n  : in    std_logic;
+		sda_i  : in    std_logic;
+		sda_o  : out   std_logic;
+		scl_i  : in    std_logic
+	);
+	end component;
+
+	signal wb_clk_i  : std_logic;
+	signal wb_rst_i  : std_logic;
+	signal wb_adr_i  : std_logic_vector(15 downto 0);
+	signal wb_dat_i  : std_logic_vector(7 downto 0);
+	signal wb_dat_o  : std_logic_vector(7 downto 0);
+	signal wb_we_i   : std_logic;
+	signal wb_stb_i  : std_logic;
+	signal wb_ack_o  : std_logic;
+	signal scl_wi    : std_logic;
+	signal scl_wo    : std_logic;
+	signal sda_wi    : std_logic;
+	signal sda_wo    : std_logic;
+	signal debug     : std_logic_vector(3 downto 0);
+	signal sda_ro    : std_logic;
+begin
+	rst   <= transport '1', '0' after (4 * CLK_PERIOD);
+	rst_n <= not rst;
+	clock: process begin
+		clk <= '1', '0' after CLK_PERIOD/2;
+		wait for CLK_PERIOD;
+	end process;
+	wb_clk_i <= clk;
+	wb_rst_i <= rst;
+
+
+	beh_mst: process
+	begin
+		wb_dat_i <= x"00";
+		wb_we_i <= '0';
+		wb_adr_i <= x"6a08";
+		wb_stb_i <= '0';
+		wait for 20*CLK_PERIOD;
+		wb_stb_i <= '1';
+		wait until wb_ack_o = '1';
+		wb_stb_i <= '0';
+		wait;
+	end process beh_mst;
+
+	DUT_MST: i2c_wrapper
+	port map (
+		wb_clk_i  => wb_clk_i,
+		wb_rst_i  => wb_rst_i,
+		wb_adr_i  => wb_adr_i,
+		wb_dat_i  => wb_dat_i,
+		wb_dat_o  => wb_dat_o,
+		wb_we_i   => wb_we_i,
+		wb_stb_i  => wb_stb_i,
+		wb_ack_o  => wb_ack_o,
+		scl_i     => scl_wi,
+		scl_o     => scl_wo,
+		sda_i     => sda_wi,
+		sda_o     => sda_wo
+	);
+
+	scl_wi <= scl_wo;
+	sda_wi <=   '1'  when sda_ro = 'Z' else
+	            '0'  when sda_ro = '0' else sda_wo;
+
+	DUT: i2c_rom
+	port map (
+		clk    => wb_clk_i,
+		rst_n  => rst_n,
+		sda_i  => sda_wo,
+		sda_o  => sda_ro,
+		scl_i  => scl_wo
+	);
+
+end rtl;
diff --git a/fpga/src/i2c/slave/hdmi_in.dat b/fpga/src/i2c/slave/hdmi_in.dat
new file mode 100644
index 0000000..ce26889
--- /dev/null
+++ b/fpga/src/i2c/slave/hdmi_in.dat
@@ -0,0 +1,256 @@
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diff --git a/fpga/src/i2c/slave/hdmi_in_syncmaster191t.dat b/fpga/src/i2c/slave/hdmi_in_syncmaster191t.dat
new file mode 100644
index 0000000..1740943
--- /dev/null
+++ b/fpga/src/i2c/slave/hdmi_in_syncmaster191t.dat
@@ -0,0 +1,128 @@
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diff --git a/fpga/src/i2c/slave/hdmi_in_syncmaster940t.dat b/fpga/src/i2c/slave/hdmi_in_syncmaster940t.dat
new file mode 100644
index 0000000..880a7a8
--- /dev/null
+++ b/fpga/src/i2c/slave/hdmi_in_syncmaster940t.dat
@@ -0,0 +1,256 @@
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diff --git a/fpga/src/i2c/slave/i2c_rom.vhd b/fpga/src/i2c/slave/i2c_rom.vhd
new file mode 100644
index 0000000..c250897
--- /dev/null
+++ b/fpga/src/i2c/slave/i2c_rom.vhd
@@ -0,0 +1,80 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+
+entity i2c_rom is
+	port (
+		clk    : in    std_logic;
+		rst_n  : in    std_logic;
+		sda_i  : in    std_logic;
+		sda_o  : out   std_logic;
+		scl_i  : in    std_logic
+	);
+end i2c_rom;
+
+architecture i2c_rom of i2c_rom is
+	--type rom_t is array (0 to 255) of std_logic_vector (7 downto 0);
+	type rom_t is array (0 to 127) of std_logic_vector (7 downto 0);
+	impure function init_rom_from_file(filename : in string) return rom_t is
+	file romfile   : text is in filename;
+	variable rline : line;
+	variable rom   : rom_t;
+	begin
+		for i in rom_t'range loop
+			readline(romfile, rline);
+			hread(rline, rom(i));
+		end loop;
+		return rom;
+	end function;
+	--signal rom : rom_t := init_rom_from_file("hdmi_in_syncmaster940t.dat");
+	signal rom : rom_t := init_rom_from_file("hdmi_in_syncmaster191t.dat");
+
+	signal rd_data         : std_logic_vector(7 downto 0);
+	signal wr_data         : std_logic_vector(7 downto 0);
+	signal address         : std_logic_vector(7 downto 0);
+	signal wr_pulse        : std_logic;
+	signal rd_pulse        : std_logic;
+	signal rd_wr           : std_logic;
+begin
+	rd_data <= rom(to_integer(unsigned(address)));
+
+	i2c_blk_0: entity work.i2c_slave
+	generic map ( ADDRESS => "0101000" ) -- 6A write, 6B read
+	port map (
+		clk             => clk,
+		rst_n           => rst_n,
+		sda_i           => sda_i,
+		sda_o           => sda_o,
+		scl_i           => scl_i,
+		rd_dat_i        => rd_data,
+		addr_o          => address,
+		wr_dat_o        => wr_data,
+		wr_pulse_o      => wr_pulse,
+		rd_pulse_o      => rd_pulse,
+		rd_wr_o         => rd_wr
+	);
+
+end i2c_rom;
diff --git a/fpga/src/i2c/slave/i2c_slave.vhd b/fpga/src/i2c/slave/i2c_slave.vhd
new file mode 100644
index 0000000..a6a5471
--- /dev/null
+++ b/fpga/src/i2c/slave/i2c_slave.vhd
@@ -0,0 +1,282 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+--
+-- Verilog to VHDL translation of:
+-- http://www.eda365.com/thread-31086-1-1.html
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity i2c_slave is
+	generic (ADDRESS : std_logic_vector(6 downto 0) := "0110101"); -- 6A write, 6B read
+	port (
+		clk             : in  std_logic;
+		rst_n           : in  std_logic;
+		sda_i           : in  std_logic;
+		sda_o           : out std_logic;
+		scl_i           : in  std_logic;
+		rd_dat_i        : in  std_logic_vector(7 downto 0);
+		addr_o          : out std_logic_vector(7 downto 0);
+		wr_dat_o        : out std_logic_vector(7 downto 0);
+		wr_pulse_o      : out std_logic;
+		rd_pulse_o      : out std_logic;
+		rd_wr_o         : out std_logic
+	);
+end i2c_slave;
+
+architecture i2c_slave of i2c_slave is
+	signal sda_sr        : std_logic_vector(3 downto 0);
+	signal scl_sr        : std_logic_vector(3 downto 0);
+	signal sda, was_sda  : std_logic;
+	signal sda_in        : std_logic;
+	signal scl, was_scl  : std_logic;
+	signal scl_in        : std_logic;
+	signal i2c_start     : std_logic;
+	signal i2c_stop      : std_logic;
+	signal ack_cyc       : std_logic;
+	signal byte_count    : unsigned(3 downto 0);
+	signal was_ack       : std_logic;
+	signal addr_byte     : std_logic;
+	signal addr_ack      : std_logic;
+	signal subad_byte    : std_logic;
+	signal subad_ack     : std_logic;
+	signal wr_pulse      : std_logic;
+	signal rd_pulse      : std_logic;
+	signal rd_wr         : std_logic;
+	signal wr_dat        : std_logic_vector(7 downto 0);
+	signal addr          : unsigned(7 downto 0);
+	signal out_sr        : std_logic_vector(7 downto 0);
+	signal in_sr         : std_logic_vector(7 downto 0);
+	signal wr_pls_dly    : std_logic;
+	signal rd_pls_dly    : std_logic;
+	signal drive_sda     : std_logic;
+	signal my_cyc        : std_logic;
+	signal data_byte     : std_logic;
+begin
+	wr_dat_o   <= wr_dat;
+	addr_o     <= std_logic_vector(addr);
+	rd_wr_o    <= rd_wr;
+	wr_pulse_o <= wr_pulse;
+	rd_pulse_o <= rd_pulse;
+	sda_o      <= '0' when drive_sda = '1' else '1';
+
+	-- Debounce, then delay debounced signals for edge detection
+	debounce: process (clk, rst_n)
+	begin
+	if rst_n = '0' then
+		sda_sr  <= "1111";  -- Start up assuming quiescent state of inputs
+		sda     <= '1';
+		was_sda <= '0';
+		scl_sr  <= "1111";  -- Start up assuming quiescent state of inputs
+		scl     <= '1';
+		was_scl <= '0';
+		sda_in  <= '1';
+	elsif rising_edge(clk) then
+		sda_in  <= sda_i;
+		scl_in  <= scl_i;
+
+		sda_sr  <= sda_sr(2 downto 0) & sda_in;
+		if sda_sr = "0000" then
+			sda <= '0';
+		elsif sda_sr = "1111" then
+			sda <= '1';
+		end if;
+		was_sda <= sda;
+
+		scl_sr <= scl_sr(2 downto 0) & scl_in;
+		if scl_sr = "0000" then
+			scl <= '0';
+		elsif scl_sr = "1111" then
+			scl <= '1';
+		end if;
+		was_scl <= scl;
+	end if;
+	end process;
+
+	ack_cyc <= byte_count(3);
+	process (clk, rst_n)
+	begin
+	if rst_n = '0' then
+		i2c_start    <= '0';
+		i2c_stop     <= '0';
+		byte_count   <= (others => '0');
+		was_ack      <= '0';
+		addr_byte    <= '0';
+		addr_ack     <= '0';
+		subad_byte   <= '0';
+		subad_ack    <= '0';
+		wr_pulse     <= '0';
+		rd_pulse     <= '0';
+		wr_dat       <= (others => '0');
+		addr         <= (others => '0');
+		out_sr       <= (others => '1');
+		in_sr        <= (others => '0');
+		wr_pls_dly   <= '0';
+		rd_pls_dly   <= '0';
+		rd_wr        <= '0';
+		drive_sda    <= '0';
+		my_cyc       <= '0';
+	elsif rising_edge(clk) then
+		-- Falling edge of SDA with SCL high
+		if scl = '1' and was_scl = '1' and sda = '0' and was_sda = '1' then
+			i2c_start <= '1';
+		elsif scl = '0' and was_scl = '0' then -- Hold until SCL has fallen
+			i2c_start <= '0';
+		end if;
+
+		-- Rising edge of SDA with SCL high
+		-- i2c_stop is only on for one clock cycle
+		i2c_stop <= scl and was_scl and sda and not was_sda;
+
+
+		-- Increment bit counter on falling edges of the
+		-- SCL signal after the first in a packet.
+		-- Count bit position within bytes:
+		if i2c_start = '1' then
+			byte_count <= (others => '0');
+		elsif scl = '0' and was_scl = '1' and i2c_start = '0' then
+			if ack_cyc = '1' then
+				byte_count <= (others => '0');
+			else
+				byte_count <= byte_count + "1";
+			end if;
+		end if;
+
+		-- For edge detection of ack cycles:
+		was_ack <= ack_cyc;
+
+		-- addr_byte is on during the first byte transmitted after
+		-- a START condition.
+		if i2c_start = '1' then
+			addr_byte <= '1';
+		elsif ack_cyc = '1' then
+			addr_byte <= '0';
+		end if;
+
+		-- addr_ack is on during acknowledge cycle of the address
+		-- byte.
+		if addr_byte = '1' and ack_cyc = '1' then
+			addr_ack <= '1';
+		elsif ack_cyc = '0' then
+			addr_ack <= '0';
+		end if;
+
+		-- subad_byte is on for the second byte of my write cycle.
+		if addr_ack = '1' and ack_cyc = '0' and rd_wr = '0' and my_cyc = '1' then
+			subad_byte <= '1';
+		elsif ack_cyc = '1' then
+			subad_byte <= '0';
+		end if;
+
+		-- subad_ack is on during the acknowledge cycle of the
+		-- subaddress byte.
+		if subad_byte = '1' and ack_cyc = '1' then
+			subad_ack <= '1';
+		elsif ack_cyc = '0' then
+			subad_ack <= '0';
+		end if;
+
+		-- data_byte is on for my read or write data cycles.  This is
+		-- any read cycle after the address, or write cycles after
+		-- the subaddress.  It remains on until the I2C STOP event or
+		-- any NACK.
+		if (addr_ack = '1' and ack_cyc = '0' and rd_wr = '1' and my_cyc = '1')
+		or (subad_ack = '1' and ack_cyc = '0') then
+			data_byte <= '1';
+		elsif i2c_stop = '1' or (ack_cyc = '1' and scl = '1' and sda = '1') then
+			data_byte <= '0';
+		end if;
+
+		-- wr_pulse_o is on for one clock cycle while the data
+		-- on the output bus is valid.
+		wr_pulse <= data_byte and not ack_cyc and was_ack and not rd_wr;
+		-- rd_pulse_o is on for one clock cycle when external
+		-- read data is transfered into the output shift register
+		-- for transmission to the I2C bus.
+		rd_pulse <= (addr_ack and not ack_cyc and rd_wr and my_cyc)    -- First read cycle
+		         or (data_byte and not ack_cyc and was_ack and rd_wr); -- Subsequent read cycles
+
+
+		-- wr_dat_o is loaded from the I2C input S/R at the
+		-- end of each write data cycle.
+		if data_byte = '1' and ack_cyc = '1' and was_ack = '0' and rd_wr = '0' then
+			wr_dat <= in_sr;
+		end if;
+
+		-- out_sr shifts data out to the I2C bus during read
+		-- data cycles.  Transitions occur after the falling
+		-- edge of SCL.  Fills with 1's from right.
+		if rd_pulse = '1' then
+			out_sr <= rd_dat_i;
+		elsif scl = '0' and was_scl = '1' then
+			out_sr <= out_sr(6 downto 0) & '1';
+		end if;
+
+		-- Delayed pulses for incrementing subaddress:
+		wr_pls_dly <= wr_pulse;
+		rd_pls_dly <= rd_pulse;
+
+		-- addr_o is loaded after the second byte of a write
+		-- cycle has fully shifted in.  It increments after each
+		-- read or write access.
+		if subad_byte = '1' and ack_cyc = '1' then
+			addr <= unsigned(in_sr);
+		elsif wr_pls_dly = '1' or rd_pls_dly = '1' then
+			-- Leave Out this else clause for simple single register version
+			-- In this case addr_o becomes the register output and should be
+			-- wrapped back to rd_dat_i externally
+			addr <= addr + "1";
+		end if;
+
+		-- Shift I2C data in after rising edge of SCL.
+		if scl = '1' and was_scl = '0' then
+			in_sr <= in_sr(6 downto 0) & sda;
+		end if;
+
+		-- Read / not Write.  For external bus drivers if necessary.
+		-- Latch the Read bit of the address cycle.
+		if addr_byte = '1' and ack_cyc = '1' then
+			rd_wr <= in_sr(0);
+		end if;
+
+		-- Decode address.  My cycle if address upper 7 bits
+		-- match with i2c_address defined above.
+		if i2c_start = '1' then
+			my_cyc <= '0'; --- ??!?!?
+		elsif addr_byte = '1' and ack_cyc = '1' then
+			if in_sr(7 downto 1) = ADDRESS then
+				my_cyc <= '1';
+			else
+				my_cyc <= '1';
+			end if;
+		end if;
+
+		-- I2C data output drive low signal (1 = drive SDA low)
+		-- Invert this signal for T input of OBUFT or IOBUF
+		-- or use it directly for OBUFE.
+		drive_sda <= (my_cyc and addr_ack)                                    -- Address acknowledge
+		          or (my_cyc and not rd_wr and ack_cyc)                       -- Write byte acknowledge
+		          or (data_byte and rd_wr and not ack_cyc and not out_sr(7)); -- Read Data
+	end if;
+	end process;
+
+end i2c_slave;
diff --git a/fpga/src/sig/ddr2dvi.vhd b/fpga/src/sig/ddr2dvi.vhd
new file mode 100644
index 0000000..d59ce75
--- /dev/null
+++ b/fpga/src/sig/ddr2dvi.vhd
@@ -0,0 +1,194 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.dvi_package.all;
+
+library UNISIM;
+use UNISIM.Vcomponents.all;
+
+entity ddr2dvi is
+	port (
+		clk                   : in  std_logic;
+		rst_n                 : in  std_logic;
+		rst_pll               : in  std_logic;
+
+		tx_tmds               : out std_logic_vector(3 downto 0);
+		tx_tmds_n             : out std_logic_vector(3 downto 0);
+		tx_pll_locked_o       : out std_logic;
+
+		-- memory interface
+		ddr2_cmd_en_o         : out std_logic;
+		ddr2_cmd_instr_o      : out std_logic_vector( 2 downto 0);
+		ddr2_cmd_bl_o         : out std_logic_vector( 5 downto 0);
+		ddr2_cmd_byte_addr_o  : out std_logic_vector(29 downto 0);
+		ddr2_cmd_empty_i      : in  std_logic;
+		ddr2_cmd_full_i       : in  std_logic;
+
+		ddr2_rd_en_o          : out std_logic;
+		ddr2_rd_data_i        : in  std_logic_vector(31 downto 0);
+		ddr2_rd_full_i        : in  std_logic;
+		ddr2_rd_empty_i       : in  std_logic;
+		ddr2_rd_count_i       : in  std_logic_vector( 6 downto 0);
+		ddr2_rd_overflow_i    : in  std_logic;
+		ddr2_rd_error_i       : in  std_logic
+	);
+end ddr2dvi;
+
+architecture ddr2dvi of ddr2dvi is
+	signal pclk                     : std_logic;
+	signal pclk_buf                 : std_logic;
+	signal tx_hsync                 : std_logic;
+	signal tx_vsync                 : std_logic;
+	signal tx_color_en              : std_logic;
+	signal tx_color                 : color_t(COLOR_CNT-1 downto 0);
+	signal tx_pclkx2                : std_logic;
+	signal tx_pclkx10               : std_logic;
+	signal tx_reset_n               : std_logic;
+	signal tx_serdesstrobe          : std_logic;
+	signal tx_clkfbout              : std_logic;
+	signal tx_clkfbin               : std_logic;
+	signal tx_plllckd               : std_logic;
+	signal tx_pllclk0               : std_logic;
+	signal tx_pllclk2               : std_logic;
+	signal tx_bufpll_lock           : std_logic;
+begin
+	tx_pll_locked_o <= tx_plllckd;
+
+	-- ----------------------------------------------------------------------------
+	-- DDR2 READ Signal Generator
+	-- ----------------------------------------------------------------------------
+	sig_read_0: entity work.sig_read
+	generic map (
+		MEM_START_ADR  => "00" & x"0000000",
+		H_ACTIVE_PIXEL => x"500",
+		H_BLANKING     => x"198",
+		H_SYNC_WIDTH   => x"070",
+		H_SYNC_OFFSET  => x"030",
+		V_ACTIVE_LINES => x"400",
+		V_BLANKING     => x"02a",
+		V_SYNC_WIDTH   => x"01",
+		V_SYNC_OFFSET  => x"03"
+	)
+	port map (
+		clk                   => pclk,
+		rst_n                 => rst_n,
+
+		-- memory interface
+		ddr2_clk              => clk,
+		ddr2_cmd_en_o         => ddr2_cmd_en_o,
+		ddr2_cmd_instr_o      => ddr2_cmd_instr_o,
+		ddr2_cmd_bl_o         => ddr2_cmd_bl_o,
+		ddr2_cmd_byte_addr_o  => ddr2_cmd_byte_addr_o,
+		ddr2_cmd_empty_i      => ddr2_cmd_empty_i,
+		ddr2_cmd_full_i       => ddr2_cmd_full_i,
+
+		ddr2_rd_en_o          => ddr2_rd_en_o,
+		ddr2_rd_data_i        => ddr2_rd_data_i,
+		ddr2_rd_full_i        => ddr2_rd_full_i,
+		ddr2_rd_empty_i       => ddr2_rd_empty_i,
+		ddr2_rd_count_i       => ddr2_rd_count_i,
+		ddr2_rd_overflow_i    => ddr2_rd_overflow_i,
+		ddr2_rd_error_i       => ddr2_rd_error_i,
+
+		en_stb_i              => '1',
+		hsync_o               => tx_hsync,
+		vsync_o               => tx_vsync,
+		color_en_o            => tx_color_en,
+		color_o               => tx_color
+	);
+
+	-- ----------------------------------------------------------------------------
+	-- Instantiate a dedicate PLL for output port
+	-- ----------------------------------------------------------------------------
+	--pclk <= ddr2_clk_out;
+	pll_oserdes_0: PLL_BASE
+	generic map (
+		CLKIN_PERIOD   => 9.0,
+		CLKFBOUT_MULT  => 29, --10 --set VCO to 10x of CLKIN
+		DIVCLK_DIVIDE  => 3,
+		CLKOUT0_DIVIDE => 1,
+		CLKOUT1_DIVIDE => 10,
+		CLKOUT2_DIVIDE => 5,
+		COMPENSATION   => "SOURCE_SYNCHRONOUS"
+	)
+	port map (
+		CLKFBOUT  => tx_clkfbout,
+		CLKOUT0   => tx_pllclk0,
+		CLKOUT1   => pclk_buf,
+		CLKOUT2   => tx_pllclk2,
+		CLKOUT3   => open,
+		CLKOUT4   => open,
+		CLKOUT5   => open,
+		LOCKED    => tx_plllckd,
+		CLKFBIN   => tx_clkfbin,
+		CLKIN     => clk,
+		RST       => rst_pll
+	);
+
+	pclk_buf_0: BUFG port map(I => pclk_buf, O => pclk);
+
+	-- ----------------------------------------------------------------------------
+	-- This BUFG is needed in order to deskew between PLL clkin and clkout
+	-- So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input
+	-- ----------------------------------------------------------------------------
+	tx_clkfb_buf: BUFG port map(I => tx_clkfbout, O => tx_clkfbin);
+
+	-- --------------------------------
+	-- regenerate pclkx2 for TX
+	-- --------------------------------
+	tx_pclkx2_buf: BUFG port map(I => tx_pllclk2, O => tx_pclkx2);
+
+	-- --------------------------------
+	-- regenerate pclkx10 for TX
+	-- --------------------------------
+	tx_ioclk_buf: BUFPLL
+	generic map ( DIVIDE => 5 )
+	port map (
+		PLLIN        => tx_pllclk0,
+		GCLK         => tx_pclkx2,
+		LOCKED       => tx_plllckd,
+		IOCLK        => tx_pclkx10,
+		SERDESSTROBE => tx_serdesstrobe,
+		LOCK         => tx_bufpll_lock
+	);
+	tx_reset_n <= tx_bufpll_lock;
+
+	dvi_encoder_0: entity work.dvi_encoder
+	port map (
+		rst_n          => tx_reset_n,
+		pclk           => pclk,
+		pclkx2         => tx_pclkx2,
+		pclkx10        => tx_pclkx10,
+		serdesstrobe_i => tx_serdesstrobe,
+		color_i        => tx_color,
+		hsync_i        => tx_hsync,
+		vsync_i        => tx_vsync,
+		dat_en_i       => tx_color_en,
+		tmds_p         => tx_tmds,
+		tmds_n         => tx_tmds_n
+	);
+
+end ddr2dvi;
diff --git a/fpga/src/sig/dvi2ddr.vhd b/fpga/src/sig/dvi2ddr.vhd
new file mode 100644
index 0000000..5aac210
--- /dev/null
+++ b/fpga/src/sig/dvi2ddr.vhd
@@ -0,0 +1,112 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.dvi_package.all;
+
+library UNISIM;
+use UNISIM.Vcomponents.all;
+
+entity dvi2ddr is
+	port (
+		clk                   : in  std_logic;
+		rst                   : in  std_logic;
+
+		ctrl_disable_wr       : in  std_logic;
+		
+		rx_tmds               : in  std_logic_vector(3 downto 0);
+		rx_tmds_n             : in  std_logic_vector(3 downto 0);
+
+		-- memory interface
+		ddr2_cmd_en_o         : out std_logic;
+		ddr2_cmd_instr_o      : out std_logic_vector( 2 downto 0);
+		ddr2_cmd_bl_o         : out std_logic_vector( 5 downto 0);
+		ddr2_cmd_byte_addr_o  : out std_logic_vector(29 downto 0);
+		ddr2_cmd_empty_i      : in  std_logic;
+		ddr2_cmd_full_i       : in  std_logic;
+		ddr2_wr_en_o          : out std_logic;
+		ddr2_wr_mask_o        : out std_logic_vector( 3 downto 0);
+		ddr2_wr_data_o        : out std_logic_vector(31 downto 0);
+		ddr2_wr_full_i        : in  std_logic;
+		ddr2_wr_empty_i       : in  std_logic;
+		ddr2_wr_count_i       : in  std_logic_vector( 6 downto 0);
+		ddr2_wr_underrun_i    : in  std_logic;
+		ddr2_wr_error_i       : in  std_logic
+	);
+end dvi2ddr;
+
+architecture dvi2ddr of dvi2ddr is
+	signal rx_tmds_s                : std_logic_vector(3 downto 0);
+	signal rx_color                 : color_t(COLOR_CNT-1 downto 0);
+	signal rx_color_en              : std_logic;
+	signal rx_pll_lckd              : std_logic;
+	signal rx_rst_n                 : std_logic;
+	signal rx_pclk                  : std_logic;
+	signal rx_hsync                 : std_logic;
+	signal rx_vsync                 : std_logic;
+begin
+	-- ----------------------------------------------------------------------------
+	-- HDMI to DDR2
+	-- ----------------------------------------------------------------------------
+	dvi_decoder_0: entity work.dvi_decoder
+	port map (
+		ext_rst        => rst,
+
+		tmdsclk_p      => rx_tmds(3),
+		tmdsclk_n      => rx_tmds_n(3),
+		din_p          => rx_tmds(2 downto 0),
+		din_n          => rx_tmds_n(2 downto 0),
+
+		reset_n        => rx_rst_n,    -- rx reset
+		pclk_o         => rx_pclk,     -- regenerated pixel clock
+		pclkx2_o       => open,         -- double rate pixel clock
+		pclkx10_o      => open,         -- 10x pixel as IOCLK
+
+		pll_lckd_o     => rx_pll_lckd,     -- send pll_lckd out so it can be fed into a different BUFPLL
+		serdesstrobe_o => open,         -- BUFPLL serdesstrobe output
+		tmdsclk_o      => open,         -- TMDS cable clock
+
+		hsync_o        => rx_hsync,    -- hsync data
+		vsync_o        => rx_vsync,    -- vsync data
+		valid_o        => open,
+		ready_o        => open,
+		psalgnerr_o    => open,
+		sdout_o        => open,
+		dat_en_o       => rx_color_en, -- data enable
+		color_o        => rx_color
+	);
+
+	sig_write_0: entity work.sig_write
+	generic map (MEM_START_ADR => "00" & x"0000000")
+	port map (
+		clk                   => rx_pclk,
+		rst_n                 => rx_rst_n,
+		ctrl_disable_wr       => ctrl_disable_wr,
+
+		-- memory interface
+		ddr2_clk              => clk,
+		ddr2_cmd_en_o         => ddr2_cmd_en_o,
+		ddr2_cmd_instr_o      => ddr2_cmd_instr_o,
+		ddr2_cmd_bl_o         => ddr2_cmd_bl_o,
+		ddr2_cmd_byte_addr_o  => ddr2_cmd_byte_addr_o,
+		ddr2_cmd_empty_i      => ddr2_cmd_empty_i,
+		ddr2_cmd_full_i       => ddr2_cmd_full_i,
+
+		ddr2_wr_en_o          => ddr2_wr_en_o,
+		ddr2_wr_mask_o        => ddr2_wr_mask_o,
+		ddr2_wr_data_o        => ddr2_wr_data_o,
+		ddr2_wr_full_i        => ddr2_wr_full_i,
+		ddr2_wr_empty_i       => ddr2_wr_empty_i,
+		ddr2_wr_count_i       => ddr2_wr_count_i,
+		ddr2_wr_underrun_i    => ddr2_wr_underrun_i,
+		ddr2_wr_error_i       => ddr2_wr_error_i,
+
+		-- display output
+		hsync_i               => rx_hsync,
+		vsync_i               => rx_vsync,
+		color_en_i            => rx_color_en,
+		color_i               => rx_color
+	);
+
+end dvi2ddr;
diff --git a/fpga/src/sig/sig.vhd b/fpga/src/sig/sig.vhd
new file mode 100644
index 0000000..137a018
--- /dev/null
+++ b/fpga/src/sig/sig.vhd
@@ -0,0 +1,127 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.dvi_package.all;
+
+entity sig is
+	generic (
+		H_ACTIVE_PIXEL : unsigned(11 downto 0) := x"5a0";
+		H_BLANKING     : unsigned(11 downto 0) := x"0dd";
+		H_SYNC_WIDTH   : unsigned(11 downto 0) := x"03c";
+		H_SYNC_OFFSET  : unsigned(11 downto 0) := x"050"; -- front porch
+		V_ACTIVE_LINES : unsigned(11 downto 0) := x"21c";
+		V_BLANKING     : unsigned(11 downto 0) := x"022";
+		V_SYNC_WIDTH   : unsigned( 7 downto 0) := x"02";
+		V_SYNC_OFFSET  : unsigned( 7 downto 0) := x"18"   -- front porch
+	);
+	port (
+		clk        : in  std_logic;
+		rst_n      : in  std_logic;
+
+		-- memory interface
+		--address_o  : out std_logic_vector();
+
+		-- display output
+		en_stb_i   : in  std_logic;
+		hsync_o    : out std_logic;
+		vsync_o    : out std_logic;
+		color_en_o : out std_logic;
+		color_o    : out color_t
+	);
+end sig;
+
+architecture sig of sig is
+	signal h_cnt            : unsigned(11 downto 0);
+	signal v_cnt            : unsigned(11 downto 0);
+	signal one_screen       : std_logic;
+	signal h_state          : unsigned(1 downto 0);
+	signal h_state_i        : unsigned(1 downto 0);
+	signal v_state          : unsigned(1 downto 0);
+	signal v_state_i        : unsigned(1 downto 0);
+	constant SYNC_OFF       : unsigned(1 downto 0) := "00";
+	constant SYNC           : unsigned(1 downto 0) := "01";
+	constant SYNC_BACK      : unsigned(1 downto 0) := "10";
+	constant ACTIVE_LINE    : unsigned(1 downto 0) := "11";
+
+	constant H_SYNC_BACK    : unsigned(11 downto 0) := H_BLANKING - H_SYNC_OFFSET - H_SYNC_WIDTH;
+	constant V_SYNC_BACK    : unsigned(11 downto 0) := V_BLANKING - V_SYNC_OFFSET - V_SYNC_WIDTH;
+begin
+	hsync_o    <= '1' when h_state = SYNC and v_state = ACTIVE_LINE else '0';
+	vsync_o    <= '1' when v_state = SYNC                           else '0';
+	color_en_o <= '1' when h_state = ACTIVE_LINE and v_state = ACTIVE_LINE else '0';
+	color_o    <= ((others => v_cnt(3)), (others => v_cnt(2)), (others => v_cnt(1)));
+
+	process (clk, rst_n)
+	begin
+	if rst_n = '0' then
+		h_cnt      <= x"000"; 
+		v_cnt      <= x"000";
+		v_state    <= "00";
+		v_state_i  <= "00";
+		h_state    <= "00";
+		h_state_i  <= "00";
+		one_screen <= '0';
+	elsif rising_edge(clk) then
+		if v_state = ACTIVE_LINE and v_cnt = x"000" then
+			one_screen <= '0';
+		elsif en_stb_i = '1' then
+			one_screen <= '1';
+		end if;
+
+		if one_screen = '1' and h_cnt = x"000" then
+			h_state <= h_state_i;
+			case h_state_i is
+			when SYNC_OFF    => h_cnt <= H_SYNC_OFFSET-1;
+			when SYNC        => h_cnt <= H_SYNC_WIDTH-1;
+			when SYNC_BACK   => h_cnt <= H_SYNC_BACK-1;
+			when ACTIVE_LINE => h_cnt <= H_ACTIVE_PIXEL-1;
+			when others      => h_cnt <= x"000";
+			end case;
+		elsif h_cnt /= x"000" then
+			h_cnt <= h_cnt - "1";
+		end if;
+
+		if one_screen = '1' and h_cnt = x"000" then
+			h_state_i <= h_state_i + "01";
+		end if;
+
+		if one_screen = '1' and v_cnt = x"000" and h_state = SYNC_OFF then
+			v_state <= v_state_i;
+			case v_state_i is
+			when SYNC_OFF    => v_cnt <= x"0" & V_SYNC_OFFSET;
+			when SYNC        => v_cnt <= x"0" & V_SYNC_WIDTH;
+			when SYNC_BACK   => v_cnt <= V_SYNC_BACK;
+			when ACTIVE_LINE => v_cnt <= V_ACTIVE_LINES;
+			when others      => v_cnt <= x"000";
+			end case;
+		elsif v_cnt /= x"000" and (h_state = ACTIVE_LINE and h_cnt = x"000") then
+			v_cnt <= v_cnt - "1";
+		end if;
+
+		if one_screen = '1' and v_cnt = x"000" then
+			v_state_i <= v_state_i + "01";
+		end if;
+	end if;
+	end process;
+end sig;
diff --git a/fpga/src/sig/sig_read.vhd b/fpga/src/sig/sig_read.vhd
new file mode 100644
index 0000000..699b064
--- /dev/null
+++ b/fpga/src/sig/sig_read.vhd
@@ -0,0 +1,281 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.dvi_package.all;
+
+entity sig_read is
+	generic (
+		MEM_START_ADR  : unsigned(29 downto 0) := "00" & x"0000000";
+		H_ACTIVE_PIXEL : unsigned(11 downto 0) := x"5a0";
+		H_BLANKING     : unsigned(11 downto 0) := x"0dd";
+		H_SYNC_WIDTH   : unsigned(11 downto 0) := x"03c";
+		H_SYNC_OFFSET  : unsigned(11 downto 0) := x"050"; -- front porch
+		V_ACTIVE_LINES : unsigned(11 downto 0) := x"21c";
+		V_BLANKING     : unsigned(11 downto 0) := x"022";
+		V_SYNC_WIDTH   : unsigned( 7 downto 0) := x"02";
+		V_SYNC_OFFSET  : unsigned( 7 downto 0) := x"18"   -- front porch
+	);
+	port (
+		clk                   : in  std_logic;
+		rst_n                 : in  std_logic;
+
+		-- memory interface
+		ddr2_clk              : in  std_logic;
+		ddr2_cmd_en_o         : out std_logic;
+		ddr2_cmd_instr_o      : out std_logic_vector( 2 downto 0);
+		ddr2_cmd_bl_o         : out std_logic_vector( 5 downto 0);
+		ddr2_cmd_byte_addr_o  : out std_logic_vector(29 downto 0);
+		ddr2_cmd_empty_i      : in  std_logic;
+		ddr2_cmd_full_i       : in  std_logic;
+
+		ddr2_rd_en_o          : out std_logic;
+		ddr2_rd_data_i        : in  std_logic_vector(31 downto 0);
+		ddr2_rd_full_i        : in  std_logic;
+		ddr2_rd_empty_i       : in  std_logic;
+		ddr2_rd_count_i       : in  std_logic_vector( 6 downto 0);
+		ddr2_rd_overflow_i    : in  std_logic;
+		ddr2_rd_error_i       : in  std_logic;
+
+		-- display output
+		en_stb_i              : in  std_logic;
+		hsync_o               : out std_logic;
+		vsync_o               : out std_logic;
+		color_en_o            : out std_logic;
+		color_o               : out color_t(COLOR_CNT-1 downto 0)
+	);
+end sig_read;
+
+architecture sig_read of sig_read is
+	signal rst              : std_logic;
+	signal h_cnt            : unsigned(11 downto 0);
+	signal v_cnt            : unsigned(11 downto 0);
+	signal one_screen       : std_logic;
+	signal h_state          : unsigned(1 downto 0);
+	signal h_state_m        : unsigned(1 downto 0);
+	signal h_state_v        : unsigned(1 downto 0);
+	signal h_state_i        : unsigned(1 downto 0);
+	signal v_state          : unsigned(1 downto 0);
+	signal v_state_m        : unsigned(1 downto 0);
+	signal v_state_v        : unsigned(1 downto 0);
+	signal v_state_i        : unsigned(1 downto 0);
+	constant SYNC_OFF       : unsigned(1 downto 0) := "00";
+	constant SYNC           : unsigned(1 downto 0) := "01";
+	constant SYNC_BACK      : unsigned(1 downto 0) := "10";
+	constant ACTIVE_LINE    : unsigned(1 downto 0) := "11";
+
+	constant H_SYNC_BACK    : unsigned(11 downto 0) := H_BLANKING - H_SYNC_OFFSET - H_SYNC_WIDTH;
+	constant V_SYNC_BACK    : unsigned(11 downto 0) := V_BLANKING - V_SYNC_OFFSET - V_SYNC_WIDTH;
+
+	signal disp_rd_en       : std_logic;
+	signal disp_rd_data     : color_t(COLOR_CNT-1 downto 0);
+
+	signal px_fifo_rd_en    : std_logic;
+	signal px_fifo_full     : std_logic;
+	signal px_fifo_empty    : std_logic;
+	signal px_fifo_cnt      : std_logic_vector(10 downto 0);
+	signal px_fifo_dat_out  : std_logic_vector(31 downto 0);
+
+	-- memory
+	signal mem_address      : unsigned(27 downto 0);
+	signal mem_burst_len    : unsigned( 5 downto 0);
+	signal mem_cmd_en       : std_logic;
+	signal mem_rd_en        : std_logic;
+	signal mem_rd_data      : std_logic_vector(31 downto 0);
+	signal mem_rd_cnt       : unsigned( 6 downto 0);
+	signal mem_fetch_cnt    : unsigned( 5 downto 0);
+	signal mem_read_cnt     : unsigned( 6 downto 0);
+	signal mem_read_wait    : std_logic;
+
+	signal new_line         : std_logic;
+	signal new_line_q0      : std_logic;
+	signal new_line_q1      : std_logic;
+	signal new_line_q2      : std_logic;
+	signal new_line_q3      : std_logic;
+	signal new_line_s       : std_logic;
+begin
+	rst <= not rst_n;
+	-- -------------------------------------------------------------------------------
+	-- MEMORY
+	-- -------------------------------------------------------------------------------
+	ddr2_cmd_byte_addr_o <= std_logic_vector(mem_address(27 downto 0) & "00");
+	ddr2_cmd_bl_o        <= std_logic_vector(mem_burst_len);
+	ddr2_cmd_instr_o     <= "001"; -- only read from this interface
+	ddr2_cmd_en_o        <= mem_cmd_en;
+	ddr2_rd_en_o         <= mem_rd_en;
+	mem_rd_cnt           <= unsigned(ddr2_rd_count_i);
+
+	new_line   <= '1' when h_state_v = SYNC and v_state_v = ACTIVE_LINE else '0';
+	new_line_s <= new_line and new_line_q0 and not new_line_q1 and not new_line_q2;
+	process (ddr2_clk, rst_n)
+	begin
+	if rst_n = '0' then
+		mem_address   <= (others => '0');
+		mem_cmd_en    <= '0';
+		mem_burst_len <= (others => '0');
+		mem_fetch_cnt <= (others => '0');
+		h_state_m     <= (others => '0');
+		h_state_v     <= (others => '0');
+		v_state_m     <= (others => '0');
+		v_state_v     <= (others => '0');
+		new_line_q0   <= '0';
+		new_line_q1   <= '0';
+		new_line_q2   <= '0';
+		new_line_q3   <= '0';
+		mem_read_cnt  <= (others => '0');
+		mem_read_wait <= '0';
+	elsif rising_edge(ddr2_clk) then
+		new_line_q0 <= new_line;
+		new_line_q1 <= new_line_q0;
+		new_line_q2 <= new_line_q1;
+		new_line_q3 <= new_line_q2;
+
+		-- synchronizer
+		h_state_m <= h_state;
+		h_state_v <= h_state_m;
+		v_state_m <= v_state;
+		v_state_v <= v_state_m;
+
+		-- calculate memory fetch count
+		if new_line_s = '1' then
+			mem_fetch_cnt <= H_ACTIVE_PIXEL(11 downto 6);
+		elsif mem_cmd_en = '1' then
+			mem_fetch_cnt <= mem_fetch_cnt - "1";
+		end if;
+
+		-- wait state
+		if mem_cmd_en = '1' then
+			mem_read_wait <= '1';
+		elsif mem_read_cnt = "0101111" and mem_read_wait = '1' then
+			mem_read_wait <= '0';
+		end if;
+
+		-- mem raw read count
+		if mem_read_cnt = x"40" and mem_rd_en = '1' then
+			mem_read_cnt <= "0000001";
+		elsif mem_read_cnt = x"40" then
+			mem_read_cnt <= (others => '0');
+		elsif mem_rd_en = '1' then
+			mem_read_cnt <= mem_read_cnt + "1";
+		end if;
+
+		mem_cmd_en <= '0';
+		if  ddr2_cmd_full_i = '0' and mem_fetch_cnt /= "000000" and mem_cmd_en = '0' and mem_read_wait = '0' then
+			mem_cmd_en    <= '1';
+			mem_burst_len <= "111111";
+		end if;
+
+		if v_state_v = SYNC then
+			mem_address   <= MEM_START_ADR(29 downto 2);
+		elsif mem_cmd_en = '1' then
+			mem_address   <= mem_address + x"040";
+		end if;
+
+	end if;
+	end process;
+	mem_rd_data  <= ddr2_rd_data_i;
+	mem_rd_en    <= not ddr2_rd_empty_i;
+
+	px_fifo_0: entity work.px_fifo
+	port map (
+		wr_clk        => ddr2_clk,
+		rd_clk        => clk,
+		rst           => rst,
+		din           => mem_rd_data,
+		wr_en         => mem_rd_en,
+		rd_en         => px_fifo_rd_en,
+		dout          => px_fifo_dat_out,
+		full          => px_fifo_full,
+		empty         => px_fifo_empty,
+		rd_data_count => px_fifo_cnt
+	);
+
+	px_fifo_rd_en <= disp_rd_en and not px_fifo_empty;
+	disp_rd_en   <= '1' when h_state = ACTIVE_LINE and v_state = ACTIVE_LINE else '0';
+	disp_rd_data <= (px_fifo_dat_out(23 downto 16), px_fifo_dat_out(15 downto 8), px_fifo_dat_out(7 downto 0))
+	                when px_fifo_empty = '0' else
+	                (x"ff", x"00", x"00");
+
+	-- -------------------------------------------------------------------------------
+	-- DISPLAY
+	-- -------------------------------------------------------------------------------
+	hsync_o    <= '1' when h_state = SYNC and v_state = ACTIVE_LINE else '0';
+	vsync_o    <= '1' when v_state = SYNC                           else '0';
+	color_en_o <= disp_rd_en;
+	color_o    <= disp_rd_data;
+	--color_en_o <= '1' when h_state = ACTIVE_LINE and v_state = ACTIVE_LINE else '0';
+	--color_o    <= ((others => v_cnt(3)), (others => v_cnt(2)), (others => v_cnt(1)));
+
+	process (clk, rst_n)
+	begin
+	if rst_n = '0' then
+		h_cnt      <= x"000";
+		v_cnt      <= x"000";
+		v_state    <= "00";
+		v_state_i  <= "00";
+		h_state    <= "00";
+		h_state_i  <= "00";
+		one_screen <= '0';
+	elsif rising_edge(clk) then
+		if v_state = ACTIVE_LINE and v_cnt = x"000" then
+			one_screen <= '0';
+		elsif en_stb_i = '1' then
+			one_screen <= '1';
+		end if;
+
+		if one_screen = '1' and h_cnt = x"000" then
+			h_state <= h_state_i;
+			case h_state_i is
+			when SYNC_OFF    => h_cnt <= H_SYNC_OFFSET-1;
+			when SYNC        => h_cnt <= H_SYNC_WIDTH-1;
+			when SYNC_BACK   => h_cnt <= H_SYNC_BACK-1;
+			when ACTIVE_LINE => h_cnt <= H_ACTIVE_PIXEL-1;
+			when others      => h_cnt <= x"000";
+			end case;
+		elsif h_cnt /= x"000" then
+			h_cnt <= h_cnt - "1";
+		end if;
+
+		if one_screen = '1' and h_cnt = x"000" then
+			h_state_i <= h_state_i + "01";
+		end if;
+
+		if one_screen = '1' and v_cnt = x"000" and h_state = SYNC_OFF then
+			v_state <= v_state_i;
+			case v_state_i is
+			when SYNC_OFF    => v_cnt <= x"0" & V_SYNC_OFFSET;
+			when SYNC        => v_cnt <= x"0" & V_SYNC_WIDTH;
+			when SYNC_BACK   => v_cnt <= V_SYNC_BACK;
+			when ACTIVE_LINE => v_cnt <= V_ACTIVE_LINES;
+			when others      => v_cnt <= x"000";
+			end case;
+		elsif v_cnt /= x"000" and (h_state = ACTIVE_LINE and h_cnt = x"000") then
+			v_cnt <= v_cnt - "1";
+		end if;
+
+		if one_screen = '1' and v_cnt = x"000" then
+			v_state_i <= v_state_i + "01";
+		end if;
+	end if;
+	end process;
+end sig_read;
diff --git a/fpga/src/sig/sig_read_tb.vhd b/fpga/src/sig/sig_read_tb.vhd
new file mode 100644
index 0000000..ccba289
--- /dev/null
+++ b/fpga/src/sig/sig_read_tb.vhd
@@ -0,0 +1,263 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.dvi_package.all;
+
+ENTITY sig_read_tb IS
+END sig_read_tb;
+
+ARCHITECTURE rtl OF sig_read_tb IS
+	constant CLK_PERIOD : time := 10 ns;
+	constant CLK_PERIOD2: time := 5 ns;
+	signal clk          : std_logic;
+	signal ddr2_clk     : std_logic;
+	signal rst          : std_logic;
+	signal rst_n        : std_logic;
+
+	signal en_stb_i     : std_logic;
+	signal hsync_o      : std_logic;
+	signal vsync_o      : std_logic;
+	signal color_en_o   : std_logic;
+	signal color_o      : color_t(COLOR_CNT-1 downto 0);
+	signal ddr2_rd_cmd_en_o         : std_logic;
+	signal ddr2_rd_cmd_instr_o      : std_logic_vector( 2 downto 0);
+	signal ddr2_rd_cmd_bl_o         : std_logic_vector( 5 downto 0);
+	signal ddr2_rd_cmd_byte_addr_o  : std_logic_vector(29 downto 0);
+	signal ddr2_rd_cmd_empty_i      : std_logic;
+	signal ddr2_rd_cmd_full_i       : std_logic;
+	signal ddr2_rd_en_o          : std_logic;
+	signal ddr2_rd_data_i        : std_logic_vector(31 downto 0);
+	signal ddr2_rd_full_i        : std_logic;
+	signal ddr2_rd_empty_i       : std_logic;
+	signal ddr2_rd_count_i       : std_logic_vector( 6 downto 0);
+	signal ddr2_rd_overflow_i    : std_logic;
+	signal ddr2_rd_error_i       : std_logic;
+	signal ddr2_wr_cmd_en_o         : std_logic;
+	signal ddr2_wr_cmd_instr_o      : std_logic_vector( 2 downto 0);
+	signal ddr2_wr_cmd_bl_o         : std_logic_vector( 5 downto 0);
+	signal ddr2_wr_cmd_byte_addr_o  : std_logic_vector(29 downto 0);
+	signal ddr2_wr_cmd_empty_i      : std_logic;
+	signal ddr2_wr_cmd_full_i       : std_logic;
+	signal ddr2_wr_en_o          : std_logic;
+	signal ddr2_wr_mask_o        : std_logic_vector( 3 downto 0);
+	signal ddr2_wr_data_o        : std_logic_vector(31 downto 0);
+	signal ddr2_wr_full_i        : std_logic;
+	signal ddr2_wr_empty_i       : std_logic;
+	signal ddr2_wr_count_i       : std_logic_vector( 6 downto 0);
+	signal ddr2_wr_underrun_i    : std_logic;
+	signal ddr2_wr_error_i       : std_logic;
+	signal wr_cnt                : unsigned( 7 downto 0);
+	signal wr_lat                : unsigned( 7 downto 0);
+
+	signal en_stb_iq    : std_logic;
+	signal hsync_oq     : std_logic;
+	signal vsync_oq     : std_logic;
+	signal color_en_oq  : std_logic;
+	signal color_oq     : color_t(COLOR_CNT-1 downto 0);
+
+	signal req_cnt      : unsigned(15 downto 0);
+	signal req_save_cnt : unsigned(15 downto 0);
+	signal lat_cnt      : unsigned(15 downto 0);
+	signal latency_done : std_logic;
+	signal latency      : std_logic;
+BEGIN
+	rst   <= transport '1', '0' after ( 4 * CLK_PERIOD);
+	rst_n <= not rst;
+
+	clock: process
+	begin
+		clk <= '1', '0' after CLK_PERIOD/2;
+		wait for CLK_PERIOD;
+	end process;
+	ddr_clk: process
+	begin
+		ddr2_clk <= '1', '0' after CLK_PERIOD2/2;
+		wait for CLK_PERIOD2;
+	end process;
+
+	reg: process begin
+	wait until rising_edge(clk);
+		en_stb_iq   <= en_stb_i;
+		hsync_o     <= hsync_oq;
+		vsync_o     <= vsync_oq;
+		color_o     <= color_oq;
+		color_en_o  <= color_en_oq;
+	end process;
+
+	dut_writ: entity work.sig_write
+	port map (
+		clk                   => clk,
+		rst_n                 => rst_n,
+		ctrl_disable_wr       => '0',
+
+		ddr2_clk              => ddr2_clk,
+		ddr2_cmd_en_o         => ddr2_wr_cmd_en_o,
+		ddr2_cmd_instr_o      => ddr2_wr_cmd_instr_o,
+		ddr2_cmd_bl_o         => ddr2_wr_cmd_bl_o,
+		ddr2_cmd_byte_addr_o  => ddr2_wr_cmd_byte_addr_o,
+		ddr2_cmd_empty_i      => ddr2_wr_cmd_empty_i,
+		ddr2_cmd_full_i       => ddr2_wr_cmd_full_i,
+		ddr2_wr_en_o          => ddr2_wr_en_o,
+		ddr2_wr_mask_o        => ddr2_wr_mask_o,
+		ddr2_wr_data_o        => ddr2_wr_data_o,
+		ddr2_wr_full_i        => ddr2_wr_full_i,
+		ddr2_wr_empty_i       => ddr2_wr_empty_i,
+		ddr2_wr_count_i       => ddr2_wr_count_i,
+		ddr2_wr_underrun_i    => ddr2_wr_underrun_i,
+		ddr2_wr_error_i       => ddr2_wr_error_i,
+
+		hsync_i    => hsync_o,
+		vsync_i    => vsync_o,
+		color_en_i => color_en_o,
+		color_i    => color_o
+	);
+
+	mem_wr: process begin
+		ddr2_wr_cmd_empty_i   <= '1';
+		ddr2_wr_underrun_i    <= '0';
+		ddr2_wr_error_i       <= '0';
+		wait;
+	end process;
+
+	ddr2_wr_empty_i <= '1' when wr_cnt = 0 else '0';
+	ddr2_wr_full_i  <= wr_cnt(7);
+	ddr2_wr_count_i <= std_logic_vector(wr_cnt(6 downto 0));
+	ddr2_wr_cmd_full_i <= '1' when wr_lat /= x"00" else '0';
+	mem_wr_l: process (ddr2_clk, rst_n)
+	begin
+	if rst_n = '0' then
+		wr_cnt      <= (others => '0');
+		wr_lat      <= (others => '0');
+	elsif rising_edge(ddr2_clk) then
+		if wr_lat <= x"10" and wr_lat > x"00" and ddr2_wr_en_o = '1' then
+			wr_cnt <= wr_cnt - x"03";
+		elsif wr_lat <= x"10" and wr_lat > x"00" then
+			wr_cnt <= wr_cnt - x"04";
+		elsif ddr2_wr_en_o = '1' then
+			wr_cnt <= wr_cnt + "1";
+		end if;
+
+		if ddr2_wr_cmd_en_o = '1' then
+			wr_lat <= x"11";
+		end if;
+
+		if wr_lat /= x"00" then
+			wr_lat <= wr_lat - "1";
+		end if;
+	end if;
+	end process;
+
+	dut_read: entity work.sig_read
+	generic map (
+		H_ACTIVE_PIXEL => x"500",
+		H_BLANKING     => x"198",
+		H_SYNC_WIDTH   => x"070",
+		H_SYNC_OFFSET  => x"030",
+		V_ACTIVE_LINES => x"400",
+		V_BLANKING     => x"02a",
+		V_SYNC_WIDTH   => x"01",
+		V_SYNC_OFFSET  => x"03"
+	)
+	port map (
+		clk        => clk,
+		rst_n      => rst_n,
+
+		ddr2_clk              => ddr2_clk,
+		ddr2_cmd_en_o         => ddr2_rd_cmd_en_o,
+		ddr2_cmd_instr_o      => ddr2_rd_cmd_instr_o,
+		ddr2_cmd_bl_o         => ddr2_rd_cmd_bl_o,
+		ddr2_cmd_byte_addr_o  => ddr2_rd_cmd_byte_addr_o,
+		ddr2_cmd_empty_i      => ddr2_rd_cmd_empty_i,
+		ddr2_cmd_full_i       => ddr2_rd_cmd_full_i,
+		ddr2_rd_en_o          => ddr2_rd_en_o,
+		ddr2_rd_data_i        => ddr2_rd_data_i,
+		ddr2_rd_full_i        => ddr2_rd_full_i,
+		ddr2_rd_empty_i       => ddr2_rd_empty_i,
+		ddr2_rd_count_i       => ddr2_rd_count_i,
+		ddr2_rd_overflow_i    => ddr2_rd_overflow_i,
+		ddr2_rd_error_i       => ddr2_rd_error_i,
+
+		en_stb_i   => en_stb_iq,
+		hsync_o    => hsync_oq,
+		vsync_o    => vsync_oq,
+		color_en_o => color_en_oq,
+		color_o    => color_oq
+	);
+
+	beh: process begin
+		en_stb_i <= '0';
+		wait for 20*CLK_PERIOD;
+		en_stb_i <= '1';
+		--wait for CLK_PERIOD;
+		--en_stb_i <= '0';
+		wait;
+	end process;
+
+	mem_rd: process begin
+		ddr2_rd_cmd_empty_i   <= '1';
+		ddr2_rd_data_i        <= (others => '0');
+		ddr2_rd_overflow_i    <= '0';
+		ddr2_rd_error_i       <= '0';
+		wait;
+	end process;
+	ddr2_rd_count_i    <= std_logic_vector(req_cnt(6 downto 0));
+	ddr2_rd_empty_i    <= '0' when      req_cnt /= x"0000" else '1';
+	ddr2_rd_cmd_full_i <= '1' when req_save_cnt /= x"0000" else '0';
+	ddr2_rd_full_i     <= '1' when      req_cnt  = x"0040" else '0';
+
+	latency_done <= '1' when lat_cnt = x"0001" else '0';
+	mem_rd_l: process (ddr2_clk, rst_n)
+	begin
+	if rst_n = '0' then
+		req_cnt      <= (others => '0');
+		req_save_cnt <= (others => '0');
+		lat_cnt      <= (others => '0');
+		latency      <= '1';
+	elsif rising_edge(ddr2_clk) then
+		if ddr2_rd_cmd_en_o = '1' then
+			req_save_cnt <= x"00" & "00" & unsigned(ddr2_rd_cmd_bl_o) + "1";
+			lat_cnt      <= x"0020";
+		elsif latency_done = '1' then
+			req_save_cnt <= (others => '0');
+		end if;
+
+		if lat_cnt /= x"0000" then
+			lat_cnt <= lat_cnt - "1";
+		end if;
+
+		if latency_done = '1' and ddr2_rd_en_o = '1' then
+			req_cnt <= req_cnt + req_save_cnt - "1";
+		elsif latency_done = '1' then
+			req_cnt <= req_cnt + req_save_cnt;
+		elsif ddr2_rd_en_o = '1' and req_cnt /= x"0000" then
+			req_cnt <= req_cnt - "1";
+		end if;
+	end if;
+	end process;
+end rtl;
+
+configuration sig_read_tb_rtl_cfg of sig_read_tb is
+  for rtl
+  end for;
+end sig_read_tb_rtl_cfg;
diff --git a/fpga/src/sig/sig_tb.vhd b/fpga/src/sig/sig_tb.vhd
new file mode 100644
index 0000000..631b34a
--- /dev/null
+++ b/fpga/src/sig/sig_tb.vhd
@@ -0,0 +1,112 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.dvi_package.all;
+
+ENTITY sig_tb IS
+END sig_tb;
+
+ARCHITECTURE rtl OF sig_tb IS
+	constant CLK_PERIOD : time := 20 ns;
+	signal clk          : std_logic;
+	signal rst          : std_logic;
+	signal rst_n        : std_logic;
+                            
+	signal en_stb_i     : std_logic;
+	signal hsync_o      : std_logic;
+	signal vsync_o      : std_logic;
+	signal color_en_o   : std_logic;
+	signal color_o      : color_t(COLOR_CNT-1 downto 0);
+
+	signal en_stb_iq    : std_logic;
+	signal hsync_oq     : std_logic;
+	signal vsync_oq     : std_logic;
+	signal color_en_oq  : std_logic;
+	signal color_oq     : color_t(COLOR_CNT-1 downto 0);
+BEGIN
+	rst   <= transport '1', '0' after ( 4 * CLK_PERIOD);
+	rst_n <= not rst;
+
+	clock: process
+	begin
+		clk <= '1', '0' after CLK_PERIOD/2;
+		wait for CLK_PERIOD;
+	end process;
+
+	reg: process begin
+	wait until rising_edge(clk);
+		en_stb_iq   <= en_stb_i;
+		hsync_o     <= hsync_oq;
+		vsync_o     <= vsync_oq;
+		color_o     <= color_oq;
+		color_en_o  <= color_en_oq;
+	end process;
+
+	dut: entity work.sig
+	generic map (
+		H_ACTIVE_PIXEL => x"500",
+		H_BLANKING     => x"198",
+		H_SYNC_WIDTH   => x"070",
+		H_SYNC_OFFSET  => x"030",
+		V_ACTIVE_LINES => x"400",
+		V_BLANKING     => x"02a",
+		V_SYNC_WIDTH   => x"01",
+		V_SYNC_OFFSET  => x"03"
+	)
+	port map (  
+		clk        => clk,
+		rst_n      => rst_n,
+                           
+		en_stb_i   => en_stb_iq,
+		hsync_o    => hsync_oq,
+		vsync_o    => vsync_oq,
+		color_en_o => color_en_oq,
+		color_o    => color_oq
+	);
+
+	dut2: entity work.vga
+	port map (
+		pixelClock => clk,
+		Red        => open,
+		Green      => open,
+		Blue       => open,
+		hSync      => open,
+		vSync      => open,
+		blank      => open
+	);
+
+	beh: process begin
+		en_stb_i <= '0';
+		wait for 20*CLK_PERIOD;
+		en_stb_i <= '1';
+		--wait for CLK_PERIOD;
+		--en_stb_i <= '0';
+		wait;
+	end process;
+end rtl;
+
+configuration sig_tb_rtl_cfg of sig_tb is
+  for rtl
+  end for;
+end sig_tb_rtl_cfg;
diff --git a/fpga/src/sig/sig_write.vhd b/fpga/src/sig/sig_write.vhd
new file mode 100644
index 0000000..0966e53
--- /dev/null
+++ b/fpga/src/sig/sig_write.vhd
@@ -0,0 +1,171 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.dvi_package.all;
+
+entity sig_write is
+	generic (
+		MEM_START_ADR  : unsigned(29 downto 0) := "00" & x"0000000"
+	);
+	port (
+		clk                   : in  std_logic;
+		rst_n                 : in  std_logic;
+		ctrl_disable_wr       : in  std_logic;
+
+		-- memory interface
+		ddr2_clk              : in  std_logic;
+		ddr2_cmd_en_o         : out std_logic;
+		ddr2_cmd_instr_o      : out std_logic_vector( 2 downto 0);
+		ddr2_cmd_bl_o         : out std_logic_vector( 5 downto 0);
+		ddr2_cmd_byte_addr_o  : out std_logic_vector(29 downto 0);
+		ddr2_cmd_empty_i      : in  std_logic;
+		ddr2_cmd_full_i       : in  std_logic;
+
+		ddr2_wr_en_o          : out std_logic;
+		ddr2_wr_mask_o        : out std_logic_vector( 3 downto 0);
+		ddr2_wr_data_o        : out std_logic_vector(31 downto 0);
+		ddr2_wr_full_i        : in  std_logic;
+		ddr2_wr_empty_i       : in  std_logic;
+		ddr2_wr_count_i       : in  std_logic_vector( 6 downto 0);
+		ddr2_wr_underrun_i    : in  std_logic;
+		ddr2_wr_error_i       : in  std_logic;
+
+		-- display output
+		hsync_i               : in  std_logic;
+		vsync_i               : in  std_logic;
+		color_en_i            : in  std_logic;
+		color_i               : in  color_t(COLOR_CNT-1 downto 0)
+	);
+end sig_write;
+
+architecture sig_write of sig_write is
+	signal color_en_l       : std_logic;
+	signal color_en_iq      : std_logic;
+	signal rst              : std_logic;
+	signal px_fifo_wr       : std_logic;
+	signal px_fifo_full     : std_logic;
+	signal px_fifo_empty    : std_logic;
+	signal px_fifo_cnt      : std_logic_vector(10 downto 0);
+	signal px_fifo_din      : std_logic_vector(31 downto 0);
+	signal enabled          : std_logic;
+	signal vsync            : std_logic;
+	signal vsync_m          : std_logic;
+	signal vsync_v          : std_logic;
+	signal vsync_vq         : std_logic;
+	signal vsync_sh         : std_logic_vector( 3 downto 0);
+
+	-- memory
+	signal mem_address      : unsigned(27 downto 0);
+	signal mem_cmd_en       : std_logic;
+	signal mem_wr_en        : std_logic;
+	signal mem_wr_data      : std_logic_vector(31 downto 0);
+	signal px_cnt           : unsigned( 7 downto 0);
+begin
+	rst <= not rst_n;
+
+	-- -------------------------------------------------------------------------------
+	-- MEMORY
+	-- -------------------------------------------------------------------------------
+	ddr2_cmd_byte_addr_o <= std_logic_vector(mem_address(27 downto 0) & "00");
+	ddr2_cmd_bl_o        <= "111111";
+	ddr2_cmd_instr_o     <= "000";
+	ddr2_cmd_en_o        <= mem_cmd_en;
+	ddr2_wr_data_o       <= mem_wr_data;
+	ddr2_wr_en_o         <= mem_wr_en;
+	ddr2_wr_mask_o       <= (others => '0');
+
+	process (clk, rst_n)
+	begin
+	if rst_n = '0' then
+		enabled <= '0';
+		vsync <= '0';
+	elsif rising_edge(clk) then
+		-- eliminate glitches
+		vsync_sh <= vsync_sh(2 downto 0) & vsync_i;
+		if vsync_sh = "1111" then
+			vsync <= '1';
+		elsif vsync_sh = "0000" then
+			vsync <= '0';
+		end if;
+
+		-- freeze frame switch
+		if vsync = '1' then
+			if ctrl_disable_wr = '1' then
+				enabled <= '0';
+			else
+				enabled <= '1';
+			end if;
+		end if;
+	end if;
+	end process;
+
+	px_fifo_wr  <= color_en_i and enabled;
+	px_fifo_din <= (31 downto 24 => '0') & color_i(RED) & color_i(GREEN) & color_i(BLUE);
+	px_fifo_0: entity work.px_fifo
+	port map (
+		wr_clk        => clk,
+		rd_clk        => ddr2_clk,
+		rst           => rst,
+		din           => px_fifo_din,
+		wr_en         => px_fifo_wr,
+		rd_en         => mem_wr_en,
+		dout          => mem_wr_data,
+		full          => px_fifo_full,
+		empty         => px_fifo_empty,
+		rd_data_count => px_fifo_cnt
+	);
+
+	mem_wr_en  <= '1' when px_fifo_empty = '0' and ddr2_wr_full_i = '0' else '0';
+	mem_cmd_en <= '1' when px_cnt = x"40" else '0';
+	process (ddr2_clk, rst_n)
+	begin
+	if rst_n = '0' then
+		px_cnt        <= (others => '0');
+		mem_address   <= (others => '0');
+		vsync_m       <= '0';
+		vsync_v       <= '0';
+		vsync_vq      <= '0';
+	elsif rising_edge(ddr2_clk) then
+		-- signal synchronizer
+		vsync_m  <= vsync;
+		vsync_v  <= vsync_m;
+		vsync_vq <= vsync_v;
+
+		if mem_cmd_en = '1' and mem_wr_en = '1' then
+			px_cnt <= x"01";
+		elsif mem_cmd_en = '1' then
+			px_cnt <= (others => '0');
+		elsif mem_wr_en = '1' then
+			px_cnt <= px_cnt + "1";
+		end if;
+
+		if vsync_vq = '1' and vsync_v = '0' then
+			mem_address <= MEM_START_ADR(29 downto 2);
+		elsif mem_cmd_en = '1' then
+			mem_address <= mem_address + x"040";
+		end if;
+	end if;
+	end process;
+
+end sig_write;
diff --git a/fpga/src/snippets b/fpga/src/snippets
new file mode 160000
index 0000000..8893270
--- /dev/null
+++ b/fpga/src/snippets
@@ -0,0 +1 @@
+Subproject commit 8893270fc31fcf66f3da8d233ec515120bb14f71
diff --git a/fpga/src/top/atlys.ucf b/fpga/src/top/atlys.ucf
new file mode 100644
index 0000000..2ac82fa
--- /dev/null
+++ b/fpga/src/top/atlys.ucf
@@ -0,0 +1,93 @@
+#FPGA_PART=xc6slx45-3-csg324
+CONFIG VCCAUX = 3.3;
+
+##############################################################################
+# SYSCLK Input
+##############################################################################
+NET "clk100" LOC = "L15" | IOSTANDARD = LVCMOS33 | TNM_NET = clk100;
+TIMESPEC TS_clk100 = PERIOD "clk100" 100 MHz HIGH 50%;
+
+# Constraint for RX0
+NET "dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
+TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;
+
+##############################################################################
+# Mechanical Switches (SW)
+##############################################################################
+#NET "switch<0>"         LOC = "A10" |IOSTANDARD = LVCMOS33 ;
+#NET "switch<1>"         LOC = "D14" |IOSTANDARD = LVCMOS33 ;
+#NET "switch<2>"         LOC = "C14" | IOSTANDARD = LVCMOS33 ;
+#NET "switch<3>"         LOC = "P15" | IOSTANDARD = LVCMOS33 ;
+
+#############################################
+## TMDS pairs for Atlys top OUT: J2 - Bank 0
+#############################################
+NET "tx0_tmds(3)"   LOC = "B6" |IOSTANDARD = TMDS_33 ; # Clock
+NET "tx0_tmds_n(3)" LOC = "A6" |IOSTANDARD = TMDS_33 ;
+NET "tx0_tmds(2)"   LOC = "B8" |IOSTANDARD = TMDS_33 ; # Red
+NET "tx0_tmds_n(2)" LOC = "A8" |IOSTANDARD = TMDS_33 ;
+NET "tx0_tmds(1)"   LOC = "C7" |IOSTANDARD = TMDS_33 ; # Green
+NET "tx0_tmds_n(1)" LOC = "A7" |IOSTANDARD = TMDS_33 ;
+NET "tx0_tmds(0)"   LOC = "D8" |IOSTANDARD = TMDS_33 ; # Blue
+NET "tx0_tmds_n(0)" LOC = "C8" |IOSTANDARD = TMDS_33 ;
+#
+###############################################
+## TMDS pairs for Atlys top OUT: JA - Bank 2
+## Use TML_33 to add output series termination
+###############################################
+#NET "tx1_tmds(3)"   LOC = "T9" |IOSTANDARD = TML_33; #TMDS_33 ; ## Clock
+#NET "tx1_tmds_n(3)" LOC = "V9" |IOSTANDARD = TML_33; #TMDS_33 ; #
+#NET "tx1_tmds(2)"   LOC = "N5" |IOSTANDARD = TML_33; #TMDS_33 ; ## Red
+#NET "tx1_tmds_n(2)" LOC = "P6" |IOSTANDARD = TML_33; #TMDS_33 ; #
+#NET "tx1_tmds(1)"   LOC = "T4" |IOSTANDARD = TML_33; #TMDS_33 ; ## Green
+#NET "tx1_tmds_n(1)" LOC = "V4" |IOSTANDARD = TML_33; #TMDS_33 ; #
+#NET "tx1_tmds(0)"   LOC = "R3" |IOSTANDARD = TML_33; #TMDS_33 ; ## Blue
+#NET "tx1_tmds_n(0)" LOC = "T3" |IOSTANDARD = TML_33; #TMDS_33 ; #
+#
+###################################################
+## TMDS pairs for Atlys IN (FPGA Bank 1): J3
+###################################################
+#NET "rx1_tmds(3)"   LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
+#NET "rx1_tmds_n(3)" LOC = "H18" |IOSTANDARD = TMDS_33 ;
+#NET "rx1_tmds(2)"   LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
+#NET "rx1_tmds_n(2)" LOC = "J18" |IOSTANDARD = TMDS_33 ;
+#NET "rx1_tmds(1)"   LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green
+#NET "rx1_tmds_n(1)" LOC = "L18" |IOSTANDARD = TMDS_33 ;
+#NET "rx1_tmds(0)"   LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue
+#NET "rx1_tmds_n(0)" LOC = "K18" |IOSTANDARD = TMDS_33 ;
+#
+###############################################
+## TMDS pairs for Atlys IN (FPGA Bank 0): J1
+###############################################
+NET "rx0_tmds(3)"   LOC = "D11" |IOSTANDARD = TMDS_33 ; # CLK
+NET "rx0_tmds_n(3)" LOC = "C11" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(2)"   LOC = "B12" |IOSTANDARD = TMDS_33 ; # Red
+NET "rx0_tmds_n(2)" LOC = "A12" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(1)"   LOC = "B11" |IOSTANDARD = TMDS_33 ; # Green
+NET "rx0_tmds_n(1)" LOC = "A11" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(0)"   LOC = "G9"  |IOSTANDARD = TMDS_33 ; # Blue
+NET "rx0_tmds_n(0)" LOC = "F9"  |IOSTANDARD = TMDS_33 ;
+NET "rx0_scl"       LOC = "C13" |IOSTANDARD = LVCMOS33 ;
+NET "rx0_sda"       LOC = "A13" |IOSTANDARD = LVCMOS33 ;
+
+
+########################################
+# Reset button and LEDs and Mechanical Switches (SW)
+########################################
+NET "rstbtn_n" LOC = "T15" |IOSTANDARD = LVCMOS33;
+NET "led<0>"   LOC = "U18" |IOSTANDARD = LVCMOS33;
+NET "led<1>"   LOC = "M14" |IOSTANDARD = LVCMOS33;
+NET "led<2>"   LOC = "N14" |IOSTANDARD = LVCMOS33;
+NET "led<3>"   LOC = "L14" |IOSTANDARD = LVCMOS33;
+NET "led<4>"   LOC = "M13" |IOSTANDARD = LVCMOS33;
+NET "led<5>"   LOC = "D4"  |IOSTANDARD = LVCMOS33;
+NET "led<6>"   LOC = "P16" |IOSTANDARD = LVCMOS33;
+NET "led<7>"   LOC = "N12" |IOSTANDARD = LVCMOS33;
+
+# Multi-cycle paths for TX0 / encoder_0
+#TIMEGRP "bramgrp_0" = RAMS(dvi_encoder_0/pixel2x/data_i<*>);
+#TIMEGRP "fddbgrp_0" = FFS(dvi_encoder_0/pixel2x/db<*>);
+#TIMEGRP "bramra_0"  = FFS(dvi_encoder_0/pixel2x/ra<*>);
+#
+#TIMESPEC "TS_ramdo_0" = FROM "bramgrp_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
+#TIMESPEC "TS_ramra_0" = FROM "bramra_0"  TO "fddbgrp_0" TS_DVI_CLOCK0;
diff --git a/fpga/src/top/atlys.vhd b/fpga/src/top/atlys.vhd
new file mode 100644
index 0000000..b31b7d5
--- /dev/null
+++ b/fpga/src/top/atlys.vhd
@@ -0,0 +1,275 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.dvi_package.all;
+
+library work;
+use work.all;
+
+library UNISIM;
+use UNISIM.Vcomponents.all;
+
+entity atlys is
+	generic ( MODE : string := "encode");
+	--generic ( MODE : string := "direct");
+	port (
+	rstbtn_n                   : in    std_logic; -- The pink reset button
+	clk100                     : in    std_logic; -- 100 MHz osicallator
+
+	tx0_tmds                   : out   std_logic_vector(3 downto 0);
+	tx0_tmds_n                 : out   std_logic_vector(3 downto 0);
+	rx0_tmds                   : in    std_logic_vector(3 downto 0);
+	rx0_tmds_n                 : in    std_logic_vector(3 downto 0);
+	rx0_sda                    : inout std_logic;
+	rx0_scl                    : in    std_logic;
+
+	tx1_tmds                   : out   std_logic_vector(3 downto 0);
+	tx1_tmds_n                 : out   std_logic_vector(3 downto 0);
+	rx1_tmds                   : in    std_logic_vector(3 downto 0);
+	rx1_tmds_n                 : in    std_logic_vector(3 downto 0);
+
+	switch                     : in    std_logic_vector(1 downto 0);
+	led                        : out   std_logic_vector(7 downto 0)
+	);
+end atlys;
+
+architecture top of atlys is
+	signal rstbtn            : std_logic;
+	signal rst_n             : std_logic;
+	signal rst               : std_logic;
+	signal pclk              : std_logic;
+	signal pclkx2            : std_logic;
+	signal pclkx10           : std_logic;
+	signal pllclk1           : std_logic;
+	signal pllclk1bg         : std_logic;
+	signal pll_lckd          : std_logic;
+	signal serdesstrobe      : std_logic;
+	signal tmdsclk           : std_logic;
+	signal hsync             : std_logic;
+	signal vsync             : std_logic;
+	signal dat_en            : std_logic;
+	signal valid             : std_logic_vector(COLOR_CNT-1 downto 0);
+	signal ready             : std_logic_vector(COLOR_CNT-1 downto 0);
+	signal psalgnerr         : std_logic;
+	signal color             : color_t(COLOR_CNT-1 downto 0);
+	signal sdout             : sdat_t(COLOR_CNT-1 downto 0);
+	signal rx0_sda_i         : std_logic;
+	signal rx0_sda_o         : std_logic;
+	signal rx0_tmds_s        : std_logic_vector(3 downto 0);
+
+	signal toggle            : std_logic;
+	signal tmdsclkint        : std_logic_vector(4 downto 0);
+	type tmds_data_t is array(natural range <>) of std_logic_vector(4 downto 0);
+	signal tmds_data         : tmds_data_t(COLOR_CNT-1 downto 0);
+	signal tmdsint           : std_logic_vector(2 downto 0);
+	signal tmds_clk          : std_logic;
+	signal sdata             : std_logic_vector(29 downto 0);
+
+	signal tx0_pclkx2        : std_logic;
+	signal tx0_pclkx10       : std_logic;
+	signal tx0_reset_n       : std_logic;
+	signal tx0_serdesstrobe  : std_logic;
+	signal tx0_clkfbout      : std_logic;
+	signal tx0_clkfbin       : std_logic;
+	signal tx0_plllckd       : std_logic;
+	signal tx0_pllclk0       : std_logic;
+	signal tx0_pllclk2       : std_logic;
+	signal tx0_bufpll_lock   : std_logic;
+begin
+	rstbtn <= not rstbtn_n;
+	rst    <= not rst_n;
+	led    <= ready(RED) & ready(GREEN) & ready(BLUE) & valid(RED) & valid(GREEN) & valid(BLUE)  & dat_en & rst_n;
+
+	dvi_decoder_0: entity work.dvi_decoder
+	port map (
+		ext_rst        => rstbtn,
+
+		tmdsclk_p      => rx0_tmds(3),
+		tmdsclk_n      => rx0_tmds_n(3),
+		din_p          => rx0_tmds(2 downto 0),
+		din_n          => rx0_tmds_n(2 downto 0),
+
+		reset_n        => rst_n,        -- rx reset
+		pclk_o         => pclk,         -- regenerated pixel clock
+		pclkx2_o       => pclkx2,       -- double rate pixel clock
+		pclkx10_o      => pclkx10,      -- 10x pixel as IOCLK
+
+		pll_lckd_o     => pll_lckd,     -- send pll_lckd out so it can be fed into a different BUFPLL
+		serdesstrobe_o => serdesstrobe, -- BUFPLL serdesstrobe output
+		tmdsclk_o      => tmdsclk,      -- TMDS cable clock
+
+		hsync_o        => hsync,        -- hsync data
+		vsync_o        => vsync,        -- vsync data
+		dat_en_o       => dat_en,       -- data enable
+		valid_o        => valid,
+		ready_o        => ready,
+		psalgnerr_o    => psalgnerr,
+		sdout_o        => sdout,
+		color_o        => color
+	);
+
+direct: if MODE = "direct" generate
+	-- ----------------------------------------------------------
+	-- Forward TMDS Clock Using OSERDES2 block
+	-- ----------------------------------------------------------
+	process (pclkx2, rst_n)
+	begin
+	if rst_n = '0' then
+		toggle     <= '0';
+		tmdsclkint <= (others => '0');
+	elsif rising_edge(pclkx2) then
+		toggle <= not toggle;
+		if toggle = '1' then
+			tmdsclkint <= (others => '1');
+		else
+			tmdsclkint <= (others => '0');
+		end if;
+	end if;
+	end process;
+
+	clkout: entity work.serdes_n_to_1
+	generic map (SF => 5)
+	port map (
+		ioclk          => pclkx10,
+		gclk           => pclkx2,
+		rst            => rst,
+		serdesstrobe_i => serdesstrobe,
+		data_i         => tmdsclkint,
+		data_o         => tmds_clk
+	);
+
+  	TMDS3: OBUFDS port map (I => tmds_clk, O => tx0_tmds(3), OB => tx0_tmds_n(3)); -- clock
+
+	d: for I in 0 to COLOR_CNT-1 generate
+		outI: entity work.serdes_n_to_1
+		generic map (SF => 5)
+		port map (
+			ioclk          => pclkx10,
+			gclk           => pclkx2,
+			rst            => rst,
+			serdesstrobe_i => serdesstrobe,
+			data_i         => tmds_data(I),
+			data_o         => tmdsint(I)
+		);
+		tx_tmdsI: OBUFDS port map (i => tmdsint(I), o => tx0_tmds(I), ob => tx0_tmds_n(I));
+	end generate;
+
+	sdata <= sdout(RED)(9 downto 5) & sdout(GREEN)(9 downto 5) & sdout(BLUE)(9 downto 5)
+	       & sdout(RED)(4 downto 0) & sdout(GREEN)(4 downto 0) & sdout(BLUE)(4 downto 0);
+	pixel2x: entity work.convert_30to15_fifo
+	port map (
+		rst     => rst,
+		clk     => pclk,
+		clkx2   => pclkx2,
+		data_i  => sdata,
+		data_o( 4 downto  0) => tmds_data(0),
+		data_o( 9 downto  5) => tmds_data(1),
+		data_o(14 downto 10) => tmds_data(2)
+	);
+end generate;
+
+decode: if MODE = "encode" generate
+	-- ----------------------------------------------------------------------------
+	-- Instantiate a dedicate PLL for output port
+	-- ----------------------------------------------------------------------------
+	pll_oserdes_0: PLL_BASE
+	generic map (
+		CLKIN_PERIOD   => 10.0,
+		CLKFBOUT_MULT  => 10, --set VCO to 10x of CLKIN
+		CLKOUT0_DIVIDE => 1,
+		CLKOUT1_DIVIDE => 10,
+		CLKOUT2_DIVIDE => 5,
+		COMPENSATION   => "SOURCE_SYNCHRONOUS"
+	)
+	port map (
+		CLKFBOUT  => tx0_clkfbout,
+		CLKOUT0   => tx0_pllclk0,
+		CLKOUT1   => open,
+		CLKOUT2   => tx0_pllclk2,
+		CLKOUT3   => open,
+		CLKOUT4   => open,
+		CLKOUT5   => open,
+		LOCKED    => tx0_plllckd,
+		CLKFBIN   => tx0_clkfbin,
+		CLKIN     => pclk, -- pllclk1bg,
+		RST       => rst
+	);
+
+	-- ----------------------------------------------------------------------------
+	-- This BUFG is needed in order to deskew between PLL clkin and clkout
+	-- So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input
+	-- ----------------------------------------------------------------------------
+	tx0_clkfb_buf: BUFG port map(I => tx0_clkfbout, O => tx0_clkfbin);
+
+	-- --------------------------------
+	-- regenerate pclkx2 for TX
+	-- --------------------------------
+	tx0_pclkx2_buf: BUFG port map(I => tx0_pllclk2, O => tx0_pclkx2);
+
+	-- --------------------------------
+	-- regenerate pclkx10 for TX
+	-- --------------------------------
+	tx0_ioclk_buf: BUFPLL
+	generic map ( DIVIDE => 5 )
+	port map (
+		PLLIN        => tx0_pllclk0,
+		GCLK         => tx0_pclkx2,
+		LOCKED       => tx0_plllckd,
+		IOCLK        => tx0_pclkx10,
+		SERDESSTROBE => tx0_serdesstrobe,
+		LOCK         => tx0_bufpll_lock
+	);
+	tx0_reset_n <= tx0_bufpll_lock;
+
+	dvi_encoder_0: entity work.dvi_encoder
+	port map (
+		rst_n          => tx0_reset_n,
+		pclk           => pclk,
+		pclkx2         => tx0_pclkx2,
+		pclkx10        => tx0_pclkx10,
+		serdesstrobe_i => tx0_serdesstrobe,
+		color_i        => color,
+		hsync_i        => hsync,
+		vsync_i        => vsync,
+		dat_en_i       => dat_en,
+		tmds_p         => tx0_tmds,
+		tmds_n         => tx0_tmds_n
+	);
+end generate;
+
+	-- ----------------------------------------------------------------------------
+	-- I2C EDID Emulation
+	-- ----------------------------------------------------------------------------
+	rx0_sda_i <= rx0_sda;
+	rx0_sda   <= '0' when rx0_sda_o = '0' else 'Z';
+	i2c_rom_0: entity work.i2c_rom
+	port map (
+		clk    => clk100,
+		rst_n  => rstbtn_n,
+		sda_i  => rx0_sda_i,
+		sda_o  => rx0_sda_o,
+		scl_i  => rx0_scl
+	);
+
+end top;
diff --git a/fpga/src/top/atlys_sig.ucf b/fpga/src/top/atlys_sig.ucf
new file mode 100644
index 0000000..7345344
--- /dev/null
+++ b/fpga/src/top/atlys_sig.ucf
@@ -0,0 +1,196 @@
+#FPGA_PART=xc6slx45-3-csg324
+CONFIG VCCAUX = 3.3;
+
+##############################################################################
+# SYSCLK Input
+##############################################################################
+NET "clk100" LOC = "L15" | IOSTANDARD = LVCMOS33 | TNM_NET = clk100;
+TIMESPEC TS_clk100 = PERIOD "clk100" 100 MHz HIGH 50%;
+
+# Constraint for RX0
+NET "dvi2ddr_0/dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
+TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;
+
+##############################################################################
+# Mechanical Switches (SW)
+##############################################################################
+NET "switch<0>"         LOC = "A10" |IOSTANDARD = LVCMOS33 ;
+#NET "switch<1>"         LOC = "D14" |IOSTANDARD = LVCMOS33 ;
+#NET "switch<2>"         LOC = "C14" | IOSTANDARD = LVCMOS33 ;
+#NET "switch<3>"         LOC = "P15" | IOSTANDARD = LVCMOS33 ;
+
+#############################################
+## TMDS pairs for Atlys top OUT: J2 - Bank 0
+#############################################
+NET "tx0_tmds(3)"   LOC = "B6" | IOSTANDARD = TMDS_33 ; # Clock
+NET "tx0_tmds_n(3)" LOC = "A6" | IOSTANDARD = TMDS_33 ;
+NET "tx0_tmds(2)"   LOC = "B8" | IOSTANDARD = TMDS_33 ; # Red
+NET "tx0_tmds_n(2)" LOC = "A8" | IOSTANDARD = TMDS_33 ;
+NET "tx0_tmds(1)"   LOC = "C7" | IOSTANDARD = TMDS_33 ; # Green
+NET "tx0_tmds_n(1)" LOC = "A7" | IOSTANDARD = TMDS_33 ;
+NET "tx0_tmds(0)"   LOC = "D8" | IOSTANDARD = TMDS_33 ; # Blue
+NET "tx0_tmds_n(0)" LOC = "C8" | IOSTANDARD = TMDS_33 ;
+
+###############################################
+## TMDS pairs for Atlys top OUT: JA - Bank 2
+## Use TML_33 to add output series termination
+###############################################
+#NET "tx1_tmds(3)"   LOC = "T9" |IOSTANDARD = TML_33; #TMDS_33 ; ## Clock
+#NET "tx1_tmds_n(3)" LOC = "V9" |IOSTANDARD = TML_33; #TMDS_33 ; #
+#NET "tx1_tmds(2)"   LOC = "N5" |IOSTANDARD = TML_33; #TMDS_33 ; ## Red
+#NET "tx1_tmds_n(2)" LOC = "P6" |IOSTANDARD = TML_33; #TMDS_33 ; #
+#NET "tx1_tmds(1)"   LOC = "T4" |IOSTANDARD = TML_33; #TMDS_33 ; ## Green
+#NET "tx1_tmds_n(1)" LOC = "V4" |IOSTANDARD = TML_33; #TMDS_33 ; #
+#NET "tx1_tmds(0)"   LOC = "R3" |IOSTANDARD = TML_33; #TMDS_33 ; ## Blue
+#NET "tx1_tmds_n(0)" LOC = "T3" |IOSTANDARD = TML_33; #TMDS_33 ; #
+#
+###################################################
+## TMDS pairs for Atlys IN (FPGA Bank 1): J3
+###################################################
+#NET "rx1_tmds(3)"   LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
+#NET "rx1_tmds_n(3)" LOC = "H18" |IOSTANDARD = TMDS_33 ;
+#NET "rx1_tmds(2)"   LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
+#NET "rx1_tmds_n(2)" LOC = "J18" |IOSTANDARD = TMDS_33 ;
+#NET "rx1_tmds(1)"   LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green
+#NET "rx1_tmds_n(1)" LOC = "L18" |IOSTANDARD = TMDS_33 ;
+#NET "rx1_tmds(0)"   LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue
+#NET "rx1_tmds_n(0)" LOC = "K18" |IOSTANDARD = TMDS_33 ;
+#
+###############################################
+## TMDS pairs for Atlys IN (FPGA Bank 0): J1
+###############################################
+NET "rx0_tmds(3)"   LOC = "D11" |IOSTANDARD = TMDS_33 ; # CLK
+NET "rx0_tmds_n(3)" LOC = "C11" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(2)"   LOC = "B12" |IOSTANDARD = TMDS_33 ; # Red
+NET "rx0_tmds_n(2)" LOC = "A12" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(1)"   LOC = "B11" |IOSTANDARD = TMDS_33 ; # Green
+NET "rx0_tmds_n(1)" LOC = "A11" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(0)"   LOC = "G9"  |IOSTANDARD = TMDS_33 ; # Blue
+NET "rx0_tmds_n(0)" LOC = "F9"  |IOSTANDARD = TMDS_33 ;
+NET "rx0_scl"       LOC = "C13" |IOSTANDARD = LVCMOS33 ;
+NET "rx0_sda"       LOC = "A13" |IOSTANDARD = LVCMOS33 ;
+
+
+########################################
+# Reset button and LEDs and Mechanical Switches (SW)
+########################################
+NET "rstbtn_n" LOC = "T15" | IOSTANDARD = LVCMOS33;
+NET "led<0>"   LOC = "U18" | IOSTANDARD = LVCMOS33;
+NET "led<1>"   LOC = "M14" | IOSTANDARD = LVCMOS33;
+NET "led<2>"   LOC = "N14" | IOSTANDARD = LVCMOS33;
+NET "led<3>"   LOC = "L14" | IOSTANDARD = LVCMOS33;
+NET "led<4>"   LOC = "M13" | IOSTANDARD = LVCMOS33;
+NET "led<5>"   LOC = "D4"  | IOSTANDARD = LVCMOS33;
+NET "led<6>"   LOC = "P16" | IOSTANDARD = LVCMOS33;
+NET "led<7>"   LOC = "N12" | IOSTANDARD = LVCMOS33;
+
+# Multi-cycle paths for TX0 / encoder_0
+TIMEGRP "bramgrp_0" = RAMS(ddr2dvi_0/dvi_encoder_0/pixel2x/data_int<*>);
+TIMEGRP "fddbgrp_0" = FFS(ddr2dvi_0/dvi_encoder_0/pixel2x/db<*>);
+TIMEGRP "bramra_0"  = FFS(ddr2dvi_0/dvi_encoder_0/pixel2x/ra<*>);
+TIMESPEC "TS_ramdo_0" = FROM "bramgrp_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
+TIMESPEC "TS_ramra_0" = FROM "bramra_0"  TO "fddbgrp_0" TS_DVI_CLOCK0;
+
+#######################################################################################
+#### onBoard USB controller
+#######################################################################################
+####NET "UsbMode"     LOC = "A5";  # Bank = 0, Pin name = IO_L6N, Sch name = U1-INT0#
+NET "usb_clk"     LOC = "C10" | IOSTANDARD = LVCMOS33 | TNM_NET = clk48; # Bank = 0, Pin name = IO_L37P_GCLK13, Sch name = U1-IFCLK
+TIMESPEC TS_clk48 = PERIOD "clk48" 48 MHz HIGH 50%;
+NET "usb_flag_a"  LOC = "B9"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L35P_GCLK17, Sch name = U1-FLAGA
+NET "usb_flag_b"  LOC = "A9"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L35N_GCLK16, Sch name = U1-FLAGB
+NET "usb_flag_c"  LOC = "C15" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L64P_SCP5, Sch name = U1-FLAGC
+NET "usb_cs"      LOC = "B2"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L2P, Sch name = U1-SLCS
+NET "usb_oe"      LOC = "A15" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L64N_SCP4, Sch name = U1-SLOE
+NET "usb_rd"      LOC = "F13" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L63P_SCP7, Sch name = U1-SLRD
+NET "usb_wr"      LOC = "E13" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L63N_SCP6, Sch name = U1-SLWR
+NET "usb_pktend"  LOC = "C4"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L1N_VREF, Sch name = U1-PKTEND
+NET "usb_adr<0>"  LOC = "A14" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L62N_VREF, Sch name = U1-FIFOAD0
+NET "usb_adr<1>"  LOC = "B14" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L62P, Sch name = U1-FIFOAD1
+NET "usb_dat<0>"  LOC = "A2"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L2N, Sch name = U1-FD0
+NET "usb_dat<1>"  LOC = "D6"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L3P, Sch name = U1-FD1
+NET "usb_dat<2>"  LOC = "C6"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L3N, Sch name = U1-FD2
+NET "usb_dat<3>"  LOC = "B3"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L4P, Sch name = U1-FD3
+NET "usb_dat<4>"  LOC = "A3"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L4N, Sch name = U1-FD4
+NET "usb_dat<5>"  LOC = "B4"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L5P, Sch name = U1-FD5
+NET "usb_dat<6>"  LOC = "A4"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L5N, Sch name = U1-FD6
+NET "usb_dat<7>"  LOC = "C5"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L6P, Sch name = U1-FD7
+
+#######################################################################################
+#### SIG READ
+#######################################################################################
+# FIXME: for now just TIG between the FIFO clocks
+TIMESPEC "TS_async_0" = FROM "ddr2dvi_0_pclk_buf" TO "ddr2_0_memc3_infrastructure_inst_clk0_bufg_in" TIG;
+TIMESPEC "TS_async_1" = FROM "ddr2_0_memc3_infrastructure_inst_clk0_bufg_in" TO "ddr2dvi_0_pclk_buf" TIG;
+
+#######################################################################################
+#### DDR2
+#######################################################################################
+CONFIG MCB_PERFORMANCE= STANDARD;
+NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+#NET "c?_pll_lock" TIG;
+#INST "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
+
+#Please uncomment the below TIG if used in a design which enables self-refresh mode
+#NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
+
+NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
+NET "ddr2_dq[*]"  IN_TERM = NONE;
+NET "ddr2_dqs"    IN_TERM = NONE;
+NET "ddr2_dqs_n"  IN_TERM = NONE;
+NET "ddr2_udqs"   IN_TERM = NONE;
+NET "ddr2_udqs_n" IN_TERM = NONE;
+NET "ddr2_clk"    LOC = "G3" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L46P_M3CLK, Sch name = DDR-CK_P
+NET "ddr2_clk_n"  LOC = "G1" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L46N_M3CLKN, Sch name = DDR-CK_N
+NET "ddr2_cke"    LOC = "H7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L53P_M3CKE, Sch name = DDR-CKE
+NET "ddr2_ras_n"  LOC = "L5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN, Sch name = DDR-RAS
+NET "ddr2_cas_n"  LOC = "K5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = DDR-CAS
+NET "ddr2_we_n"   LOC = "E3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L50P_M3WE, Sch name = DDR-WE
+NET "ddr2_rzq"	  LOC = "L6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L31P, Sch name = RZQ
+NET "ddr2_zio"	  LOC = "C2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L83P, Sch name = ZIO
+
+NET "ddr2_ba<0>"  LOC = "F2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L48P_M3BA0, Sch name = DDR-BA0
+NET "ddr2_ba<1>"  LOC = "F1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L48N_M3BA1, Sch name = DDR-BA1
+NET "ddr2_ba<2>"  LOC = "E1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L50N_M3BA2, Sch name = DDR-BA2
+
+NET "ddr2_a<0>"   LOC = "J7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L47P_M3A0, Sch name = DDR-A0
+NET "ddr2_a<1>"   LOC = "J6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L47N_M3A1, Sch name = DDR-A1
+NET "ddr2_a<2>"   LOC = "H5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L49N_M3A2, Sch name = DDR-A2
+NET "ddr2_a<3>"   LOC = "L7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L45P_M3A3, Sch name = DDR-A3
+NET "ddr2_a<4>"   LOC = "F3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L51N_M3A4, Sch name = DDR-A4
+NET "ddr2_a<5>"   LOC = "H4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L44P_GCLK21_M3A5, Sch name = DDR-A5
+NET "ddr2_a<6>"   LOC = "H3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L44N_GCLK20_M3A6, Sch name = DDR-A6
+NET "ddr2_a<7>"   LOC = "H6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L49P_M3A7, Sch name = DDR-A7
+NET "ddr2_a<8>"   LOC = "D2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L52P_M3A8, Sch name = DDR-A8
+NET "ddr2_a<9>"   LOC = "D1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L52N_M3A9, Sch name = DDR-A9
+NET "ddr2_a<10>"  LOC = "F4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L51P_M3A10, Sch name = DDR-A10
+NET "ddr2_a<11>"  LOC = "D3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L54N_M3A11, Sch name = DDR-A11
+NET "ddr2_a<12>"  LOC = "G6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L53N_M3A12, Sch name = DDR-A12
+
+NET "ddr2_dq<0>"  LOC = "L2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L37P_M3DQ0, Sch name = DDR-DQ0
+NET "ddr2_dq<1>"  LOC = "L1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L37N_M3DQ1, Sch name = DDR-DQ1
+NET "ddr2_dq<2>"  LOC = "K2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L38P_M3DQ2, Sch name = DDR-DQ2
+NET "ddr2_dq<3>"  LOC = "K1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L38N_M3DQ3, Sch name = DDR-DQ3
+NET "ddr2_dq<4>"  LOC = "H2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4, Sch name = DDR-DQ4
+NET "ddr2_dq<5>"  LOC = "H1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = DDR-DQ5
+NET "ddr2_dq<6>"  LOC = "J3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L40P_M3DQ6, Sch name = DDR-DQ6
+NET "ddr2_dq<7>"  LOC = "J1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L40N_M3DQ7, Sch name = DDR-DQ7
+NET "ddr2_dq<8>"  LOC = "M3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L36P_M3DQ8, Sch name = DDR-DQ8
+NET "ddr2_dq<9>"  LOC = "M1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L36N_M3DQ9, Sch name = DDR-DQ9
+NET "ddr2_dq<10>" LOC = "N2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L35P_M3DQ10, Sch name = DDR-DQ10
+NET "ddr2_dq<11>" LOC = "N1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L35N_M3DQ11, Sch name = DDR-DQ11
+NET "ddr2_dq<12>" LOC = "T2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L33P_M3DQ12, Sch name = DDR-DQ12
+NET "ddr2_dq<13>" LOC = "T1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L33N_M3DQ13, Sch name = DDR-DQ13
+NET "ddr2_dq<14>" LOC = "U2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L32P_M3DQ14, Sch name = DDR-DQ14
+NET "ddr2_dq<15>" LOC = "U1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L32N_M3DQ15, Sch name = DDR-DQ15
+
+NET "ddr2_udqs"   LOC="P2" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L34P_M3UDQS, Sch name = DDR-UDQS_P
+NET "ddr2_udqs_n" LOC="P1" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L34N_M3UDQSN, Sch name = DDR-UDQS_N
+NET "ddr2_dqs"    LOC="L4" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L39P_M3LDQS, Sch name = DDR-LDQS_P
+NET "ddr2_dqs_n"  LOC="L3" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L39N_M3LDQSN, Sch name = DDR-LDQS_N
+NET "ddr2_dm"     LOC="K3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM, Sch name = DDR-LDM
+NET "ddr2_udm"    LOC="K4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM,	Sch name = DDR-UDM
+NET "ddr2_odt"    LOC="K6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L45N_M3ODT, Sch name = DDR-ODT
+
+NET "ddr2_zio"    LOC="C2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L83P, Sch name = DDR-ODT
+# NET "ddr2_rzm"    LOC="L6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L31P, Sch name = DDR-ODT
diff --git a/fpga/src/top/atlys_sig.vhd b/fpga/src/top/atlys_sig.vhd
new file mode 100644
index 0000000..6313731
--- /dev/null
+++ b/fpga/src/top/atlys_sig.vhd
@@ -0,0 +1,466 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.dvi_package.all;
+use work.strm_package.all;
+
+library UNISIM;
+use UNISIM.Vcomponents.all;
+
+entity atlys_sig is
+	port (
+	rstbtn_n                   : in    std_logic; -- The pink reset button
+	clk100                     : in    std_logic; -- 100 MHz osicallator
+
+	-- HDMI
+	tx0_tmds                   : out   std_logic_vector(3 downto 0);
+	tx0_tmds_n                 : out   std_logic_vector(3 downto 0);
+	rx0_tmds                   : in    std_logic_vector(3 downto 0);
+	rx0_tmds_n                 : in    std_logic_vector(3 downto 0);
+	rx0_sda                    : inout std_logic;
+	rx0_scl                    : in    std_logic;
+
+	-- DDR2
+	ddr2_dq                    : inout std_logic_vector(15 downto 0);
+	ddr2_a                     : out   std_logic_vector(12 downto 0);
+	ddr2_ba                    : out   std_logic_vector( 2 downto 0);
+	ddr2_ras_n                 : out   std_logic;
+	ddr2_cas_n                 : out   std_logic;
+	ddr2_we_n                  : out   std_logic;
+	ddr2_odt                   : out   std_logic;
+	ddr2_cke                   : out   std_logic;
+	ddr2_dm                    : out   std_logic;
+	ddr2_udqs                  : inout std_logic;
+	ddr2_udqs_n                : inout std_logic;
+	ddr2_rzq                   : inout std_logic;
+	ddr2_zio                   : inout std_logic;
+	ddr2_udm                   : out   std_logic;
+	ddr2_dqs                   : inout std_logic;
+	ddr2_dqs_n                 : inout std_logic;
+	ddr2_clk                   : out   std_logic;
+	ddr2_clk_n                 : out   std_logic;
+
+	-- cypress interface
+	usb_clk                    : in    std_logic;
+	usb_flag_a                 : in    std_logic; -- programmable flag
+	usb_flag_b                 : in    std_logic; -- full flag
+	usb_flag_c                 : in    std_logic; -- empty flag
+	usb_cs                     : inout std_logic; -- put to GND, not need for this application
+	usb_oe                     : out   std_logic; -- active_low
+	usb_rd                     : out   std_logic; -- active_low
+	usb_wr                     : out   std_logic; -- active_low
+	usb_pktend                 : out   std_logic; -- active_low
+	usb_adr                    : out   std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8
+	usb_dat                    : inout std_logic_vector(7 downto 0);
+
+	switch                     : in    std_logic_vector(0 downto 0);
+	led                        : out   std_logic_vector(7 downto 0)
+	);
+end atlys_sig;
+
+architecture top of atlys_sig is
+	signal rstbtn                    : std_logic;
+	signal rst_n                     : std_logic;
+	signal rst                       : std_logic;
+	signal rst_pll                   : std_logic;
+
+	-- hdmi rx0
+	signal rx0_sda_i                 : std_logic;
+	signal rx0_sda_o                 : std_logic;
+	signal rx0_ddr2_cmd_en           : std_logic;
+	signal rx0_ddr2_cmd_instr        : std_logic_vector( 2 downto 0);
+	signal rx0_ddr2_cmd_bl           : std_logic_vector( 5 downto 0);
+	signal rx0_ddr2_cmd_byte_addr    : std_logic_vector(29 downto 0);
+	signal rx0_ddr2_cmd_empty        : std_logic;
+	signal rx0_ddr2_cmd_full         : std_logic;
+	signal rx0_ddr2_wr_en            : std_logic;
+	signal rx0_ddr2_wr_mask          : std_logic_vector( 3 downto 0);
+	signal rx0_ddr2_wr_data          : std_logic_vector(31 downto 0);
+	signal rx0_ddr2_wr_full          : std_logic;
+	signal rx0_ddr2_wr_empty         : std_logic;
+	signal rx0_ddr2_wr_count         : std_logic_vector( 6 downto 0);
+	signal rx0_ddr2_wr_underrun      : std_logic;
+	signal rx0_ddr2_wr_error         : std_logic;
+
+	-- hdmi tx0
+	signal tx0_pll_locked            : std_logic;
+	signal tx0_ddr2_cmd_en           : std_logic;
+	signal tx0_ddr2_cmd_instr        : std_logic_vector( 2 downto 0);
+	signal tx0_ddr2_cmd_bl           : std_logic_vector( 5 downto 0);
+	signal tx0_ddr2_cmd_byte_addr    : std_logic_vector(29 downto 0);
+	signal tx0_ddr2_cmd_empty        : std_logic;
+	signal tx0_ddr2_cmd_full         : std_logic;
+	signal tx0_ddr2_rd_en            : std_logic;
+	signal tx0_ddr2_rd_data          : std_logic_vector(31 downto 0);
+	signal tx0_ddr2_rd_full          : std_logic;
+	signal tx0_ddr2_rd_empty         : std_logic;
+	signal tx0_ddr2_rd_count         : std_logic_vector( 6 downto 0);
+	signal tx0_ddr2_rd_overflow      : std_logic;
+	signal tx0_ddr2_rd_error         : std_logic;
+
+	-- ddr2
+	signal clk333                    : std_logic;
+	signal clk333in                  : std_logic;
+	signal ddr2_calib_done           : std_logic;
+	signal ddr2_clk_out              : std_logic;
+	signal ddr2_rst_out              : std_logic;
+
+	-- strm cy_usb
+	constant STRM_DDR2_BUS           : integer := 0;
+	constant STRM_OUT_SLV_CNT        : integer := 1;
+	signal strm_in_data              : std_logic_vector(31 downto 0);
+	signal strm_in_eop               : std_logic;
+	signal strm_in_sop               : std_logic;
+	signal strm_in_en                : std_logic;
+	signal strm_in_busy              : std_logic;
+	signal strm_out_slv_reqs         : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
+	signal strm_out_slv_busy         : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
+	signal strm_out_data             : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
+	signal strm_out_eop              : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
+	signal strm_out_en               : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
+
+	-- strm ddr2
+	signal strm_ddr2_cmd_en          : std_logic;
+	signal strm_ddr2_cmd_instr       : std_logic_vector( 2 downto 0);
+	signal strm_ddr2_cmd_bl          : std_logic_vector( 5 downto 0);
+	signal strm_ddr2_cmd_byte_addr   : std_logic_vector(29 downto 0);
+	signal strm_ddr2_cmd_empty       : std_logic;
+	signal strm_ddr2_cmd_full        : std_logic;
+	signal strm_ddr2_wr_en           : std_logic;
+	signal strm_ddr2_wr_mask         : std_logic_vector( 3 downto 0);
+	signal strm_ddr2_wr_data         : std_logic_vector(31 downto 0);
+	signal strm_ddr2_wr_full         : std_logic;
+	signal strm_ddr2_wr_empty        : std_logic;
+	signal strm_ddr2_wr_count        : std_logic_vector( 6 downto 0);
+	signal strm_ddr2_wr_underrun     : std_logic;
+	signal strm_ddr2_wr_error        : std_logic;
+	signal strm_ddr2_rd_en           : std_logic;
+	signal strm_ddr2_rd_data         : std_logic_vector(31 downto 0);
+	signal strm_ddr2_rd_full         : std_logic;
+	signal strm_ddr2_rd_empty        : std_logic;
+	signal strm_ddr2_rd_count        : std_logic_vector( 6 downto 0);
+	signal strm_ddr2_rd_overflow     : std_logic;
+	signal strm_ddr2_rd_error        : std_logic;
+	signal ddr2_strm_in_busy         : std_logic;
+	signal ddr2_strm_out_req         : std_logic;
+	signal ddr2_strm_out_busy        : std_logic;
+	signal ddr2_strm_out_data        : std_logic_vector(31 downto 0);
+	signal ddr2_strm_out_eop         : std_logic;
+	signal ddr2_strm_out_en          : std_logic;
+
+	signal debug_usb                 : std_logic_vector( 7 downto 0);
+	signal debug_strm_ddr2           : std_logic_vector( 7 downto 0);
+begin
+	rstbtn  <= not rstbtn_n;
+	rst_pll <= ddr2_rst_out;
+	rst_n   <= not ddr2_rst_out and tx0_pll_locked;
+	rst     <= not rst_n;
+	led     <= (others => '0');
+
+	dvi2ddr_0: entity work.dvi2ddr
+	port map (
+		clk                   => ddr2_clk_out,
+		rst                   => ddr2_rst_out,
+
+		ctrl_disable_wr       => switch(0),
+
+		rx_tmds               => rx0_tmds,
+		rx_tmds_n             => rx0_tmds_n,
+
+		-- memory interface
+		ddr2_cmd_en_o         => rx0_ddr2_cmd_en,
+		ddr2_cmd_instr_o      => rx0_ddr2_cmd_instr,
+		ddr2_cmd_bl_o         => rx0_ddr2_cmd_bl,
+		ddr2_cmd_byte_addr_o  => rx0_ddr2_cmd_byte_addr,
+		ddr2_cmd_empty_i      => rx0_ddr2_cmd_empty,
+		ddr2_cmd_full_i       => rx0_ddr2_cmd_full,
+		ddr2_wr_en_o          => rx0_ddr2_wr_en,
+		ddr2_wr_mask_o        => rx0_ddr2_wr_mask,
+		ddr2_wr_data_o        => rx0_ddr2_wr_data,
+		ddr2_wr_full_i        => rx0_ddr2_wr_full,
+		ddr2_wr_empty_i       => rx0_ddr2_wr_empty,
+		ddr2_wr_count_i       => rx0_ddr2_wr_count,
+		ddr2_wr_underrun_i    => rx0_ddr2_wr_underrun,
+		ddr2_wr_error_i       => rx0_ddr2_wr_error
+	);
+
+	-- ----------------------------------------------------------------------------
+	-- I2C EDID Emulation
+	-- ----------------------------------------------------------------------------
+	rx0_sda_i <= rx0_sda;
+	rx0_sda   <= '0' when rx0_sda_o = '0' else 'Z';
+	i2c_rom_0: entity work.i2c_rom
+	port map (
+		clk    => ddr2_clk_out,
+		rst_n  => rst_n,
+		sda_i  => rx0_sda_i,
+		sda_o  => rx0_sda_o,
+		scl_i  => rx0_scl
+	);
+
+	-- ----------------------------------------------------------------------------
+	-- DDR2
+	-- ----------------------------------------------------------------------------
+	ddr2_0: entity work.ddr2
+	port map (
+		c3_sys_clk                              => clk100,
+		c3_sys_rst_i                            => rstbtn,
+		c3_calib_done                           => ddr2_calib_done,
+		c3_clk0                                 => ddr2_clk_out,
+		c3_rst0                                 => ddr2_rst_out,
+		mcb3_dram_dq                            => ddr2_dq,
+		mcb3_dram_a                             => ddr2_a,
+		mcb3_dram_ba                            => ddr2_ba,
+		mcb3_dram_ras_n                         => ddr2_ras_n,
+		mcb3_dram_cas_n                         => ddr2_cas_n,
+		mcb3_dram_we_n                          => ddr2_we_n,
+		mcb3_dram_odt                           => ddr2_odt,
+		mcb3_dram_cke                           => ddr2_cke,
+		mcb3_dram_dm                            => ddr2_dm,
+		mcb3_dram_udqs                          => ddr2_udqs,
+		mcb3_dram_udqs_n                        => ddr2_udqs_n,
+		mcb3_rzq                                => ddr2_rzq,
+		mcb3_zio                                => ddr2_zio,
+		mcb3_dram_udm                           => ddr2_udm,
+		mcb3_dram_dqs                           => ddr2_dqs,
+		mcb3_dram_dqs_n                         => ddr2_dqs_n,
+		mcb3_dram_ck                            => ddr2_clk,
+		mcb3_dram_ck_n                          => ddr2_clk_n,
+
+		c3_p0_cmd_clk                           => ddr2_clk_out,
+		c3_p0_cmd_en                            => tx0_ddr2_cmd_en,
+		c3_p0_cmd_instr                         => tx0_ddr2_cmd_instr,
+		c3_p0_cmd_bl                            => tx0_ddr2_cmd_bl,
+		c3_p0_cmd_byte_addr                     => tx0_ddr2_cmd_byte_addr,
+		c3_p0_cmd_empty                         => tx0_ddr2_cmd_empty,
+		c3_p0_cmd_full                          => tx0_ddr2_cmd_full,
+		c3_p0_wr_clk                            => ddr2_clk_out,
+		c3_p0_wr_en                             => '0',
+		c3_p0_wr_mask                           => (others => '0'),
+		c3_p0_wr_data                           => (others => '0'),
+		c3_p0_wr_full                           => open,
+		c3_p0_wr_empty                          => open,
+		c3_p0_wr_count                          => open,
+		c3_p0_wr_underrun                       => open,
+		c3_p0_wr_error                          => open,
+		c3_p0_rd_clk                            => ddr2_clk_out,
+		c3_p0_rd_en                             => tx0_ddr2_rd_en,
+		c3_p0_rd_data                           => tx0_ddr2_rd_data,
+		c3_p0_rd_full                           => tx0_ddr2_rd_full,
+		c3_p0_rd_empty                          => tx0_ddr2_rd_empty,
+		c3_p0_rd_count                          => tx0_ddr2_rd_count,
+		c3_p0_rd_overflow                       => tx0_ddr2_rd_overflow,
+		c3_p0_rd_error                          => tx0_ddr2_rd_error,
+
+		c3_p1_cmd_clk                           => ddr2_clk_out,
+		c3_p1_cmd_en                            => rx0_ddr2_cmd_en,
+		c3_p1_cmd_instr                         => rx0_ddr2_cmd_instr,
+		c3_p1_cmd_bl                            => rx0_ddr2_cmd_bl,
+		c3_p1_cmd_byte_addr                     => rx0_ddr2_cmd_byte_addr,
+		c3_p1_cmd_empty                         => rx0_ddr2_cmd_empty,
+		c3_p1_cmd_full                          => rx0_ddr2_cmd_full,
+		c3_p1_wr_clk                            => ddr2_clk_out,
+		c3_p1_wr_en                             => rx0_ddr2_wr_en,
+		c3_p1_wr_mask                           => rx0_ddr2_wr_mask,
+		c3_p1_wr_data                           => rx0_ddr2_wr_data,
+		c3_p1_wr_full                           => rx0_ddr2_wr_full,
+		c3_p1_wr_empty                          => rx0_ddr2_wr_empty,
+		c3_p1_wr_count                          => rx0_ddr2_wr_count,
+		c3_p1_wr_underrun                       => rx0_ddr2_wr_underrun,
+		c3_p1_wr_error                          => rx0_ddr2_wr_error,
+		c3_p1_rd_clk                            => ddr2_clk_out,
+		c3_p1_rd_en                             => '0',
+		c3_p1_rd_data                           => open,
+		c3_p1_rd_full                           => open,
+		c3_p1_rd_empty                          => open,
+		c3_p1_rd_count                          => open,
+		c3_p1_rd_overflow                       => open,
+		c3_p1_rd_error                          => open,
+
+		c3_p2_cmd_clk                           => ddr2_clk_out,
+		c3_p2_cmd_en                            => strm_ddr2_cmd_en,
+		c3_p2_cmd_instr                         => strm_ddr2_cmd_instr,
+		c3_p2_cmd_bl                            => strm_ddr2_cmd_bl,
+		c3_p2_cmd_byte_addr                     => strm_ddr2_cmd_byte_addr,
+		c3_p2_cmd_empty                         => strm_ddr2_cmd_empty,
+		c3_p2_cmd_full                          => strm_ddr2_cmd_full,
+		c3_p2_wr_clk                            => ddr2_clk_out,
+		c3_p2_wr_en                             => strm_ddr2_wr_en,
+		c3_p2_wr_mask                           => strm_ddr2_wr_mask,
+		c3_p2_wr_data                           => strm_ddr2_wr_data,
+		c3_p2_wr_full                           => strm_ddr2_wr_full,
+		c3_p2_wr_empty                          => strm_ddr2_wr_empty,
+		c3_p2_wr_count                          => strm_ddr2_wr_count,
+		c3_p2_wr_underrun                       => strm_ddr2_wr_underrun,
+		c3_p2_wr_error                          => strm_ddr2_wr_error,
+		c3_p2_rd_clk                            => ddr2_clk_out,
+		c3_p2_rd_en                             => strm_ddr2_rd_en,
+		c3_p2_rd_data                           => strm_ddr2_rd_data,
+		c3_p2_rd_full                           => strm_ddr2_rd_full,
+		c3_p2_rd_empty                          => strm_ddr2_rd_empty,
+		c3_p2_rd_count                          => strm_ddr2_rd_count,
+		c3_p2_rd_overflow                       => strm_ddr2_rd_overflow,
+		c3_p2_rd_error                          => strm_ddr2_rd_error,
+	
+		c3_p3_cmd_clk                           => '0',
+		c3_p3_cmd_en                            => '0',
+		c3_p3_cmd_instr                         => (others => '0'),
+		c3_p3_cmd_bl                            => (others => '0'),
+		c3_p3_cmd_byte_addr                     => (others => '0'),
+		c3_p3_cmd_empty                         => open,
+		c3_p3_cmd_full                          => open,
+		c3_p3_wr_clk                            => '0',
+		c3_p3_wr_en                             => '0',
+		c3_p3_wr_mask                           => (others => '0'),
+		c3_p3_wr_data                           => (others => '0'),
+		c3_p3_wr_full                           => open,
+		c3_p3_wr_empty                          => open,
+		c3_p3_wr_count                          => open,
+		c3_p3_wr_underrun                       => open,
+		c3_p3_wr_error                          => open,
+		c3_p3_rd_clk                            => '0',
+		c3_p3_rd_en                             => '0',
+		c3_p3_rd_data                           => open,
+		c3_p3_rd_full                           => open,
+		c3_p3_rd_empty                          => open,
+		c3_p3_rd_count                          => open,
+		c3_p3_rd_overflow                       => open,
+		c3_p3_rd_error                          => open
+	);
+
+	ddr2dvi_0: entity work.ddr2dvi
+	port map (
+		clk                   => ddr2_clk_out,
+		rst_n                 => rst_n,
+		rst_pll               => rst_pll,
+
+		tx_tmds               => tx0_tmds,
+		tx_tmds_n             => tx0_tmds_n,
+		tx_pll_locked_o       => tx0_pll_locked,
+
+		-- memory interface
+		ddr2_cmd_en_o         => tx0_ddr2_cmd_en,
+		ddr2_cmd_instr_o      => tx0_ddr2_cmd_instr,
+		ddr2_cmd_bl_o         => tx0_ddr2_cmd_bl,
+		ddr2_cmd_byte_addr_o  => tx0_ddr2_cmd_byte_addr,
+		ddr2_cmd_empty_i      => tx0_ddr2_cmd_empty,
+		ddr2_cmd_full_i       => tx0_ddr2_cmd_full,
+
+		ddr2_rd_en_o          => tx0_ddr2_rd_en,
+		ddr2_rd_data_i        => tx0_ddr2_rd_data,
+		ddr2_rd_full_i        => tx0_ddr2_rd_full,
+		ddr2_rd_empty_i       => tx0_ddr2_rd_empty,
+		ddr2_rd_count_i       => tx0_ddr2_rd_count,
+		ddr2_rd_overflow_i    => tx0_ddr2_rd_overflow,
+		ddr2_rd_error_i       => tx0_ddr2_rd_error
+	);
+
+	-- ----------------------------------------------------------------------------
+	-- USB
+	-- ----------------------------------------------------------------------------
+	f2p_strm_top_0: entity work.f2p_strm_top
+	generic map (STRM_OUT_SLV_CNT => STRM_OUT_SLV_CNT)
+	port map (
+		clk                   => ddr2_clk_out,
+		rst_n                 => rst_n,
+		debug                 => debug_usb,
+
+		-- cypress interface
+		usb_clk               => usb_clk,
+		usb_flag_a_i          => usb_flag_a,
+		usb_flag_b_i          => usb_flag_b,
+		usb_flag_c_i          => usb_flag_c,
+		usb_cs_o              => usb_cs,
+		usb_oe_o              => usb_oe,
+		usb_rd_o              => usb_rd,
+		usb_wr_o              => usb_wr,
+		usb_pktend_o          => usb_pktend,
+		usb_adr_o             => usb_adr,
+		usb_dat_io            => usb_dat,
+
+		-- streaming bus
+		strm_in_data_o        => strm_in_data,
+		strm_in_eop_o         => strm_in_eop,
+		strm_in_sop_o         => strm_in_sop,
+		strm_in_en_o          => strm_in_en,
+		strm_in_busy_i        => strm_in_busy,
+		strm_out_slv_reqs_i   => strm_out_slv_reqs,
+		strm_out_slv_busy_o   => strm_out_slv_busy,
+		strm_out_data_i       => strm_out_data,
+		strm_out_eop_i        => strm_out_eop,
+		strm_out_en_i         => strm_out_en
+	);
+
+	strm_out_slv_reqs(STRM_DDR2_BUS) <= ddr2_strm_out_req;
+	strm_out_eop(STRM_DDR2_BUS)      <= ddr2_strm_out_eop;
+	strm_out_en(STRM_DDR2_BUS)       <= ddr2_strm_out_en;
+	strm_out_data(STRM_DDR2_BUS)     <= ddr2_strm_out_data;
+	ddr2_strm_out_busy               <= strm_out_slv_busy(STRM_DDR2_BUS);
+	strm_in_busy                     <= ddr2_strm_in_busy;
+
+	strm_ddr2_0: entity work.strm_ddr2
+	port map (
+		clk                   => ddr2_clk_out,
+		rst_n                 => rst_n,
+		debug                 => debug_strm_ddr2,
+
+		-- streaming bus
+		strm_in_data_i        => strm_in_data,
+		strm_in_eop_i         => strm_in_eop,
+		strm_in_sop_i         => strm_in_sop,
+		strm_in_en_i          => strm_in_en,
+		strm_in_busy_o        => ddr2_strm_in_busy,
+		strm_out_req_o        => ddr2_strm_out_req,
+		strm_out_busy_i       => ddr2_strm_out_busy,
+		strm_out_data_o       => ddr2_strm_out_data,
+		strm_out_eop_o        => ddr2_strm_out_eop,
+		strm_out_en_o         => ddr2_strm_out_en,
+
+		-- memory interface
+		ddr2_cmd_en_o         => strm_ddr2_cmd_en,
+		ddr2_cmd_instr_o      => strm_ddr2_cmd_instr,
+		ddr2_cmd_bl_o         => strm_ddr2_cmd_bl,
+		ddr2_cmd_byte_addr_o  => strm_ddr2_cmd_byte_addr,
+		ddr2_cmd_empty_i      => strm_ddr2_cmd_empty,
+		ddr2_cmd_full_i       => strm_ddr2_cmd_full,
+		ddr2_wr_en_o          => strm_ddr2_wr_en,
+		ddr2_wr_mask_o        => strm_ddr2_wr_mask,
+		ddr2_wr_data_o        => strm_ddr2_wr_data,
+		ddr2_wr_full_i        => strm_ddr2_wr_full,
+		ddr2_wr_empty_i       => strm_ddr2_wr_empty,
+		ddr2_wr_count_i       => strm_ddr2_wr_count,
+		ddr2_wr_underrun_i    => strm_ddr2_wr_underrun,
+		ddr2_wr_error_i       => strm_ddr2_wr_error,
+		ddr2_rd_en_o          => strm_ddr2_rd_en,
+		ddr2_rd_data_i        => strm_ddr2_rd_data,
+		ddr2_rd_full_i        => strm_ddr2_rd_full,
+		ddr2_rd_empty_i       => strm_ddr2_rd_empty,
+		ddr2_rd_count_i       => strm_ddr2_rd_count,
+		ddr2_rd_overflow_i    => strm_ddr2_rd_overflow,
+		ddr2_rd_error_i       => strm_ddr2_rd_error
+	);
+
+end top;
diff --git a/fpga/src/top/dmb.ucf b/fpga/src/top/dmb.ucf
new file mode 100644
index 0000000..22d255e
--- /dev/null
+++ b/fpga/src/top/dmb.ucf
@@ -0,0 +1,98 @@
+#FPGA_PART=xc6slx9-2tqg144
+CONFIG VCCAUX = 3.3;
+
+###############################################################################
+## SYSCLK/RESET Input
+###############################################################################
+
+NET "clk100_i" LOC = "P84" | IOSTANDARD = LVCMOS33 | TNM_NET = "clk100_i";
+TIMESPEC TS_clk100_i = PERIOD "clk100_i" 100 MHz HIGH 50%;
+
+NET "usb_clk_i" TNM_NET = "usb_clk_i";
+TIMESPEC "TS_usb_clk_i" = PERIOD "usb_clk_i" 20.833 ns HIGH 50% INPUT_JITTER 208.33ps;
+
+## Constraint for RX0
+NET "dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
+TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;
+
+## allow 
+#PIN "dvi_decoder_0/pclkbufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
+
+################################################
+### TMDS pairs
+################################################
+NET "rx0_tmds(3)"   LOC = "P132" |IOSTANDARD = TMDS_33 ; # CLK
+NET "rx0_tmds_n(3)" LOC = "P131" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(2)"   LOC = "P134" |IOSTANDARD = TMDS_33 ; # Red
+NET "rx0_tmds_n(2)" LOC = "P133" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(1)"   LOC = "P140" |IOSTANDARD = TMDS_33 ; # Green
+NET "rx0_tmds_n(1)" LOC = "P139" |IOSTANDARD = TMDS_33 ;
+NET "rx0_tmds(0)"   LOC = "P144"  |IOSTANDARD = TMDS_33 ; # Blue
+NET "rx0_tmds_n(0)" LOC = "P143"  |IOSTANDARD = TMDS_33 ;
+##NET "rx0_scl"       LOC = "C13" |IOSTANDARD = LVCMOS33 ;
+##NET "rx0_sda"       LOC = "A13" |IOSTANDARD = LVCMOS33 ;
+
+#######################################################################################
+#### onBoard USB controller
+#######################################################################################
+NET "usb_clk_i"     LOC = "P16"  | IOSTANDARD = LVCMOS33;
+NET "usb_flag_a_i"  LOC = "P10"  | IOSTANDARD = LVCMOS33;
+NET "usb_flag_b_i"  LOC = "P9"   | IOSTANDARD = LVCMOS33;
+NET "usb_flag_c_i"  LOC = "P8"   | IOSTANDARD = LVCMOS33;
+NET "usb_cs_io"     LOC = "P142" | IOSTANDARD = LVCMOS33;
+NET "usb_oe_o"      LOC = "P6"   | IOSTANDARD = LVCMOS33;
+NET "usb_rd_o"      LOC = "P116" | IOSTANDARD = LVCMOS33;
+NET "usb_wr_o"      LOC = "P117" | IOSTANDARD = LVCMOS33;
+NET "usb_pktend_o"  LOC = "P1"   | IOSTANDARD = LVCMOS33;
+NET "usb_adr_o<0>"  LOC = "P5"   | IOSTANDARD = LVCMOS33;
+NET "usb_adr_o<1>"  LOC = "P2"   | IOSTANDARD = LVCMOS33;
+NET "usb_dat_io<0>" LOC = "P23"  | IOSTANDARD = LVCMOS33;
+NET "usb_dat_io<1>" LOC = "P22"  | IOSTANDARD = LVCMOS33;
+NET "usb_dat_io<2>" LOC = "P21"  | IOSTANDARD = LVCMOS33;
+NET "usb_dat_io<3>" LOC = "P17"  | IOSTANDARD = LVCMOS33;
+NET "usb_dat_io<4>" LOC = "P15"  | IOSTANDARD = LVCMOS33;
+NET "usb_dat_io<5>" LOC = "P14"  | IOSTANDARD = LVCMOS33;
+NET "usb_dat_io<6>" LOC = "P12"  | IOSTANDARD = LVCMOS33;
+NET "usb_dat_io<7>" LOC = "P11"  | IOSTANDARD = LVCMOS33;
+
+#########################################
+## VMC header
+#########################################
+NET "vmc_clk_o"      LOC = "P55" | IOSTANDARD = LVCMOS33;
+NET "vmc_hsync_o"    LOC = "P61" | IOSTANDARD = LVCMOS33;
+NET "vmc_vsync_o"    LOC = "P62" | IOSTANDARD = LVCMOS33;
+NET "vmc_de_o"       LOC = "P66" | IOSTANDARD = LVCMOS33;
+NET "vmc_red_o<0>"   LOC = "P59" | IOSTANDARD = LVCMOS33;
+NET "vmc_red_o<1>"   LOC = "P51" | IOSTANDARD = LVCMOS33;
+NET "vmc_red_o<2>"   LOC = "P58" | IOSTANDARD = LVCMOS33;
+NET "vmc_red_o<3>"   LOC = "P50" | IOSTANDARD = LVCMOS33;
+NET "vmc_red_o<4>"   LOC = "P57" | IOSTANDARD = LVCMOS33;
+NET "vmc_red_o<5>"   LOC = "P48" | IOSTANDARD = LVCMOS33;
+NET "vmc_red_o<6>"   LOC = "P56" | IOSTANDARD = LVCMOS33;
+NET "vmc_red_o<7>"   LOC = "P47" | IOSTANDARD = LVCMOS33;
+NET "vmc_green_o<0>" LOC = "P46" | IOSTANDARD = LVCMOS33;
+NET "vmc_green_o<1>" LOC = "P41" | IOSTANDARD = LVCMOS33;
+NET "vmc_green_o<2>" LOC = "P45" | IOSTANDARD = LVCMOS33;
+NET "vmc_green_o<3>" LOC = "P40" | IOSTANDARD = LVCMOS33;
+NET "vmc_green_o<4>" LOC = "P44" | IOSTANDARD = LVCMOS33;
+NET "vmc_green_o<5>" LOC = "P39" | IOSTANDARD = LVCMOS33;
+NET "vmc_green_o<6>" LOC = "P43" | IOSTANDARD = LVCMOS33;
+NET "vmc_green_o<7>" LOC = "P38" | IOSTANDARD = LVCMOS33;
+NET "vmc_blue_o<0>"  LOC = "P35" | IOSTANDARD = LVCMOS33;
+NET "vmc_blue_o<1>"  LOC = "P30" | IOSTANDARD = LVCMOS33;
+NET "vmc_blue_o<2>"  LOC = "P34" | IOSTANDARD = LVCMOS33;
+NET "vmc_blue_o<3>"  LOC = "P29" | IOSTANDARD = LVCMOS33;
+NET "vmc_blue_o<4>"  LOC = "P33" | IOSTANDARD = LVCMOS33;
+NET "vmc_blue_o<5>"  LOC = "P27" | IOSTANDARD = LVCMOS33;
+NET "vmc_blue_o<6>"  LOC = "P32" | IOSTANDARD = LVCMOS33;
+NET "vmc_blue_o<7>"  LOC = "P26" | IOSTANDARD = LVCMOS33;
+
+#########################################
+## Reset button and LEDs and Mechanical Switches (SW)
+#########################################
+#PIN "rstbtn_n" TIG;
+#NET "rstbtn_n" LOC = "" |IOSTANDARD = LVCMOS33;
+NET "led_o<0>"   LOC = "P75" | IOSTANDARD = LVCMOS33;
+NET "led_o<1>"   LOC = "P78" | IOSTANDARD = LVCMOS33;
+NET "led_o<2>"   LOC = "P79" | IOSTANDARD = LVCMOS33;
+NET "led_o<3>"   LOC = "P80" | IOSTANDARD = LVCMOS33;
diff --git a/fpga/src/top/dmb.vhd b/fpga/src/top/dmb.vhd
new file mode 100644
index 0000000..18bfb39
--- /dev/null
+++ b/fpga/src/top/dmb.vhd
@@ -0,0 +1,345 @@
+-- -----------------------------------------------------------------------------
+-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+--
+-- Permission is hereby granted, free of charge, to any person obtaining a copy
+-- of this software and associated documentation files (the "Software"), to deal
+-- in the Software without restriction, including without limitation the rights
+-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+-- copies of the Software, and to permit persons to whom the Software is
+-- furnished to do so, subject to the following conditions:
+--
+-- The above copyright notice and this permission notice shall be included in
+-- all copies or substantial portions of the Software.
+--
+-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+-- THE SOFTWARE.
+-- -----------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.dvi_package.all;
+use work.strm_package.all;
+
+library work;
+use work.all;
+
+library UNISIM;
+use UNISIM.Vcomponents.all;
+
+entity dmb is
+	port (
+		clk100_i                   : in    std_logic; -- 100 MHz osicallator
+
+		-- HDMI
+		rx0_tmds                   : in    std_logic_vector(3 downto 0);
+		rx0_tmds_n                 : in    std_logic_vector(3 downto 0);
+		--rx0_sda                    : inout std_logic;
+		--rx0_scl                    : in    std_logic;
+
+		-- vcm
+		vmc_clk_o                  : out   std_logic;
+		vmc_red_o                  : out   std_logic_vector(7 downto 0);
+		vmc_green_o                : out   std_logic_vector(7 downto 0);
+		vmc_blue_o                 : out   std_logic_vector(7 downto 0);
+		vmc_hsync_o                : out   std_logic;
+		vmc_vsync_o                : out   std_logic;
+		vmc_de_o                   : out   std_logic;
+
+		-- cypress interface
+		usb_clk_i                  : in    std_logic;
+		usb_flag_a_i               : in    std_logic; -- programmable flag
+		usb_flag_b_i               : in    std_logic; -- full flag
+		usb_flag_c_i               : in    std_logic; -- empty flag
+		usb_cs_io                  : inout std_logic; -- put to GND, not need for this application
+		usb_oe_o                   : out   std_logic; -- active_low
+		usb_rd_o                   : out   std_logic; -- active_low
+		usb_wr_o                   : out   std_logic; -- active_low
+		usb_pktend_o               : out   std_logic; -- active_low
+		usb_adr_o                  : out   std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8
+		usb_dat_io                 : inout std_logic_vector(7 downto 0);
+
+		led_o                      : out   std_logic_vector(3 downto 0)
+	);
+end dmb;
+
+architecture top of dmb is
+	signal rst_n                     : std_logic;
+	signal rstbtn                    : std_logic;
+                                         
+	-- hdmi                          
+	signal pclk                      : std_logic;
+	signal pclkx2                    : std_logic;
+	signal pclkx10                   : std_logic;
+	signal pll_lckd                  : std_logic;
+	signal serdesstrobe              : std_logic;
+	signal tmdsclk                   : std_logic;
+	signal hsync                     : std_logic;
+	signal vsync                     : std_logic;
+	signal dat_en                    : std_logic;
+	signal valid                     : std_logic_vector(COLOR_CNT-1 downto 0);
+	signal ready                     : std_logic_vector(COLOR_CNT-1 downto 0);
+	signal psalgnerr                 : std_logic;
+	signal color                     : color_t(COLOR_CNT-1 downto 0);
+	signal sdout                     : sdat_t(COLOR_CNT-1 downto 0);
+
+	-- clockinga
+	signal usb_rst_n                 : std_logic;
+	signal usb_clk_locked            : std_logic;
+	signal usb_clk_gb                : std_logic;
+	signal usb_clk_ib                : std_logic;
+	signal usb_clk                   : std_logic;
+	signal rst100_n                  : std_logic;
+	signal clk100_locked             : std_logic;
+	signal clk100_ib                 : std_logic;
+	signal clk100_gb                 : std_logic;
+	signal clk48_gb                  : std_logic;
+	signal clk100                    : std_logic;
+	signal clk48                     : std_logic;
+
+
+	-- strm cy_usb
+	constant STRM_REGFILE_BUS        : integer := 0;
+	constant STRM_OUT_SLV_CNT        : integer := 1;
+	signal strm_in_data              : std_logic_vector(31 downto 0);
+	signal strm_in_eop               : std_logic;
+	signal strm_in_sop               : std_logic;
+	signal strm_in_en                : std_logic;
+	signal strm_in_busy              : std_logic;
+	signal strm_out_slv_reqs         : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
+	signal strm_out_slv_busy         : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
+	signal strm_out_data             : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
+	signal strm_out_eop              : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
+	signal strm_out_en               : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
+	-- regfile
+	signal rf_strm_in_busy           : std_logic;
+	signal rf_strm_out_req           : std_logic;
+	signal rf_strm_out_busy          : std_logic;
+	signal rf_strm_out_data          : std_logic_vector(31 downto 0);
+	signal rf_strm_out_eop           : std_logic;
+	signal rf_strm_out_en            : std_logic;
+	constant REG_CNT                 : integer := 8;
+	signal regfile                   : std_logic_vector((32*REG_CNT)-1 downto 0);
+
+	signal test                      : std_logic;
+begin 
+	rstbtn    <= '0';
+	usb_rst_n <= usb_clk_locked;
+	rst100_n  <= clk100_locked;
+	led_o     <= regfile(2 downto 0) & test;
+
+	-- ----------------------------------------------------------------------------
+	-- clocking
+	-- ----------------------------------------------------------------------------
+	-- USB
+	ibufg_usb_clk: IBUFG port map (O => usb_clk_ib, I => usb_clk_i);
+ 	bufg_usb_clk: BUFG port map (O => usb_clk, I => usb_clk_gb);
+	dcm_usb_clk: DCM_SP
+	generic map (
+		CLKDV_DIVIDE          => 2.000,
+		CLKFX_DIVIDE          => 1,
+		CLKFX_MULTIPLY        => 4,
+		CLKIN_DIVIDE_BY_2     => FALSE,
+		CLKIN_PERIOD          => 20.833,
+		CLKOUT_PHASE_SHIFT    => "NONE",
+		CLK_FEEDBACK          => "1X",
+		DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
+		PHASE_SHIFT           => 0,
+		STARTUP_WAIT          => FALSE
+	)
+	port map (
+		CLKIN                 => usb_clk_ib,
+		CLKFB                 => usb_clk,
+		-- Output clocks
+		CLK0                  => usb_clk_gb,
+		CLK90                 => open,
+		CLK180                => open,
+		CLK270                => open,
+		CLK2X                 => open,
+		CLK2X180              => open,
+		CLKFX                 => open,
+		CLKFX180              => open,
+		CLKDV                 => open,
+		-- Ports for dynamic phase shift
+		PSCLK                 => '0',
+		PSEN                  => '0',
+		PSINCDEC              => '0',
+		PSDONE                => open,
+		-- Other control and status signals
+		LOCKED                => usb_clk_locked,
+		STATUS                => open,
+		RST                   => rstbtn,
+		-- Unused pin, tie low 
+		DSSEN                 => '0'
+	);
+
+	-- MAIN
+	process (clk100, rst100_n)
+	begin
+	if rst100_n = '0' then
+		test <= '0';
+	elsif rising_edge(clk100) then
+		test <= not test;
+	end if;
+	end process;
+	ibufg_clk100: IBUFG port map (O => clk100_ib, I => clk100_i);
+ 	bufg_clk100: BUFG port map (O => clk100, I => clk100_gb);
+ 	bufg_clk48: BUFG port map (O => clk48, I => clk48_gb);
+	dcm_clk100: DCM_SP
+	generic map (
+		CLKDV_DIVIDE          => 2.000,
+		CLKFX_DIVIDE          => 25,
+		CLKFX_MULTIPLY        => 12,
+		CLKIN_DIVIDE_BY_2     => FALSE,
+		CLKIN_PERIOD          => 10.0,
+		CLKOUT_PHASE_SHIFT    => "NONE",
+		CLK_FEEDBACK          => "1X",
+		DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
+		PHASE_SHIFT           => 0,
+		STARTUP_WAIT          => FALSE
+	)
+	port map (
+		CLKIN                 => clk100_ib,
+		CLKFB                 => clk100,
+		-- Output clocks
+		CLK0                  => clk100_gb,
+		CLK90                 => open,
+		CLK180                => open,
+		CLK270                => open,
+		CLK2X                 => open,
+		CLK2X180              => open,
+		CLKFX                 => clk48_gb,
+		CLKFX180              => open,
+		CLKDV                 => open,
+		-- Ports for dynamic phase shift
+		PSCLK                 => '0',
+		PSEN                  => '0',
+		PSINCDEC              => '0',
+		PSDONE                => open,
+		-- Other control and status signals
+		LOCKED                => clk100_locked,
+		STATUS                => open,
+		RST                   => rstbtn,
+		-- Unused pin, tie low 
+		DSSEN                 => '0'
+	);
+
+
+	dvi_decoder_0: entity work.dvi_decoder
+	port map (
+		ext_rst        => rstbtn,
+
+		tmdsclk_p      => rx0_tmds(3),
+		tmdsclk_n      => rx0_tmds_n(3),
+		din_p          => rx0_tmds(2 downto 0),
+		din_n          => rx0_tmds_n(2 downto 0),
+
+		reset_n        => rst_n,        -- rx reset
+		pclk_o         => pclk,         -- regenerated pixel clock
+		pclkx2_o       => pclkx2,       -- double rate pixel clock
+		pclkx10_o      => pclkx10,      -- 10x pixel as IOCLK
+
+		pll_lckd_o     => pll_lckd,     -- send pll_lckd out so it can be fed into a different BUFPLL
+		serdesstrobe_o => serdesstrobe, -- BUFPLL serdesstrobe output
+		tmdsclk_o      => tmdsclk,      -- TMDS cable clock
+
+		hsync_o        => hsync,        -- hsync data
+		vsync_o        => vsync,        -- vsync data
+		dat_en_o       => dat_en,       -- data enable
+		valid_o        => valid,
+		ready_o        => ready,
+		psalgnerr_o    => psalgnerr,
+		sdout_o        => sdout,
+		color_o        => color
+	);
+
+	vmc_clk_ddr: ODDR2
+	port map (
+		Q     => vmc_clk_o,  -- 1-bit DDR output data
+		C0    => pclk,       -- clock input
+		C1    => not pclk,   -- clock input, inverted
+		CE    => '1',        -- clock enable always
+		D0    => '1',        -- sampled on clock posedge, output when clock is HIGH
+		D1    => '0',        -- sampled on clock negedge, output when clock is LOW
+		R     => '0',        -- set/reset disabled
+		S     => '1'         -- set/reset disabled
+	);
+	--vmc_clk_o    <= pclk;
+	vmc_red_o    <= color(RED);
+	vmc_green_o  <= color(GREEN);
+	vmc_blue_o   <= color(BLUE);
+	vmc_hsync_o  <= hsync;
+	vmc_vsync_o  <= vsync;
+	vmc_de_o     <= dat_en;
+
+	-- ----------------------------------------------------------------------------
+	-- core logic
+	-- ----------------------------------------------------------------------------
+	f2p_strm_top_0: entity work.f2p_strm_top
+	generic map (STRM_OUT_SLV_CNT => STRM_OUT_SLV_CNT)
+	port map (
+		clk                   => usb_clk,
+		rst_n                 => usb_rst_n,
+		debug                 => open,
+
+		-- cypress interface
+		usb_clk               => usb_clk,
+		usb_flag_a_i          => usb_flag_a_i,
+		usb_flag_b_i          => usb_flag_b_i,
+		usb_flag_c_i          => usb_flag_c_i,
+		usb_cs_o              => usb_cs_io,
+		usb_oe_o              => usb_oe_o,
+		usb_rd_o              => usb_rd_o,
+		usb_wr_o              => usb_wr_o,
+		usb_pktend_o          => usb_pktend_o,
+		usb_adr_o             => usb_adr_o,
+		usb_dat_io            => usb_dat_io,
+
+		-- streaming bus
+		strm_in_data_o        => strm_in_data,
+		strm_in_eop_o         => strm_in_eop,
+		strm_in_sop_o         => strm_in_sop,
+		strm_in_en_o          => strm_in_en,
+		strm_in_busy_i        => strm_in_busy,
+		strm_out_slv_reqs_i   => strm_out_slv_reqs,
+		strm_out_slv_busy_o   => strm_out_slv_busy,
+		strm_out_data_i       => strm_out_data,
+		strm_out_eop_i        => strm_out_eop,
+		strm_out_en_i         => strm_out_en
+	);
+	strm_out_slv_reqs(STRM_REGFILE_BUS) <= rf_strm_out_req;
+	strm_out_eop(STRM_REGFILE_BUS)      <= rf_strm_out_eop;
+	strm_out_en(STRM_REGFILE_BUS)       <= rf_strm_out_en;
+	strm_out_data(STRM_REGFILE_BUS)     <= rf_strm_out_data;
+	rf_strm_out_busy                    <= strm_out_slv_busy(STRM_REGFILE_BUS);
+	strm_in_busy                        <= rf_strm_in_busy;
+
+	strm_regfile_0: entity work.strm_regfile 
+	generic map ( REGISTER_CNT => REG_CNT )
+	port map (
+		clk                   => usb_clk,
+		rst_n                 => usb_rst_n,
+		debug                 => open,
+
+		-- streaming bus
+		strm_in_data_i        => strm_in_data,
+		strm_in_eop_i         => strm_in_eop,
+		strm_in_sop_i         => strm_in_sop,
+		strm_in_en_i          => strm_in_en,
+		strm_in_busy_o        => rf_strm_in_busy,
+		strm_out_req_o        => rf_strm_out_req,
+		strm_out_busy_i       => rf_strm_out_busy,
+		strm_out_data_o       => rf_strm_out_data,
+		strm_out_eop_o        => rf_strm_out_eop,
+		strm_out_en_o         => rf_strm_out_en,
+
+		-- regfile
+		regfile_i             => regfile,
+		regfile_o             => regfile
+	);
+
+end top;
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/coregen.cgp b/fpga/src/vendor/xilinx/atlys_ddr2/coregen.cgp
new file mode 100644
index 0000000..7e78087
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/create_ddr2.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/create_ddr2.tcl
new file mode 100644
index 0000000..613cb63
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/create_ddr2.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:mig:3.92" "ddr2" "MIG Virtex-6 and Spartan-6" "MIG Virtex-6 and Spartan-6 (xilinx.com:ip:mig:3.92) generated by Project Navigator" xc6slx45-3csg324 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.gise b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.gise
new file mode 100644
index 0000000..e2f75fc
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.gise
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ddr2.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema"/>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1377105194" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377105194">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3822657174530342864" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7467621048142235521" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8481875126579356750" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
+
+</generated_project>
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.ncf b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.ncf
new file mode 100644
index 0000000..b45f564
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.ncf
@@ -0,0 +1,164 @@
+############################################################################
+## 
+##  Xilinx, Inc. 2006            www.xilinx.com 
+##  Sun Jul 28 12:10:25 2013
+##  Generated by MIG Version 3.92
+##  
+############################################################################
+##  File name :       ddr2.ucf
+## 
+##  Details :     Constraints file
+##                    FPGA family:       spartan6
+##                    FPGA:              xc6slx45-csg324
+##                    Speedgrade:        -3
+##                    Design Entry:      VHDL
+##                    Design:            without Test bench
+##                    DCM Used:          Enable
+##                    No.Of Memory Controllers: 1
+##
+############################################################################ 
+############################################################################
+# VCC AUX VOLTAGE 
+############################################################################
+CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
+
+############################################################################
+# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
+# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
+# follows the corresponding GUI option setting. However, DDR3 can operate at higher 
+# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
+# remove/edit the below constraint to avoid false errors.
+############################################################################
+CONFIG MCB_PERFORMANCE= STANDARD;
+
+
+##################################################################################
+# Timing Ignore constraints for paths crossing the clock domain 
+##################################################################################
+NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "c?_pll_lock" TIG;
+INST "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
+
+#Please uncomment the below TIG if used in a design which enables self-refresh mode
+#NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
+     
+NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
+     
+
+############################################################################
+## Memory Controller 3                               
+## Memory Device: DDR2_SDRAM->MT47H64M16XX-25E 
+## Frequency: 333.333 MHz
+## Time Period: 3000 ps
+## Supported Part Numbers: MT47H64M16HR-25E
+############################################################################
+
+############################################################################
+## Clock constraints                                                        
+############################################################################
+NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
+TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3"  3  ns HIGH 50 %;
+############################################################################
+
+############################################################################
+## I/O TERMINATION                                                          
+############################################################################
+NET "mcb3_dram_dq[*]"                                 IN_TERM = NONE;
+NET "mcb3_dram_dqs"                                   IN_TERM = NONE;
+NET "mcb3_dram_dqs_n"                                 IN_TERM = NONE;
+NET "mcb3_dram_udqs"                                  IN_TERM = NONE;
+NET "mcb3_dram_udqs_n"                                IN_TERM = NONE;
+
+############################################################################
+# I/O STANDARDS 
+############################################################################
+
+NET  "mcb3_dram_dq[*]"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_a[*]"                                IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_ba[*]"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_dqs"                                 IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_udqs"                                IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_dqs_n"                               IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_udqs_n"                              IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_ck"                                  IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_ck_n"                                IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_cke"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_ras_n"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_cas_n"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_we_n"                                IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_odt"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_dm"                                  IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_udm"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_rzq"                                      IOSTANDARD = SSTL18_II ;
+NET  "mcb3_zio"                                      IOSTANDARD = SSTL18_II ;
+NET  "c3_sys_clk"                                  IOSTANDARD = LVCMOS25 ;
+NET  "c3_sys_rst_i"                                IOSTANDARD = LVCMOS18 ;
+############################################################################
+# MCB 3
+# Pin Location Constraints for Clock, Masks, Address, and Controls
+############################################################################
+
+NET  "mcb3_dram_a[0]"                            LOC = "J7" ;
+NET  "mcb3_dram_a[10]"                           LOC = "F4" ;
+NET  "mcb3_dram_a[11]"                           LOC = "D3" ;
+NET  "mcb3_dram_a[12]"                           LOC = "G6" ;
+NET  "mcb3_dram_a[1]"                            LOC = "J6" ;
+NET  "mcb3_dram_a[2]"                            LOC = "H5" ;
+NET  "mcb3_dram_a[3]"                            LOC = "L7" ;
+NET  "mcb3_dram_a[4]"                            LOC = "F3" ;
+NET  "mcb3_dram_a[5]"                            LOC = "H4" ;
+NET  "mcb3_dram_a[6]"                            LOC = "H3" ;
+NET  "mcb3_dram_a[7]"                            LOC = "H6" ;
+NET  "mcb3_dram_a[8]"                            LOC = "D2" ;
+NET  "mcb3_dram_a[9]"                            LOC = "D1" ;
+NET  "mcb3_dram_ba[0]"                           LOC = "F2" ;
+NET  "mcb3_dram_ba[1]"                           LOC = "F1" ;
+NET  "mcb3_dram_ba[2]"                           LOC = "E1" ;
+NET  "mcb3_dram_cas_n"                           LOC = "K5" ;
+NET  "mcb3_dram_ck"                              LOC = "G3" ;
+NET  "mcb3_dram_ck_n"                            LOC = "G1" ;
+NET  "mcb3_dram_cke"                             LOC = "H7" ;
+NET  "mcb3_dram_dm"                              LOC = "K3" ;
+NET  "mcb3_dram_dq[0]"                           LOC = "L2" ;
+NET  "mcb3_dram_dq[10]"                          LOC = "N2" ;
+NET  "mcb3_dram_dq[11]"                          LOC = "N1" ;
+NET  "mcb3_dram_dq[12]"                          LOC = "T2" ;
+NET  "mcb3_dram_dq[13]"                          LOC = "T1" ;
+NET  "mcb3_dram_dq[14]"                          LOC = "U2" ;
+NET  "mcb3_dram_dq[15]"                          LOC = "U1" ;
+NET  "mcb3_dram_dq[1]"                           LOC = "L1" ;
+NET  "mcb3_dram_dq[2]"                           LOC = "K2" ;
+NET  "mcb3_dram_dq[3]"                           LOC = "K1" ;
+NET  "mcb3_dram_dq[4]"                           LOC = "H2" ;
+NET  "mcb3_dram_dq[5]"                           LOC = "H1" ;
+NET  "mcb3_dram_dq[6]"                           LOC = "J3" ;
+NET  "mcb3_dram_dq[7]"                           LOC = "J1" ;
+NET  "mcb3_dram_dq[8]"                           LOC = "M3" ;
+NET  "mcb3_dram_dq[9]"                           LOC = "M1" ;
+NET  "mcb3_dram_dqs"                             LOC = "L4" ;
+NET  "mcb3_dram_dqs_n"                           LOC = "L3" ;
+NET  "mcb3_dram_odt"                             LOC = "K6" ;
+NET  "mcb3_dram_ras_n"                           LOC = "L5" ;
+NET  "c3_sys_clk"                                LOC = "R10" ;
+NET  "c3_sys_rst_i"                              LOC = "M8" ;
+NET  "mcb3_dram_udm"                             LOC = "K4" ;
+NET  "mcb3_dram_udqs"                            LOC = "P2" ;
+NET  "mcb3_dram_udqs_n"                          LOC = "P1" ;
+NET  "mcb3_dram_we_n"                            LOC = "E3" ;
+
+##################################################################################
+#RZQ is required for all MCB designs.   Do not move the location #
+#of this pin for ES devices.For production devices, RZQ can be moved to any #
+#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
+#a 2R resistor should be connected between RZQand ground, where R is the desired#
+#input termination value.  Otherwise, RZQ should be left as a no-connect (NC) pin.#
+##################################################################################
+NET  "mcb3_rzq"                                  LOC = "N4" ;
+##################################################################################
+#ZIO is only required for MCB designs using Calibrated Input Termination.#
+#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
+#MCB bank but must be left as a no-connect (NC) pin.#
+##################################################################################
+NET  "mcb3_zio"                                  LOC = "P4" ;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.vho b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.vho
new file mode 100644
index 0000000..7ca2304
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.vho
@@ -0,0 +1,365 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /   Vendor             : Xilinx
+-- \   \   \/    Version            : 3.92
+--  \   \        Application        : MIG
+--  /   /        Filename           : ddr2.vho
+-- /___/   /\    Date Last Modified : $Date: 2011/06/02 07:19:03 $
+-- \   \  /  \   Date Created       : Fri Aug 7 2009
+--  \___\/\___\
+--
+-- Purpose     : Template file containing code that can be used as a model
+--               for instantiating a CORE Generator module in a HDL design.
+-- Revision History:
+--*****************************************************************************
+
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+
+component ddr2
+ generic(
+    C3_P0_MASK_SIZE           : integer := 4;
+    C3_P0_DATA_PORT_SIZE      : integer := 32;
+    C3_P1_MASK_SIZE           : integer := 4;
+    C3_P1_DATA_PORT_SIZE      : integer := 32;
+    C3_MEMCLK_PERIOD          : integer := 3000;
+    C3_RST_ACT_LOW            : integer := 0;
+    C3_INPUT_CLK_TYPE         : string := "SINGLE_ENDED";
+    C3_CALIB_SOFT_IP          : string := "TRUE";
+    C3_SIMULATION             : string := "FALSE";
+    DEBUG_EN                  : integer := 0;
+    C3_MEM_ADDR_ORDER         : string := "BANK_ROW_COLUMN";
+    C3_NUM_DQ_PINS            : integer := 16;
+    C3_MEM_ADDR_WIDTH         : integer := 13;
+    C3_MEM_BANKADDR_WIDTH     : integer := 3
+);
+    port (
+   mcb3_dram_dq                            : inout  std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
+   mcb3_dram_a                             : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+   mcb3_dram_ba                            : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
+   mcb3_dram_ras_n                         : out std_logic;
+   mcb3_dram_cas_n                         : out std_logic;
+   mcb3_dram_we_n                          : out std_logic;
+   mcb3_dram_odt                           : out std_logic;
+   mcb3_dram_cke                           : out std_logic;
+   mcb3_dram_dm                            : out std_logic;
+   mcb3_dram_udqs                          : inout  std_logic;
+   mcb3_dram_udqs_n                        : inout  std_logic;
+   mcb3_rzq                                : inout  std_logic;
+   mcb3_zio                                : inout  std_logic;
+   mcb3_dram_udm                           : out std_logic;
+   c3_sys_clk                              : in  std_logic;
+   c3_sys_rst_i                            : in  std_logic;
+   c3_calib_done                           : out std_logic;
+   c3_clk0                                 : out std_logic;
+   c3_rst0                                 : out std_logic;
+   mcb3_dram_dqs                           : inout  std_logic;
+   mcb3_dram_dqs_n                         : inout  std_logic;
+   mcb3_dram_ck                            : out std_logic;
+   mcb3_dram_ck_n                          : out std_logic;
+   c3_p0_cmd_clk                           : in std_logic;
+   c3_p0_cmd_en                            : in std_logic;
+   c3_p0_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p0_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p0_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p0_cmd_empty                         : out std_logic;
+   c3_p0_cmd_full                          : out std_logic;
+   c3_p0_wr_clk                            : in std_logic;
+   c3_p0_wr_en                             : in std_logic;
+   c3_p0_wr_mask                           : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
+   c3_p0_wr_data                           : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+   c3_p0_wr_full                           : out std_logic;
+   c3_p0_wr_empty                          : out std_logic;
+   c3_p0_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p0_wr_underrun                       : out std_logic;
+   c3_p0_wr_error                          : out std_logic;
+   c3_p0_rd_clk                            : in std_logic;
+   c3_p0_rd_en                             : in std_logic;
+   c3_p0_rd_data                           : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+   c3_p0_rd_full                           : out std_logic;
+   c3_p0_rd_empty                          : out std_logic;
+   c3_p0_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p0_rd_overflow                       : out std_logic;
+   c3_p0_rd_error                          : out std_logic;
+   c3_p1_cmd_clk                           : in std_logic;
+   c3_p1_cmd_en                            : in std_logic;
+   c3_p1_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p1_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p1_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p1_cmd_empty                         : out std_logic;
+   c3_p1_cmd_full                          : out std_logic;
+   c3_p1_wr_clk                            : in std_logic;
+   c3_p1_wr_en                             : in std_logic;
+   c3_p1_wr_mask                           : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
+   c3_p1_wr_data                           : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+   c3_p1_wr_full                           : out std_logic;
+   c3_p1_wr_empty                          : out std_logic;
+   c3_p1_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p1_wr_underrun                       : out std_logic;
+   c3_p1_wr_error                          : out std_logic;
+   c3_p1_rd_clk                            : in std_logic;
+   c3_p1_rd_en                             : in std_logic;
+   c3_p1_rd_data                           : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+   c3_p1_rd_full                           : out std_logic;
+   c3_p1_rd_empty                          : out std_logic;
+   c3_p1_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p1_rd_overflow                       : out std_logic;
+   c3_p1_rd_error                          : out std_logic;
+   c3_p2_cmd_clk                           : in std_logic;
+   c3_p2_cmd_en                            : in std_logic;
+   c3_p2_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p2_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p2_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p2_cmd_empty                         : out std_logic;
+   c3_p2_cmd_full                          : out std_logic;
+   c3_p2_wr_clk                            : in std_logic;
+   c3_p2_wr_en                             : in std_logic;
+   c3_p2_wr_mask                           : in std_logic_vector(3 downto 0);
+   c3_p2_wr_data                           : in std_logic_vector(31 downto 0);
+   c3_p2_wr_full                           : out std_logic;
+   c3_p2_wr_empty                          : out std_logic;
+   c3_p2_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p2_wr_underrun                       : out std_logic;
+   c3_p2_wr_error                          : out std_logic;
+   c3_p2_rd_clk                            : in std_logic;
+   c3_p2_rd_en                             : in std_logic;
+   c3_p2_rd_data                           : out std_logic_vector(31 downto 0);
+   c3_p2_rd_full                           : out std_logic;
+   c3_p2_rd_empty                          : out std_logic;
+   c3_p2_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p2_rd_overflow                       : out std_logic;
+   c3_p2_rd_error                          : out std_logic;
+   c3_p3_cmd_clk                           : in std_logic;
+   c3_p3_cmd_en                            : in std_logic;
+   c3_p3_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p3_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p3_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p3_cmd_empty                         : out std_logic;
+   c3_p3_cmd_full                          : out std_logic;
+   c3_p3_wr_clk                            : in std_logic;
+   c3_p3_wr_en                             : in std_logic;
+   c3_p3_wr_mask                           : in std_logic_vector(3 downto 0);
+   c3_p3_wr_data                           : in std_logic_vector(31 downto 0);
+   c3_p3_wr_full                           : out std_logic;
+   c3_p3_wr_empty                          : out std_logic;
+   c3_p3_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p3_wr_underrun                       : out std_logic;
+   c3_p3_wr_error                          : out std_logic;
+   c3_p3_rd_clk                            : in std_logic;
+   c3_p3_rd_en                             : in std_logic;
+   c3_p3_rd_data                           : out std_logic_vector(31 downto 0);
+   c3_p3_rd_full                           : out std_logic;
+   c3_p3_rd_empty                          : out std_logic;
+   c3_p3_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p3_rd_overflow                       : out std_logic;
+   c3_p3_rd_error                          : out std_logic
+);
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+  u_ddr2 : ddr2
+    generic map (
+    C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
+    C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
+    C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
+    C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
+    C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
+    C3_RST_ACT_LOW => C3_RST_ACT_LOW,
+    C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
+    C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
+    C3_SIMULATION => C3_SIMULATION,
+    DEBUG_EN => DEBUG_EN,
+    C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
+    C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
+    C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
+    C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH
+)
+    port map (
+
+    c3_sys_clk  =>         c3_sys_clk,
+  c3_sys_rst_i    =>       c3_sys_rst_i,                        
+
+  mcb3_dram_dq       =>    mcb3_dram_dq,  
+  mcb3_dram_a        =>    mcb3_dram_a,  
+  mcb3_dram_ba       =>    mcb3_dram_ba,
+  mcb3_dram_ras_n    =>    mcb3_dram_ras_n,                        
+  mcb3_dram_cas_n    =>    mcb3_dram_cas_n,                        
+  mcb3_dram_we_n     =>    mcb3_dram_we_n,                          
+  mcb3_dram_odt    =>      mcb3_dram_odt,
+  mcb3_dram_cke      =>    mcb3_dram_cke,                          
+  mcb3_dram_ck       =>    mcb3_dram_ck,                          
+  mcb3_dram_ck_n     =>    mcb3_dram_ck_n,       
+  mcb3_dram_dqs      =>    mcb3_dram_dqs,                          
+  mcb3_dram_dqs_n  =>      mcb3_dram_dqs_n,
+  mcb3_dram_udqs  =>       mcb3_dram_udqs,    -- for X16 parts           
+  mcb3_dram_udqs_n    =>   mcb3_dram_udqs_n,  -- for X16 parts
+  mcb3_dram_udm  =>        mcb3_dram_udm,     -- for X16 parts
+  mcb3_dram_dm  =>       mcb3_dram_dm,
+    c3_clk0	=>	        c3_clk0,
+  c3_rst0		=>        c3_rst0,
+	
+ 
+  c3_calib_done      =>    c3_calib_done,
+     mcb3_rzq        =>            rzq3,
+	
+     mcb3_zio        =>            zio3,
+	
+     c3_p0_cmd_clk                           =>  c3_p0_cmd_clk,
+   c3_p0_cmd_en                            =>  c3_p0_cmd_en,
+   c3_p0_cmd_instr                         =>  c3_p0_cmd_instr,
+   c3_p0_cmd_bl                            =>  c3_p0_cmd_bl,
+   c3_p0_cmd_byte_addr                     =>  c3_p0_cmd_byte_addr,
+   c3_p0_cmd_empty                         =>  c3_p0_cmd_empty,
+   c3_p0_cmd_full                          =>  c3_p0_cmd_full,
+   c3_p0_wr_clk                            =>  c3_p0_wr_clk,
+   c3_p0_wr_en                             =>  c3_p0_wr_en,
+   c3_p0_wr_mask                           =>  c3_p0_wr_mask,
+   c3_p0_wr_data                           =>  c3_p0_wr_data,
+   c3_p0_wr_full                           =>  c3_p0_wr_full,
+   c3_p0_wr_empty                          =>  c3_p0_wr_empty,
+   c3_p0_wr_count                          =>  c3_p0_wr_count,
+   c3_p0_wr_underrun                       =>  c3_p0_wr_underrun,
+   c3_p0_wr_error                          =>  c3_p0_wr_error,
+   c3_p0_rd_clk                            =>  c3_p0_rd_clk,
+   c3_p0_rd_en                             =>  c3_p0_rd_en,
+   c3_p0_rd_data                           =>  c3_p0_rd_data,
+   c3_p0_rd_full                           =>  c3_p0_rd_full,
+   c3_p0_rd_empty                          =>  c3_p0_rd_empty,
+   c3_p0_rd_count                          =>  c3_p0_rd_count,
+   c3_p0_rd_overflow                       =>  c3_p0_rd_overflow,
+   c3_p0_rd_error                          =>  c3_p0_rd_error,
+   c3_p1_cmd_clk                           =>  c3_p1_cmd_clk,
+   c3_p1_cmd_en                            =>  c3_p1_cmd_en,
+   c3_p1_cmd_instr                         =>  c3_p1_cmd_instr,
+   c3_p1_cmd_bl                            =>  c3_p1_cmd_bl,
+   c3_p1_cmd_byte_addr                     =>  c3_p1_cmd_byte_addr,
+   c3_p1_cmd_empty                         =>  c3_p1_cmd_empty,
+   c3_p1_cmd_full                          =>  c3_p1_cmd_full,
+   c3_p1_wr_clk                            =>  c3_p1_wr_clk,
+   c3_p1_wr_en                             =>  c3_p1_wr_en,
+   c3_p1_wr_mask                           =>  c3_p1_wr_mask,
+   c3_p1_wr_data                           =>  c3_p1_wr_data,
+   c3_p1_wr_full                           =>  c3_p1_wr_full,
+   c3_p1_wr_empty                          =>  c3_p1_wr_empty,
+   c3_p1_wr_count                          =>  c3_p1_wr_count,
+   c3_p1_wr_underrun                       =>  c3_p1_wr_underrun,
+   c3_p1_wr_error                          =>  c3_p1_wr_error,
+   c3_p1_rd_clk                            =>  c3_p1_rd_clk,
+   c3_p1_rd_en                             =>  c3_p1_rd_en,
+   c3_p1_rd_data                           =>  c3_p1_rd_data,
+   c3_p1_rd_full                           =>  c3_p1_rd_full,
+   c3_p1_rd_empty                          =>  c3_p1_rd_empty,
+   c3_p1_rd_count                          =>  c3_p1_rd_count,
+   c3_p1_rd_overflow                       =>  c3_p1_rd_overflow,
+   c3_p1_rd_error                          =>  c3_p1_rd_error,
+   c3_p2_cmd_clk                           =>  c3_p2_cmd_clk,
+   c3_p2_cmd_en                            =>  c3_p2_cmd_en,
+   c3_p2_cmd_instr                         =>  c3_p2_cmd_instr,
+   c3_p2_cmd_bl                            =>  c3_p2_cmd_bl,
+   c3_p2_cmd_byte_addr                     =>  c3_p2_cmd_byte_addr,
+   c3_p2_cmd_empty                         =>  c3_p2_cmd_empty,
+   c3_p2_cmd_full                          =>  c3_p2_cmd_full,
+   c3_p2_wr_clk                            =>  c3_p2_wr_clk,
+   c3_p2_wr_en                             =>  c3_p2_wr_en,
+   c3_p2_wr_mask                           =>  c3_p2_wr_mask,
+   c3_p2_wr_data                           =>  c3_p2_wr_data,
+   c3_p2_wr_full                           =>  c3_p2_wr_full,
+   c3_p2_wr_empty                          =>  c3_p2_wr_empty,
+   c3_p2_wr_count                          =>  c3_p2_wr_count,
+   c3_p2_wr_underrun                       =>  c3_p2_wr_underrun,
+   c3_p2_wr_error                          =>  c3_p2_wr_error,
+   c3_p2_rd_clk                            =>  c3_p2_rd_clk,
+   c3_p2_rd_en                             =>  c3_p2_rd_en,
+   c3_p2_rd_data                           =>  c3_p2_rd_data,
+   c3_p2_rd_full                           =>  c3_p2_rd_full,
+   c3_p2_rd_empty                          =>  c3_p2_rd_empty,
+   c3_p2_rd_count                          =>  c3_p2_rd_count,
+   c3_p2_rd_overflow                       =>  c3_p2_rd_overflow,
+   c3_p2_rd_error                          =>  c3_p2_rd_error,
+   c3_p3_cmd_clk                           =>  c3_p3_cmd_clk,
+   c3_p3_cmd_en                            =>  c3_p3_cmd_en,
+   c3_p3_cmd_instr                         =>  c3_p3_cmd_instr,
+   c3_p3_cmd_bl                            =>  c3_p3_cmd_bl,
+   c3_p3_cmd_byte_addr                     =>  c3_p3_cmd_byte_addr,
+   c3_p3_cmd_empty                         =>  c3_p3_cmd_empty,
+   c3_p3_cmd_full                          =>  c3_p3_cmd_full,
+   c3_p3_wr_clk                            =>  c3_p3_wr_clk,
+   c3_p3_wr_en                             =>  c3_p3_wr_en,
+   c3_p3_wr_mask                           =>  c3_p3_wr_mask,
+   c3_p3_wr_data                           =>  c3_p3_wr_data,
+   c3_p3_wr_full                           =>  c3_p3_wr_full,
+   c3_p3_wr_empty                          =>  c3_p3_wr_empty,
+   c3_p3_wr_count                          =>  c3_p3_wr_count,
+   c3_p3_wr_underrun                       =>  c3_p3_wr_underrun,
+   c3_p3_wr_error                          =>  c3_p3_wr_error,
+   c3_p3_rd_clk                            =>  c3_p3_rd_clk,
+   c3_p3_rd_en                             =>  c3_p3_rd_en,
+   c3_p3_rd_data                           =>  c3_p3_rd_data,
+   c3_p3_rd_full                           =>  c3_p3_rd_full,
+   c3_p3_rd_empty                          =>  c3_p3_rd_empty,
+   c3_p3_rd_count                          =>  c3_p3_rd_count,
+   c3_p3_rd_overflow                       =>  c3_p3_rd_overflow,
+   c3_p3_rd_error                          =>  c3_p3_rd_error
+);
+
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file ddr2.vhd when simulating
+-- the core, ddr2. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xco b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xco
new file mode 100644
index 0000000..f0e69a4
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xco
@@ -0,0 +1,49 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Sun Jul 28 10:10:27 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:mig:3.92
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92
+# END Select
+# BEGIN Parameters
+CSET component_name=ddr2
+CSET xml_input_file=./ddr2/user_design/mig.prj
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2013-06-08T23:00:50Z
+# END Extra information
+GENERATE
+# CRC: ede738a9
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xise b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xise
new file mode 100644
index 0000000..0ef39db
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xise
@@ -0,0 +1,123 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="ddr2/user_design/rtl/ddr2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="ddr2/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="ddr2/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="ddr2/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="ddr2/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="ddr2/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="ddr2/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
+    </file>
+    <file xil_pn:name="ddr2/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
+    </file>
+    <file xil_pn:name="ddr2/user_design/par/ddr2.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ddr2|arc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="ddr2/user_design/rtl/ddr2.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ddr2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="ddr2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-07-28T12:10:31" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1E4028521BF14C180A8024C9024AB5B9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings>
+    <binding xil_pn:location="/ddr2" xil_pn:name="ddr2/user_design/par/ddr2.ucf"/>
+  </bindings>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/docs/ug388.pdf b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/docs/ug388.pdf
new file mode 100755
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diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/docs/ug416.pdf b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/docs/ug416.pdf
new file mode 100755
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HK3)A67(NYt

literal 0
HcmV?d00001

diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/datasheet.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/datasheet.txt
new file mode 100644
index 0000000..b80460d
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/datasheet.txt
@@ -0,0 +1,72 @@
+
+
+CORE Generator Options:
+   Target Device              : xc6slx45-csg324
+   Speed Grade                : -3
+   HDL                        : vhdl
+   Synthesis Tool             : Foundation_ISE
+
+MIG Output Options:
+   Component Name             : ddr2
+   No of Controllers          : 1
+   Hardware Test Bench           : enabled
+
+    
+/*******************************************************/
+/*                  Controller 3                       */
+/*******************************************************/
+Controller Options : 
+   Memory                  : DDR2_SDRAM
+   Interface               : NATIVE
+   Design Clock Frequency  : 3000 ps (333.33 MHz)
+   Memory Type             : Components
+   Memory Part             : MT47H64M16XX-25E
+   Equivalent Part(s)      : MT47H64M16HR-25E
+   Row Address             : 13
+   Column Address          : 10
+   Bank Address            : 3
+   Data Mask               : enabled
+
+Memory Options :
+   Burst Length                       : 4(010)
+   CAS Latency                        : 5
+   DQS# Enable                        : Enable
+   DLL Enable                         : Enable-Normal
+   OCD Operation                      : OCD Exit
+   Output Drive Strength              : Fullstrength
+   Outputs                            : Enable
+   Additive Latency (AL)              : 0
+   RDQS Enable                        : Disable
+   RTT (nominal) - ODT                : 50ohms       
+   High Temparature Self Refresh Rate : Disable
+
+User Interface Parameters :
+   Configuration Type     : Four 32-bit bi-directional ports
+   Ports Selected         : Port0, Port1, Port2, Port3
+   Memory Address Mapping : BANK_ROW_COLUMN
+
+   Arbitration Algorithm  : Round Robin
+
+   Arbitration            : 
+      Time Slot0 : 0123
+      Time Slot1 : 1230
+      Time Slot2 : 2301
+      Time Slot3 : 3012
+      Time Slot4 : 0123
+      Time Slot5 : 1230
+      Time Slot6 : 2301
+      Time Slot7 : 3012
+      Time Slot8 : 0123
+      Time Slot9 : 1230
+      Time Slot10: 2301
+      Time Slot11: 3012
+
+FPGA Options :
+   Class for Address and Control       : II
+   Class for Data                      : II
+   Memory Interface Pin Termination    : CALIB_TERM
+   DQ/DQS                              : 25 Ohms
+   Bypass Calibration                  : enabled
+   Debug Signals for Memory Controller : Disable
+   Input Clock Type                    : Single-Ended 
+    
\ No newline at end of file
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/create_ise.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/create_ise.sh
new file mode 100755
index 0000000..d71e95f
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/create_ise.sh
@@ -0,0 +1,72 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+#   ____  ____
+#  /   /\/   /
+# /___/  \  /    Vendor                : Xilinx
+# \   \   \/     Version               : 3.92
+#  \   \         Application           : MIG
+#  /   /         Filename              : create_ise.bat
+# /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+# \   \  /  \    Date Created          : Fri Feb 06 2009
+#  \___\/\___\
+#
+# Device            : Spartan-6
+# Design Name       : DDR/DDR2/DDR3/LPDDR
+# Purpose           : Batch file to run PAR through ISE
+# Reference         :
+# Revision History  :
+# ****************************************************************************
+
+./rem_files.sh
+
+
+
+
+xtclsh set_ise_prop.tcl
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/example_top.ucf b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/example_top.ucf
new file mode 100644
index 0000000..b344cc7
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/example_top.ucf
@@ -0,0 +1,172 @@
+############################################################################
+## 
+##  Xilinx, Inc. 2006            www.xilinx.com 
+##  Sun Jul 28 12:10:23 2013
+##  Generated by MIG Version 3.92
+##  
+############################################################################
+##  File name :       example_top.ucf
+## 
+##  Details :     Constraints file
+##                    FPGA family:       spartan6
+##                    FPGA:              xc6slx45-csg324
+##                    Speedgrade:        -3
+##                    Design Entry:      VHDL
+##                    Design:            with Test bench
+##                    DCM Used:          Enable
+##                    No.Of Memory Controllers: 1
+##
+############################################################################ 
+############################################################################
+# VCC AUX VOLTAGE 
+############################################################################
+CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
+
+############################################################################
+# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
+# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
+# follows the corresponding GUI option setting. However, DDR3 can operate at higher 
+# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
+# remove/edit the below constraint to avoid false errors.
+############################################################################
+CONFIG MCB_PERFORMANCE= STANDARD;
+
+
+##################################################################################
+# Timing Ignore constraints for paths crossing the clock domain 
+##################################################################################
+NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "c?_pll_lock" TIG;
+INST "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
+
+#Please uncomment the below TIG if used in a design which enables self-refresh mode
+#NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
+     
+NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
+     
+
+############################################################################
+## Memory Controller 3                               
+## Memory Device: DDR2_SDRAM->MT47H64M16XX-25E 
+## Frequency: 333.333 MHz
+## Time Period: 3000 ps
+## Supported Part Numbers: MT47H64M16HR-25E
+############################################################################
+
+############################################################################
+## Clock constraints                                                        
+############################################################################
+NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
+TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3"  3  ns HIGH 50 %;
+############################################################################
+
+############################################################################
+## I/O TERMINATION                                                          
+############################################################################
+NET "mcb3_dram_dq[*]"                                 IN_TERM = NONE;
+NET "mcb3_dram_dqs"                                   IN_TERM = NONE;
+NET "mcb3_dram_dqs_n"                                 IN_TERM = NONE;
+NET "mcb3_dram_udqs"                                  IN_TERM = NONE;
+NET "mcb3_dram_udqs_n"                                IN_TERM = NONE;
+
+############################################################################
+# Status Signals 
+############################################################################
+
+NET  "error"                                    IOSTANDARD = LVCMOS18 ;
+NET  "calib_done"                               IOSTANDARD = LVCMOS18 ;
+NET  "calib_done"                               LOC = "B2" ;
+NET  "error"                                    LOC = "A2" ;
+
+############################################################################
+# I/O STANDARDS 
+############################################################################
+
+NET  "mcb3_dram_dq[*]"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_a[*]"                                IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_ba[*]"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_dqs"                                 IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_udqs"                                IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_dqs_n"                               IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_udqs_n"                              IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_ck"                                  IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_ck_n"                                IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_cke"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_ras_n"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_cas_n"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_we_n"                                IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_odt"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_dm"                                  IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_udm"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_rzq"                                      IOSTANDARD = SSTL18_II ;
+NET  "mcb3_zio"                                      IOSTANDARD = SSTL18_II ;
+NET  "c3_sys_clk"                                  IOSTANDARD = LVCMOS25 ;
+NET  "c3_sys_rst_i"                                IOSTANDARD = LVCMOS18 ;
+############################################################################
+# MCB 3
+# Pin Location Constraints for Clock, Masks, Address, and Controls
+############################################################################
+
+NET  "mcb3_dram_a[0]"                            LOC = "J7" ;
+NET  "mcb3_dram_a[10]"                           LOC = "F4" ;
+NET  "mcb3_dram_a[11]"                           LOC = "D3" ;
+NET  "mcb3_dram_a[12]"                           LOC = "G6" ;
+NET  "mcb3_dram_a[1]"                            LOC = "J6" ;
+NET  "mcb3_dram_a[2]"                            LOC = "H5" ;
+NET  "mcb3_dram_a[3]"                            LOC = "L7" ;
+NET  "mcb3_dram_a[4]"                            LOC = "F3" ;
+NET  "mcb3_dram_a[5]"                            LOC = "H4" ;
+NET  "mcb3_dram_a[6]"                            LOC = "H3" ;
+NET  "mcb3_dram_a[7]"                            LOC = "H6" ;
+NET  "mcb3_dram_a[8]"                            LOC = "D2" ;
+NET  "mcb3_dram_a[9]"                            LOC = "D1" ;
+NET  "mcb3_dram_ba[0]"                           LOC = "F2" ;
+NET  "mcb3_dram_ba[1]"                           LOC = "F1" ;
+NET  "mcb3_dram_ba[2]"                           LOC = "E1" ;
+NET  "mcb3_dram_cas_n"                           LOC = "K5" ;
+NET  "mcb3_dram_ck"                              LOC = "G3" ;
+NET  "mcb3_dram_ck_n"                            LOC = "G1" ;
+NET  "mcb3_dram_cke"                             LOC = "H7" ;
+NET  "mcb3_dram_dm"                              LOC = "K3" ;
+NET  "mcb3_dram_dq[0]"                           LOC = "L2" ;
+NET  "mcb3_dram_dq[10]"                          LOC = "N2" ;
+NET  "mcb3_dram_dq[11]"                          LOC = "N1" ;
+NET  "mcb3_dram_dq[12]"                          LOC = "T2" ;
+NET  "mcb3_dram_dq[13]"                          LOC = "T1" ;
+NET  "mcb3_dram_dq[14]"                          LOC = "U2" ;
+NET  "mcb3_dram_dq[15]"                          LOC = "U1" ;
+NET  "mcb3_dram_dq[1]"                           LOC = "L1" ;
+NET  "mcb3_dram_dq[2]"                           LOC = "K2" ;
+NET  "mcb3_dram_dq[3]"                           LOC = "K1" ;
+NET  "mcb3_dram_dq[4]"                           LOC = "H2" ;
+NET  "mcb3_dram_dq[5]"                           LOC = "H1" ;
+NET  "mcb3_dram_dq[6]"                           LOC = "J3" ;
+NET  "mcb3_dram_dq[7]"                           LOC = "J1" ;
+NET  "mcb3_dram_dq[8]"                           LOC = "M3" ;
+NET  "mcb3_dram_dq[9]"                           LOC = "M1" ;
+NET  "mcb3_dram_dqs"                             LOC = "L4" ;
+NET  "mcb3_dram_dqs_n"                           LOC = "L3" ;
+NET  "mcb3_dram_odt"                             LOC = "K6" ;
+NET  "mcb3_dram_ras_n"                           LOC = "L5" ;
+NET  "c3_sys_clk"                                LOC = "R10" ;
+NET  "c3_sys_rst_i"                              LOC = "M8" ;
+NET  "mcb3_dram_udm"                             LOC = "K4" ;
+NET  "mcb3_dram_udqs"                            LOC = "P2" ;
+NET  "mcb3_dram_udqs_n"                          LOC = "P1" ;
+NET  "mcb3_dram_we_n"                            LOC = "E3" ;
+
+##################################################################################
+#RZQ is required for all MCB designs.   Do not move the location #
+#of this pin for ES devices.For production devices, RZQ can be moved to any #
+#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
+#a 2R resistor should be connected between RZQand ground, where R is the desired#
+#input termination value.  Otherwise, RZQ should be left as a no-connect (NC) pin.#
+##################################################################################
+NET  "mcb3_rzq"                                  LOC = "N4" ;
+##################################################################################
+#ZIO is only required for MCB designs using Calibrated Input Termination.#
+#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
+#MCB bank but must be left as a no-connect (NC) pin.#
+##################################################################################
+NET  "mcb3_zio"                                  LOC = "P4" ;
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/icon_coregen.xco b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/icon_coregen.xco
new file mode 100644
index 0000000..ac21f7c
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/icon_coregen.xco
@@ -0,0 +1,48 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.1
+# Date: Wed Mar 11 07:09:11 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -3
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
+# END Select
+# BEGIN Parameters
+CSET component_name=icon
+CSET enable_jtag_bufg=true
+CSET number_control_ports=2
+CSET use_ext_bscan=false
+CSET use_softbscan=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+GENERATE
+# CRC: 7da1f376
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ila_coregen.xco b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ila_coregen.xco
new file mode 100644
index 0000000..888c551
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ila_coregen.xco
@@ -0,0 +1,131 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.1
+# Date: Wed Mar 11 06:55:40 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -3
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
+# END Select
+# BEGIN Parameters
+CSET component_name=ila
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=256
+CSET data_same_as_trigger=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET exclude_from_data_storage_1=true
+CSET exclude_from_data_storage_10=true
+CSET exclude_from_data_storage_11=true
+CSET exclude_from_data_storage_12=true
+CSET exclude_from_data_storage_13=true
+CSET exclude_from_data_storage_14=true
+CSET exclude_from_data_storage_15=true
+CSET exclude_from_data_storage_16=true
+CSET exclude_from_data_storage_2=true
+CSET exclude_from_data_storage_3=true
+CSET exclude_from_data_storage_4=true
+CSET exclude_from_data_storage_5=true
+CSET exclude_from_data_storage_6=true
+CSET exclude_from_data_storage_7=true
+CSET exclude_from_data_storage_8=true
+CSET exclude_from_data_storage_9=true
+CSET match_type_1=basic_with_edges
+CSET match_type_10=basic
+CSET match_type_11=basic
+CSET match_type_12=basic
+CSET match_type_13=basic
+CSET match_type_14=basic
+CSET match_type_15=basic
+CSET match_type_16=basic
+CSET match_type_2=basic
+CSET match_type_3=basic
+CSET match_type_4=basic
+CSET match_type_5=basic
+CSET match_type_6=basic
+CSET match_type_7=basic
+CSET match_type_8=basic
+CSET match_type_9=basic
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=1024
+CSET sample_on=Rising
+CSET trigger_port_width_1=2
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=true
+# END Parameters
+GENERATE
+# CRC: eff89f81
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ise_flow.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ise_flow.sh
new file mode 100755
index 0000000..98494b7
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ise_flow.sh
@@ -0,0 +1,86 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+#   ____  ____
+#  /   /\/   /
+# /___/  \  /    Vendor                : Xilinx
+# \   \   \/     Version               : 3.92
+#  \   \         Application           : MIG
+#  /   /         Filename              : ise_flow.bat
+# /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+# \   \  /  \    Date Created          : Fri Feb 06 2009
+#  \___\/\___\
+#
+# Device            : Spartan-6
+# Design Name       : DDR/DDR2/DDR3/LPDDR
+# Purpose           : Batch file to run PAR through ISE batch mode
+# Reference         :
+# Revision History  :
+# ****************************************************************************
+
+./rem_files.sh
+
+
+
+
+echo Synthesis Tool: XST
+
+mkdir "../synth/__projnav" > ise_flow_results.txt
+mkdir "../synth/xst" >> ise_flow_results.txt
+mkdir "../synth/xst/work" >> ise_flow_results.txt
+
+xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt
+ngdbuild -intstyle ise -dd ../synth/_ngo -uc example_top.ucf -p xc6slx45csg324-3 example_top.ngc example_top.ngd >> ise_flow_results.txt
+
+map -intstyle ise -detail -w -pr off -c 100 -o example_top_map.ncd example_top.ngd example_top.pcf >> ise_flow_results.txt
+par -w -intstyle ise -ol std example_top_map.ncd example_top.ncd example_top.pcf >> ise_flow_results.txt
+trce -e 100 example_top.ncd example_top.pcf >> ise_flow_results.txt
+bitgen -intstyle ise -f mem_interface_top.ut example_top.ncd >> ise_flow_results.txt
+
+echo done!
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ise_run.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ise_run.txt
new file mode 100644
index 0000000..0d4338e
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/ise_run.txt
@@ -0,0 +1,58 @@
+set -tmpdir ../synth/__projnav 
+set -xsthdpdir ../synth/xst
+run 
+#Source Parameters
+-ifn ../synth/example_top.prj
+-ifmt mixed
+-iuc No
+#Target Parameters
+-ofn example_top
+-ofmt NGC
+-p xc6slx45-3csg324
+#AXI_ENABLE definition is not required for NATIVE interface
+#Source Options
+-top example_top
+-fsm_extract Yes 
+-fsm_encoding one-hot
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-rom_style Auto
+-shreg_extract Yes
+-resource_sharing Yes
+-async_to_sync no
+-mult_style auto
+-register_balancing No
+#Target Options
+-iobuf Yes
+#Max fanout value shouldn't be set below 64 for MCB design
+-max_fanout 500
+-bufg 16 
+-register_duplication yes
+-optimize_primitives No
+-use_clock_enable Auto 
+-use_sync_set Auto   
+-use_sync_reset Auto 
+-iob auto
+-equivalent_register_removal yes
+#General Options
+-opt_mode Speed
+-opt_level 1
+-lso ../synth/example_top.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt allclocknets
+-read_cores Yes
+-write_timing_constraints No
+-cross_clock_analysis No
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-auto_bram_packing No
+-slice_utilization_ratio_maxmargin 5
+quit
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/makeproj.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/makeproj.sh
new file mode 100755
index 0000000..2f5c9f7
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/makeproj.sh
@@ -0,0 +1,2 @@
+NEWPROJECT .
+SETPROJECT .
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/mem_interface_top.ut b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/mem_interface_top.ut
new file mode 100644
index 0000000..bc59a01
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/mem_interface_top.ut
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullNone
+-g UserID:0xFFFFFFFF
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g ConfigRate:6
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/readme.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/readme.txt
new file mode 100644
index 0000000..97a4e9d
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/readme.txt
@@ -0,0 +1,146 @@
+::****************************************************************************
+:: (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+::
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+::
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+::
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+::
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+::
+::****************************************************************************
+::   ____  ____
+::  /   /\/   /
+:: /___/  \  /    Vendor                : Xilinx
+:: \   \   \/     Version               : 3.92
+::  \   \         Application           : MIG
+::  /   /         Filename              : readme.txt
+:: /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+:: \   \  /  \    Date Created          : Fri Feb 06 2009
+::  \___\/\___\
+::
+:: Device            : Spartan-6
+:: Design Name       : DDR/DDR2/DDR3/LPDDR
+:: Purpose           : Information about par folder
+:: Reference         :
+:: Revision History  :
+::****************************************************************************
+
+This folder has the batch files to synthesize using XST or Synplify Pro and
+implement the design either in "Command Line Mode" or in "GUI Mode".
+
+Steps to run the design using the ise_flow (batch mode):
+
+1. Executing the "ise_flow.bat" file synthesizes the design using XST or
+   Synplify Pro and does implement the design.
+     a. First it removes the XST/Synplify Pro report files, implementation
+        files, supporting scripts, the generated chipscope designs (if 
+        enabled) and the ISE project files (if exist any on previous runs)
+     b. Synthesizes the design either with XST or Synplicity
+     c. Implements the design with ISE.   
+
+2. After the design is run, it creates ise_flow_results.txt file that will have
+   the ISE log information.
+
+Steps to run the design using the create_ise (GUI mode - for XST cases only):
+
+1. This file will appear for XST cases only.
+
+2. On executing the "create_ise.bat" file creates "test.xise" project file
+   and set all the properties of the design selected.
+
+3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
+
+4. In Linux operating systems, test.xise project can be invoked by executing the command
+   'ise test.xise' from the terminal.
+
+Other files in PAR folder :
+
+* "example_top.ucf" file is the constraint file for the design.
+  It has clock constraints, location constraints and IO standards.
+
+* "mem_interface_top.ut" file has the options for the Configuration file
+  generation i.e. the "example_top.bit" file to run in batch mode.
+
+* "rem_files.bat" file has all the ISE/Synplify Pro generated report files, 
+  implementation files, supporting scripts, the generated chipscope designs
+  (if enabled) and the ISE project files.
+
+* "set_ise_prop.tcl" file has all the properties that are to be
+  set in GUI mode.
+
+* "ise_run.txt" file has synthesis options for the XST tool.
+  This file is used for batch mode.
+
+* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to 
+   generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the 
+   EDIF/NGC files, you must execute the following commands before starting 
+   synthesis and PAR.
+
+           coregen -b ila_coregen.xco
+           coregen -b icon_coregen.xco
+           coregen -b vio_coregen.xco
+
+Note : When you generate the design using "Debug Signals for Memory Controller"
+       option Enable, the above mentioned ChipScope coregen commands are printed
+       into ise_flow.bat and create_ise.bat files. The example_top rtl file
+       will have the design debug signals portmapped to vio and icon
+       ChipScope modules.
+
+* At the start of a Chip Scope Analyzer project, all of the signals in
+  every core have generic names. "example_top.cdc" is a file that contains
+  all the signal names of all cores. Upon importing this file, signal names are
+  renamed to the specified names in "example_top.cdc" file. This file will work
+  for the generated designs from MIG. If any of the design parameter values
+  are changed after generating the design, this file will not work.
+  For Multiple Controller designs, signal names provided in CDC file are of 
+  the controller that is enabled for Debug in the GUI.
+
+synth folder:
+
+1. mem_interface_top_synp.sdc
+2. script_synp.tcl
+3. example_top.prj
+4. example_top.lso
+
+   mem_interface_top_synp.sdc and script_synp.tcl files are being used by
+   Synplify Pro and example_top.prj and example_top.lso are being used by XST.
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/rem_files.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/rem_files.sh
new file mode 100755
index 0000000..a7e5dec
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/rem_files.sh
@@ -0,0 +1,169 @@
+##!/bin/csh -f
+##****************************************************************************
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+##****************************************************************************
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor                : Xilinx
+## \   \   \/     Version               : 3.92
+##  \   \         Application           : MIG
+##  /   /         Filename              : rem_files.bat
+## /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+## \   \  /  \    Date Created          : Fri Feb 06 2009
+##  \___\/\___\
+##
+## Device            : Spartan-6
+## Design Name       : DDR/DDR2/DDR3/LPDDR
+## Purpose           : Batch file to remove files generated from ISE
+## Reference         :
+## Revision History  :
+##****************************************************************************
+
+rm -rf "../synth/__projnav" 
+rm -rf "../synth/xst" 
+rm -rf "../synth/_ngo" 
+
+rm -rf tmp 
+rm -rf _xmsgs
+rm -rf ila_xdb 
+rm -rf icon_xdb
+rm -rf vio_xdb
+
+rm -rf xlnx_auto_0_xdb 
+
+rm -rf vio_xmdf.tcl
+rm -rf vio_readme.txt
+rm -rf vio_flist.txt
+rm -rf vio.xise del
+rm -rf vio.xco del
+rm -rf vio.ngc del
+rm -rf vio.ise del
+rm -rf vio.gise del
+rm -rf vio.cdc del
+
+rm -rf coregen.cgp
+rm -rf coregen.cgc
+rm -rf coregen.log 
+rm -rf ila.cdc 
+rm -rf ila.gise 
+rm -rf ila.ise 
+rm -rf ila.ngc 
+rm -rf ila.xco 
+rm -rf ila.xise 
+rm -rf ila_flist.txt 
+rm -rf ila_readme.txt 
+rm -rf ila_xmdf.tcl 
+
+rm -rf icon.asy
+rm -rf icon.gise
+rm -rf icon.ise
+rm -rf icon.ncf
+rm -rf icon.ngc
+rm -rf icon.xco
+rm -rf icon.xise
+rm -rf icon_flist.txt
+rm -rf icon_readme.txt
+rm -rf icon_xmdf.tcl
+
+rm -rf ise_flow_results.txt 
+rm -rf example_top_vhdl.prj 
+rm -rf mem_interface_top.syr 
+rm -rf example_top.ngc 
+rm -rf example_top.ngr 
+rm -rf example_top_xst.xrpt 
+rm -rf example_top.bld 
+rm -rf example_top.ngd 
+rm -rf example_top_ngdbuild.xrpt 
+rm -rf example_top_map.map 
+rm -rf example_top_map.mrp 
+rm -rf example_top_map.ngm 
+rm -rf example_top.pcf 
+rm -rf example_top_map.ncd 
+rm -rf example_top_map.xrpt 
+rm -rf example_top_summary.xml 
+rm -rf example_top_usage.xml 
+rm -rf example_top.ncd 
+rm -rf example_top.par 
+rm -rf example_top.xpi 
+rm -rf example_top.ptwx 
+rm -rf example_top.pad 
+rm -rf example_top.unroutes 
+rm -rf example_top_pad.csv 
+rm -rf example_top_pad.txt 
+rm -rf example_top_par.xrpt 
+rm -rf example_top.twx 
+rm -rf example_top.bgn 
+rm -rf example_top.twr 
+rm -rf example_top.drc 
+rm -rf example_top_bitgen.xwbt
+rm -rf example_top.bit 
+
+# Files and folders generated by create ise
+rm -rf test_xdb
+rm -rf _xmsgs
+rm -rf test.gise
+rm -rf test.xise
+rm -rf test.xise
+
+# Files and folders generated by ISE through GUI mode
+rm -rf _ngo
+rm -rf xst
+rm -rf example_top.lso 
+rm -rf example_top.prj 
+rm -rf example_top.xst 
+rm -rf example_top.stx 
+rm -rf example_top_prev_built.ngd 
+rm -rf test.ntrc_log 
+rm -rf example_top_guide.ncd 
+rm -rf example_top.cmd_log 
+rm -rf example_top_summary.html 
+rm -rf example_top.ut 
+rm -rf par_usage_statistics.html
+rm -rf usage_statistics_webtalk.html
+rm -rf webtalk.log
+rm -rf device_usage_statistics.html 
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/set_ise_prop.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/set_ise_prop.tcl
new file mode 100644
index 0000000..f602216
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/set_ise_prop.tcl
@@ -0,0 +1,106 @@
+project new test.xise
+
+project set "Device Family" "spartan6"
+
+project set "Device" "xc6slx45"
+
+project set "Package" "csg324"
+
+project set "Speed Grade" "-3"
+
+project set "Synthesis Tool" "XST (VHDL/Verilog)"
+
+project set "Simulator" "ISim (VHDL/Verilog)"
+
+xfile add "../rtl/example_top.vhd"
+xfile add "../rtl/iodrp_controller.vhd"
+xfile add "../rtl/iodrp_mcb_controller.vhd"
+xfile add "../rtl/mcb_raw_wrapper.vhd"
+xfile add "../rtl/mcb_soft_calibration.vhd"
+xfile add "../rtl/mcb_soft_calibration_top.vhd"
+xfile add "../rtl/memc3_infrastructure.vhd"
+xfile add "../rtl/memc3_tb_top.vhd"
+xfile add "../rtl/memc3_wrapper.vhd"
+xfile add "../rtl/traffic_gen/afifo.vhd"
+xfile add "../rtl/traffic_gen/cmd_gen.vhd"
+xfile add "../rtl/traffic_gen/cmd_prbs_gen.vhd"
+xfile add "../rtl/traffic_gen/data_prbs_gen.vhd"
+xfile add "../rtl/traffic_gen/init_mem_pattern_ctr.vhd"
+xfile add "../rtl/traffic_gen/mcb_flow_control.vhd"
+xfile add "../rtl/traffic_gen/mcb_traffic_gen.vhd"
+xfile add "../rtl/traffic_gen/rd_data_gen.vhd"
+xfile add "../rtl/traffic_gen/read_data_path.vhd"
+xfile add "../rtl/traffic_gen/read_posted_fifo.vhd"
+xfile add "../rtl/traffic_gen/sp6_data_gen.vhd"
+xfile add "../rtl/traffic_gen/tg_status.vhd"
+xfile add "../rtl/traffic_gen/v6_data_gen.vhd"
+xfile add "../rtl/traffic_gen/wr_data_gen.vhd"
+xfile add "../rtl/traffic_gen/write_data_path.vhd"
+
+xfile add "example_top.ucf"
+
+
+project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
+project set "Safe Implementation" "No" -process "Synthesize - XST"
+project set "FSM Style" "LUT" -process "Synthesize - XST"
+project set "RAM Extraction" "True" -process "Synthesize - XST"
+project set "RAM Style" "Auto" -process "Synthesize - XST"
+project set "ROM Extraction" "True" -process "Synthesize - XST"
+project set "ROM Style" "Auto" -process "Synthesize - XST"
+project set "Resource Sharing" "True" -process "Synthesize - XST"
+project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST"
+project set "Register Balancing" "No" -process "Synthesize - XST"
+project set "Add I/O Buffers" "True" -process "Synthesize - XST"
+project set "Max Fanout" "500" -process "Synthesize - XST"
+project set "Number of Clock Buffers" "8" -process "Synthesize - XST"
+project set "Register Duplication" "True" -process "Synthesize - XST"
+project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST"
+project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
+project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
+project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
+project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
+project set "Equivalent Register Removal" "True" -process "Synthesize - XST"
+project set "Optimization Goal" "Speed" -process "Synthesize - XST"
+project set "Optimization Effort" "Normal" -process "Synthesize - XST"
+project set "Library Search Order" "../synth/example_top.lso" -process "Synthesize - XST"
+project set "Keep Hierarchy" "Soft" -process "Synthesize - XST"
+project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
+project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
+project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
+project set "Read Cores" "True" -process "Synthesize - XST"
+project set "Write Timing Constraints" "False" -process "Synthesize - XST"
+project set "Cross Clock Analysis" "False" -process "Synthesize - XST"
+project set "Hierarchy Separator" "/" -process "Synthesize - XST"
+project set "Bus Delimiter" "<>" -process "Synthesize - XST"
+project set "Case" "Maintain" -process "Synthesize - XST"
+project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
+project set "Automatic BRAM Packing" "False" -process "Synthesize - XST"
+project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map
+
+project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
+
+project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing"
+
+project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File"
+project set "Create Binary Configuration File" "False" -process "Generate Programming File"
+project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File"
+project set "Configuration Rate" "6" -process "Generate Programming File"
+project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
+project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
+project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
+project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
+project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
+project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
+project set "Unused IOB Pins" "Float" -process "Generate Programming File"
+project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
+project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
+project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
+project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
+project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
+project set "Enable Internal Done Pipe" "False" -process "Generate Programming File"
+project set "Drive Done Pin High" "False" -process "Generate Programming File"
+project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
+
+project close
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/vio_coregen.xco b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/vio_coregen.xco
new file mode 100644
index 0000000..ec8adfb
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/vio_coregen.xco
@@ -0,0 +1,51 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.2
+# Date: Fri Jun 12 05:42:56 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped  
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -3
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
+# END Select
+# BEGIN Parameters
+CSET asynchronous_input_port_width=8
+CSET asynchronous_output_port_width=7
+CSET component_name=vio
+CSET enable_asynchronous_input_port=false
+CSET enable_asynchronous_output_port=true
+CSET enable_synchronous_input_port=false
+CSET enable_synchronous_output_port=false
+CSET invert_clock_input=false
+CSET synchronous_input_port_width=8
+CSET synchronous_output_port_width=8
+# END Parameters
+GENERATE
+# CRC: 66fe39ed
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/example_top.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/example_top.vhd
new file mode 100644
index 0000000..58b3e95
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/example_top.vhd
@@ -0,0 +1,1059 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : 3.92
+--  \   \         Application        : MIG
+--  /   /         Filename           : example_top.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:56 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+--Device           : Spartan-6
+--Design Name      : DDR/DDR2/DDR3/LPDDR 
+--Purpose          : This is the design top level. which instantiates top wrapper,
+--                   test bench top and infrastructure modules.
+--Reference        :
+--Revision History :
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+entity example_top is
+generic
+  (
+            C3_P0_MASK_SIZE           : integer := 4;
+          C3_P0_DATA_PORT_SIZE      : integer := 32;
+          C3_P1_MASK_SIZE           : integer := 4;
+          C3_P1_DATA_PORT_SIZE      : integer := 32;
+    C3_MEMCLK_PERIOD        : integer := 3000; 
+                                       -- Memory data transfer clock period.
+    C3_RST_ACT_LOW          : integer := 0; 
+                                       -- # = 1 for active low reset,
+                                       -- # = 0 for active high reset.
+    C3_INPUT_CLK_TYPE       : string := "SINGLE_ENDED"; 
+                                       -- input clock type DIFFERENTIAL or SINGLE_ENDED.
+    C3_CALIB_SOFT_IP        : string := "TRUE"; 
+                                       -- # = TRUE, Enables the soft calibration logic,
+                                       -- # = FALSE, Disables the soft calibration logic.
+    C3_SIMULATION           : string := "FALSE"; 
+                                       -- # = TRUE, Simulating the design. Useful to reduce the simulation time,
+                                       -- # = FALSE, Implementing the design.
+    C3_HW_TESTING           : string := "FALSE"; 
+                                       -- Determines the address space accessed by the traffic generator,
+                                       -- # = FALSE, Smaller address space,
+                                       -- # = TRUE, Large address space.
+    DEBUG_EN                : integer := 0; 
+                                       -- # = 1, Enable debug signals/controls,
+                                       --   = 0, Disable debug signals/controls.
+    C3_MEM_ADDR_ORDER       : string := "BANK_ROW_COLUMN"; 
+                                       -- The order in which user address is provided to the memory controller,
+                                       -- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
+    C3_NUM_DQ_PINS          : integer := 16; 
+                                       -- External memory data width.
+    C3_MEM_ADDR_WIDTH       : integer := 13; 
+                                       -- External memory address width.
+    C3_MEM_BANKADDR_WIDTH   : integer := 3 
+                                       -- External memory bank address width.
+  );
+   
+  port
+  (
+   calib_done                              : out std_logic;
+   error                                   : out std_logic;
+   mcb3_dram_dq                            : inout  std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
+   mcb3_dram_a                             : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+   mcb3_dram_ba                            : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
+   mcb3_dram_ras_n                         : out std_logic;
+   mcb3_dram_cas_n                         : out std_logic;
+   mcb3_dram_we_n                          : out std_logic;
+   mcb3_dram_odt                           : out std_logic;
+   mcb3_dram_cke                           : out std_logic;
+   mcb3_dram_dm                            : out std_logic;
+   mcb3_dram_udqs                          : inout  std_logic;
+   mcb3_dram_udqs_n                        : inout  std_logic;
+   mcb3_rzq                                : inout  std_logic;
+   mcb3_zio                                : inout  std_logic;
+   mcb3_dram_udm                           : out std_logic;
+   c3_sys_clk                              : in  std_logic;
+   c3_sys_rst_i                            : in  std_logic;
+   mcb3_dram_dqs                           : inout  std_logic;
+   mcb3_dram_dqs_n                         : inout  std_logic;
+   mcb3_dram_ck                            : out std_logic;
+   mcb3_dram_ck_n                          : out std_logic
+  );
+end example_top;
+
+architecture arc of example_top is
+
+ 
+
+component memc3_infrastructure is
+    generic (
+      C_RST_ACT_LOW        : integer;
+      C_INPUT_CLK_TYPE     : string;
+      C_CLKOUT0_DIVIDE     : integer;
+      C_CLKOUT1_DIVIDE     : integer;
+      C_CLKOUT2_DIVIDE     : integer;
+      C_CLKOUT3_DIVIDE     : integer;
+      C_CLKFBOUT_MULT      : integer;
+      C_DIVCLK_DIVIDE      : integer;
+      C_INCLK_PERIOD       : integer
+
+      );
+    port (
+      sys_clk_p                              : in    std_logic;
+      sys_clk_n                              : in    std_logic;
+      sys_clk                                : in    std_logic;
+      sys_rst_i                              : in    std_logic;
+      clk0                                   : out   std_logic;
+      rst0                                   : out   std_logic;
+      async_rst                              : out   std_logic;
+      sysclk_2x                              : out   std_logic;
+      sysclk_2x_180                          : out   std_logic;
+      pll_ce_0                               : out   std_logic;
+      pll_ce_90                              : out   std_logic;
+      pll_lock                               : out   std_logic;
+      mcb_drp_clk                            : out   std_logic
+
+      );
+  end component;
+
+
+component memc3_wrapper is
+    generic (
+      C_MEMCLK_PERIOD      : integer;
+      C_CALIB_SOFT_IP      : string;
+      C_SIMULATION         : string;
+      C_P0_MASK_SIZE       : integer;
+      C_P0_DATA_PORT_SIZE   : integer;
+      C_P1_MASK_SIZE       : integer;
+      C_P1_DATA_PORT_SIZE   : integer;
+      C_ARB_NUM_TIME_SLOTS   : integer;
+      C_ARB_TIME_SLOT_0    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_1    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_2    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_3    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_4    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_5    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_6    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_7    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_8    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_9    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_10   : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_11   : bit_vector(11 downto 0);
+      C_MEM_TRAS           : integer;
+      C_MEM_TRCD           : integer;
+      C_MEM_TREFI          : integer;
+      C_MEM_TRFC           : integer;
+      C_MEM_TRP            : integer;
+      C_MEM_TWR            : integer;
+      C_MEM_TRTP           : integer;
+      C_MEM_TWTR           : integer;
+      C_MEM_ADDR_ORDER     : string;
+      C_NUM_DQ_PINS        : integer;
+      C_MEM_TYPE           : string;
+      C_MEM_DENSITY        : string;
+      C_MEM_BURST_LEN      : integer;
+      C_MEM_CAS_LATENCY    : integer;
+      C_MEM_ADDR_WIDTH     : integer;
+      C_MEM_BANKADDR_WIDTH   : integer;
+      C_MEM_NUM_COL_BITS   : integer;
+      C_MEM_DDR1_2_ODS     : string;
+      C_MEM_DDR2_RTT       : string;
+      C_MEM_DDR2_DIFF_DQS_EN   : string;
+      C_MEM_DDR2_3_PA_SR   : string;
+      C_MEM_DDR2_3_HIGH_TEMP_SR   : string;
+      C_MEM_DDR3_CAS_LATENCY   : integer;
+      C_MEM_DDR3_ODS       : string;
+      C_MEM_DDR3_RTT       : string;
+      C_MEM_DDR3_CAS_WR_LATENCY   : integer;
+      C_MEM_DDR3_AUTO_SR   : string;
+      C_MEM_DDR3_DYN_WRT_ODT   : string;
+      C_MEM_MOBILE_PA_SR   : string;
+      C_MEM_MDDR_ODS       : string;
+      C_MC_CALIB_BYPASS    : string;
+      C_MC_CALIBRATION_MODE   : string;
+      C_MC_CALIBRATION_DELAY   : string;
+      C_SKIP_IN_TERM_CAL   : integer;
+      C_SKIP_DYNAMIC_CAL   : integer;
+      C_LDQSP_TAP_DELAY_VAL   : integer;
+      C_LDQSN_TAP_DELAY_VAL   : integer;
+      C_UDQSP_TAP_DELAY_VAL   : integer;
+      C_UDQSN_TAP_DELAY_VAL   : integer;
+      C_DQ0_TAP_DELAY_VAL   : integer;
+      C_DQ1_TAP_DELAY_VAL   : integer;
+      C_DQ2_TAP_DELAY_VAL   : integer;
+      C_DQ3_TAP_DELAY_VAL   : integer;
+      C_DQ4_TAP_DELAY_VAL   : integer;
+      C_DQ5_TAP_DELAY_VAL   : integer;
+      C_DQ6_TAP_DELAY_VAL   : integer;
+      C_DQ7_TAP_DELAY_VAL   : integer;
+      C_DQ8_TAP_DELAY_VAL   : integer;
+      C_DQ9_TAP_DELAY_VAL   : integer;
+      C_DQ10_TAP_DELAY_VAL   : integer;
+      C_DQ11_TAP_DELAY_VAL   : integer;
+      C_DQ12_TAP_DELAY_VAL   : integer;
+      C_DQ13_TAP_DELAY_VAL   : integer;
+      C_DQ14_TAP_DELAY_VAL   : integer;
+      C_DQ15_TAP_DELAY_VAL   : integer
+      );
+    port (
+      mcb3_dram_dq                           : inout  std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
+      mcb3_dram_a                            : out  std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
+      mcb3_dram_ba                           : out  std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
+      mcb3_dram_ras_n                        : out  std_logic;
+      mcb3_dram_cas_n                        : out  std_logic;
+      mcb3_dram_we_n                         : out  std_logic;
+      mcb3_dram_odt                          : out  std_logic;
+      mcb3_dram_cke                          : out  std_logic;
+      mcb3_dram_dm                           : out  std_logic;
+      mcb3_dram_udqs                         : inout  std_logic;
+      mcb3_dram_udqs_n                       : inout  std_logic;
+      mcb3_rzq                               : inout  std_logic;
+      mcb3_zio                               : inout  std_logic;
+      mcb3_dram_udm                          : out  std_logic;
+      calib_done                             : out  std_logic;
+      async_rst                              : in  std_logic;
+      sysclk_2x                              : in  std_logic;
+      sysclk_2x_180                          : in  std_logic;
+      pll_ce_0                               : in  std_logic;
+      pll_ce_90                              : in  std_logic;
+      pll_lock                               : in  std_logic;
+      mcb_drp_clk                            : in  std_logic;
+      mcb3_dram_dqs                          : inout  std_logic;
+      mcb3_dram_dqs_n                        : inout  std_logic;
+      mcb3_dram_ck                           : out  std_logic;
+      mcb3_dram_ck_n                         : out  std_logic;
+      p0_cmd_clk                            : in std_logic;
+      p0_cmd_en                             : in std_logic;
+      p0_cmd_instr                          : in std_logic_vector(2 downto 0);
+      p0_cmd_bl                             : in std_logic_vector(5 downto 0);
+      p0_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
+      p0_cmd_empty                          : out std_logic;
+      p0_cmd_full                           : out std_logic;
+      p0_wr_clk                             : in std_logic;
+      p0_wr_en                              : in std_logic;
+      p0_wr_mask                            : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+      p0_wr_data                            : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_wr_full                            : out std_logic;
+      p0_wr_empty                           : out std_logic;
+      p0_wr_count                           : out std_logic_vector(6 downto 0);
+      p0_wr_underrun                        : out std_logic;
+      p0_wr_error                           : out std_logic;
+      p0_rd_clk                             : in std_logic;
+      p0_rd_en                              : in std_logic;
+      p0_rd_data                            : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_rd_full                            : out std_logic;
+      p0_rd_empty                           : out std_logic;
+      p0_rd_count                           : out std_logic_vector(6 downto 0);
+      p0_rd_overflow                        : out std_logic;
+      p0_rd_error                           : out std_logic;
+      p1_cmd_clk                            : in std_logic;
+      p1_cmd_en                             : in std_logic;
+      p1_cmd_instr                          : in std_logic_vector(2 downto 0);
+      p1_cmd_bl                             : in std_logic_vector(5 downto 0);
+      p1_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
+      p1_cmd_empty                          : out std_logic;
+      p1_cmd_full                           : out std_logic;
+      p1_wr_clk                             : in std_logic;
+      p1_wr_en                              : in std_logic;
+      p1_wr_mask                            : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+      p1_wr_data                            : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_wr_full                            : out std_logic;
+      p1_wr_empty                           : out std_logic;
+      p1_wr_count                           : out std_logic_vector(6 downto 0);
+      p1_wr_underrun                        : out std_logic;
+      p1_wr_error                           : out std_logic;
+      p1_rd_clk                             : in std_logic;
+      p1_rd_en                              : in std_logic;
+      p1_rd_data                            : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_rd_full                            : out std_logic;
+      p1_rd_empty                           : out std_logic;
+      p1_rd_count                           : out std_logic_vector(6 downto 0);
+      p1_rd_overflow                        : out std_logic;
+      p1_rd_error                           : out std_logic;
+      p2_cmd_clk                            : in std_logic;
+      p2_cmd_en                             : in std_logic;
+      p2_cmd_instr                          : in std_logic_vector(2 downto 0);
+      p2_cmd_bl                             : in std_logic_vector(5 downto 0);
+      p2_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
+      p2_cmd_empty                          : out std_logic;
+      p2_cmd_full                           : out std_logic;
+      p2_wr_clk                             : in std_logic;
+      p2_wr_en                              : in std_logic;
+      p2_wr_mask                            : in std_logic_vector(3 downto 0);
+      p2_wr_data                            : in std_logic_vector(31 downto 0);
+      p2_wr_full                            : out std_logic;
+      p2_wr_empty                           : out std_logic;
+      p2_wr_count                           : out std_logic_vector(6 downto 0);
+      p2_wr_underrun                        : out std_logic;
+      p2_wr_error                           : out std_logic;
+      p2_rd_clk                             : in std_logic;
+      p2_rd_en                              : in std_logic;
+      p2_rd_data                            : out std_logic_vector(31 downto 0);
+      p2_rd_full                            : out std_logic;
+      p2_rd_empty                           : out std_logic;
+      p2_rd_count                           : out std_logic_vector(6 downto 0);
+      p2_rd_overflow                        : out std_logic;
+      p2_rd_error                           : out std_logic;
+      p3_cmd_clk                            : in std_logic;
+      p3_cmd_en                             : in std_logic;
+      p3_cmd_instr                          : in std_logic_vector(2 downto 0);
+      p3_cmd_bl                             : in std_logic_vector(5 downto 0);
+      p3_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
+      p3_cmd_empty                          : out std_logic;
+      p3_cmd_full                           : out std_logic;
+      p3_wr_clk                             : in std_logic;
+      p3_wr_en                              : in std_logic;
+      p3_wr_mask                            : in std_logic_vector(3 downto 0);
+      p3_wr_data                            : in std_logic_vector(31 downto 0);
+      p3_wr_full                            : out std_logic;
+      p3_wr_empty                           : out std_logic;
+      p3_wr_count                           : out std_logic_vector(6 downto 0);
+      p3_wr_underrun                        : out std_logic;
+      p3_wr_error                           : out std_logic;
+      p3_rd_clk                             : in std_logic;
+      p3_rd_en                              : in std_logic;
+      p3_rd_data                            : out std_logic_vector(31 downto 0);
+      p3_rd_full                            : out std_logic;
+      p3_rd_empty                           : out std_logic;
+      p3_rd_count                           : out std_logic_vector(6 downto 0);
+      p3_rd_overflow                        : out std_logic;
+      p3_rd_error                           : out std_logic;
+      selfrefresh_enter                     : in std_logic;
+      selfrefresh_mode                      : out std_logic
+
+      );
+  end component;
+
+
+component memc3_tb_top is
+    generic (
+      C_SIMULATION         : string;
+      C_P0_MASK_SIZE       : integer;
+      C_P0_DATA_PORT_SIZE   : integer;
+      C_P1_MASK_SIZE       : integer;
+      C_P1_DATA_PORT_SIZE   : integer;
+      C_NUM_DQ_PINS        : integer;
+      C_MEM_BURST_LEN      : integer;
+      C_MEM_NUM_COL_BITS   : integer;
+      C_SMALL_DEVICE       : string;
+      C_p0_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0); 
+      C_p0_DATA_MODE                          : std_logic_vector(3 downto 0); 
+      C_p0_END_ADDRESS                        : std_logic_vector(31 downto 0); 
+      C_p0_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0); 
+      C_p0_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0); 
+      C_p1_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0); 
+      C_p1_DATA_MODE                          : std_logic_vector(3 downto 0); 
+      C_p1_END_ADDRESS                        : std_logic_vector(31 downto 0); 
+      C_p1_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0); 
+      C_p1_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0); 
+      C_p2_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0); 
+      C_p2_DATA_MODE                          : std_logic_vector(3 downto 0); 
+      C_p2_END_ADDRESS                        : std_logic_vector(31 downto 0); 
+      C_p2_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0); 
+      C_p2_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0); 
+      C_p3_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0); 
+      C_p3_DATA_MODE                          : std_logic_vector(3 downto 0); 
+      C_p3_END_ADDRESS                        : std_logic_vector(31 downto 0); 
+      C_p3_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0); 
+      C_p3_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0) 
+
+      );
+    port (
+      error                                  : out   std_logic;
+      calib_done                             : in    std_logic;
+      clk0                                   : in    std_logic;
+      rst0                                   : in    std_logic;
+      cmp_error                              : out   std_logic;
+      cmp_data_valid                         : out   std_logic;
+      vio_modify_enable                      : in    std_logic;
+      error_status                           : out   std_logic_vector(127 downto 0);
+      vio_data_mode_value                    : in  std_logic_vector(2 downto 0);
+      vio_addr_mode_value                    : in  std_logic_vector(2 downto 0);
+      cmp_data                               : out  std_logic_vector(31 downto 0);
+      p0_mcb_cmd_en_o                           : out std_logic;
+      p0_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p0_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p0_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p0_mcb_cmd_full_i                         : in std_logic;
+      p0_mcb_wr_en_o                            : out std_logic;
+      p0_mcb_wr_mask_o                          : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+      p0_mcb_wr_data_o                          : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_mcb_wr_full_i                          : in std_logic;
+      p0_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+      p0_mcb_rd_en_o                            : out std_logic;
+      p0_mcb_rd_data_i                          : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_mcb_rd_empty_i                         : in std_logic;
+      p0_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+      p1_mcb_cmd_en_o                           : out std_logic;
+      p1_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p1_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p1_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p1_mcb_cmd_full_i                         : in std_logic;
+      p1_mcb_wr_en_o                            : out std_logic;
+      p1_mcb_wr_mask_o                          : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+      p1_mcb_wr_data_o                          : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_mcb_wr_full_i                          : in std_logic;
+      p1_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+      p1_mcb_rd_en_o                            : out std_logic;
+      p1_mcb_rd_data_i                          : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_mcb_rd_empty_i                         : in std_logic;
+      p1_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+      p2_mcb_cmd_en_o                           : out std_logic;
+      p2_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p2_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p2_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p2_mcb_cmd_full_i                         : in std_logic;
+      p2_mcb_wr_en_o                            : out std_logic;
+      p2_mcb_wr_mask_o                          : out std_logic_vector(3 downto 0);
+      p2_mcb_wr_data_o                          : out std_logic_vector(31 downto 0);
+      p2_mcb_wr_full_i                          : in std_logic;
+      p2_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+      p2_mcb_rd_en_o                            : out std_logic;
+      p2_mcb_rd_data_i                          : in std_logic_vector(31 downto 0);
+      p2_mcb_rd_empty_i                         : in std_logic;
+      p2_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+      p3_mcb_cmd_en_o                           : out std_logic;
+      p3_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p3_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p3_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p3_mcb_cmd_full_i                         : in std_logic;
+      p3_mcb_wr_en_o                            : out std_logic;
+      p3_mcb_wr_mask_o                          : out std_logic_vector(3 downto 0);
+      p3_mcb_wr_data_o                          : out std_logic_vector(31 downto 0);
+      p3_mcb_wr_full_i                          : in std_logic;
+      p3_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+      p3_mcb_rd_en_o                            : out std_logic;
+      p3_mcb_rd_data_i                          : in std_logic_vector(31 downto 0);
+      p3_mcb_rd_empty_i                         : in std_logic;
+      p3_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0)
+
+      );
+  end component;
+
+
+
+  function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) )  return  std_logic_vector is
+   begin
+   if (C3_HW_TESTING = "FALSE") then
+     return val1;
+   else
+     return val2;
+   end if;
+   end function;
+
+
+
+   constant C3_CLKOUT0_DIVIDE       : integer := 1; 
+   constant C3_CLKOUT1_DIVIDE       : integer := 1; 
+   constant C3_CLKOUT2_DIVIDE       : integer := 16; 
+   constant C3_CLKOUT3_DIVIDE       : integer := 8; 
+   constant C3_CLKFBOUT_MULT        : integer := 2; 
+   constant C3_DIVCLK_DIVIDE        : integer := 1; 
+   constant C3_INCLK_PERIOD         : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); 
+   constant C3_ARB_NUM_TIME_SLOTS   : integer := 12; 
+   constant C3_ARB_TIME_SLOT_0      : bit_vector(11 downto 0) := o"0124"; 
+   constant C3_ARB_TIME_SLOT_1      : bit_vector(11 downto 0) := o"1240"; 
+   constant C3_ARB_TIME_SLOT_2      : bit_vector(11 downto 0) := o"2401"; 
+   constant C3_ARB_TIME_SLOT_3      : bit_vector(11 downto 0) := o"4012"; 
+   constant C3_ARB_TIME_SLOT_4      : bit_vector(11 downto 0) := o"0124"; 
+   constant C3_ARB_TIME_SLOT_5      : bit_vector(11 downto 0) := o"1240"; 
+   constant C3_ARB_TIME_SLOT_6      : bit_vector(11 downto 0) := o"2401"; 
+   constant C3_ARB_TIME_SLOT_7      : bit_vector(11 downto 0) := o"4012"; 
+   constant C3_ARB_TIME_SLOT_8      : bit_vector(11 downto 0) := o"0124"; 
+   constant C3_ARB_TIME_SLOT_9      : bit_vector(11 downto 0) := o"1240"; 
+   constant C3_ARB_TIME_SLOT_10     : bit_vector(11 downto 0) := o"2401"; 
+   constant C3_ARB_TIME_SLOT_11     : bit_vector(11 downto 0) := o"4012"; 
+   constant C3_MEM_TRAS             : integer := 42500; 
+   constant C3_MEM_TRCD             : integer := 12500; 
+   constant C3_MEM_TREFI            : integer := 7800000; 
+   constant C3_MEM_TRFC             : integer := 127500; 
+   constant C3_MEM_TRP              : integer := 12500; 
+   constant C3_MEM_TWR              : integer := 15000; 
+   constant C3_MEM_TRTP             : integer := 7500; 
+   constant C3_MEM_TWTR             : integer := 7500; 
+   constant C3_MEM_TYPE             : string := "DDR2"; 
+   constant C3_MEM_DENSITY          : string := "1Gb"; 
+   constant C3_MEM_BURST_LEN        : integer := 4; 
+   constant C3_MEM_CAS_LATENCY      : integer := 5; 
+   constant C3_MEM_NUM_COL_BITS     : integer := 10; 
+   constant C3_MEM_DDR1_2_ODS       : string := "FULL"; 
+   constant C3_MEM_DDR2_RTT         : string := "50OHMS"; 
+   constant C3_MEM_DDR2_DIFF_DQS_EN  : string := "YES"; 
+   constant C3_MEM_DDR2_3_PA_SR     : string := "FULL"; 
+   constant C3_MEM_DDR2_3_HIGH_TEMP_SR  : string := "NORMAL"; 
+   constant C3_MEM_DDR3_CAS_LATENCY  : integer := 6; 
+   constant C3_MEM_DDR3_ODS         : string := "DIV6"; 
+   constant C3_MEM_DDR3_RTT         : string := "DIV2"; 
+   constant C3_MEM_DDR3_CAS_WR_LATENCY  : integer := 5; 
+   constant C3_MEM_DDR3_AUTO_SR     : string := "ENABLED"; 
+   constant C3_MEM_DDR3_DYN_WRT_ODT  : string := "OFF"; 
+   constant C3_MEM_MOBILE_PA_SR     : string := "FULL"; 
+   constant C3_MEM_MDDR_ODS         : string := "FULL"; 
+   constant C3_MC_CALIB_BYPASS      : string := "NO"; 
+   constant C3_MC_CALIBRATION_MODE  : string := "CALIBRATION"; 
+   constant C3_MC_CALIBRATION_DELAY  : string := "HALF"; 
+   constant C3_SKIP_IN_TERM_CAL     : integer := 0; 
+   constant C3_SKIP_DYNAMIC_CAL     : integer := 0; 
+   constant C3_LDQSP_TAP_DELAY_VAL  : integer := 0; 
+   constant C3_LDQSN_TAP_DELAY_VAL  : integer := 0; 
+   constant C3_UDQSP_TAP_DELAY_VAL  : integer := 0; 
+   constant C3_UDQSN_TAP_DELAY_VAL  : integer := 0; 
+   constant C3_DQ0_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ1_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ2_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ3_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ4_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ5_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ6_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ7_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ8_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ9_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ10_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ11_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ12_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ13_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ14_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ15_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_SMALL_DEVICE         : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
+                                                         -- as most of them cannot fit the complete example design when the
+                                                         -- Chip scope modules are enabled
+   constant C3_p0_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000100", x"01000000");
+   constant C3_p0_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
+   constant C3_p0_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000002ff", x"02ffffff");
+   constant C3_p0_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffffc00", x"fc000000");
+   constant C3_p0_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000100", x"01000000");
+   constant C3_p1_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000300", x"03000000");
+   constant C3_p1_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
+   constant C3_p1_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000004ff", x"04ffffff");
+   constant C3_p1_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffff800", x"f8000000");
+   constant C3_p1_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000300", x"03000000");
+   constant C3_p2_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000500", x"05000000");
+   constant C3_p2_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
+   constant C3_p2_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000006ff", x"06ffffff");
+   constant C3_p2_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffff800", x"f8000000");
+   constant C3_p2_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000500", x"05000000");
+   constant C3_p3_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000700", x"01000000");
+   constant C3_p3_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
+   constant C3_p3_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000008ff", x"02ffffff");
+   constant C3_p3_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffff000", x"fc000000");
+   constant C3_p3_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000700", x"01000000");
+
+  signal  c3_sys_clk_p                             : std_logic;
+  signal  c3_sys_clk_n                             : std_logic;
+  signal  c3_error                                 : std_logic;
+  signal  c3_calib_done                            : std_logic;
+  signal  c3_clk0                                  : std_logic;
+  signal  c3_rst0                                  : std_logic;
+  signal  c3_async_rst                             : std_logic;
+  signal  c3_sysclk_2x                             : std_logic;
+  signal  c3_sysclk_2x_180                         : std_logic;
+  signal  c3_pll_ce_0                              : std_logic;
+  signal  c3_pll_ce_90                             : std_logic;
+  signal  c3_pll_lock                              : std_logic;
+  signal  c3_mcb_drp_clk                           : std_logic;
+  signal  c3_cmp_error                             : std_logic;
+  signal  c3_cmp_data_valid                        : std_logic;
+  signal  c3_vio_modify_enable                     : std_logic;
+  signal  c3_error_status                          : std_logic_vector(127 downto 0);
+  signal  c3_vio_data_mode_value                   : std_logic_vector(2 downto 0);
+  signal  c3_vio_addr_mode_value                   : std_logic_vector(2 downto 0);
+  signal  c3_cmp_data                              : std_logic_vector(31 downto 0);
+  signal  c3_p0_cmd_en                             : std_logic;
+  signal  c3_p0_cmd_instr                          : std_logic_vector(2 downto 0);
+  signal  c3_p0_cmd_bl                             : std_logic_vector(5 downto 0);
+  signal  c3_p0_cmd_byte_addr                      : std_logic_vector(29 downto 0);
+  signal  c3_p0_cmd_empty                          : std_logic;
+  signal  c3_p0_cmd_full                           : std_logic;
+  signal  c3_p0_wr_en                              : std_logic;
+  signal  c3_p0_wr_mask                            : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
+  signal  c3_p0_wr_data                            : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+  signal  c3_p0_wr_full                            : std_logic;
+  signal  c3_p0_wr_empty                           : std_logic;
+  signal  c3_p0_wr_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p0_wr_underrun                        : std_logic;
+  signal  c3_p0_wr_error                           : std_logic;
+  signal  c3_p0_rd_en                              : std_logic;
+  signal  c3_p0_rd_data                            : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+  signal  c3_p0_rd_full                            : std_logic;
+  signal  c3_p0_rd_empty                           : std_logic;
+  signal  c3_p0_rd_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p0_rd_overflow                        : std_logic;
+  signal  c3_p0_rd_error                           : std_logic;
+
+  signal  c3_p1_cmd_en                             : std_logic;
+  signal  c3_p1_cmd_instr                          : std_logic_vector(2 downto 0);
+  signal  c3_p1_cmd_bl                             : std_logic_vector(5 downto 0);
+  signal  c3_p1_cmd_byte_addr                      : std_logic_vector(29 downto 0);
+  signal  c3_p1_cmd_empty                          : std_logic;
+  signal  c3_p1_cmd_full                           : std_logic;
+  signal  c3_p1_wr_en                              : std_logic;
+  signal  c3_p1_wr_mask                            : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
+  signal  c3_p1_wr_data                            : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+  signal  c3_p1_wr_full                            : std_logic;
+  signal  c3_p1_wr_empty                           : std_logic;
+  signal  c3_p1_wr_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p1_wr_underrun                        : std_logic;
+  signal  c3_p1_wr_error                           : std_logic;
+  signal  c3_p1_rd_en                              : std_logic;
+  signal  c3_p1_rd_data                            : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+  signal  c3_p1_rd_full                            : std_logic;
+  signal  c3_p1_rd_empty                           : std_logic;
+  signal  c3_p1_rd_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p1_rd_overflow                        : std_logic;
+  signal  c3_p1_rd_error                           : std_logic;
+
+  signal  c3_p2_cmd_en                             : std_logic;
+  signal  c3_p2_cmd_instr                          : std_logic_vector(2 downto 0);
+  signal  c3_p2_cmd_bl                             : std_logic_vector(5 downto 0);
+  signal  c3_p2_cmd_byte_addr                      : std_logic_vector(29 downto 0);
+  signal  c3_p2_cmd_empty                          : std_logic;
+  signal  c3_p2_cmd_full                           : std_logic;
+  signal  c3_p2_wr_en                              : std_logic;
+  signal  c3_p2_wr_mask                            : std_logic_vector(3 downto 0);
+  signal  c3_p2_wr_data                            : std_logic_vector(31 downto 0);
+  signal  c3_p2_wr_full                            : std_logic;
+  signal  c3_p2_wr_empty                           : std_logic;
+  signal  c3_p2_wr_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p2_wr_underrun                        : std_logic;
+  signal  c3_p2_wr_error                           : std_logic;
+  signal  c3_p2_rd_en                              : std_logic;
+  signal  c3_p2_rd_data                            : std_logic_vector(31 downto 0);
+  signal  c3_p2_rd_full                            : std_logic;
+  signal  c3_p2_rd_empty                           : std_logic;
+  signal  c3_p2_rd_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p2_rd_overflow                        : std_logic;
+  signal  c3_p2_rd_error                           : std_logic;
+
+  signal  c3_p3_cmd_en                             : std_logic;
+  signal  c3_p3_cmd_instr                          : std_logic_vector(2 downto 0);
+  signal  c3_p3_cmd_bl                             : std_logic_vector(5 downto 0);
+  signal  c3_p3_cmd_byte_addr                      : std_logic_vector(29 downto 0);
+  signal  c3_p3_cmd_empty                          : std_logic;
+  signal  c3_p3_cmd_full                           : std_logic;
+  signal  c3_p3_wr_en                              : std_logic;
+  signal  c3_p3_wr_mask                            : std_logic_vector(3 downto 0);
+  signal  c3_p3_wr_data                            : std_logic_vector(31 downto 0);
+  signal  c3_p3_wr_full                            : std_logic;
+  signal  c3_p3_wr_empty                           : std_logic;
+  signal  c3_p3_wr_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p3_wr_underrun                        : std_logic;
+  signal  c3_p3_wr_error                           : std_logic;
+  signal  c3_p3_rd_en                              : std_logic;
+  signal  c3_p3_rd_data                            : std_logic_vector(31 downto 0);
+  signal  c3_p3_rd_full                            : std_logic;
+  signal  c3_p3_rd_empty                           : std_logic;
+  signal  c3_p3_rd_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p3_rd_overflow                        : std_logic;
+  signal  c3_p3_rd_error                           : std_logic;
+
+  signal  c3_selfrefresh_enter                     : std_logic;
+  signal  c3_selfrefresh_mode                      : std_logic;
+
+
+
+
+begin
+ error <= c3_error;
+calib_done <= c3_calib_done;
+c3_sys_clk_p <= '0';
+c3_sys_clk_n <= '0';
+c3_selfrefresh_enter <= '0';
+memc3_infrastructure_inst : memc3_infrastructure
+
+generic map
+ (
+   C_RST_ACT_LOW                     => C3_RST_ACT_LOW,
+   C_INPUT_CLK_TYPE                  => C3_INPUT_CLK_TYPE,
+   C_CLKOUT0_DIVIDE                  => C3_CLKOUT0_DIVIDE,
+   C_CLKOUT1_DIVIDE                  => C3_CLKOUT1_DIVIDE,
+   C_CLKOUT2_DIVIDE                  => C3_CLKOUT2_DIVIDE,
+   C_CLKOUT3_DIVIDE                  => C3_CLKOUT3_DIVIDE,
+   C_CLKFBOUT_MULT                   => C3_CLKFBOUT_MULT,
+   C_DIVCLK_DIVIDE                   => C3_DIVCLK_DIVIDE,
+   C_INCLK_PERIOD                    => C3_INCLK_PERIOD
+   )
+port map
+ (
+   sys_clk_p                       => c3_sys_clk_p,
+   sys_clk_n                       => c3_sys_clk_n,
+   sys_clk                         => c3_sys_clk,
+   sys_rst_i                       => c3_sys_rst_i,
+   clk0                            => c3_clk0,
+   rst0                            => c3_rst0,
+   async_rst                       => c3_async_rst,
+   sysclk_2x                       => c3_sysclk_2x,
+   sysclk_2x_180                   => c3_sysclk_2x_180,
+   pll_ce_0                        => c3_pll_ce_0,
+   pll_ce_90                       => c3_pll_ce_90,
+   pll_lock                        => c3_pll_lock,
+   mcb_drp_clk                     => c3_mcb_drp_clk
+   );
+
+
+-- wrapper instantiation
+ memc3_wrapper_inst : memc3_wrapper
+
+generic map
+ (
+   C_MEMCLK_PERIOD                   => C3_MEMCLK_PERIOD,
+   C_CALIB_SOFT_IP                   => C3_CALIB_SOFT_IP,
+   C_SIMULATION                      => C3_SIMULATION,
+   C_P0_MASK_SIZE                    => C3_P0_MASK_SIZE,
+   C_P0_DATA_PORT_SIZE               => C3_P0_DATA_PORT_SIZE,
+   C_P1_MASK_SIZE                    => C3_P1_MASK_SIZE,
+   C_P1_DATA_PORT_SIZE               => C3_P1_DATA_PORT_SIZE,
+   C_ARB_NUM_TIME_SLOTS              => C3_ARB_NUM_TIME_SLOTS,
+   C_ARB_TIME_SLOT_0                 => C3_ARB_TIME_SLOT_0,
+   C_ARB_TIME_SLOT_1                 => C3_ARB_TIME_SLOT_1,
+   C_ARB_TIME_SLOT_2                 => C3_ARB_TIME_SLOT_2,
+   C_ARB_TIME_SLOT_3                 => C3_ARB_TIME_SLOT_3,
+   C_ARB_TIME_SLOT_4                 => C3_ARB_TIME_SLOT_4,
+   C_ARB_TIME_SLOT_5                 => C3_ARB_TIME_SLOT_5,
+   C_ARB_TIME_SLOT_6                 => C3_ARB_TIME_SLOT_6,
+   C_ARB_TIME_SLOT_7                 => C3_ARB_TIME_SLOT_7,
+   C_ARB_TIME_SLOT_8                 => C3_ARB_TIME_SLOT_8,
+   C_ARB_TIME_SLOT_9                 => C3_ARB_TIME_SLOT_9,
+   C_ARB_TIME_SLOT_10                => C3_ARB_TIME_SLOT_10,
+   C_ARB_TIME_SLOT_11                => C3_ARB_TIME_SLOT_11,
+   C_MEM_TRAS                        => C3_MEM_TRAS,
+   C_MEM_TRCD                        => C3_MEM_TRCD,
+   C_MEM_TREFI                       => C3_MEM_TREFI,
+   C_MEM_TRFC                        => C3_MEM_TRFC,
+   C_MEM_TRP                         => C3_MEM_TRP,
+   C_MEM_TWR                         => C3_MEM_TWR,
+   C_MEM_TRTP                        => C3_MEM_TRTP,
+   C_MEM_TWTR                        => C3_MEM_TWTR,
+   C_MEM_ADDR_ORDER                  => C3_MEM_ADDR_ORDER,
+   C_NUM_DQ_PINS                     => C3_NUM_DQ_PINS,
+   C_MEM_TYPE                        => C3_MEM_TYPE,
+   C_MEM_DENSITY                     => C3_MEM_DENSITY,
+   C_MEM_BURST_LEN                   => C3_MEM_BURST_LEN,
+   C_MEM_CAS_LATENCY                 => C3_MEM_CAS_LATENCY,
+   C_MEM_ADDR_WIDTH                  => C3_MEM_ADDR_WIDTH,
+   C_MEM_BANKADDR_WIDTH              => C3_MEM_BANKADDR_WIDTH,
+   C_MEM_NUM_COL_BITS                => C3_MEM_NUM_COL_BITS,
+   C_MEM_DDR1_2_ODS                  => C3_MEM_DDR1_2_ODS,
+   C_MEM_DDR2_RTT                    => C3_MEM_DDR2_RTT,
+   C_MEM_DDR2_DIFF_DQS_EN            => C3_MEM_DDR2_DIFF_DQS_EN,
+   C_MEM_DDR2_3_PA_SR                => C3_MEM_DDR2_3_PA_SR,
+   C_MEM_DDR2_3_HIGH_TEMP_SR         => C3_MEM_DDR2_3_HIGH_TEMP_SR,
+   C_MEM_DDR3_CAS_LATENCY            => C3_MEM_DDR3_CAS_LATENCY,
+   C_MEM_DDR3_ODS                    => C3_MEM_DDR3_ODS,
+   C_MEM_DDR3_RTT                    => C3_MEM_DDR3_RTT,
+   C_MEM_DDR3_CAS_WR_LATENCY         => C3_MEM_DDR3_CAS_WR_LATENCY,
+   C_MEM_DDR3_AUTO_SR                => C3_MEM_DDR3_AUTO_SR,
+   C_MEM_DDR3_DYN_WRT_ODT            => C3_MEM_DDR3_DYN_WRT_ODT,
+   C_MEM_MOBILE_PA_SR                => C3_MEM_MOBILE_PA_SR,
+   C_MEM_MDDR_ODS                    => C3_MEM_MDDR_ODS,
+   C_MC_CALIB_BYPASS                 => C3_MC_CALIB_BYPASS,
+   C_MC_CALIBRATION_MODE             => C3_MC_CALIBRATION_MODE,
+   C_MC_CALIBRATION_DELAY            => C3_MC_CALIBRATION_DELAY,
+   C_SKIP_IN_TERM_CAL                => C3_SKIP_IN_TERM_CAL,
+   C_SKIP_DYNAMIC_CAL                => C3_SKIP_DYNAMIC_CAL,
+   C_LDQSP_TAP_DELAY_VAL             => C3_LDQSP_TAP_DELAY_VAL,
+   C_LDQSN_TAP_DELAY_VAL             => C3_LDQSN_TAP_DELAY_VAL,
+   C_UDQSP_TAP_DELAY_VAL             => C3_UDQSP_TAP_DELAY_VAL,
+   C_UDQSN_TAP_DELAY_VAL             => C3_UDQSN_TAP_DELAY_VAL,
+   C_DQ0_TAP_DELAY_VAL               => C3_DQ0_TAP_DELAY_VAL,
+   C_DQ1_TAP_DELAY_VAL               => C3_DQ1_TAP_DELAY_VAL,
+   C_DQ2_TAP_DELAY_VAL               => C3_DQ2_TAP_DELAY_VAL,
+   C_DQ3_TAP_DELAY_VAL               => C3_DQ3_TAP_DELAY_VAL,
+   C_DQ4_TAP_DELAY_VAL               => C3_DQ4_TAP_DELAY_VAL,
+   C_DQ5_TAP_DELAY_VAL               => C3_DQ5_TAP_DELAY_VAL,
+   C_DQ6_TAP_DELAY_VAL               => C3_DQ6_TAP_DELAY_VAL,
+   C_DQ7_TAP_DELAY_VAL               => C3_DQ7_TAP_DELAY_VAL,
+   C_DQ8_TAP_DELAY_VAL               => C3_DQ8_TAP_DELAY_VAL,
+   C_DQ9_TAP_DELAY_VAL               => C3_DQ9_TAP_DELAY_VAL,
+   C_DQ10_TAP_DELAY_VAL              => C3_DQ10_TAP_DELAY_VAL,
+   C_DQ11_TAP_DELAY_VAL              => C3_DQ11_TAP_DELAY_VAL,
+   C_DQ12_TAP_DELAY_VAL              => C3_DQ12_TAP_DELAY_VAL,
+   C_DQ13_TAP_DELAY_VAL              => C3_DQ13_TAP_DELAY_VAL,
+   C_DQ14_TAP_DELAY_VAL              => C3_DQ14_TAP_DELAY_VAL,
+   C_DQ15_TAP_DELAY_VAL              => C3_DQ15_TAP_DELAY_VAL
+   )
+port map
+(
+   mcb3_dram_dq                         => mcb3_dram_dq,
+   mcb3_dram_a                          => mcb3_dram_a,
+   mcb3_dram_ba                         => mcb3_dram_ba,
+   mcb3_dram_ras_n                      => mcb3_dram_ras_n,
+   mcb3_dram_cas_n                      => mcb3_dram_cas_n,
+   mcb3_dram_we_n                       => mcb3_dram_we_n,
+   mcb3_dram_odt                        => mcb3_dram_odt,
+   mcb3_dram_cke                        => mcb3_dram_cke,
+   mcb3_dram_dm                         => mcb3_dram_dm,
+   mcb3_dram_udqs                       => mcb3_dram_udqs,
+   mcb3_dram_udqs_n                     => mcb3_dram_udqs_n,
+   mcb3_rzq                             => mcb3_rzq,
+   mcb3_zio                             => mcb3_zio,
+   mcb3_dram_udm                        => mcb3_dram_udm,
+   calib_done                      => c3_calib_done,
+   async_rst                       => c3_async_rst,
+   sysclk_2x                       => c3_sysclk_2x,
+   sysclk_2x_180                   => c3_sysclk_2x_180,
+   pll_ce_0                        => c3_pll_ce_0,
+   pll_ce_90                       => c3_pll_ce_90,
+   pll_lock                        => c3_pll_lock,
+   mcb_drp_clk                     => c3_mcb_drp_clk,
+   mcb3_dram_dqs                        => mcb3_dram_dqs,
+   mcb3_dram_dqs_n                      => mcb3_dram_dqs_n,
+   mcb3_dram_ck                         => mcb3_dram_ck,
+   mcb3_dram_ck_n                       => mcb3_dram_ck_n,
+   p0_cmd_clk                           =>  c3_clk0,
+   p0_cmd_en                            =>  c3_p0_cmd_en,
+   p0_cmd_instr                         =>  c3_p0_cmd_instr,
+   p0_cmd_bl                            =>  c3_p0_cmd_bl,
+   p0_cmd_byte_addr                     =>  c3_p0_cmd_byte_addr,
+   p0_cmd_empty                         =>  c3_p0_cmd_empty,
+   p0_cmd_full                          =>  c3_p0_cmd_full,
+   p0_wr_clk                            =>  c3_clk0,
+   p0_wr_en                             =>  c3_p0_wr_en,
+   p0_wr_mask                           =>  c3_p0_wr_mask,
+   p0_wr_data                           =>  c3_p0_wr_data,
+   p0_wr_full                           =>  c3_p0_wr_full,
+   p0_wr_empty                          =>  c3_p0_wr_empty,
+   p0_wr_count                          =>  c3_p0_wr_count,
+   p0_wr_underrun                       =>  c3_p0_wr_underrun,
+   p0_wr_error                          =>  c3_p0_wr_error,
+   p0_rd_clk                            =>  c3_clk0,
+   p0_rd_en                             =>  c3_p0_rd_en,
+   p0_rd_data                           =>  c3_p0_rd_data,
+   p0_rd_full                           =>  c3_p0_rd_full,
+   p0_rd_empty                          =>  c3_p0_rd_empty,
+   p0_rd_count                          =>  c3_p0_rd_count,
+   p0_rd_overflow                       =>  c3_p0_rd_overflow,
+   p0_rd_error                          =>  c3_p0_rd_error,
+   p1_cmd_clk                           =>  c3_clk0,
+   p1_cmd_en                            =>  c3_p1_cmd_en,
+   p1_cmd_instr                         =>  c3_p1_cmd_instr,
+   p1_cmd_bl                            =>  c3_p1_cmd_bl,
+   p1_cmd_byte_addr                     =>  c3_p1_cmd_byte_addr,
+   p1_cmd_empty                         =>  c3_p1_cmd_empty,
+   p1_cmd_full                          =>  c3_p1_cmd_full,
+   p1_wr_clk                            =>  c3_clk0,
+   p1_wr_en                             =>  c3_p1_wr_en,
+   p1_wr_mask                           =>  c3_p1_wr_mask,
+   p1_wr_data                           =>  c3_p1_wr_data,
+   p1_wr_full                           =>  c3_p1_wr_full,
+   p1_wr_empty                          =>  c3_p1_wr_empty,
+   p1_wr_count                          =>  c3_p1_wr_count,
+   p1_wr_underrun                       =>  c3_p1_wr_underrun,
+   p1_wr_error                          =>  c3_p1_wr_error,
+   p1_rd_clk                            =>  c3_clk0,
+   p1_rd_en                             =>  c3_p1_rd_en,
+   p1_rd_data                           =>  c3_p1_rd_data,
+   p1_rd_full                           =>  c3_p1_rd_full,
+   p1_rd_empty                          =>  c3_p1_rd_empty,
+   p1_rd_count                          =>  c3_p1_rd_count,
+   p1_rd_overflow                       =>  c3_p1_rd_overflow,
+   p1_rd_error                          =>  c3_p1_rd_error,
+   p2_cmd_clk                           =>  c3_clk0,
+   p2_cmd_en                            =>  c3_p2_cmd_en,
+   p2_cmd_instr                         =>  c3_p2_cmd_instr,
+   p2_cmd_bl                            =>  c3_p2_cmd_bl,
+   p2_cmd_byte_addr                     =>  c3_p2_cmd_byte_addr,
+   p2_cmd_empty                         =>  c3_p2_cmd_empty,
+   p2_cmd_full                          =>  c3_p2_cmd_full,
+   p2_wr_clk                            =>  c3_clk0,
+   p2_wr_en                             =>  c3_p2_wr_en,
+   p2_wr_mask                           =>  c3_p2_wr_mask,
+   p2_wr_data                           =>  c3_p2_wr_data,
+   p2_wr_full                           =>  c3_p2_wr_full,
+   p2_wr_empty                          =>  c3_p2_wr_empty,
+   p2_wr_count                          =>  c3_p2_wr_count,
+   p2_wr_underrun                       =>  c3_p2_wr_underrun,
+   p2_wr_error                          =>  c3_p2_wr_error,
+   p2_rd_clk                            =>  c3_clk0,
+   p2_rd_en                             =>  c3_p2_rd_en,
+   p2_rd_data                           =>  c3_p2_rd_data,
+   p2_rd_full                           =>  c3_p2_rd_full,
+   p2_rd_empty                          =>  c3_p2_rd_empty,
+   p2_rd_count                          =>  c3_p2_rd_count,
+   p2_rd_overflow                       =>  c3_p2_rd_overflow,
+   p2_rd_error                          =>  c3_p2_rd_error,
+   p3_cmd_clk                           =>  c3_clk0,
+   p3_cmd_en                            =>  c3_p3_cmd_en,
+   p3_cmd_instr                         =>  c3_p3_cmd_instr,
+   p3_cmd_bl                            =>  c3_p3_cmd_bl,
+   p3_cmd_byte_addr                     =>  c3_p3_cmd_byte_addr,
+   p3_cmd_empty                         =>  c3_p3_cmd_empty,
+   p3_cmd_full                          =>  c3_p3_cmd_full,
+   p3_wr_clk                            =>  c3_clk0,
+   p3_wr_en                             =>  c3_p3_wr_en,
+   p3_wr_mask                           =>  c3_p3_wr_mask,
+   p3_wr_data                           =>  c3_p3_wr_data,
+   p3_wr_full                           =>  c3_p3_wr_full,
+   p3_wr_empty                          =>  c3_p3_wr_empty,
+   p3_wr_count                          =>  c3_p3_wr_count,
+   p3_wr_underrun                       =>  c3_p3_wr_underrun,
+   p3_wr_error                          =>  c3_p3_wr_error,
+   p3_rd_clk                            =>  c3_clk0,
+   p3_rd_en                             =>  c3_p3_rd_en,
+   p3_rd_data                           =>  c3_p3_rd_data,
+   p3_rd_full                           =>  c3_p3_rd_full,
+   p3_rd_empty                          =>  c3_p3_rd_empty,
+   p3_rd_count                          =>  c3_p3_rd_count,
+   p3_rd_overflow                       =>  c3_p3_rd_overflow,
+   p3_rd_error                          =>  c3_p3_rd_error,
+   selfrefresh_enter                    =>  c3_selfrefresh_enter,
+   selfrefresh_mode                     =>  c3_selfrefresh_mode
+);
+
+ memc3_tb_top_inst : memc3_tb_top
+
+generic map
+ (
+   C_SIMULATION                      => C3_SIMULATION,
+   C_P0_MASK_SIZE                    => C3_P0_MASK_SIZE,
+   C_P0_DATA_PORT_SIZE               => C3_P0_DATA_PORT_SIZE,
+   C_P1_MASK_SIZE                    => C3_P1_MASK_SIZE,
+   C_P1_DATA_PORT_SIZE               => C3_P1_DATA_PORT_SIZE,
+   C_NUM_DQ_PINS                     => C3_NUM_DQ_PINS,
+   C_MEM_BURST_LEN                   => C3_MEM_BURST_LEN,
+   C_MEM_NUM_COL_BITS                => C3_MEM_NUM_COL_BITS,
+   C_SMALL_DEVICE                    => C3_SMALL_DEVICE,
+   C_p0_BEGIN_ADDRESS                       =>  C3_p0_BEGIN_ADDRESS, 
+   C_p0_DATA_MODE                           =>  C3_p0_DATA_MODE, 
+   C_p0_END_ADDRESS                         =>  C3_p0_END_ADDRESS, 
+   C_p0_PRBS_EADDR_MASK_POS                 =>  C3_p0_PRBS_EADDR_MASK_POS, 
+   C_p0_PRBS_SADDR_MASK_POS                 =>  C3_p0_PRBS_SADDR_MASK_POS, 
+   C_p1_BEGIN_ADDRESS                       =>  C3_p1_BEGIN_ADDRESS, 
+   C_p1_DATA_MODE                           =>  C3_p1_DATA_MODE, 
+   C_p1_END_ADDRESS                         =>  C3_p1_END_ADDRESS, 
+   C_p1_PRBS_EADDR_MASK_POS                 =>  C3_p1_PRBS_EADDR_MASK_POS, 
+   C_p1_PRBS_SADDR_MASK_POS                 =>  C3_p1_PRBS_SADDR_MASK_POS, 
+   C_p2_BEGIN_ADDRESS                       =>  C3_p2_BEGIN_ADDRESS, 
+   C_p2_DATA_MODE                           =>  C3_p2_DATA_MODE, 
+   C_p2_END_ADDRESS                         =>  C3_p2_END_ADDRESS, 
+   C_p2_PRBS_EADDR_MASK_POS                 =>  C3_p2_PRBS_EADDR_MASK_POS, 
+   C_p2_PRBS_SADDR_MASK_POS                 =>  C3_p2_PRBS_SADDR_MASK_POS, 
+   C_p3_BEGIN_ADDRESS                       =>  C3_p3_BEGIN_ADDRESS, 
+   C_p3_DATA_MODE                           =>  C3_p3_DATA_MODE, 
+   C_p3_END_ADDRESS                         =>  C3_p3_END_ADDRESS, 
+   C_p3_PRBS_EADDR_MASK_POS                 =>  C3_p3_PRBS_EADDR_MASK_POS, 
+   C_p3_PRBS_SADDR_MASK_POS                 =>  C3_p3_PRBS_SADDR_MASK_POS 
+   )
+port map
+(
+   error                           => c3_error,
+   calib_done                      => c3_calib_done,
+   clk0                            => c3_clk0,
+   rst0                            => c3_rst0,
+   cmp_error                       => c3_cmp_error,
+   cmp_data_valid                  => c3_cmp_data_valid,
+   vio_modify_enable               => c3_vio_modify_enable,
+   error_status                    => c3_error_status,
+   vio_data_mode_value             => c3_vio_data_mode_value,
+   vio_addr_mode_value             => c3_vio_addr_mode_value,
+   cmp_data                        => c3_cmp_data,
+   p0_mcb_cmd_en_o                          =>  c3_p0_cmd_en,
+   p0_mcb_cmd_instr_o                       =>  c3_p0_cmd_instr,
+   p0_mcb_cmd_bl_o                          =>  c3_p0_cmd_bl,
+   p0_mcb_cmd_addr_o                        =>  c3_p0_cmd_byte_addr,
+   p0_mcb_cmd_full_i                        =>  c3_p0_cmd_full,
+   p0_mcb_wr_en_o                           =>  c3_p0_wr_en,
+   p0_mcb_wr_mask_o                         =>  c3_p0_wr_mask,
+   p0_mcb_wr_data_o                         =>  c3_p0_wr_data,
+   p0_mcb_wr_full_i                         =>  c3_p0_wr_full,
+   p0_mcb_wr_fifo_counts                    =>  c3_p0_wr_count,
+   p0_mcb_rd_en_o                           =>  c3_p0_rd_en,
+   p0_mcb_rd_data_i                         =>  c3_p0_rd_data,
+   p0_mcb_rd_empty_i                        =>  c3_p0_rd_empty,
+   p0_mcb_rd_fifo_counts                    =>  c3_p0_rd_count,
+   p1_mcb_cmd_en_o                          =>  c3_p1_cmd_en,
+   p1_mcb_cmd_instr_o                       =>  c3_p1_cmd_instr,
+   p1_mcb_cmd_bl_o                          =>  c3_p1_cmd_bl,
+   p1_mcb_cmd_addr_o                        =>  c3_p1_cmd_byte_addr,
+   p1_mcb_cmd_full_i                        =>  c3_p1_cmd_full,
+   p1_mcb_wr_en_o                           =>  c3_p1_wr_en,
+   p1_mcb_wr_mask_o                         =>  c3_p1_wr_mask,
+   p1_mcb_wr_data_o                         =>  c3_p1_wr_data,
+   p1_mcb_wr_full_i                         =>  c3_p1_wr_full,
+   p1_mcb_wr_fifo_counts                    =>  c3_p1_wr_count,
+   p1_mcb_rd_en_o                           =>  c3_p1_rd_en,
+   p1_mcb_rd_data_i                         =>  c3_p1_rd_data,
+   p1_mcb_rd_empty_i                        =>  c3_p1_rd_empty,
+   p1_mcb_rd_fifo_counts                    =>  c3_p1_rd_count,
+   p2_mcb_cmd_en_o                          =>  c3_p2_cmd_en,
+   p2_mcb_cmd_instr_o                       =>  c3_p2_cmd_instr,
+   p2_mcb_cmd_bl_o                          =>  c3_p2_cmd_bl,
+   p2_mcb_cmd_addr_o                        =>  c3_p2_cmd_byte_addr,
+   p2_mcb_cmd_full_i                        =>  c3_p2_cmd_full,
+   p2_mcb_wr_en_o                           =>  c3_p2_wr_en,
+   p2_mcb_wr_mask_o                         =>  c3_p2_wr_mask,
+   p2_mcb_wr_data_o                         =>  c3_p2_wr_data,
+   p2_mcb_wr_full_i                         =>  c3_p2_wr_full,
+   p2_mcb_wr_fifo_counts                    =>  c3_p2_wr_count,
+   p2_mcb_rd_en_o                           =>  c3_p2_rd_en,
+   p2_mcb_rd_data_i                         =>  c3_p2_rd_data,
+   p2_mcb_rd_empty_i                        =>  c3_p2_rd_empty,
+   p2_mcb_rd_fifo_counts                    =>  c3_p2_rd_count,
+   p3_mcb_cmd_en_o                          =>  c3_p3_cmd_en,
+   p3_mcb_cmd_instr_o                       =>  c3_p3_cmd_instr,
+   p3_mcb_cmd_bl_o                          =>  c3_p3_cmd_bl,
+   p3_mcb_cmd_addr_o                        =>  c3_p3_cmd_byte_addr,
+   p3_mcb_cmd_full_i                        =>  c3_p3_cmd_full,
+   p3_mcb_wr_en_o                           =>  c3_p3_wr_en,
+   p3_mcb_wr_mask_o                         =>  c3_p3_wr_mask,
+   p3_mcb_wr_data_o                         =>  c3_p3_wr_data,
+   p3_mcb_wr_full_i                         =>  c3_p3_wr_full,
+   p3_mcb_wr_fifo_counts                    =>  c3_p3_wr_count,
+   p3_mcb_rd_en_o                           =>  c3_p3_rd_en,
+   p3_mcb_rd_data_i                         =>  c3_p3_rd_data,
+   p3_mcb_rd_empty_i                        =>  c3_p3_rd_empty,
+   p3_mcb_rd_fifo_counts                    =>  c3_p3_rd_count
+  );
+
+ 
+  
+
+ end  arc;
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_controller.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_controller.vhd
new file mode 100755
index 0000000..f0a4b52
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_controller.vhd
@@ -0,0 +1,372 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: iodrp_controller.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:25 $
+-- \   \  /  \    Date Created: Mon Feb 9 2009
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR
+--Purpose:  Xilinx reference design for IODRP controller for v0.9 device
+--
+--Reference:
+--
+--    Revision: Date:       Comment
+--    1.0:      02/06/09:   Initial version for MIG wrapper.
+--    1.1:      02/01/09:   updates to indentations.
+--    1.2:      02/12/09:   changed non-blocking assignments to blocking ones
+--                          for state machine always block.  Also, assigned
+--                          intial value to load_shift_n to avoid latch
+-- End Revision
+--*******************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+
+entity iodrp_controller is
+      --output to IODRP SDI pin
+      --input from IODRP SDO pin
+      
+      -- Register where memcell_address is captured during the READY state
+      -- Register which stores the write data until it is ready to be shifted out
+      -- The shift register which shifts out SDO and shifts in SDI.
+      -- This register is loaded before the address or data phase, but continues
+      -- to shift for a writeback of read data
+      -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
+      -- The signal which indicates where the shift_through_reg should load from.  0 -> data_reg  1 -> memcell_addr_reg
+      -- The counter for which bit is being shifted during address or data phase
+      -- This is set after the first address phase has executed
+      
+      --  (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate;
+      
+      -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
+      -- added so that DRP_SDI output is only active when DRP_CS is active
+      
+   port (
+      memcell_address    : in std_logic_vector(7 downto 0);
+      write_data         : in std_logic_vector(7 downto 0);
+      read_data          : out std_logic_vector(7 downto 0);
+      rd_not_write       : in std_logic;
+      cmd_valid          : in std_logic;
+      rdy_busy_n         : out std_logic;
+      use_broadcast      : in std_logic;
+      sync_rst           : in std_logic;
+      DRP_CLK            : in std_logic;
+      DRP_CS             : out std_logic;
+      DRP_SDI            : out std_logic;
+      DRP_ADD            : out std_logic;
+      DRP_BKST           : out std_logic;
+      DRP_SDO            : in std_logic
+   );
+end entity iodrp_controller;
+
+architecture trans of iodrp_controller is
+
+
+     constant READY              : std_logic_vector(2 downto 0) := "000";
+     constant DECIDE             : std_logic_vector(2 downto 0) := "001";
+     constant ADDR_PHASE         : std_logic_vector(2 downto 0) := "010";
+     constant ADDR_TO_DATA_GAP   : std_logic_vector(2 downto 0) := "011";
+     constant ADDR_TO_DATA_GAP2  : std_logic_vector(2 downto 0) := "100";
+     constant ADDR_TO_DATA_GAP3  : std_logic_vector(2 downto 0) := "101";
+     constant DATA_PHASE         : std_logic_vector(2 downto 0) := "110";
+     constant ALMOST_READY       : std_logic_vector(2 downto 0) := "111";
+      
+     constant IOI_DQ0            : std_logic_vector(4 downto 0) := "00001"; 
+     constant IOI_DQ1            : std_logic_vector(4 downto 0) := "00000"; 
+     constant IOI_DQ2            : std_logic_vector(4 downto 0) := "00011"; 
+     constant IOI_DQ3            : std_logic_vector(4 downto 0) := "00010"; 
+     constant IOI_DQ4            : std_logic_vector(4 downto 0) := "00101"; 
+     constant IOI_DQ5            : std_logic_vector(4 downto 0) := "00100"; 
+     constant IOI_DQ6            : std_logic_vector(4 downto 0) := "00111"; 
+     constant IOI_DQ7            : std_logic_vector(4 downto 0) := "00110"; 
+     constant IOI_DQ8            : std_logic_vector(4 downto 0) := "01001"; 
+     constant IOI_DQ9            : std_logic_vector(4 downto 0) := "01000"; 
+     constant IOI_DQ10           : std_logic_vector(4 downto 0) := "01011"; 
+     constant IOI_DQ11           : std_logic_vector(4 downto 0) := "01010"; 
+     constant IOI_DQ12           : std_logic_vector(4 downto 0) := "01101"; 
+     constant IOI_DQ13           : std_logic_vector(4 downto 0) := "01100"; 
+     constant IOI_DQ14           : std_logic_vector(4 downto 0) := "01111"; 
+     constant IOI_DQ15           : std_logic_vector(4 downto 0) := "01110"; 
+     constant IOI_UDQS_CLK       : std_logic_vector(4 downto 0) := "11101"; 
+     constant IOI_UDQS_PIN       : std_logic_vector(4 downto 0) := "11100"; 
+     constant IOI_LDQS_CLK       : std_logic_vector(4 downto 0) := "11111"; 
+     constant IOI_LDQS_PIN       : std_logic_vector(4 downto 0) := "11110"; 
+
+
+
+
+   signal memcell_addr_reg  : std_logic_vector(7 downto 0);
+   signal data_reg          : std_logic_vector(7 downto 0);
+   signal shift_through_reg : std_logic_vector(7 downto 0);
+   signal load_shift_n      : std_logic;
+   signal addr_data_sel_n   : std_logic;
+   signal bit_cnt           : std_logic_vector(2 downto 0);
+   signal rd_not_write_reg  : std_logic;
+   signal AddressPhase      : std_logic;
+   signal capture_read_data : std_logic;
+   signal state             : std_logic_vector(2 downto 0);
+   signal nextstate         : std_logic_vector(2 downto 0);
+   signal data_out_mux      : std_logic_vector(7 downto 0);
+   signal DRP_SDI_pre       : std_logic;
+
+   signal ALMOST_READY_ST   : std_logic;
+   signal ADDR_PHASE_ST     : std_logic;
+   signal BIT_CNT7          : std_logic;
+   signal ADDR_PHASE_ST1     : std_logic;
+   signal DATA_PHASE_ST     : std_logic;
+
+   signal state_ascii       : std_logic_vector(32 * 8 - 1 downto 0);
+begin
+   --synthesis translate_off
+   
+--   process (state)
+--   begin
+--      case state is
+--         when READY =>
+--            state_ascii <= "READY";
+--         when DECIDE =>
+--            state_ascii <= "DECIDE";
+--         when ADDR_PHASE =>
+--            state_ascii <= "ADDR_PHASE";
+--         when ADDR_TO_DATA_GAP =>
+--            state_ascii <= "ADDR_TO_DATA_GAP";
+--         when ADDR_TO_DATA_GAP2 =>
+--            state_ascii <= "ADDR_TO_DATA_GAP2";
+--         when ADDR_TO_DATA_GAP3 =>
+--            state_ascii <= "ADDR_TO_DATA_GAP3";
+--         when DATA_PHASE =>
+--            state_ascii <= "DATA_PHASE";
+--         when ALMOST_READY =>		-- case(state)
+--            state_ascii <= "ALMOST_READY";
+--         when others =>
+--            null;
+--      end case;
+--   end process;
+   
+   --synthesis translate_on
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (state = READY) then
+            memcell_addr_reg <= memcell_address;
+            data_reg <= write_data;
+            rd_not_write_reg <= rd_not_write;
+         end if;
+      end if;
+   end process;
+   
+   
+   rdy_busy_n <= '1' when (state = READY) else '0';
+   
+   data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else
+                   data_reg;
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            shift_through_reg <= "00000000";
+         else
+            if (load_shift_n = '1') then		--Assume the shifter is either loading or shifting, bit 0 is shifted out first
+               shift_through_reg <= data_out_mux;
+            else
+               shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1));
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
+            bit_cnt <= bit_cnt + "001";
+         else
+            bit_cnt <= "000";
+         end if;
+      end if;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            --     capture_read_data <= 1'b0;
+            read_data <= "00000000";
+         else
+            --       capture_read_data <= (state == DATA_PHASE);
+            --       if(capture_read_data)
+            if (state = ALMOST_READY) then
+               --      else
+               --        read_data <= read_data;
+               read_data <= shift_through_reg;
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0';
+   ADDR_PHASE_ST   <= '1' when state = ADDR_PHASE else '0';
+   BIT_CNT7         <= '1' when bit_cnt = "111" else '0';
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            AddressPhase <= '0';
+         else
+            if (AddressPhase = '1') then
+               -- Keep it set until we finish the cycle
+               AddressPhase <= AddressPhase and (not ALMOST_READY_ST);
+            else
+               -- set the address phase when ever we finish the address phase
+               AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
+            end if;
+         end if;
+      end if;
+   end process;
+   
+ADDR_PHASE_ST1 <= '1' when  nextstate = ADDR_PHASE else '0';
+DATA_PHASE_ST <= '1' when  nextstate = DATA_PHASE else '0';
+
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         DRP_ADD <= ADDR_PHASE_ST1;
+         DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
+         if (state = READY) then
+            DRP_BKST <= use_broadcast;
+         end if;
+      end if;
+   end process;
+   
+   
+   --  assign DRP_SDI_pre  = (DRP_CS)? shift_through_reg[0] : 1'b0;  //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
+   --  assign DRP_SDI      = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
+   DRP_SDI <= shift_through_reg(0);		-- The new read method only requires that we shift out the address and the write data
+   
+   process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
+   begin
+      addr_data_sel_n <= '0';
+      load_shift_n <= '0';
+      case state is
+         when READY =>
+            if (cmd_valid = '1') then
+               nextstate <= DECIDE;
+            else
+               nextstate <= READY;
+            end if;
+         when DECIDE =>
+            load_shift_n <= '1';
+            addr_data_sel_n <= '1';
+            nextstate <= ADDR_PHASE;
+         -- After the second pass go to end of statemachine
+         -- execute a second address phase for the read access.
+         when ADDR_PHASE =>
+            if (BIT_CNT7 = '1') then
+               if (rd_not_write_reg = '1') then
+                  if (AddressPhase = '1') then
+                     nextstate <= ALMOST_READY;
+                  else
+                     nextstate <= DECIDE;
+                  end if;
+               else
+                  nextstate <= ADDR_TO_DATA_GAP;
+               end if;
+            else
+               nextstate <= ADDR_PHASE;
+            end if;
+         when ADDR_TO_DATA_GAP =>
+            load_shift_n <= '1';
+            nextstate <= ADDR_TO_DATA_GAP2;
+         when ADDR_TO_DATA_GAP2 =>
+            load_shift_n <= '1';
+            nextstate <= ADDR_TO_DATA_GAP3;
+         when ADDR_TO_DATA_GAP3 =>
+            load_shift_n <= '1';
+            nextstate <= DATA_PHASE;
+         when DATA_PHASE =>
+            if (BIT_CNT7 = '1') then
+               nextstate <= ALMOST_READY;
+            else
+               nextstate <= DATA_PHASE;
+            end if;
+         when ALMOST_READY =>
+            nextstate <= READY;
+         when others =>
+            nextstate <= READY;
+      end case;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            state <= READY;
+         else
+            state <= nextstate;
+         end if;
+      end if;
+   end process;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_mcb_controller.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_mcb_controller.vhd
new file mode 100755
index 0000000..22451be
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_mcb_controller.vhd
@@ -0,0 +1,517 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: iodrp_mcb_controller.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:25 $
+-- \   \  /  \    Date Created: Mon Feb 9 2009
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR
+--Purpose:  Xilinx reference design for IODRP controller for v0.9 device
+--
+--Reference:
+--
+--    Revision: Date:       Comment
+--    1.0:      03/19/09:   Initial version for IODRP_MCB read operations.
+--    1.1:      04/03/09:   SLH - Added left shift for certain IOI's   
+--    1.2:      02/14/11:   Change FSM encoding from one-hot to gray to match Verilog version.
+-- End Revision
+--*******************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+
+entity iodrp_mcb_controller is
+      --output to IODRP SDI pin
+      --input from IODRP SDO pin
+      
+      -- Register where memcell_address is captured during the READY state
+      -- Register which stores the write data until it is ready to be shifted out
+      -- The shift register which shifts out SDO and shifts in SDI.
+      --    This register is loaded before the address or data phase, but continues to shift for a writeback of read data
+      -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
+      -- The signal which indicates where the shift_through_reg should load from.  0 -> data_reg  1 -> memcell_addr_reg
+      -- The counter for which bit is being shifted during address or data phase
+      -- This is set after the first address phase has executed
+      
+      -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
+      --added so that DRP_SDI output is only active when DRP_CS is active
+   port (
+      memcell_address    : in std_logic_vector(7 downto 0);
+      write_data         : in std_logic_vector(7 downto 0);
+      read_data          : out std_logic_vector(7 downto 0);
+      rd_not_write       : in std_logic;
+      cmd_valid          : in std_logic;
+      rdy_busy_n         : out std_logic;
+      use_broadcast      : in std_logic;
+      drp_ioi_addr       : in std_logic_vector(4 downto 0);
+      sync_rst           : in std_logic;
+      DRP_CLK            : in std_logic;
+      DRP_CS             : out std_logic;
+      DRP_SDI            : out std_logic;
+      DRP_ADD            : out std_logic;
+      DRP_BKST           : out std_logic;
+      DRP_SDO            : in std_logic;
+      MCB_UIREAD         : out std_logic
+   );
+end entity iodrp_mcb_controller;
+
+architecture trans of iodrp_mcb_controller is
+
+
+    type StType is (
+    
+    READY,
+    DECIDE  ,         
+    ADDR_PHASE ,      
+    ADDR_TO_DATA_GAP ,
+    ADDR_TO_DATA_GAP2,
+    ADDR_TO_DATA_GAP3,
+    DATA_PHASE ,      
+    
+    ALMOST_READY  ,   
+    ALMOST_READY2 ,   
+    ALMOST_READY3    
+        
+    );
+
+
+      
+     constant IOI_DQ0            : std_logic_vector(4 downto 0) := "00001"; 
+     constant IOI_DQ1            : std_logic_vector(4 downto 0) := "00000"; 
+     constant IOI_DQ2            : std_logic_vector(4 downto 0) := "00011"; 
+     constant IOI_DQ3            : std_logic_vector(4 downto 0) := "00010"; 
+     constant IOI_DQ4            : std_logic_vector(4 downto 0) := "00101"; 
+     constant IOI_DQ5            : std_logic_vector(4 downto 0) := "00100"; 
+     constant IOI_DQ6            : std_logic_vector(4 downto 0) := "00111"; 
+     constant IOI_DQ7            : std_logic_vector(4 downto 0) := "00110"; 
+     constant IOI_DQ8            : std_logic_vector(4 downto 0) := "01001"; 
+     constant IOI_DQ9            : std_logic_vector(4 downto 0) := "01000"; 
+     constant IOI_DQ10           : std_logic_vector(4 downto 0) := "01011"; 
+     constant IOI_DQ11           : std_logic_vector(4 downto 0) := "01010"; 
+     constant IOI_DQ12           : std_logic_vector(4 downto 0) := "01101"; 
+     constant IOI_DQ13           : std_logic_vector(4 downto 0) := "01100"; 
+     constant IOI_DQ14           : std_logic_vector(4 downto 0) := "01111"; 
+     constant IOI_DQ15           : std_logic_vector(4 downto 0) := "01110"; 
+     constant IOI_UDQS_CLK       : std_logic_vector(4 downto 0) := "11101"; 
+     constant IOI_UDQS_PIN       : std_logic_vector(4 downto 0) := "11100"; 
+     constant IOI_LDQS_CLK       : std_logic_vector(4 downto 0) := "11111"; 
+     constant IOI_LDQS_PIN       : std_logic_vector(4 downto 0) := "11110"; 
+
+
+   signal memcell_addr_reg  : std_logic_vector(7 downto 0);
+   signal data_reg          : std_logic_vector(7 downto 0);
+   signal shift_through_reg : std_logic_vector(8 downto 0);
+   signal load_shift_n      : std_logic;
+   signal addr_data_sel_n   : std_logic;
+   signal bit_cnt           : std_logic_vector(2 downto 0);
+   signal rd_not_write_reg  : std_logic;
+   signal AddressPhase      : std_logic;
+   signal DRP_CS_pre        : std_logic;
+   signal extra_cs          : std_logic;
+   
+   
+   signal state,nextstate : StType;
+   
+   attribute fsm_encoding : string;
+   attribute fsm_encoding of state : signal is "gray";
+   attribute fsm_encoding of nextstate : signal is "gray";
+   
+   signal data_out          : std_logic_vector(8 downto 0);
+   signal data_out_mux      : std_logic_vector(8 downto 0);
+   signal DRP_SDI_pre       : std_logic;
+   
+   --synthesis translate_off
+   signal state_ascii       : std_logic_vector(32 * 8 - 1 downto 0);
+   -- case(state)
+   --synthesis translate_on
+   
+   -- The changes below are to compensate for an issue with 1.0 silicon.
+   -- It may still be necessary to add a clock cycle to the ADD and CS signals
+   
+   --`define DRP_v1_0_FIX    // Uncomment out this line for synthesis
+   
+   procedure shift_n_expand(
+      data_in            : in std_logic_vector(7 downto 0);
+      data_out           : out std_logic_vector(8 downto 0)) is
+   
+      variable data_out_xilinx2 : std_logic_vector(8 downto 0);
+      begin
+      if ((data_in(0)) = '1') then
+         data_out_xilinx2(1 downto 0) := "11";
+      else
+         
+         data_out_xilinx2(1 downto 0) := "00";
+      end if;
+      if (data_in(1 downto 0) = "10") then
+         data_out_xilinx2(2 downto 1) := "11";
+      else
+         
+         data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
+      end if;
+      if (data_in(2 downto 1) = "10") then
+         data_out_xilinx2(3 downto 2) := "11";
+      else
+         
+         data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
+      end if;
+      if (data_in(3 downto 2) = "10") then
+         data_out_xilinx2(4 downto 3) := "11";
+      else
+         
+         data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
+      end if;
+      if (data_in(4 downto 3) = "10") then
+         data_out_xilinx2(5 downto 4) := "11";
+      else
+         
+         data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
+      end if;
+      if (data_in(5 downto 4) = "10") then
+         data_out_xilinx2(6 downto 5) := "11";
+      else
+         
+         data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
+      end if;
+      if (data_in(6 downto 5) = "10") then
+         data_out_xilinx2(7 downto 6) := "11";
+      else
+         
+         data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
+      end if;
+      if (data_in(7 downto 6) = "10") then
+         data_out_xilinx2(8 downto 7) := "11";
+      else
+         data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
+      end if;
+   end shift_n_expand;
+   
+   
+   -- Declare intermediate signals for referenced outputs
+   signal DRP_CS_xilinx1    : std_logic;
+   signal DRP_ADD_xilinx0   : std_logic;
+
+   signal ALMOST_READY2_ST : std_logic;
+   signal ADDR_PHASE_ST     : std_logic;
+   signal BIT_CNT7          : std_logic;
+   signal ADDR_PHASE_ST1     : std_logic;
+   signal DATA_PHASE_ST     : std_logic;
+
+begin
+   -- Drive referenced outputs
+   DRP_CS <= DRP_CS_xilinx1;
+   DRP_ADD <= DRP_ADD_xilinx0;
+
+
+--   process (state)
+--   begin
+--      case state is
+--         when READY =>
+--            state_ascii <= "READY";
+--         when DECIDE =>
+--            state_ascii <= "DECIDE";
+--         when ADDR_PHASE =>
+--            state_ascii <= "ADDR_PHASE";
+--         when ADDR_TO_DATA_GAP =>
+--            state_ascii <= "ADDR_TO_DATA_GAP";
+--         when ADDR_TO_DATA_GAP2 =>
+--            state_ascii <= "ADDR_TO_DATA_GAP2";
+--         when ADDR_TO_DATA_GAP3 =>
+--            state_ascii <= "ADDR_TO_DATA_GAP3";
+--         when DATA_PHASE =>
+--            state_ascii <= "DATA_PHASE";
+--         when ALMOST_READY =>
+--            state_ascii <= "ALMOST_READY";
+--         when ALMOST_READY2 =>
+--            state_ascii <= "ALMOST_READY2";
+--         when ALMOST_READY3 =>
+--            state_ascii <= "ALMOST_READY3";
+--         when others =>
+--            null;
+--      end case;
+--   end process;
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (state = READY) then
+            memcell_addr_reg <= memcell_address;
+            data_reg <= write_data;
+            rd_not_write_reg <= rd_not_write;
+         end if;
+      end if;
+   end process;
+   
+   rdy_busy_n <= '1'  when state = READY else '0';
+   
+   process (drp_ioi_addr, data_out)
+   begin
+      
+      case drp_ioi_addr is
+         when IOI_DQ0 =>
+            data_out_mux <= data_out;
+         when IOI_DQ1 =>
+            data_out_mux <= data_out;
+         when IOI_DQ2 =>
+            data_out_mux <= data_out;
+         when IOI_DQ3 =>
+            data_out_mux <= data_out;
+         when IOI_DQ4 =>
+            data_out_mux <= data_out;
+         when IOI_DQ5 =>
+            data_out_mux <= data_out;
+         when IOI_DQ6 =>
+            data_out_mux <= data_out;
+         when IOI_DQ7 =>
+            data_out_mux <= data_out;
+         when IOI_DQ8 =>
+            data_out_mux <= data_out;
+         when IOI_DQ9 =>
+            data_out_mux <= data_out;
+         when IOI_DQ10 =>
+            data_out_mux <= data_out;
+         when IOI_DQ11 =>
+            data_out_mux <= data_out;
+         when IOI_DQ12 =>
+            data_out_mux <= data_out;
+         when IOI_DQ13 =>
+            data_out_mux <= data_out;
+         when IOI_DQ14 =>
+            data_out_mux <= data_out;
+         when IOI_DQ15 =>
+            data_out_mux <= data_out;
+         when IOI_UDQS_CLK =>
+            data_out_mux <= data_out;
+         when IOI_UDQS_PIN =>
+            data_out_mux <= data_out;
+         when IOI_LDQS_CLK =>
+            data_out_mux <= data_out;
+         when IOI_LDQS_PIN =>
+            data_out_mux <= data_out;
+         when others =>
+            data_out_mux <= data_out;
+      end case;
+   end process;
+   
+   
+   data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
+               ('0' & data_reg);
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            shift_through_reg <= "000000000";
+         else
+            if (load_shift_n = '1') then                --Assume the shifter is either loading or shifting, bit 0 is shifted out first
+               shift_through_reg <= data_out_mux;
+            else
+               shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then
+            bit_cnt <= bit_cnt + "001";
+         else
+            bit_cnt <= "000";
+         end if;
+      end if;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            read_data <= "00000000";
+         else
+            if (state = ALMOST_READY3) then
+               read_data <= shift_through_reg(7 downto 0);
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
+   ADDR_PHASE_ST   <= '1' when state = ADDR_PHASE else '0';
+   BIT_CNT7         <= '1' when bit_cnt = "111" else '0';
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            AddressPhase <= '0';
+         else
+            if (AddressPhase = '1') then
+               -- Keep it set until we finish the cycle
+               AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
+            else
+               -- set the address phase when ever we finish the address phase
+               AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
+            end if;
+         end if;
+      end if;
+   end process;
+   
+ADDR_PHASE_ST1 <= '1' when  nextstate = ADDR_PHASE else '0';
+DATA_PHASE_ST <= '1' when  nextstate = DATA_PHASE else '0';
+
+
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
+         --      DRP_CS      <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
+         DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
+         MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
+         if (state = READY) then
+            DRP_BKST <= use_broadcast;
+         end if;
+      end if;
+   end process;
+   
+   
+   DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else         --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
+                  '0';
+   DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else          --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
+              DRP_SDI_pre;
+   
+   process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
+   begin
+      addr_data_sel_n <= '0';
+      load_shift_n <= '0';
+      case state is
+         when READY =>
+            load_shift_n <= '0';
+            if (cmd_valid = '1') then
+               nextstate <= DECIDE;
+            else
+               nextstate <= READY;
+            end if;
+         when DECIDE =>
+            load_shift_n <= '1';
+            addr_data_sel_n <= '1';
+            nextstate <= ADDR_PHASE;
+         -- After the second pass go to end of statemachine
+         -- execute a second address phase for the alternative access method.
+         when ADDR_PHASE =>
+            load_shift_n <= '0';
+            if (BIT_CNT7 = '1') then
+               if (('1' and rd_not_write_reg) = '1') then
+                  if (AddressPhase = '1') then
+                     nextstate <= ALMOST_READY;
+                  else
+                     nextstate <= DECIDE;
+                  end if;
+               else
+                  nextstate <= ADDR_TO_DATA_GAP;
+               end if;
+            else
+               nextstate <= ADDR_PHASE;
+            end if;
+         when ADDR_TO_DATA_GAP =>
+            load_shift_n <= '1';
+            nextstate <= ADDR_TO_DATA_GAP2;
+         when ADDR_TO_DATA_GAP2 =>
+            load_shift_n <= '1';
+            nextstate <= ADDR_TO_DATA_GAP3;
+         when ADDR_TO_DATA_GAP3 =>
+            load_shift_n <= '1';
+            nextstate <= DATA_PHASE;
+         when DATA_PHASE =>
+            load_shift_n <= '0';
+            if (BIT_CNT7 = '1') then
+               nextstate <= ALMOST_READY;
+            else
+               nextstate <= DATA_PHASE;
+            end if;
+         when ALMOST_READY =>
+            load_shift_n <= '0';
+            nextstate <= ALMOST_READY2;
+         when ALMOST_READY2 =>
+            load_shift_n <= '0';
+            nextstate <= ALMOST_READY3;
+         when ALMOST_READY3 =>
+            load_shift_n <= '0';
+            nextstate <= READY;
+         when others =>
+            load_shift_n <= '0';
+            nextstate <= READY;
+      end case;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            state <= READY;
+         else
+            state <= nextstate;
+         end if;
+      end if;
+   end process;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_raw_wrapper.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_raw_wrapper.vhd
new file mode 100755
index 0000000..51dc7cc
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_raw_wrapper.vhd
@@ -0,0 +1,7117 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_raw_wrapper.v
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:04 $
+-- \   \  /  \    Date Created: Thu June 24 2008
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR 
+--Purpose:
+--Reference:
+--   This module is the intialization control logic of the memory interface.
+--   All commands are issued from here acoording to the burst, CAS Latency and
+--   the user commands.
+--   
+-- Revised History:  
+--    Rev 1.1 - added port_enable assignment for all configurations  and rearrange 
+--              assignment siganls according to port number
+--            - added timescale directive  -SN 7-28-08
+--            - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through 
+--              15 -SN 7-28-08
+--            - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
+--            - removed ghighb, gpwrdnb, gsr, gwe in port declaration. 
+--              For now tb need to force the signals inside the MCB and Wrapper
+--              until a glbl.v is ready.  Not sure how to do this in NCVerilog 
+--              flow. -SN 7-28-08
+--
+--    Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
+--    Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5   - SN 8-8-08
+--    Rev 1.4 -- update changes that required by MCB core.  - SN 9-11-09
+--    Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
+--               delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90 
+--               delay_we_90 ,delay_address,delay_ba_90 =
+--              --removed :assign #50 delay_dqnum = dqnum;
+--              --removed :assign #50 delay_dqpum = dqpum;
+--              --removed :assign #50 delay_dqnlm = dqnlm;
+--              --removed :assign #50 delay_dqplm = dqplm;
+--              --removed : delay_dqsIO_w_en_90_n
+--              --removed : delay_dqsIO_w_en_90_p              
+--              --removed : delay_dqsIO_w_en_0     
+--              -- corrected spelling error: C_MEM_RTRAS
+--    Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip.  1-12-09              
+--                 -- rename the memc_wrapper.v to mcb_raw_wrapper.v
+--    Rev 1.7  -- --  .READEN    is removed in IODRP2_MCB 1-28-09
+--              -- connection has been updated                            
+--    Rev 1.8   -- update memory parameter equations.    1-30_2009
+--              -- added portion of Soft IP               
+--              -- CAL_CLK_DIV is not used but MCB still has it
+--    Rev  1.9  -- added Error checking for Invalid command to unidirectional port   
+--    Rev  1.10 -- changed the backend connection so that Simulation will work while
+--                 sw tools try to fix the model issues.                  2-3-2009      
+--                 sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
+--                 It is acutally 180 degree difference.
+--    Rev  1.11 -- Added MCB_Soft_Calibration_top. 
+--    Rev  1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009   
+--    Rev  1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
+--    Rev  1.14 -- Added minium condition for tRTP valud/                        
+--    REv  1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top.  6-16-2009
+--    Rev  1.16 -- Fixed the WTR for DDR. 6-23-2009
+--    Rev  1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
+--    Rev  1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
+--    Rev  1.19 -- Added soft fix to support refresh command. 7-15-2009.
+--    Rev  1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
+--                 Dynamic DQS calibration in Soft Calibration module.
+--    Rev  1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
+--                 RTT value is set to "disabled"
+--              -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
+--              -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010                
+--    Rev  1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
+--    Rev  1.23 -- Fixed  CR 558661.  In Config "B64B64" mode, mig_p5_wr_data  <= p1_wr_data(63 downto 32).
+--    Rev  1.24 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE"
+--    Rev  1.25 -- Fixed reset problem when MCB exits from SUSPEND SELFREFRESH mode. 10-20-2010	 
+--    Rev  1.26 -- Synchronize sys_rst before connecting to mcb_soft_calibration module to fix
+--                 CDC static timing issue.	 2-14-2011
+
+
+--*************************************************************************************************************************
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+library unisim;
+use unisim.vcomponents.all;
+
+entity mcb_raw_wrapper is
+generic(
+      C_MEMCLK_PERIOD                  : integer := 2500;
+      C_PORT_ENABLE                    : std_logic_vector(5 downto 0) := (others => '1');
+
+      C_MEM_ADDR_ORDER                 : string := "BANK_ROW_COLUMN";
+      
+      C_ARB_NUM_TIME_SLOTS             : integer := 12;
+      C_ARB_TIME_SLOT_0                : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
+      C_ARB_TIME_SLOT_1                : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
+      C_ARB_TIME_SLOT_2                : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011"; 
+      C_ARB_TIME_SLOT_3                : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
+      C_ARB_TIME_SLOT_4                : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
+      C_ARB_TIME_SLOT_5                : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
+      C_ARB_TIME_SLOT_6                : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
+      C_ARB_TIME_SLOT_7                : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
+      C_ARB_TIME_SLOT_8                : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011"; 
+      C_ARB_TIME_SLOT_9                : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
+      C_ARB_TIME_SLOT_10               : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
+      C_ARB_TIME_SLOT_11               : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
+      C_PORT_CONFIG                    : string :=  "B32_B32_W32_W32_W32_W32";  
+
+      
+      C_MEM_TRAS                       : integer := 45000;
+      C_MEM_TRCD                       : integer := 12500;
+      C_MEM_TREFI                      : integer := 7800;
+      C_MEM_TRFC                       : integer := 127500;
+      C_MEM_TRP                        : integer := 12500;
+      C_MEM_TWR                        : integer := 15000;
+      C_MEM_TRTP                       : integer := 7500;
+      C_MEM_TWTR                       : integer := 7500;
+      
+      C_NUM_DQ_PINS                    : integer := 8;
+      C_MEM_TYPE                       : string := "DDR3";
+      C_MEM_DENSITY                    : string := "512M";
+      C_MEM_BURST_LEN                  : integer := 8;
+      
+      C_MEM_CAS_LATENCY                : integer := 4;
+      C_MEM_ADDR_WIDTH                 : integer := 13;
+      C_MEM_BANKADDR_WIDTH             : integer := 3;
+      C_MEM_NUM_COL_BITS               : integer := 11;
+      
+      C_MEM_DDR3_CAS_LATENCY           : integer := 7;
+      C_MEM_MOBILE_PA_SR               : string := "FULL";
+      C_MEM_DDR1_2_ODS                 : string := "FULL";
+      C_MEM_DDR3_ODS                   : string := "DIV6";
+      C_MEM_DDR2_RTT                   : string := "50OHMS";
+      C_MEM_DDR3_RTT                   : string := "DIV2";
+      C_MEM_MDDR_ODS                   : string := "FULL";
+      
+      C_MEM_DDR2_DIFF_DQS_EN           : string := "YES";
+      C_MEM_DDR2_3_PA_SR               : string := "OFF";
+      C_MEM_DDR3_CAS_WR_LATENCY        : integer := 5;
+      
+      C_MEM_DDR3_AUTO_SR               : string := "ENABLED";
+      C_MEM_DDR2_3_HIGH_TEMP_SR        : string := "NORMAL";
+      C_MEM_DDR3_DYN_WRT_ODT           : string := "OFF";
+      C_MEM_TZQINIT_MAXCNT             : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets 
+      
+      C_MC_CALIB_BYPASS                : string := "NO";
+      C_MC_CALIBRATION_RA              : bit_vector(15 downto 0) := X"0000";
+      C_MC_CALIBRATION_BA              : bit_vector(2 downto 0) := "000";
+
+      C_CALIB_SOFT_IP                  : string := "TRUE";
+      C_SKIP_IN_TERM_CAL               : integer := 0;        --provides option to skip the input termination calibration
+      C_SKIP_DYNAMIC_CAL               : integer := 0;        --provides option to skip the dynamic delay calibration
+      C_SKIP_DYN_IN_TERM               : integer := 1;        -- provides option to skip the input termination calibration
+      C_SIMULATION                     : string  := "FALSE";  -- Tells us whether the design is being simulated or implemented
+
+
+--- ADDED for 1.0 silicon support to bypass Calibration //////
+-- 07-10-09 chipl
+--////////////////////////////////////////////////////////////
+     LDQSP_TAP_DELAY_VAL                : integer := 0;
+     UDQSP_TAP_DELAY_VAL                : integer := 0;
+     LDQSN_TAP_DELAY_VAL                : integer := 0;
+     UDQSN_TAP_DELAY_VAL                : integer := 0;
+     DQ0_TAP_DELAY_VAL                  : integer := 0;  
+     DQ1_TAP_DELAY_VAL                  : integer := 0;  
+     DQ2_TAP_DELAY_VAL                  : integer := 0;  
+     DQ3_TAP_DELAY_VAL                  : integer := 0;  
+     DQ4_TAP_DELAY_VAL                  : integer := 0;  
+     DQ5_TAP_DELAY_VAL                  : integer := 0;  
+     DQ6_TAP_DELAY_VAL                  : integer := 0;  
+     DQ7_TAP_DELAY_VAL                  : integer := 0;  
+     DQ8_TAP_DELAY_VAL                  : integer := 0;  
+     DQ9_TAP_DELAY_VAL                  : integer := 0;  
+     DQ10_TAP_DELAY_VAL                  : integer := 0;  
+     DQ11_TAP_DELAY_VAL                  : integer := 0;  
+     DQ12_TAP_DELAY_VAL                  : integer := 0;  
+     DQ13_TAP_DELAY_VAL                  : integer := 0;  
+     DQ14_TAP_DELAY_VAL                  : integer := 0;  
+     DQ15_TAP_DELAY_VAL                  : integer := 0;  
+
+      C_MC_CALIBRATION_CA              : bit_vector(11 downto 0) := X"000";
+      C_MC_CALIBRATION_CLK_DIV         : integer := 1;
+      C_MC_CALIBRATION_MODE            : string := "CALIBRATION";
+      C_MC_CALIBRATION_DELAY           : string := "HALF";
+      
+      C_P0_MASK_SIZE                   : integer := 4;
+      C_P0_DATA_PORT_SIZE              : integer := 32;
+      C_P1_MASK_SIZE                   : integer := 4;
+      C_P1_DATA_PORT_SIZE              : integer := 32
+      );
+   PORT (
+
+      sysclk_2x                        : in std_logic;
+      sysclk_2x_180                    : in std_logic;
+      pll_ce_0                         : in std_logic;
+      pll_ce_90                        : in std_logic;
+      pll_lock                         : in std_logic;
+      sys_rst                          : in std_logic;
+      
+      p0_arb_en                        : in std_logic;
+      p0_cmd_clk                       : in std_logic;
+      p0_cmd_en                        : in std_logic;
+      p0_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p0_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p0_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p0_cmd_empty                     : out std_logic;
+      p0_cmd_full                      : out std_logic;
+
+      p0_wr_clk                        : in std_logic;
+      p0_wr_en                         : in std_logic;
+      p0_wr_mask                       : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+      p0_wr_data                       : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_wr_full                       : out std_logic;
+      p0_wr_empty                      : out std_logic;
+      p0_wr_count                      : out std_logic_vector(6 downto 0);
+      p0_wr_underrun                   : out std_logic;
+      p0_wr_error                      : out std_logic;
+
+      p0_rd_clk                        : in std_logic;
+      p0_rd_en                         : in std_logic;
+      p0_rd_data                       : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_rd_full                       : out std_logic;
+      p0_rd_empty                      : out std_logic;
+      p0_rd_count                      : out std_logic_vector(6 downto 0);
+      p0_rd_overflow                   : out std_logic;
+      p0_rd_error                      : out std_logic;
+
+      p1_arb_en                        : in std_logic;
+      p1_cmd_clk                       : in std_logic;
+      p1_cmd_en                        : in std_logic;
+      p1_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p1_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p1_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p1_cmd_empty                     : out std_logic;
+      p1_cmd_full                      : out std_logic;
+      p1_wr_clk                        : in std_logic;
+      p1_wr_en                         : in std_logic;
+      p1_wr_mask                       : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+      p1_wr_data                       : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_wr_full                       : out std_logic;
+      p1_wr_empty                      : out std_logic;
+      p1_wr_count                      : out std_logic_vector(6 downto 0);
+      p1_wr_underrun                   : out std_logic;
+      p1_wr_error                      : out std_logic;
+      p1_rd_clk                        : in std_logic;
+      p1_rd_en                         : in std_logic;
+      p1_rd_data                       : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_rd_full                       : out std_logic;
+      p1_rd_empty                      : out std_logic;
+      p1_rd_count                      : out std_logic_vector(6 downto 0);
+      p1_rd_overflow                   : out std_logic;
+      p1_rd_error                      : out std_logic;
+
+      p2_arb_en                        : in std_logic;
+      p2_cmd_clk                       : in std_logic;
+      p2_cmd_en                        : in std_logic;
+      p2_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p2_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p2_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p2_cmd_empty                     : out std_logic;
+      p2_cmd_full                      : out std_logic;
+      p2_wr_clk                        : in std_logic;
+      p2_wr_en                         : in std_logic;
+      p2_wr_mask                       : in std_logic_vector(3 downto 0);
+      p2_wr_data                       : in std_logic_vector(31 downto 0);
+      p2_wr_full                       : out std_logic;
+      p2_wr_empty                      : out std_logic;
+      p2_wr_count                      : out std_logic_vector(6 downto 0);
+      p2_wr_underrun                   : out std_logic;
+      p2_wr_error                      : out std_logic;
+      p2_rd_clk                        : in std_logic;
+      p2_rd_en                         : in std_logic;
+      p2_rd_data                       : out std_logic_vector(31 downto 0);
+      p2_rd_full                       : out std_logic;
+      p2_rd_empty                      : out std_logic;
+      p2_rd_count                      : out std_logic_vector(6 downto 0);
+      p2_rd_overflow                   : out std_logic;
+      p2_rd_error                      : out std_logic;
+
+      p3_arb_en                        : in std_logic;
+      p3_cmd_clk                       : in std_logic;
+      p3_cmd_en                        : in std_logic;
+      p3_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p3_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p3_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p3_cmd_empty                     : out std_logic;
+      p3_cmd_full                      : out std_logic;
+      p3_wr_clk                        : in std_logic;
+      p3_wr_en                         : in std_logic;
+      p3_wr_mask                       : in std_logic_vector(3 downto 0);
+      p3_wr_data                       : in std_logic_vector(31 downto 0);
+      p3_wr_full                       : out std_logic;
+      p3_wr_empty                      : out std_logic;
+      p3_wr_count                      : out std_logic_vector(6 downto 0);
+      p3_wr_underrun                   : out std_logic;
+      p3_wr_error                      : out std_logic;
+      p3_rd_clk                        : in std_logic;
+      p3_rd_en                         : in std_logic;
+      p3_rd_data                       : out std_logic_vector(31 downto 0);
+      p3_rd_full                       : out std_logic;
+      p3_rd_empty                      : out std_logic;
+      p3_rd_count                      : out std_logic_vector(6 downto 0);
+      p3_rd_overflow                   : out std_logic;
+      p3_rd_error                      : out std_logic;
+
+      p4_arb_en                        : in std_logic;
+      p4_cmd_clk                       : in std_logic;
+      p4_cmd_en                        : in std_logic;
+      p4_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p4_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p4_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p4_cmd_empty                     : out std_logic;
+      p4_cmd_full                      : out std_logic;
+      p4_wr_clk                        : in std_logic;
+      p4_wr_en                         : in std_logic;
+      p4_wr_mask                       : in std_logic_vector(3 downto 0);
+      p4_wr_data                       : in std_logic_vector(31 downto 0);
+      p4_wr_full                       : out std_logic;
+      p4_wr_empty                      : out std_logic;
+      p4_wr_count                      : out std_logic_vector(6 downto 0);
+      p4_wr_underrun                   : out std_logic;
+      p4_wr_error                      : out std_logic;
+      p4_rd_clk                        : in std_logic;
+      p4_rd_en                         : in std_logic;
+      p4_rd_data                       : out std_logic_vector(31 downto 0);
+      p4_rd_full                       : out std_logic;
+      p4_rd_empty                      : out std_logic;
+      p4_rd_count                      : out std_logic_vector(6 downto 0);
+      p4_rd_overflow                   : out std_logic;
+      p4_rd_error                      : out std_logic;
+
+      p5_arb_en                        : in std_logic;
+      p5_cmd_clk                       : in std_logic;
+      p5_cmd_en                        : in std_logic;
+      p5_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p5_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p5_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p5_cmd_empty                     : out std_logic;
+      p5_cmd_full                      : out std_logic;
+      p5_wr_clk                        : in std_logic;
+      p5_wr_en                         : in std_logic;
+      p5_wr_mask                       : in std_logic_vector(3 downto 0);
+      p5_wr_data                       : in std_logic_vector(31 downto 0);
+      p5_wr_full                       : out std_logic;
+      p5_wr_empty                      : out std_logic;
+      p5_wr_count                      : out std_logic_vector(6 downto 0);
+      p5_wr_underrun                   : out std_logic;
+      p5_wr_error                      : out std_logic;
+      p5_rd_clk                        : in std_logic;
+      p5_rd_en                         : in std_logic;
+      p5_rd_data                       : out std_logic_vector(31 downto 0);
+      p5_rd_full                       : out std_logic;
+      p5_rd_empty                      : out std_logic;
+      p5_rd_count                      : out std_logic_vector(6 downto 0);
+      p5_rd_overflow                   : out std_logic;
+      p5_rd_error                      : out std_logic;
+
+      mcbx_dram_addr                   : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
+      mcbx_dram_ba                     : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
+      mcbx_dram_ras_n                  : out std_logic;
+      mcbx_dram_cas_n                  : out std_logic;
+      mcbx_dram_we_n                   : out std_logic;
+      mcbx_dram_cke                    : out std_logic;
+      mcbx_dram_clk                    : out std_logic;
+      mcbx_dram_clk_n                  : out std_logic;
+      mcbx_dram_dq                     : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+      mcbx_dram_dqs                    : INOUT std_logic;
+      mcbx_dram_dqs_n                  : INOUT std_logic;
+      mcbx_dram_udqs                   : INOUT std_logic;
+      mcbx_dram_udqs_n                 : INOUT std_logic;
+      mcbx_dram_udm                    : out std_logic;
+      mcbx_dram_ldm                    : out std_logic;
+      mcbx_dram_odt                    : out std_logic;
+      mcbx_dram_ddr3_rst               : out std_logic;
+
+      calib_recal                      : in std_logic;
+      rzq                              : INOUT std_logic;
+      zio                              : INOUT std_logic;
+      ui_read                          : in std_logic;
+      ui_add                           : in std_logic;
+      ui_cs                            : in std_logic;
+      ui_clk                           : in std_logic;
+      ui_sdi                           : in std_logic;
+      ui_addr                          : in std_logic_vector(4 downto 0);
+      ui_broadcast                     : in std_logic;
+      ui_drp_update                    : in std_logic;
+      ui_done_cal                      : in std_logic;
+      ui_cmd                           : in std_logic;
+      ui_cmd_in                        : in std_logic;
+      ui_cmd_en                        : in std_logic;
+      ui_dqcount                       : in std_logic_vector(3 downto 0);
+      ui_dq_lower_dec                  : in std_logic;
+      ui_dq_lower_inc                  : in std_logic;
+      ui_dq_upper_dec                  : in std_logic;
+      ui_dq_upper_inc                  : in std_logic;
+      ui_udqs_inc                      : in std_logic;
+      ui_udqs_dec                      : in std_logic;
+      ui_ldqs_inc                      : in std_logic;
+      ui_ldqs_dec                      : in std_logic;
+      uo_data                          : out std_logic_vector(7 downto 0);
+      uo_data_valid                    : out std_logic;
+      uo_done_cal                      : out std_logic;
+      uo_cmd_ready_in                  : out std_logic;
+      uo_refrsh_flag                   : out std_logic;
+      uo_cal_start                     : out std_logic;
+      uo_sdo                           : out std_logic;
+      status                           : out std_logic_vector(31 downto 0);
+      selfrefresh_enter                : in std_logic;
+      selfrefresh_mode                 : out std_logic
+   );
+end mcb_raw_wrapper;
+
+ architecture aarch of mcb_raw_wrapper is
+   
+component mcb_soft_calibration_top is
+   generic (
+      C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets 
+      C_MC_CALIBRATION_MODE : string :=  "CALIBRATION";  -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
+                                                         --  and does dynamic recal,
+                                                         -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* 
+                                                         --  no dynamic recal will be done 
+      SKIP_IN_TERM_CAL      : integer := 0;             -- provides option to skip the input termination calibration
+      SKIP_DYNAMIC_CAL      : integer := 0;             -- provides option to skip the dynamic delay calibration
+      SKIP_DYN_IN_TERM      : integer := 0;             -- provides option to skip the dynamic delay calibration
+      C_SIMULATION          : string  := "FALSE";       -- Tells us whether the design is being simulated or implemented
+      C_MEM_TYPE            : string  := "DDR3"         -- provides the memory device used for the design
+
+   );
+   port (
+      UI_CLK                : in std_logic;             -- Input - global clock to be used for input_term_tuner and IODRP clock
+      RST                   : in std_logic;             -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for 
+                                                        --  IODRP (sub)controller
+      IOCLK                 : in std_logic;             -- Input - IOCLK input to the IODRP's
+      DONE_SOFTANDHARD_CAL  : out std_logic;            -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
+                                                        --  (MCB hard calib complete)
+      PLL_LOCK              : in std_logic;             -- Lock signal from PLL
+      SELFREFRESH_REQ       : in std_logic;             
+      SELFREFRESH_MCB_MODE  : in std_logic;             
+      SELFREFRESH_MCB_REQ   : out std_logic;            
+      SELFREFRESH_MODE      : out std_logic;            
+      MCB_UIADD             : out std_logic;            -- to MCB's UIADD port
+      MCB_UISDI             : out std_logic;            -- to MCB's UISDI port
+      MCB_UOSDO             : in std_logic;
+      MCB_UODONECAL         : in std_logic;
+      MCB_UOREFRSHFLAG      : in std_logic;
+      MCB_UICS              : out std_logic;
+      MCB_UIDRPUPDATE       : out std_logic;
+      MCB_UIBROADCAST       : out std_logic;
+      MCB_UIADDR            : out std_logic_vector(4 downto 0);
+      MCB_UICMDEN           : out std_logic;
+      MCB_UIDONECAL         : out std_logic;
+      MCB_UIDQLOWERDEC      : out std_logic;
+      MCB_UIDQLOWERINC      : out std_logic;
+      MCB_UIDQUPPERDEC      : out std_logic;
+      MCB_UIDQUPPERINC      : out std_logic;
+      MCB_UILDQSDEC         : out std_logic;
+      MCB_UILDQSINC         : out std_logic;
+      MCB_UIREAD            : out std_logic;
+      MCB_UIUDQSDEC         : out std_logic;
+      MCB_UIUDQSINC         : out std_logic;
+      MCB_RECAL             : out std_logic;
+      MCB_SYSRST            : out std_logic;
+      MCB_UICMD             : out std_logic;
+      MCB_UICMDIN           : out std_logic;
+      MCB_UIDQCOUNT         : out std_logic_vector(3 downto 0);
+      MCB_UODATA            : in std_logic_vector(7 downto 0);
+      MCB_UODATAVALID       : in std_logic;
+      MCB_UOCMDREADY        : in std_logic;
+      MCB_UO_CAL_START      : in std_logic;
+      RZQ_PIN               : inout std_logic;
+      ZIO_PIN               : inout std_logic;
+      CKE_Train             : out std_logic
+   );   
+end component;
+
+constant      C_OSERDES2_DATA_RATE_OQ          : STRING := "SDR";
+constant      C_OSERDES2_DATA_RATE_OT          : STRING := "SDR";
+constant      C_OSERDES2_SERDES_MODE_MASTER    : STRING := "MASTER";
+constant      C_OSERDES2_SERDES_MODE_SLAVE     : STRING := "SLAVE";
+constant      C_OSERDES2_OUTPUT_MODE_SE        : STRING := "SINGLE_ENDED";
+constant      C_OSERDES2_OUTPUT_MODE_DIFF      : STRING := "DIFFERENTIAL";
+      
+constant      C_BUFPLL_0_LOCK_SRC              : STRING := "LOCK_TO_0";
+      
+constant      C_DQ_IODRP2_DATA_RATE            : STRING := "SDR";
+constant      C_DQ_IODRP2_SERDES_MODE_MASTER   : STRING := "MASTER";
+constant      C_DQ_IODRP2_SERDES_MODE_SLAVE    : STRING := "SLAVE";
+      
+constant      C_DQS_IODRP2_DATA_RATE           : STRING := "SDR";
+constant      C_DQS_IODRP2_SERDES_MODE_MASTER  : STRING := "MASTER";
+constant      C_DQS_IODRP2_SERDES_MODE_SLAVE   : STRING := "SLAVE";
+
+-- MIG always set the below ADD_LATENCY to zero
+constant      C_MEM_DDR3_ADD_LATENCY           : STRING := "OFF";
+constant      C_MEM_DDR2_ADD_LATENCY           : INTEGER := 0;
+constant      C_MEM_MOBILE_TC_SR               : INTEGER := 0;
+
+-- convert the memory timing to memory clock units. I
+constant      MEM_RAS_VAL   : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+constant      MEM_RCD_VAL   : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+constant      MEM_REFI_VAL  : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD) - 25;
+constant      MEM_RFC_VAL   : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+constant      MEM_RP_VAL    : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+constant      MEM_WR_VAL    : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+
+ function cdiv return integer is
+  begin
+    if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
+      return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
+    else      
+    return (C_MEM_TRTP/C_MEMCLK_PERIOD);
+    end if;
+  end function cdiv;
+
+constant      MEM_RTP_VAL1                      : INTEGER := cdiv;
+
+
+function MEM_RTP_CYC1 return integer is
+  begin
+    if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
+      return 4;
+    else if(MEM_RTP_VAL1 < 2) then
+      return 2;
+    else
+      return MEM_RTP_VAL1;
+    end if;
+    end if;
+  end function MEM_RTP_CYC1;
+
+constant      MEM_RTP_VAL                      : INTEGER := MEM_RTP_CYC1;
+
+function MEM_WTR_CYC return integer is
+  begin
+    if (C_MEM_TYPE = "DDR") then
+      return 2;
+    elsif (C_MEM_TYPE = "DDR3") then
+      return 4;
+    elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
+      return C_MEM_TWTR;
+    elsif (C_MEM_TYPE = "DDR2"  AND (((C_MEM_TWTR  + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
+      return ((C_MEM_TWTR  + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
+    elsif (C_MEM_TYPE = "DDR2")then
+      return 2;
+    else
+      return 3;
+    end if;
+  end function MEM_WTR_CYC;
+
+constant      MEM_WTR_VAL                      : INTEGER := MEM_WTR_CYC;
+
+function DDR2_WRT_RECOVERY_CYC return integer is
+  begin
+    if (not(C_MEM_TYPE = "DDR2")) then
+      return 5;
+    else
+      return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+    end if;
+  end function DDR2_WRT_RECOVERY_CYC;
+
+
+constant        C_MEM_DDR2_WRT_RECOVERY          : INTEGER := DDR2_WRT_RECOVERY_CYC;
+
+function DDR3_WRT_RECOVERY_CYC return integer is
+  begin
+    if (not(C_MEM_TYPE = "DDR3")) then
+      return 5;
+    else
+      return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+    end if;
+  end function DDR3_WRT_RECOVERY_CYC;
+
+constant      C_MEM_DDR3_WRT_RECOVERY          : INTEGER := DDR3_WRT_RECOVERY_CYC;
+
+--CR 596422
+constant allzero : std_logic_vector(127 downto 0) := (others => '0');
+--signal allzero : std_logic_vector(127 downto 0) := (others => '0');
+
+----------------------------------------------------------------------------
+-- signal Declarations
+----------------------------------------------------------------------------
+signal addr_in0 : std_logic_vector(31 downto 0);
+signal dqs_out_p : std_logic;              
+signal dqs_out_n : std_logic;              
+signal dqs_sys_p : std_logic;             --from dqs_gen to IOclk network
+signal dqs_sys_n : std_logic;             --from dqs_gen to IOclk network
+signal udqs_sys_p: std_logic;
+signal udqs_sys_n: std_logic;
+signal dqs_p : std_logic;                  -- open net now ?
+signal dqs_n : std_logic;                  -- open net now ?
+
+-- IOI and IOB enable/tristate interface
+signal dqIO_w_en_0      : std_logic;          --enable DQ pads
+signal dqsIO_w_en_90_p  : std_logic;          --enable p side of DQS
+signal dqsIO_w_en_90_n  : std_logic;          --enable n side of DQS
+
+--memory chip control interface
+signal address_90 : std_logic_vector(14 downto 0);
+signal ba_90  : std_logic_vector(2 downto 0);   
+signal ras_90 : std_logic;
+signal cas_90 : std_logic;
+signal we_90  : std_logic;
+signal cke_90 : std_logic;
+signal odt_90 : std_logic;
+signal rst_90 : std_logic;
+
+-- calibration IDELAY control  signals
+signal ioi_drp_clk       : std_logic;   --DRP interface - synchronous clock output
+signal ioi_drp_addr      : std_logic_vector(4 downto 0);   --DRP interface - IOI selection
+signal ioi_drp_sdo       : std_logic;   --DRP interface - serial output for commmands
+signal ioi_drp_sdi       : std_logic;   --DRP interface - serial input for commands
+signal ioi_drp_cs        : std_logic;   --DRP interface - chip select doubles as DONE signal
+signal ioi_drp_add       : std_logic;   --DRP interface - serial address signal
+signal ioi_drp_broadcast : std_logic; 
+signal ioi_drp_train     : std_logic;
+
+-- Calibration datacapture siganls
+signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
+signal dq_in_p : std_logic;         --positive signal sent to calibration logic
+signal dq_in_n : std_logic;         --negative signal sent to calibration logic
+signal cal_done: std_logic;   
+
+--DQS calibration interface
+signal udqs_n : std_logic;
+signal udqs_p : std_logic;
+signal udqs_dqocal_p : std_logic;
+signal udqs_dqocal_n : std_logic;
+
+-- MUI enable interface
+signal df_en_n90 : std_logic;
+
+--INTERNAL signal FOR DRP chain
+-- IOI <-> MUI
+signal ioi_int_tmp : std_logic;
+
+signal dqo_n : std_logic_vector(15 downto 0);  
+signal dqo_p : std_logic_vector(15 downto 0);  
+signal dqnlm : std_logic;      
+signal dqplm : std_logic;      
+signal dqnum : std_logic;      
+signal dqpum : std_logic;      
+
+-- IOI <-> IOB   routes
+signal  ioi_addr  : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
+signal  ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);    
+signal  ioi_cas : std_logic;  
+signal  ioi_ck  : std_logic;  
+signal  ioi_ckn : std_logic;   
+signal  ioi_cke : std_logic;  
+signal  ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0); 
+signal  ioi_dqs  : std_logic; 
+signal  ioi_dqsn : std_logic;
+signal  ioi_udqs : std_logic;
+signal  ioi_udqsn : std_logic;   
+signal  ioi_odt  : std_logic; 
+signal  ioi_ras  : std_logic; 
+signal  ioi_rst  : std_logic; 
+signal  ioi_we   : std_logic;
+signal  ioi_udm  : std_logic;
+signal  ioi_ldm  : std_logic;
+
+signal  in_dq     : std_logic_vector(15 downto 0);
+signal  in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+signal  in_dqs       : std_logic;
+signal  in_pre_dqsp  : std_logic;
+signal  in_pre_dqsn  : std_logic;
+signal  in_pre_udqsp : std_logic;
+signal  in_pre_udqsn : std_logic;
+signal  in_udqs      : std_logic;
+
+-- Memory tri-state control signals
+signal  t_addr  : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
+signal  t_ba    : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);    
+signal  t_cas   : std_logic;
+signal  t_ck    : std_logic;
+signal  t_ckn   : std_logic;
+signal  t_cke   : std_logic;
+signal  t_dq    : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+signal  t_dqs   : std_logic;   
+signal  t_dqsn  : std_logic;
+signal  t_udqs  : std_logic;
+signal  t_udqsn : std_logic;
+signal  t_odt   : std_logic;   
+signal  t_ras   : std_logic;   
+signal  t_rst   : std_logic;   
+signal  t_we    : std_logic;   
+
+signal t_udm             : std_logic;
+signal t_ldm             : std_logic;
+
+signal idelay_dqs_ioi_s  : std_logic;
+signal idelay_dqs_ioi_m  : std_logic;
+signal idelay_udqs_ioi_s : std_logic;
+signal idelay_udqs_ioi_m : std_logic;
+
+signal dqs_pin           : std_logic;
+signal udqs_pin          : std_logic;
+
+-- USER Interface signals
+-- translated memory addresses
+signal p0_cmd_ra : std_logic_vector(14 downto 0);
+signal p0_cmd_ba : std_logic_vector(2 downto 0);
+signal p0_cmd_ca : std_logic_vector(11 downto 0);
+signal p1_cmd_ra : std_logic_vector(14 downto 0);
+signal p1_cmd_ba : std_logic_vector(2 downto 0);
+signal p1_cmd_ca : std_logic_vector(11 downto 0);
+signal p2_cmd_ra : std_logic_vector(14 downto 0);
+signal p2_cmd_ba : std_logic_vector(2 downto 0);
+signal p2_cmd_ca : std_logic_vector(11 downto 0);
+signal p3_cmd_ra : std_logic_vector(14 downto 0);
+signal p3_cmd_ba : std_logic_vector(2 downto 0);
+signal p3_cmd_ca : std_logic_vector(11 downto 0);
+signal p4_cmd_ra : std_logic_vector(14 downto 0);
+signal p4_cmd_ba : std_logic_vector(2 downto 0);
+signal p4_cmd_ca : std_logic_vector(11 downto 0);
+signal p5_cmd_ra : std_logic_vector(14 downto 0);
+signal p5_cmd_ba : std_logic_vector(2 downto 0);
+signal p5_cmd_ca : std_logic_vector(11 downto 0);
+
+   -- user command wires mapped from logical ports to physical ports
+signal mig_p0_arb_en            : std_logic;
+signal mig_p0_cmd_clk           : std_logic;
+signal mig_p0_cmd_en            : std_logic;
+signal mig_p0_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p0_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p0_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p0_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p0_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p0_cmd_empty         : std_logic;
+signal mig_p0_cmd_full          : std_logic;
+
+signal mig_p1_arb_en            : std_logic;
+signal mig_p1_cmd_clk           : std_logic;
+signal mig_p1_cmd_en            : std_logic;
+signal mig_p1_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p1_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p1_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p1_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p1_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p1_cmd_empty         : std_logic;
+signal mig_p1_cmd_full          : std_logic;
+
+signal mig_p2_arb_en            : std_logic;
+signal mig_p2_cmd_clk           : std_logic;
+signal mig_p2_cmd_en            : std_logic;
+signal mig_p2_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p2_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p2_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p2_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p2_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p2_cmd_empty         : std_logic;
+signal mig_p2_cmd_full          : std_logic;
+
+signal mig_p3_arb_en            : std_logic;
+signal mig_p3_cmd_clk           : std_logic;
+signal mig_p3_cmd_en            : std_logic;
+signal mig_p3_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p3_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p3_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p3_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p3_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p3_cmd_empty         : std_logic;
+signal mig_p3_cmd_full          : std_logic;
+
+signal mig_p4_arb_en            : std_logic;
+signal mig_p4_cmd_clk           : std_logic;
+signal mig_p4_cmd_en            : std_logic;
+signal mig_p4_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p4_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p4_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p4_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p4_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p4_cmd_empty         : std_logic;
+signal mig_p4_cmd_full          : std_logic;
+
+signal mig_p5_arb_en            : std_logic;
+signal mig_p5_cmd_clk           : std_logic;
+signal mig_p5_cmd_en            : std_logic;
+signal mig_p5_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p5_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p5_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p5_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p5_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p5_cmd_empty         : std_logic;
+signal mig_p5_cmd_full          : std_logic;
+
+signal mig_p0_wr_clk            : std_logic;
+signal mig_p0_rd_clk            : std_logic;
+signal mig_p1_wr_clk            : std_logic;
+signal mig_p1_rd_clk            : std_logic;
+signal mig_p2_clk               : std_logic;
+signal mig_p3_clk               : std_logic;
+signal mig_p4_clk               : std_logic;
+signal mig_p5_clk               : std_logic;
+
+signal mig_p0_wr_en             : std_logic;
+signal mig_p0_rd_en             : std_logic;
+signal mig_p1_wr_en             : std_logic;
+signal mig_p1_rd_en             : std_logic;
+signal mig_p2_en                : std_logic;
+signal mig_p3_en                : std_logic;
+signal mig_p4_en                : std_logic;
+signal mig_p5_en                : std_logic;
+
+signal mig_p0_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p1_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p2_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p3_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p4_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p5_wr_data           : std_logic_vector(31 downto 0);
+
+signal mig_p0_wr_mask           : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+signal mig_p1_wr_mask           : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+signal mig_p2_wr_mask           : std_logic_vector(3 downto 0);
+signal mig_p3_wr_mask           : std_logic_vector(3 downto 0);
+signal mig_p4_wr_mask           : std_logic_vector(3 downto 0);
+signal mig_p5_wr_mask           : std_logic_vector(3 downto 0);
+
+signal mig_p0_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p1_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p2_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p3_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p4_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p5_rd_data           : std_logic_vector(31 downto 0);
+
+signal mig_p0_rd_overflow       : std_logic;
+signal mig_p1_rd_overflow       : std_logic;
+signal mig_p2_overflow          : std_logic;
+signal mig_p3_overflow          : std_logic;
+
+signal mig_p4_overflow          : std_logic;
+signal mig_p5_overflow          : std_logic;
+
+signal mig_p0_wr_underrun       : std_logic;
+signal mig_p1_wr_underrun       : std_logic;
+signal mig_p2_underrun          : std_logic;
+signal mig_p3_underrun          : std_logic;
+signal mig_p4_underrun          : std_logic;
+signal mig_p5_underrun          : std_logic;
+
+signal mig_p0_rd_error          : std_logic;
+signal mig_p0_wr_error          : std_logic;
+signal mig_p1_rd_error          : std_logic;
+signal mig_p1_wr_error          : std_logic;
+signal mig_p2_error             : std_logic;
+signal mig_p3_error             : std_logic;
+signal mig_p4_error             : std_logic;
+signal mig_p5_error             : std_logic;
+
+signal mig_p0_wr_count          : std_logic_vector(6 downto 0);
+signal mig_p1_wr_count          : std_logic_vector(6 downto 0);
+signal mig_p0_rd_count          : std_logic_vector(6 downto 0);
+signal mig_p1_rd_count          : std_logic_vector(6 downto 0);
+
+signal mig_p2_count             : std_logic_vector(6 downto 0);
+signal mig_p3_count             : std_logic_vector(6 downto 0);
+signal mig_p4_count             : std_logic_vector(6 downto 0);
+signal mig_p5_count             : std_logic_vector(6 downto 0);
+
+signal mig_p0_wr_full           : std_logic;
+signal mig_p1_wr_full           : std_logic;
+
+signal mig_p0_rd_empty          : std_logic;
+signal mig_p1_rd_empty          : std_logic;
+signal mig_p0_wr_empty          : std_logic;
+signal mig_p1_wr_empty          : std_logic;
+signal mig_p0_rd_full           : std_logic;
+signal mig_p1_rd_full           : std_logic;
+signal mig_p2_full              : std_logic;
+signal mig_p3_full              : std_logic;
+signal mig_p4_full              : std_logic;
+signal mig_p5_full              : std_logic;
+signal mig_p2_empty             : std_logic;
+signal mig_p3_empty             : std_logic;
+signal mig_p4_empty             : std_logic;
+signal mig_p5_empty             : std_logic;
+
+-- SELFREESH control signal for suspend feature
+signal selfrefresh_mcb_enter    : std_logic;
+signal selfrefresh_mcb_mode     : std_logic;
+signal selfrefresh_mode_sig     : std_logic;
+
+signal MCB_SYSRST : std_logic;
+signal ioclk0  : std_logic;
+signal ioclk90 : std_logic;
+signal hard_done_cal       : std_logic;
+signal uo_data_int         : std_logic_vector(7 downto 0);
+signal uo_data_valid_int   : std_logic;
+signal uo_cmd_ready_in_int : std_logic;
+signal syn_uiclk_pll_lock  : std_logic;
+signal int_sys_rst         : std_logic;
+
+--testing
+signal ioi_drp_update : std_logic;
+signal aux_sdi_sdo : std_logic_vector(7 downto 0);
+
+
+   signal mcb_recal                : std_logic;
+   signal mcb_ui_read              : std_logic;
+   signal mcb_ui_add               : std_logic;
+   signal mcb_ui_cs                : std_logic;
+   signal mcb_ui_clk               : std_logic;
+   signal mcb_ui_sdi               : std_logic;
+   signal mcb_ui_addr              : STD_LOGIC_vector(4 downto 0);
+   signal mcb_ui_broadcast         : std_logic;
+   signal mcb_ui_drp_update        : std_logic;
+   signal mcb_ui_done_cal          : std_logic;
+   signal mcb_ui_cmd               : std_logic;
+   signal mcb_ui_cmd_in            : std_logic;
+   signal mcb_ui_cmd_en            : std_logic;
+   signal mcb_ui_dqcount           : std_logic_vector(3 downto 0);
+   signal mcb_ui_dq_lower_dec      : std_logic;
+   signal mcb_ui_dq_lower_inc      : std_logic;
+   signal mcb_ui_dq_upper_dec      : std_logic;
+   signal mcb_ui_dq_upper_inc      : std_logic;
+   signal mcb_ui_udqs_inc          : std_logic;
+   signal mcb_ui_udqs_dec          : std_logic;
+   signal mcb_ui_ldqs_inc          : std_logic;
+   signal mcb_ui_ldqs_dec          : std_logic;
+   signal DONE_SOFTANDHARD_CAL     : std_logic;
+
+   signal ck_shiftout0_1           : std_logic;
+   signal ck_shiftout0_2           : std_logic;
+   signal ck_shiftout1_3           : std_logic;
+   signal ck_shiftout1_4           : std_logic;
+
+   signal udm_oq                   : std_logic;
+   signal udm_t                    : std_logic;
+   signal ldm_oq                   : std_logic;
+   signal ldm_t                    : std_logic;
+   signal dqsp_oq                  : std_logic;
+   signal dqsp_tq                  : std_logic;
+   signal dqs_shiftout0_1          : std_logic;
+   signal dqs_shiftout0_2          : std_logic;
+   signal dqs_shiftout1_3          : std_logic;
+   signal dqs_shiftout1_4          : std_logic;
+   signal dqsn_oq                  : std_logic;
+   signal dqsn_tq                  : std_logic;
+   signal udqsp_oq                 : std_logic;
+   signal udqsp_tq                 : std_logic;
+   signal udqs_shiftout0_1         : std_logic;
+   signal udqs_shiftout0_2         : std_logic;
+   signal udqs_shiftout1_3         : std_logic;
+   signal udqs_shiftout1_4         : std_logic;
+   signal udqsn_oq                 : std_logic;
+   signal udqsn_tq                 : std_logic;
+   signal aux_sdi_out_dqsp         : std_logic;
+   signal aux_sdi_out_udqsp        : std_logic;
+   signal aux_sdi_out_udqsn        : std_logic;
+   signal aux_sdi_out_0            : std_logic;
+   signal aux_sdi_out_1            : std_logic;
+   signal aux_sdi_out_2            : std_logic;
+   signal aux_sdi_out_3            : std_logic;
+   signal aux_sdi_out_5            : std_logic;
+   signal aux_sdi_out_6            : std_logic;
+   signal aux_sdi_out_7            : std_logic;
+   signal aux_sdi_out_9            : std_logic;
+   signal aux_sdi_out_10           : std_logic;
+   signal aux_sdi_out_11           : std_logic;
+   signal aux_sdi_out_12           : std_logic;
+   signal aux_sdi_out_13           : std_logic;
+   signal aux_sdi_out_14           : std_logic;
+   signal aux_sdi_out_15           : std_logic;
+   signal aux_sdi_out_8            : std_logic;
+   signal aux_sdi_out_dqsn         : std_logic;
+   signal aux_sdi_out_4            : std_logic;
+   signal aux_sdi_out_udm          : std_logic;
+   signal aux_sdi_out_ldm          : std_logic;
+   signal uo_cal_start_int         : std_logic;
+ 
+   signal cke_train                : std_logic;
+   signal dq_oq                    : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+   signal dq_tq                    : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+
+   signal p0_wr_full_i             : std_logic;
+   signal p0_rd_empty_i            : std_logic;
+   signal p1_wr_full_i             : std_logic;
+   signal p1_rd_empty_i            : std_logic;
+   signal pllclk1                  : std_logic_vector(1 downto 0);
+   signal pllce1                   : std_logic_vector(1 downto 0);
+   signal uo_refrsh_flag_xhdl23    : std_logic;
+   signal uo_sdo_xhdl24            : STD_LOGIC;
+   signal Max_Value_Cal_Error      : std_logic;
+   signal uo_done_cal_sig          : std_logic;
+   signal wait_200us_counter       : std_logic_vector(15 downto 0);
+   signal cke_train_reg            : std_logic;        
+   signal wait_200us_done_r1       : std_logic;
+   signal wait_200us_done_r2       : std_logic;
+   signal syn1_sys_rst             : std_logic;
+   signal syn2_sys_rst             : std_logic;
+   signal selfrefresh_enter_r1     : std_logic;
+   signal selfrefresh_enter_r2     : std_logic;
+   signal selfrefresh_enter_r3     : std_logic;
+   signal gated_pll_lock           : std_logic;
+   signal soft_cal_selfrefresh_req : std_logic;
+   signal normal_operation_window  : std_logic;
+
+   attribute max_fanout            : string;
+   attribute syn_maxfan            : integer;
+   attribute max_fanout of int_sys_rst : signal is "1";
+   attribute syn_maxfan of int_sys_rst : signal is 1;
+
+begin
+   uo_cmd_ready_in   <= uo_cmd_ready_in_int;
+   uo_data_valid     <= uo_data_valid_int;
+   uo_data           <= uo_data_int;
+   uo_refrsh_flag    <= uo_refrsh_flag_xhdl23;
+   uo_sdo            <= uo_sdo_xhdl24;
+
+   p0_wr_full        <= p0_wr_full_i;
+   p0_rd_empty       <= p0_rd_empty_i;
+   p1_wr_full        <= p1_wr_full_i;
+   p1_rd_empty       <= p1_rd_empty_i;
+   ioclk0            <= sysclk_2x;
+   ioclk90           <= sysclk_2x_180;
+   pllclk1           <= (ioclk90 & ioclk0);
+   pllce1            <= (pll_ce_90 & pll_ce_0);
+
+   -- Assign the output signals with corresponding intermediate signals
+   uo_done_cal       <= uo_done_cal_sig;
+
+   -- Added 2/22 - Add flop to pll_lock status signal to improve timing
+   process (ui_clk)
+   begin
+      if (ui_clk'event and ui_clk = '1') then      
+        if ((selfrefresh_enter = '0') and (gated_pll_lock = '0')) then
+         syn_uiclk_pll_lock <= pll_lock;
+        end if;
+      end if;
+   end process;               
+
+   -- logic to determine if Memory  is SELFREFRESH mode operation or NORMAL  mode.
+   process (ui_clk)
+   begin
+      if (ui_clk'event and ui_clk = '1') then      
+        if (sys_rst = '1') then  
+           normal_operation_window <= '1';
+        elsif (selfrefresh_enter_r2 = '1' or selfrefresh_mode_sig = '1') then
+           normal_operation_window <= '0';
+        elsif ((selfrefresh_enter_r2 = '0') and  (selfrefresh_mode_sig = '0')) then
+           normal_operation_window <= '1';
+        else
+           normal_operation_window <= normal_operation_window;
+        end if;
+      end if;
+   end process;   
+   
+   
+   process(normal_operation_window,pll_lock,syn_uiclk_pll_lock)
+   begin
+     if (normal_operation_window = '1') then
+      gated_pll_lock <= pll_lock;
+     else
+      gated_pll_lock <= syn_uiclk_pll_lock;
+     end if;
+   end process;
+
+-- int_sys_rst will be asserted if pll lose lock during normal operation.
+-- It uses the syn_uiclk_pll_lock version when it is entering suspend window , hence
+-- reset will not be generated. 
+
+   int_sys_rst <=  sys_rst or not(gated_pll_lock);
+
+-- synchronize the selfrefresh_enter 
+   process (ui_clk)
+   begin
+      if (ui_clk'event and ui_clk = '1') then      
+        if (sys_rst = '1') then
+          selfrefresh_enter_r1 <= '0';
+          selfrefresh_enter_r2 <= '0';
+          selfrefresh_enter_r3 <= '0';
+        else
+          selfrefresh_enter_r1 <= selfrefresh_enter;
+          selfrefresh_enter_r2 <= selfrefresh_enter_r1;
+          selfrefresh_enter_r3 <= selfrefresh_enter_r2;
+        end if;
+      end if;
+    end process;
+
+
+
+--  The soft_cal_selfrefresh siganl is conditioned before connect to mcb_soft_calibration module.
+--  It will not deassert selfrefresh_mcb_enter to MCB until input pll_lock reestablished in system.
+--  This is to ensure the IOI stables before issued a selfrefresh exit command to dram.
+   process (ui_clk)
+   begin
+      if (ui_clk'event and ui_clk = '1') then      
+        if (sys_rst = '1') then
+          soft_cal_selfrefresh_req <= '0';
+        elsif (selfrefresh_enter_r3 = '1') then
+          soft_cal_selfrefresh_req <= '1';
+        elsif (selfrefresh_enter_r3 = '0' and pll_lock = '1') then 
+          soft_cal_selfrefresh_req <= '0';
+        else
+          soft_cal_selfrefresh_req <= soft_cal_selfrefresh_req;
+        end if;
+      end if;
+    end process;
+  
+
+--Address Remapping
+-- Byte Address remapping
+-- 
+-- Bank Address[x:0] & Row Address[x:0]  & Column Address[x:0]
+-- column address remap for port 0
+
+x16_addr        : if(C_NUM_DQ_PINS = 16) generate  --  port bus remapping sections for CONFIG 2   15,3,12
+x16_addr_rbc    : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row  Column
+
+-- port 0 address remapping
+                
+ x16_p0_a15     : if (C_MEM_ADDR_WIDTH = 15) generate
+                   p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+                end generate;
+
+ x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
+                   p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1)); 
+                   end generate;
+                      
+
+ x16_p0_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p0_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p0_cmd_ba <=  (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  + C_MEM_NUM_COL_BITS + 1));
+                end generate;
+
+                
+ x16_p0_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+                end generate;
+
+ x16_p0_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p0_cmd_ca <=  (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+                end generate;
+
+-- port 1 address remapping
+  
+ x16_p1_a15     : if (C_MEM_ADDR_WIDTH = 15) generate  --Row  
+                        p1_cmd_ra <=  p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+                end generate;
+
+ x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                        p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                            
+                   end generate;
+                      
+
+ x16_p1_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p1_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  + C_MEM_NUM_COL_BITS + 1));
+
+                end generate;
+
+                
+ x16_p1_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+                end generate;
+
+ x16_p1_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+                end generate;
+
+ -- port 2 address remapping
+ x16_p2_a15     : if (C_MEM_ADDR_WIDTH = 15) generate --Row  
+                         p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+                end generate;
+
+ x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                         p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                         
+                   end generate;
+                      
+
+ x16_p2_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p2_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                         p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1));
+                end generate;
+
+                
+ x16_p2_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                         p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+                end generate;
+
+ x16_p2_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                         p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+                end generate;
+                
+
+-- port 3 address remapping
+ x16_p3_a15     : if (C_MEM_ADDR_WIDTH = 15) generate --Row  
+                         p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+
+                end generate;
+
+ x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                        p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                         
+                   end generate;
+                      
+
+ x16_p3_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+
+                end generate;
+
+ x16_p3_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                         p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  + C_MEM_NUM_COL_BITS + 1));
+
+                end generate;
+
+                
+ x16_p3_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+                end generate;
+
+ x16_p3_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+                end generate;
+                
+                
+
+
+ -- port 4 address remapping
+                
+  x16_p4_a15    : if (C_MEM_ADDR_WIDTH = 15) generate --Row  
+                        p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+
+                end generate;
+
+ x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                        p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                         
+                   end generate;
+                      
+
+ x16_p4_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p4_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  C_MEM_NUM_COL_BITS + 1));
+                end generate;
+
+                
+ x16_p4_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+                end generate;
+
+ x16_p4_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+                end generate;
+               
+
+
+-- port 5 address remapping
+  x16_p5_a15    : if (C_MEM_ADDR_WIDTH = 15) generate --Row  
+                          p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+                end generate;
+
+ x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                         p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                         
+                   end generate;
+                      
+
+ x16_p5_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p5_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                         p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  + C_MEM_NUM_COL_BITS + 1));
+                end generate;
+
+                
+ x16_p5_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+                end generate;
+
+ x16_p5_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+                end generate;
+end generate;   --x16_addr_rbc            
+                
+x16_addr_rbc_n  : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate 
+                
+                
+ -- port 0 address remapping
+
+x16_rbc_n_p0_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+               end generate;
+
+x16_rbc_n_p0_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+               end generate;
+
+x16_rbc_n_p0_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1);                         
+               end generate;
+
+x16_rbc_n_p0_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1));                         
+               end generate;
+
+x16_rbc_n_p0_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+               end generate;
+
+x16_rbc_n_p0_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+               end generate;
+                
+
+                
+
+
+-- port 1 address remapping
+ x16_rbc_n_p1_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+               end generate;
+
+x16_rbc_n_p1_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+               end generate;
+
+x16_rbc_n_p1_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1);                         
+               end generate;
+
+x16_rbc_n_p1_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1));                         
+               end generate;
+
+x16_rbc_n_p1_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+               end generate;
+
+x16_rbc_n_p1_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS  downto 1));
+               end generate;
+
+
+
+ -- port 2 address remapping
+x16_rbc_n_p2_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+               end generate;
+
+x16_rbc_n_p2_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p2_cmd_ba <= (allzero(2  downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+
+               end generate;
+
+x16_rbc_n_p2_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS    downto C_MEM_NUM_COL_BITS + 1);                         
+
+               end generate;
+
+x16_rbc_n_p2_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p2_cmd_ra <= (allzero(14  downto C_MEM_ADDR_WIDTH) &  p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS    downto C_MEM_NUM_COL_BITS + 1));    
+               end generate;
+
+x16_rbc_n_p2_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS  downto 1);
+
+               end generate;
+
+x16_rbc_n_p2_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS  downto 1));
+
+               end generate;
+
+
+ -- port 3 address remapping
+x16_rbc_n_p3_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+
+               end generate;
+
+x16_rbc_n_p3_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p3_cmd_ba <= (allzero(2  downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+
+               end generate;
+
+x16_rbc_n_p3_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS    downto C_MEM_NUM_COL_BITS + 1);                         
+
+               end generate;
+
+x16_rbc_n_p3_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p3_cmd_ra <= (allzero(14  downto C_MEM_ADDR_WIDTH) &  p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS    downto C_MEM_NUM_COL_BITS + 1));                         
+
+               end generate;
+
+x16_rbc_n_p3_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS  downto 1);
+
+               end generate;
+
+x16_rbc_n_p3_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+               end generate;
+
+
+ -- port 4 address remapping
+x16_rbc_n_p4_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+
+               end generate;
+
+x16_rbc_n_p4_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+
+               end generate;
+
+x16_rbc_n_p4_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1);                         
+
+               end generate;
+
+x16_rbc_n_p4_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1));                         
+               end generate;
+
+x16_rbc_n_p4_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+               end generate;
+
+x16_rbc_n_p4_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+               end generate;
+
+ -- port 5 address remapping
+x16_rbc_n_p5_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+
+               end generate;
+
+x16_rbc_n_p5_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+
+               end generate;
+
+x16_rbc_n_p5_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1);                         
+               end generate;
+
+x16_rbc_n_p5_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1));                         
+
+               end generate;
+
+x16_rbc_n_p5_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+               end generate;
+
+x16_rbc_n_p5_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+               end generate;
+ end generate;--x16_addr_rbc_n
+end generate; --x16_addr
+
+
+
+
+
+
+x8_addr : if(C_NUM_DQ_PINS = 8) generate
+x8_addr_rbc     : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate 
+-- port 0 address remapping
+
+x8_p0_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                           p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p0_cmd_ra <= (allzero(14  downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p0_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                           p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p0_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                           p0_cmd_ba <= (allzero(2  downto C_MEM_BANKADDR_WIDTH)&  
+                                   p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p0_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p0_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p0_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+
+                 
+                 
+-- port 1 address remapping
+ x8_p1_a15      : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p1_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p1_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p1_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p1_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p1_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p1_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                           p1_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                 
+                
+ -- port 2 address remapping
+  x8_p2_a15     : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                             p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p2_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p2_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p2_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p2_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,2,10  ***
+
+                end generate;
+
+                
+ x8_p2_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p2_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p2_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                 
+
+
+--   port 3 address remapping
+ x8_p3_a15      : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p3_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p3_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p3_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p3_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p3_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p3_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p3_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                
+--   port 4 address remapping
+ x8_p4_a15      : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p4_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p4_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p4_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p4_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p4_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p4_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p4_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                  
+
+ --   port 5 address remapping
+  x8_p5_a15     : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                           p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p5_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p5_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p5_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p5_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p5_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p5_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p5_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+  end generate; --x8_addr_rbc
+
+
+                 
+x8_addr_rbc_n   : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate 
+ -- port 0 address remapping
+  x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                             p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p0_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p0_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+
+                end generate;
+
+ x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p0_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));                
+
+                   end generate;
+
+                
+ x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p0_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+
+ -- port 1 address remapping
+  x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                             p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p1_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p1_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+
+                end generate;
+
+ x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p1_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p1_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                
+--port 2 address remapping
+ x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                         p2_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                        p2_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS  ));  
+
+                end generate;
+
+ x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p2_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p2_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+
+ -- port 3 address remapping
+  x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                             p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p3_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p3_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+
+                end generate;
+
+ x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p3_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p3_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+   
+   
+--   port 4 address remapping
+ x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &  
+                                   p4_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+                end generate;
+
+ x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p4_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p4_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+
+--   port 5 address remapping
+ x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p5_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p5_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+
+                end generate;
+
+ x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p5_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p5_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+  end generate; --x8_addr_rbc_n
+ end generate;  --x8_addr
+             
+
+
+
+
+
+
+
+
+x4_addr : if(C_NUM_DQ_PINS = 4) generate
+x4_addr_rbc     : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate 
+
+--   port 0 address remapping
+x4_p0_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p0_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+ x4_p0_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p0_cmd_ba <=  p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p0_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p0_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+ x4_p0_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+ x4_p0_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p0_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+               
+           
+--   port 1 address remapping
+x4_p1_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p1_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+ x4_p1_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p1_cmd_ba <=  p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p1_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p1_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+ x4_p1_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+ x4_p1_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p1_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+
+
+--   port 2 address remapping
+x4_p2_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p2_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+                   end generate;
+                      
+
+ x4_p2_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p2_cmd_ba <=  p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p2_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p2_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+ x4_p2_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+ x4_p2_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p2_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+
+
+--   port 3 address remapping
+x4_p3_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p3_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+ x4_p3_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p3_cmd_ba <=  p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p3_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p3_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+ x4_p3_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+ x4_p3_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p3_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+
+
+
+
+ 
+
+ x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
+             ) generate
+--   port 4 address remapping
+ 
+x4_p4_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                      p4_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+x4_p4_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                       p4_cmd_ba <=  p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+x4_p4_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                       p4_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+x4_p4_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                      p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+x4_p4_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                      p4_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+--   port 5 address remapping
+               
+
+x4_p5_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                      p5_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+x4_p5_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                       p5_cmd_ba <=  p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+x4_p5_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                       p5_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+x4_p5_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                      p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+x4_p5_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                      p5_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+     end generate; --x4_p4_p5
+ end generate; --x4_addr_rbc
+
+
+
+              
+x4_addr_rbc_n   : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate 
+            
+--   port 0 address remapping
+  x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p0_cmd_ba <=  p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+                end generate;
+
+ x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p0_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+                end generate;
+
+ x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+                end generate;
+
+ x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p0_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+                   end generate;
+
+                
+ x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+                end generate;
+
+ x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p0_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+                end generate;
+               
+           
+--   port 1 address remapping
+  x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p1_cmd_ba <=  p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p1_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p1_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p1_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+            
+--   port 2 address remapping
+  x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p2_cmd_ba <=  p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p2_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p2_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p2_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+            
+--   port 3 address remapping
+  x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p3_cmd_ba <=  p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p3_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p3_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p3_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+            
+
+  x4_p4_p5_n:  if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
+             ) generate
+--   port 4 address remapping
+
+  x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p4_cmd_ba <=  p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p4_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p4_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p4_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+               end generate;
+            
+ 
+--   port 5 address remapping
+
+  x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p5_cmd_ba <=  p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p5_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p5_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p5_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+            
+end generate;  --x4_p4_p5_n
+
+end generate; --x4_addr_rbc_n
+end generate; --x4_addr
+
+
+
+
+   --  if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
+u_config1_0:   if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
+      ) generate  
+
+  --synthesis translate_off 
+  -- PORT2
+  process (p2_cmd_en,p2_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and 
+      p2_cmd_en = '1' and  p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1')  then
+      report "ERROR - Invalid Command for write only port 2";
+    end if;
+  end process;
+
+  process (p2_cmd_en,p2_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and 
+      p2_cmd_en = '1' and  p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0')  then
+      report "ERROR - Invalid Command for read only port 2";
+    end if;
+  end process;
+
+  -- PORT3
+  process (p3_cmd_en,p3_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and 
+      p3_cmd_en = '1' and  p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1')  then
+      report "ERROR - Invalid Command for write only port 3";
+    end if;
+  end process;
+
+  process (p3_cmd_en,p3_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and 
+      p3_cmd_en = '1' and  p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0')  then
+      report "ERROR - Invalid Command for read only port 3";
+    end if;
+  end process;
+
+  -- PORT4
+  process (p4_cmd_en,p4_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and 
+      p4_cmd_en = '1' and  p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1')  then
+      report "ERROR - Invalid Command for write only port 4";
+    end if;
+  end process;
+
+  process (p4_cmd_en,p4_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and 
+      p4_cmd_en = '1' and  p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0')  then
+      report "ERROR - Invalid Command for read only port 4";
+    end if;
+  end process;
+
+  -- PORT5
+  process (p5_cmd_en,p5_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and 
+      p5_cmd_en = '1' and  p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1')  then
+      report "ERROR - Invalid Command for write only port 5";
+    end if;
+  end process;
+
+  process (p5_cmd_en,p5_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and 
+      p5_cmd_en = '1' and  p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0')  then
+      report "ERROR - Invalid Command for read only port 5";
+    end if;
+  end process;
+
+
+
+ 
+   --synthesis translate_on 
+ 
+
+ -- the local declaration of input port signals doesn't work.  The mig_p1_xxx through mig_p5_xxx always ends up
+ -- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
+ -- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
+ --
+
+              -- Inputs from Application CMD Port
+
+   p0_cmd_ena:  if (C_PORT_ENABLE(0) = '1') generate
+
+                    mig_p0_arb_en      <=      p0_arb_en ;
+                    mig_p0_cmd_clk     <=      p0_cmd_clk  ;
+                    mig_p0_cmd_en      <=      p0_cmd_en   ;
+                    mig_p0_cmd_ra      <=      p0_cmd_ra  ;
+                    mig_p0_cmd_ba      <=      p0_cmd_ba   ;
+                    mig_p0_cmd_ca      <=      p0_cmd_ca  ;
+                    mig_p0_cmd_instr   <=      p0_cmd_instr;
+                    mig_p0_cmd_bl      <=      ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;
+                    p0_cmd_empty       <=      mig_p0_cmd_empty;
+                    p0_cmd_full        <=      mig_p0_cmd_full ;
+   end generate;   
+   
+      p0_cmd_dis:  if (C_PORT_ENABLE(0) = '0') generate
+                    mig_p0_arb_en      <=     '0';
+                    mig_p0_cmd_clk     <=     '0';
+                    mig_p0_cmd_en      <=     '0';
+                    mig_p0_cmd_ra      <=     (others => '0');
+                    mig_p0_cmd_ba      <=     (others => '0');
+                    mig_p0_cmd_ca      <=     (others => '0');
+                    mig_p0_cmd_instr   <=     (others => '0');
+                    mig_p0_cmd_bl      <=     (others => '0');
+                    p0_cmd_empty       <=     '0';
+                    p0_cmd_full        <=     '0';
+                   
+   end generate;   
+               
+   p1_cmd_ena:  if (C_PORT_ENABLE(1) = '1') generate
+                    mig_p1_arb_en      <=      p1_arb_en ;
+                    mig_p1_cmd_clk     <=      p1_cmd_clk  ;
+                    mig_p1_cmd_en      <=      p1_cmd_en   ;
+                    mig_p1_cmd_ra      <=      p1_cmd_ra  ;
+                    mig_p1_cmd_ba      <=      p1_cmd_ba   ;
+                    mig_p1_cmd_ca      <=      p1_cmd_ca  ;
+                    mig_p1_cmd_instr   <=      p1_cmd_instr;
+                    mig_p1_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           
+                    p1_cmd_empty       <=      mig_p1_cmd_empty;
+                    p1_cmd_full        <=      mig_p1_cmd_full ;
+   end generate;   
+                   
+   p1_cmd_dis:  if (C_PORT_ENABLE(1) = '0') generate
+   
+                   mig_p1_arb_en      <=     '0';
+                    mig_p1_cmd_clk     <=     '0';
+                    mig_p1_cmd_en      <=     '0';
+                    mig_p1_cmd_ra      <=     (others => '0');
+                    mig_p1_cmd_ba      <=     (others => '0');
+                    mig_p1_cmd_ca      <=     (others => '0');
+                    mig_p1_cmd_instr   <=     (others => '0');
+                    mig_p1_cmd_bl      <=     (others => '0');
+                    p1_cmd_empty       <=      '0';
+                    p1_cmd_full        <=      '0';
+   end generate;                      
+
+               
+   p2_cmd_ena:  if (C_PORT_ENABLE(2) = '1') generate
+                    mig_p2_arb_en      <=      p2_arb_en ;
+                    mig_p2_cmd_clk     <=      p2_cmd_clk  ;
+                    mig_p2_cmd_en      <=      p2_cmd_en   ;
+                    mig_p2_cmd_ra      <=      p2_cmd_ra  ;
+                    mig_p2_cmd_ba      <=      p2_cmd_ba   ;
+                    mig_p2_cmd_ca      <=      p2_cmd_ca  ;
+                    mig_p2_cmd_instr   <=      p2_cmd_instr;
+                    mig_p2_cmd_bl      <=      ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0))  ;                           
+
+                    p2_cmd_empty   <=      mig_p2_cmd_empty;
+                    p2_cmd_full    <=      mig_p2_cmd_full ;
+    end generate;   
+                   
+   p2_cmd_dis:  if (C_PORT_ENABLE(2) = '0') generate
+                    mig_p2_arb_en      <=       '0';
+                    mig_p2_cmd_clk      <=       '0';
+                    mig_p2_cmd_en      <=       '0';
+                    mig_p2_cmd_ra      <=      (others => '0');
+                    mig_p2_cmd_ba      <=      (others => '0');
+                    mig_p2_cmd_ca      <=      (others => '0');
+                    mig_p2_cmd_instr   <=      (others => '0');
+                    mig_p2_cmd_bl      <=      (others => '0');
+                    p2_cmd_empty      <=       '0';
+                    p2_cmd_full      <=       '0';
+    end generate;   
+               
+   p3_cmd_ena:  if (C_PORT_ENABLE(3) = '1') generate
+
+                    mig_p3_arb_en    <=        p3_arb_en ;
+                    mig_p3_cmd_clk     <=      p3_cmd_clk  ;
+                    mig_p3_cmd_en      <=      p3_cmd_en   ;
+                    mig_p3_cmd_ra      <=      p3_cmd_ra  ;
+                    mig_p3_cmd_ba      <=      p3_cmd_ba   ;
+                    mig_p3_cmd_ca      <=      p3_cmd_ca  ;
+                    mig_p3_cmd_instr   <=      p3_cmd_instr;
+                    mig_p3_cmd_bl      <=      ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0))  ;                           
+                    p3_cmd_empty   <=      mig_p3_cmd_empty;
+                    p3_cmd_full    <=      mig_p3_cmd_full ;
+     end generate;   
+                   
+   p3_cmd_dis:  if (C_PORT_ENABLE(3) = '0') generate
+                    mig_p3_arb_en    <=       '0';
+                    mig_p3_cmd_clk     <=     '0';
+                    mig_p3_cmd_en      <=     '0';
+                    mig_p3_cmd_ra      <=     (others => '0');
+                    mig_p3_cmd_ba      <=     (others => '0');
+                    mig_p3_cmd_ca      <=     (others => '0');
+                    mig_p3_cmd_instr   <=     (others => '0');
+                    mig_p3_cmd_bl      <=     (others => '0');
+                    p3_cmd_empty      <=       '0';
+                    p3_cmd_full    <=     '0';
+     end generate;   
+
+               
+    p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
+
+                    mig_p4_arb_en    <=        p4_arb_en ;
+                    mig_p4_cmd_clk     <=      p4_cmd_clk  ;
+                    mig_p4_cmd_en      <=      p4_cmd_en   ;
+                    mig_p4_cmd_ra      <=      p4_cmd_ra  ;
+                    mig_p4_cmd_ba      <=      p4_cmd_ba   ;
+                    mig_p4_cmd_ca      <=      p4_cmd_ca  ;
+                    mig_p4_cmd_instr   <=      p4_cmd_instr;
+                    mig_p4_cmd_bl      <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0))  ;                           
+
+                    p4_cmd_empty   <=      mig_p4_cmd_empty;
+                    p4_cmd_full    <=      mig_p4_cmd_full ;
+end generate;
+
+    p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
+
+                    mig_p4_arb_en      <=       '0';
+                    mig_p4_cmd_clk      <=       '0';
+                    mig_p4_cmd_en      <=       '0';
+                    mig_p4_cmd_ra      <=      (others => '0');
+                    mig_p4_cmd_ba      <=      (others => '0');
+                    mig_p4_cmd_ca      <=      (others => '0');
+                    mig_p4_cmd_instr   <=      (others => '0');
+                    mig_p4_cmd_bl      <=      (others => '0');
+                    p4_cmd_empty      <=       '0';
+                    p4_cmd_full    <=      '0';
+end generate;
+                   
+    p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
+                     mig_p5_arb_en    <=     p5_arb_en ;
+                     mig_p5_cmd_clk   <=     p5_cmd_clk  ;
+                     mig_p5_cmd_en    <=     p5_cmd_en   ;
+                     mig_p5_cmd_ra    <=     p5_cmd_ra  ;
+                     mig_p5_cmd_ba    <=     p5_cmd_ba   ;
+                     mig_p5_cmd_ca    <=     p5_cmd_ca  ;
+                     mig_p5_cmd_instr <=     p5_cmd_instr;
+                     mig_p5_cmd_bl    <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0))  ;                           
+
+                    p5_cmd_empty   <=     mig_p5_cmd_empty;
+                    p5_cmd_full    <=     mig_p5_cmd_full ;
+                   
+end generate;
+
+    p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
+
+                     mig_p5_arb_en     <=   '0';
+                     mig_p5_cmd_clk    <=   '0';
+                     mig_p5_cmd_en     <=   '0';
+                     mig_p5_cmd_ra     <=   (others => '0');
+                     mig_p5_cmd_ba     <=   (others => '0');
+                     mig_p5_cmd_ca     <=   (others => '0');
+                    mig_p5_cmd_instr   <=   (others => '0');
+                    mig_p5_cmd_bl      <=   (others => '0');
+                    p5_cmd_empty      <=       '0';
+                    p5_cmd_full    <=     '0';
+end generate;
+
+
+
+p0_wr_rd_ena:  if (C_PORT_ENABLE(0) = '1') generate
+                 mig_p0_wr_clk   <= p0_wr_clk;
+                 mig_p0_rd_clk   <= p0_rd_clk;
+                 mig_p0_wr_en    <= p0_wr_en;
+                 mig_p0_rd_en    <= p0_rd_en;
+                 mig_p0_wr_mask  <= p0_wr_mask(3 downto 0);
+                 mig_p0_wr_data  <= p0_wr_data(31 downto 0);
+                 p0_rd_data        <= mig_p0_rd_data;
+                 p0_rd_full        <= mig_p0_rd_full;
+                 p0_rd_empty_i       <= mig_p0_rd_empty;
+                 p0_rd_error       <= mig_p0_rd_error;
+                 p0_wr_error       <= mig_p0_wr_error;
+                 p0_rd_overflow    <= mig_p0_rd_overflow;
+                 p0_wr_underrun    <= mig_p0_wr_underrun;
+                 p0_wr_empty       <= mig_p0_wr_empty;
+                 p0_wr_full_i        <= mig_p0_wr_full;
+                 p0_wr_count       <= mig_p0_wr_count;
+                 p0_rd_count       <= mig_p0_rd_count  ; 
+end generate;                
+p0_wr_rd_dis:  if (C_PORT_ENABLE(0) = '0') generate
+                 mig_p0_wr_clk     <= '0';
+                 mig_p0_rd_clk     <= '0';
+                 mig_p0_wr_en      <= '0';
+                 mig_p0_rd_en      <= '0';
+                 mig_p0_wr_mask    <= (others => '0');
+                 mig_p0_wr_data    <= (others => '0');
+                 p0_rd_data        <= (others => '0');
+                 p0_rd_full        <= '0';
+                 p0_rd_empty_i       <= '0';
+                 p0_rd_error       <= '0';
+                 p0_wr_error       <= '0';
+                 p0_rd_overflow    <= '0';
+                 p0_wr_underrun    <= '0';
+                 p0_wr_empty       <= '0';
+                 p0_wr_full_i        <= '0';
+                 p0_wr_count       <= (others => '0');
+                 p0_rd_count       <= (others => '0');
+end generate;                  
+              
+p1_wr_rd_ena:  if (C_PORT_ENABLE(1) = '1') generate
+              
+                 mig_p1_wr_clk   <= p1_wr_clk;
+                 mig_p1_rd_clk   <= p1_rd_clk;                
+                 mig_p1_wr_en    <= p1_wr_en;
+                 mig_p1_wr_mask  <= p1_wr_mask(3 downto 0);                
+                 mig_p1_wr_data  <= p1_wr_data(31 downto 0);
+                 mig_p1_rd_en    <= p1_rd_en;
+                 p1_rd_data     <= mig_p1_rd_data;
+                 p1_rd_empty_i    <= mig_p1_rd_empty;
+                 p1_rd_full     <= mig_p1_rd_full;
+                 p1_rd_error    <= mig_p1_rd_error;
+                 p1_wr_error    <= mig_p1_wr_error;
+                 p1_rd_overflow <= mig_p1_rd_overflow;
+                 p1_wr_underrun    <= mig_p1_wr_underrun;
+                 p1_wr_empty    <= mig_p1_wr_empty;
+                 p1_wr_full_i    <= mig_p1_wr_full;
+                 p1_wr_count  <= mig_p1_wr_count;
+                 p1_rd_count  <= mig_p1_rd_count  ; 
+                
+end generate;                
+p1_wr_rd_dis:  if (C_PORT_ENABLE(1) = '0') generate
+              
+                 mig_p1_wr_clk   <= '0';
+                 mig_p1_rd_clk   <= '0';           
+                 mig_p1_wr_en    <= '0';
+                 mig_p1_wr_mask  <= (others => '0');          
+                 mig_p1_wr_data  <= (others => '0');
+                 mig_p1_rd_en    <= '0';
+                 p1_rd_data     <=  (others => '0');
+                 p1_rd_empty_i    <=  '0';
+                 p1_rd_full     <=  '0';
+                 p1_rd_error    <=  '0';
+                 p1_wr_error    <=  '0';
+                 p1_rd_overflow <=  '0';
+                 p1_wr_underrun <=  '0';
+                 p1_wr_empty    <=  '0';
+                 p1_wr_full_i     <=  '0';
+                 p1_wr_count    <=  (others => '0');
+                 p1_rd_count    <=  (others => '0');
+end generate;                  
+end generate;
+                
+                
+
+
+--whenever PORT 2 is in Write mode     
+--      xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
+--u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
+
+u_config1_2W: if(    C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
+  ) generate
+
+p2_wr_ena:    if (C_PORT_ENABLE(2) = '1') generate
+                        mig_p2_clk      <= p2_wr_clk;
+                        mig_p2_wr_data  <= p2_wr_data(31 downto 0);
+                        mig_p2_wr_mask  <= p2_wr_mask(3 downto 0);
+                        mig_p2_en       <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
+                        p2_wr_error     <= mig_p2_error;                       
+                        p2_wr_full      <= mig_p2_full;
+                        p2_wr_empty     <= mig_p2_empty;
+                        p2_wr_underrun  <= mig_p2_underrun;
+                        p2_wr_count     <= mig_p2_count  ;-- wr port
+ end generate;                      
+p2_wr_dis:    if (C_PORT_ENABLE(2) = '0') generate
+                        mig_p2_clk      <= '0';
+                        mig_p2_wr_data  <= (others => '0');
+                        mig_p2_wr_mask  <= (others => '0');
+                        mig_p2_en       <= '0';
+                        p2_wr_error     <= '0';
+                        p2_wr_full      <= '0';
+                        p2_wr_empty     <= '0';
+                        p2_wr_underrun  <= '0';
+                        p2_wr_count     <= (others => '0');
+end generate;                                                
+                    p2_rd_data        <= (others => '0');
+                    p2_rd_overflow    <= '0';
+                    p2_rd_error       <= '0';
+                    p2_rd_full        <= '0';
+                    p2_rd_empty       <= '0';
+                    p2_rd_count       <= (others => '0');
+--                   p2_rd_error       <= '0';
+ end generate;                      
+--u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
+                         
+u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
+
+ p2_rd_ena :  if (C_PORT_ENABLE(2) = '1') generate
+                        mig_p2_clk        <= p2_rd_clk;
+                        p2_rd_data        <= mig_p2_rd_data;
+                        mig_p2_en         <= p2_rd_en;  
+                        p2_rd_overflow    <= mig_p2_overflow;
+                        p2_rd_error       <= mig_p2_error;
+                        p2_rd_full        <= mig_p2_full;
+                        p2_rd_empty       <= mig_p2_empty;
+                        p2_rd_count       <= mig_p2_count  ;-- wr port
+ end generate;                      
+ p2_rd_dis :  if (C_PORT_ENABLE(2) = '0') generate
+                        mig_p2_clk        <= '0';
+                        p2_rd_data        <= (others => '0');
+                        mig_p2_en         <= '0';
+                       
+                        p2_rd_overflow    <= '0';
+                        p2_rd_error       <= '0';
+                        p2_rd_full        <= '0';
+                        p2_rd_empty       <= '0';
+                        p2_rd_count       <= (others => '0');
+ end generate;                      
+                   mig_p2_wr_data  <= (others => '0');
+                   mig_p2_wr_mask  <= (others => '0');
+                   p2_wr_error     <= '0';
+                   p2_wr_full      <= '0';
+                   p2_wr_empty     <= '0';
+                   p2_wr_underrun  <= '0';
+                   p2_wr_count     <= (others => '0');
+          
+ end generate;                      
+--u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64)  = "W32") generate --whenever PORT 3 is in Write mode         
+
+u_config1_3W: if(
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode         
+
+p3_wr_ena:  if (C_PORT_ENABLE(3) = '1')generate
+
+                        mig_p3_clk   <= p3_wr_clk;
+                        mig_p3_wr_data  <= p3_wr_data(31 downto 0);
+                        mig_p3_wr_mask  <= p3_wr_mask(3 downto 0);
+                        mig_p3_en       <= p3_wr_en; 
+                        p3_wr_full      <= mig_p3_full;
+                        p3_wr_empty     <= mig_p3_empty;
+                        p3_wr_underrun  <= mig_p3_underrun;
+                        p3_wr_count     <= mig_p3_count  ;-- wr port
+                        p3_wr_error     <= mig_p3_error;
+ end generate;                      
+                       
+p3_wr_dis:  if (C_PORT_ENABLE(3) = '0')generate
+                        mig_p3_clk      <= '0';
+                        mig_p3_wr_data  <= (others => '0');
+                        mig_p3_wr_mask  <= (others => '0');
+                        mig_p3_en      <= '0';
+                        p3_wr_full      <= '0';
+                        p3_wr_empty     <= '0';
+                        p3_wr_underrun  <=  '0';
+                        p3_wr_count     <= (others => '0');
+                        p3_wr_error     <= '0';
+                                                
+ end generate;                      
+                    p3_rd_overflow <= '0';
+                    p3_rd_error    <= '0';
+                    p3_rd_full     <= '0';
+                    p3_rd_empty    <= '0';
+                    p3_rd_count    <= (others => '0');
+                    p3_rd_data     <= (others => '0');
+ end generate;                      
+                       
+u_config1_3R : if(      
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
+       
+p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
+
+                        mig_p3_clk     <= p3_rd_clk;
+                        p3_rd_data     <= mig_p3_rd_data;                
+                        mig_p3_en      <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
+                        p3_rd_overflow <= mig_p3_overflow;
+                        p3_rd_error    <= mig_p3_error;
+                        p3_rd_full     <= mig_p3_full;
+                        p3_rd_empty    <= mig_p3_empty;
+                        p3_rd_count    <= mig_p3_count  ;-- wr port
+ end generate;                      
+p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
+                        mig_p3_clk     <= '0';
+                        mig_p3_en      <= '0';
+                        p3_rd_overflow <= '0';
+                        p3_rd_full     <= '0';
+                        p3_rd_empty    <= '0';
+                        p3_rd_count    <= (others => '0');
+                        p3_rd_error    <= '0';
+                        p3_rd_data     <= (others => '0');
+ end generate;                      
+                   p3_wr_full      <= '0';
+                   p3_wr_empty     <= '0';
+                   p3_wr_underrun  <=  '0';
+                   p3_wr_count     <= (others => '0');
+                   p3_wr_error     <= '0';
+                   mig_p3_wr_data  <= (others => '0');
+                   mig_p3_wr_mask  <= (others => '0');
+ end generate;   
+ 
+
+u_config1_4W: if(      
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
+      -- whenever PORT 4 is in Write mode       
+
+p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
+                        mig_p4_clk      <= p4_wr_clk;
+                        mig_p4_wr_data  <= p4_wr_data(31 downto 0);
+                        mig_p4_wr_mask  <= p4_wr_mask(3 downto 0);
+                        mig_p4_en       <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
+                        p4_wr_full      <= mig_p4_full;
+                        p4_wr_empty     <= mig_p4_empty;
+                        p4_wr_underrun  <= mig_p4_underrun;
+                        p4_wr_count     <= mig_p4_count  ;-- wr port
+                        p4_wr_error     <= mig_p4_error;
+ end generate;   
+
+p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
+                        mig_p4_clk      <= '0';
+                        mig_p4_wr_data  <= (others => '0');
+                        mig_p4_wr_mask  <= (others => '0');
+                        mig_p4_en      <= '0';
+                        p4_wr_full      <= '0';
+                        p4_wr_empty     <= '0';
+                        p4_wr_underrun  <=  '0';
+                        p4_wr_count     <= (others => '0');
+                        p4_wr_error     <= '0';
+ end generate;   
+
+                    p4_rd_overflow    <= '0';
+                    p4_rd_error       <= '0';
+                    p4_rd_full        <=  '0';
+                    p4_rd_empty       <= '0';
+                    p4_rd_count       <= (others => '0');
+                    p4_rd_data        <= (others => '0');
+ end generate;   
+
+u_config1_4R : if(      
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
+                       
+p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
+                        mig_p4_clk        <= p4_rd_clk;
+                        p4_rd_data        <= mig_p4_rd_data;                
+                        mig_p4_en         <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
+                        p4_rd_overflow    <= mig_p4_overflow;
+                        p4_rd_error       <= mig_p4_error;
+                        p4_rd_full        <= mig_p4_full;
+                        p4_rd_empty       <= mig_p4_empty;
+                        p4_rd_count       <= mig_p4_count  ;-- wr port
+ end generate;   
+p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
+                        mig_p4_clk        <= '0';
+                        p4_rd_data        <= (others => '0');
+                        mig_p4_en         <= '0';
+                        p4_rd_overflow    <= '0';
+                        p4_rd_error       <= '0';
+                        p4_rd_full        <=  '0';
+                        p4_rd_empty       <= '0';
+                        p4_rd_count       <= (others => '0');
+ end generate;   
+                   p4_wr_full      <= '0';
+                   p4_wr_empty     <= '0';
+                   p4_wr_underrun  <=  '0';
+                   p4_wr_count     <= (others => '0');
+                   p4_wr_error     <= '0';
+                   mig_p4_wr_data  <= (others => '0');
+                   mig_p4_wr_mask  <= (others => '0');
+ end generate;   
+         
+u_config1_5W: if(      
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
+      -- whenever PORT 5 is in Write mode           
+
+                       
+p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
+                        mig_p5_clk   <= p5_wr_clk;
+                        mig_p5_wr_data  <= p5_wr_data(31 downto 0);
+                        mig_p5_wr_mask  <= p5_wr_mask(3 downto 0);
+                        mig_p5_en       <= p5_wr_en; 
+                        p5_wr_full      <= mig_p5_full;
+                        p5_wr_empty     <= mig_p5_empty;
+                        p5_wr_underrun  <= mig_p5_underrun;
+                        p5_wr_count     <= mig_p5_count  ; 
+                        p5_wr_error     <= mig_p5_error;
+                       
+end generate;
+p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
+                        mig_p5_clk      <= '0';
+                        mig_p5_wr_data  <= (others => '0');
+                        mig_p5_wr_mask  <= (others => '0');
+                        mig_p5_en      <= '0';
+                        p5_wr_full      <= '0';
+                        p5_wr_empty     <= '0';
+                        p5_wr_underrun  <=  '0';
+                        p5_wr_count     <= (others => '0');
+                        p5_wr_error     <= '0';
+end generate;
+                    p5_rd_data        <= (others => '0');
+                    p5_rd_overflow    <= '0';
+                    p5_rd_error       <= '0';
+                    p5_rd_full        <=  '0';
+                    p5_rd_empty       <= '0';
+                    p5_rd_count       <= (others => '0');
+end generate;                  
+       
+                       
+                         
+u_config1_5R :if(  
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
+
+p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
+                        mig_p5_clk        <= p5_rd_clk;
+                        p5_rd_data        <= mig_p5_rd_data;                
+                        mig_p5_en         <= p5_rd_en;  
+                        p5_rd_overflow    <= mig_p5_overflow;
+                        p5_rd_error       <= mig_p5_error;
+                        p5_rd_full        <= mig_p5_full;
+                        p5_rd_empty       <= mig_p5_empty;
+                        p5_rd_count       <= mig_p5_count  ; 
+                       
+end generate;
+
+p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
+
+                        mig_p5_clk        <= '0';
+                        p5_rd_data        <= (others => '0');           
+                        mig_p5_en         <= '0';
+                        p5_rd_overflow    <= '0';
+                        p5_rd_error       <= '0';
+                        p5_rd_full        <= '0';
+                        p5_rd_empty       <= '0';
+                        p5_rd_count       <= (others => '0');
+                 
+end generate;
+                  p5_wr_full      <= '0';
+                  p5_wr_empty     <= '0';
+                  p5_wr_underrun  <=  '0';
+                  p5_wr_count     <= (others => '0');
+                  p5_wr_error     <= '0';
+                  mig_p5_wr_data  <= (others => '0');
+                  mig_p5_wr_mask  <= (others => '0');
+                       
+end generate;
+
+     --//////////////////////////////////////////////////////////////////////////
+     --///////////////////////////////////////////////////////////////////////////
+     ----    
+     ----                        B32_B32_B32_B32
+     ----    
+     --///////////////////////////////////////////////////////////////////////////
+     --//////////////////////////////////////////////////////////////////////////
+                
+u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
+
+           
+              -- Inputs from Application CMD Port
+              -- *************  need to hook up rd /wr error outputs
+               
+p0_c2_ena:  if (C_PORT_ENABLE(0) = '1') generate
+                          -- command port signals
+                            mig_p0_arb_en      <=      p0_arb_en ;
+                            mig_p0_cmd_clk     <=      p0_cmd_clk  ;
+                            mig_p0_cmd_en      <=      p0_cmd_en   ;
+                            mig_p0_cmd_ra      <=      p0_cmd_ra  ;
+                            mig_p0_cmd_ba      <=      p0_cmd_ba   ;
+                            mig_p0_cmd_ca      <=      p0_cmd_ca  ;
+                            mig_p0_cmd_instr   <=      p0_cmd_instr;
+                            mig_p0_cmd_bl      <=      ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;                           
+                          -- Data port signals
+                            mig_p0_rd_en    <= p0_rd_en;                            
+                            mig_p0_wr_clk   <= p0_wr_clk;
+                            mig_p0_rd_clk   <= p0_rd_clk;
+                            mig_p0_wr_en    <= p0_wr_en;
+                            mig_p0_wr_data  <= p0_wr_data(31 downto 0); 
+                            mig_p0_wr_mask  <= p0_wr_mask(3 downto 0);
+                            p0_wr_count     <= mig_p0_wr_count;
+                            p0_rd_count  <= mig_p0_rd_count  ; 
+end generate;
+
+p0_c2_dis:  if (C_PORT_ENABLE(0) = '0') generate
+                           
+                            mig_p0_arb_en      <=       '0';
+                            mig_p0_cmd_clk     <=       '0';
+                            mig_p0_cmd_en      <=       '0';
+                            mig_p0_cmd_ra      <=       (others => '0');
+                            mig_p0_cmd_ba      <=       (others => '0');
+                            mig_p0_cmd_ca      <=       (others => '0');
+                            mig_p0_cmd_instr   <=       (others => '0');
+                            mig_p0_cmd_bl      <=       (others => '0');
+                           
+                            mig_p0_rd_en    <= '0';                    
+                            mig_p0_wr_clk   <= '0';
+                            mig_p0_rd_clk   <= '0';
+                            mig_p0_wr_en    <= '0';
+                            mig_p0_wr_data  <= (others => '0'); 
+                            mig_p0_wr_mask  <= (others => '0');
+                            p0_wr_count     <= (others => '0');
+                            p0_rd_count     <= (others => '0');
+
+                           
+end generate;                           
+             
+                         
+                           
+p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
+                          -- command port signals
+
+                            mig_p1_arb_en      <=      p1_arb_en ;
+                            mig_p1_cmd_clk     <=      p1_cmd_clk  ;
+                            mig_p1_cmd_en      <=      p1_cmd_en   ;
+                            mig_p1_cmd_ra      <=      p1_cmd_ra  ;
+                            mig_p1_cmd_ba      <=      p1_cmd_ba   ;
+                            mig_p1_cmd_ca      <=      p1_cmd_ca  ;
+                            mig_p1_cmd_instr   <=      p1_cmd_instr;
+                            mig_p1_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           
+
+                          -- Data port signals
+                 
+                             mig_p1_wr_en    <= p1_wr_en;
+                             mig_p1_wr_clk   <= p1_wr_clk;
+                             mig_p1_rd_en    <= p1_rd_en;
+                             mig_p1_wr_data  <= p1_wr_data(31 downto 0);
+                             mig_p1_wr_mask  <= p1_wr_mask(3 downto 0);                
+                             mig_p1_rd_clk   <= p1_rd_clk;
+                             p1_wr_count     <= mig_p1_wr_count;
+                             p1_rd_count     <= mig_p1_rd_count;
+                           
+end generate;
+p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
+
+                            mig_p1_arb_en      <=       '0';
+                            mig_p1_cmd_clk     <=       '0';
+                            mig_p1_cmd_en      <=       '0';
+                            mig_p1_cmd_ra      <=       (others => '0');
+                            mig_p1_cmd_ba      <=       (others => '0');
+                            mig_p1_cmd_ca      <=       (others => '0');
+                            mig_p1_cmd_instr   <=       (others => '0');
+                            mig_p1_cmd_bl      <=       (others => '0');
+                          -- Data port signals
+                            mig_p1_wr_en    <= '0'; 
+                            mig_p1_wr_clk   <= '0';
+                            mig_p1_rd_en    <= '0';
+                            mig_p1_wr_data  <= (others => '0');
+                            mig_p1_wr_mask  <= (others => '0');                
+                            mig_p1_rd_clk   <= '0';
+                             p1_wr_count     <= (others => '0');
+                             p1_rd_count     <= (others => '0');
+                  
+end generate;
+                           
+                           
+ 
+p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
+                    --MCB Physical port               Logical Port
+                            mig_p2_arb_en      <=      p2_arb_en ;
+                            mig_p2_cmd_clk     <=      p2_cmd_clk  ;
+                            mig_p2_cmd_en      <=      p2_cmd_en   ;
+                            mig_p2_cmd_ra      <=      p2_cmd_ra  ;
+                            mig_p2_cmd_ba      <=      p2_cmd_ba   ;
+                            mig_p2_cmd_ca      <=      p2_cmd_ca  ;
+                            mig_p2_cmd_instr   <=      p2_cmd_instr;
+                            mig_p2_cmd_bl      <=      ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0))  ;                           
+                            
+                             mig_p2_en       <= p2_rd_en;
+                             mig_p2_clk      <= p2_rd_clk;
+                             mig_p3_en       <= p2_wr_en;
+                             mig_p3_clk      <= p2_wr_clk;
+                             mig_p3_wr_data  <= p2_wr_data(31 downto 0);
+                             mig_p3_wr_mask  <= p2_wr_mask(3 downto 0);
+                             p2_wr_count     <= mig_p3_count;
+                             p2_rd_count     <= mig_p2_count;
+end generate;
+p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
+
+                            mig_p2_arb_en      <=       '0';
+                            mig_p2_cmd_clk      <=       '0';
+                            mig_p2_cmd_en      <=       '0';
+                            mig_p2_cmd_ra      <=      (others => '0');
+                            mig_p2_cmd_ba      <=      (others => '0');
+                            mig_p2_cmd_ca      <=      (others => '0');
+                            mig_p2_cmd_instr   <=      (others => '0');
+                            mig_p2_cmd_bl      <=      (others => '0');
+
+                             mig_p2_en      <= '0'; 
+                             mig_p2_clk      <= '0';
+                             mig_p3_en      <= '0';
+                             mig_p3_clk      <= '0';
+                             mig_p3_wr_data  <= (others => '0'); 
+                             mig_p3_wr_mask  <= (others => '0');
+                             p2_rd_count     <= (others => '0');
+                             p2_wr_count     <= (others => '0');
+                           
+end generate;
+                         
+  
+p3_c2_ena:  if (C_PORT_ENABLE(3) = '1') generate
+                    --MCB Physical port               Logical Port
+                            mig_p4_arb_en      <=      p3_arb_en ;
+                            mig_p4_cmd_clk     <=      p3_cmd_clk  ;
+                            mig_p4_cmd_en      <=      p3_cmd_en   ;
+                            mig_p4_cmd_ra      <=      p3_cmd_ra  ;
+                            mig_p4_cmd_ba      <=      p3_cmd_ba   ;
+                            mig_p4_cmd_ca      <=      p3_cmd_ca  ;
+                            mig_p4_cmd_instr   <=      p3_cmd_instr;
+                            mig_p4_cmd_bl      <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0))  ;                           
+
+                            mig_p4_clk      <= p3_rd_clk;
+                            mig_p4_en       <= p3_rd_en;                            
+                            mig_p5_clk      <= p3_wr_clk;
+                            mig_p5_en       <= p3_wr_en; 
+                            mig_p5_wr_data  <= p3_wr_data(31 downto 0);
+                            mig_p5_wr_mask  <= p3_wr_mask(3 downto 0);
+                            p3_rd_count     <= mig_p4_count;
+                            p3_wr_count     <= mig_p5_count;
+end generate;
+                           
+p3_c2_dis:  if (C_PORT_ENABLE(3) = '0') generate
+                            mig_p4_arb_en      <=     '0';
+                            mig_p4_cmd_clk     <=     '0';
+                            mig_p4_cmd_en      <=     '0';
+                            mig_p4_cmd_ra      <=     (others => '0');
+                            mig_p4_cmd_ba      <=     (others => '0');
+                            mig_p4_cmd_ca      <=     (others => '0');
+                            mig_p4_cmd_instr   <=     (others => '0');
+                            mig_p4_cmd_bl      <=     (others => '0');
+                           
+                             mig_p4_clk      <= '0'; 
+                             mig_p4_en      <= '0';                   
+                             mig_p5_clk      <= '0';
+                             mig_p5_en      <= '0';
+                             mig_p5_wr_data  <= (others => '0'); 
+                             mig_p5_wr_mask  <= (others => '0');
+                             p3_rd_count     <= (others => '0');
+                             p3_wr_count     <= (others => '0');
+end generate;
+                           
+                            p0_cmd_empty       <=      mig_p0_cmd_empty ;
+                            p0_cmd_full        <=      mig_p0_cmd_full  ;
+                            p1_cmd_empty       <=      mig_p1_cmd_empty ;
+                            p1_cmd_full        <=      mig_p1_cmd_full  ;
+                            p2_cmd_empty       <=      mig_p2_cmd_empty ;
+                            p2_cmd_full        <=      mig_p2_cmd_full  ;
+                            p3_cmd_empty       <=      mig_p4_cmd_empty ;
+                            p3_cmd_full        <=      mig_p4_cmd_full  ;
+                           
+                           
+                           -- outputs to Applications User Port
+                             p0_rd_data     <= mig_p0_rd_data;
+                             p1_rd_data     <= mig_p1_rd_data;
+                             p2_rd_data     <= mig_p2_rd_data;
+                             p3_rd_data     <= mig_p4_rd_data;
+
+                             p0_rd_empty_i    <= mig_p0_rd_empty;
+                             p1_rd_empty_i    <= mig_p1_rd_empty;
+                             p2_rd_empty    <= mig_p2_empty;
+                             p3_rd_empty    <= mig_p4_empty;
+
+                             p0_rd_full     <= mig_p0_rd_full;
+                             p1_rd_full     <= mig_p1_rd_full;
+                             p2_rd_full     <= mig_p2_full;
+                             p3_rd_full     <= mig_p4_full;
+
+                             p0_rd_error    <= mig_p0_rd_error;
+                             p1_rd_error    <= mig_p1_rd_error;
+                             p2_rd_error    <= mig_p2_error;
+                             p3_rd_error    <= mig_p4_error;
+                            
+                             p0_rd_overflow <= mig_p0_rd_overflow;
+                             p1_rd_overflow <= mig_p1_rd_overflow;
+                             p2_rd_overflow <= mig_p2_overflow;
+                             p3_rd_overflow <= mig_p4_overflow;
+
+                             p0_wr_underrun <= mig_p0_wr_underrun;
+                             p1_wr_underrun <= mig_p1_wr_underrun;
+                             p2_wr_underrun <= mig_p3_underrun;
+                             p3_wr_underrun <= mig_p5_underrun;
+                            
+                             p0_wr_empty    <= mig_p0_wr_empty;
+                             p1_wr_empty    <= mig_p1_wr_empty;
+                             p2_wr_empty    <= mig_p3_empty; 
+                             p3_wr_empty    <= mig_p5_empty; 
+ 
+                             p0_wr_full_i    <= mig_p0_wr_full;
+                             p1_wr_full_i    <= mig_p1_wr_full;
+                             p2_wr_full    <= mig_p3_full;
+                             p3_wr_full    <= mig_p5_full;
+
+                             p0_wr_error    <= mig_p0_wr_error;
+                             p1_wr_error    <= mig_p1_wr_error;
+                             p2_wr_error    <= mig_p3_error;
+                             p3_wr_error    <= mig_p5_error;
+
+    -- unused ports signals
+                            p4_cmd_empty        <=     '0';
+                            p4_cmd_full         <=     '0';
+                            mig_p2_wr_mask     <=      (others => '0');
+                            mig_p4_wr_mask    <=      (others => '0');
+
+                           mig_p2_wr_data     <=      (others => '0');
+                           mig_p4_wr_data     <=      (others => '0');
+
+
+                            p5_cmd_empty        <=     '0';
+                            p5_cmd_full         <=     '0';
+     
+ 
+                             mig_p3_cmd_clk      <=       '0';
+                             mig_p3_cmd_en      <=       '0';
+                             mig_p3_cmd_ra      <=      (others => '0');
+                             mig_p3_cmd_ba      <=      (others => '0');
+                             mig_p3_cmd_ca      <=      (others => '0');
+                             mig_p3_cmd_instr   <=      (others => '0');
+                             mig_p3_cmd_bl      <=      (others => '0');
+                             mig_p3_arb_en      <=       '0'; -- physical cmd port 3 is not used in this config
+                            
+                            
+                            
+                            
+                             mig_p5_arb_en      <=       '0'; -- physical cmd port 3 is not used in this config
+                             mig_p5_cmd_clk      <=       '0';
+                             mig_p5_cmd_en      <=       '0';
+                             mig_p5_cmd_ra      <=      (others => '0');
+                             mig_p5_cmd_ba      <=      (others => '0');
+                             mig_p5_cmd_ca      <=      (others => '0');
+                             mig_p5_cmd_instr   <=      (others => '0');
+                             mig_p5_cmd_bl      <=      (others => '0');
+
+end generate;
+--
+--
+--     --//////////////////////////////////////////////////////////////////////////
+--     --///////////////////////////////////////////////////////////////////////////
+--     ----    
+--     ----                        B64_B32_B32
+--     ----    
+--     --///////////////////////////////////////////////////////////////////////////
+--     --//////////////////////////////////////////////////////////////////////////
+--
+--     
+--     
+u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
+
+              -- Inputs from Application CMD Port
+ 
+ 
+p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
+                mig_p0_arb_en      <=  p0_arb_en ;
+                mig_p0_cmd_clk     <=  p0_cmd_clk  ;
+                mig_p0_cmd_en      <=  p0_cmd_en   ;
+                mig_p0_cmd_ra      <=  p0_cmd_ra  ;
+                mig_p0_cmd_ba      <=  p0_cmd_ba   ;
+                mig_p0_cmd_ca      <=  p0_cmd_ca  ;
+                mig_p0_cmd_instr   <=  p0_cmd_instr;
+                mig_p0_cmd_bl      <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;
+                p0_cmd_empty       <=  mig_p0_cmd_empty ;
+                p0_cmd_full        <=  mig_p0_cmd_full  ;
+
+                mig_p0_wr_clk   <= p0_wr_clk;
+                mig_p0_rd_clk   <= p0_rd_clk;
+                mig_p1_wr_clk   <= p0_wr_clk;
+                mig_p1_rd_clk   <= p0_rd_clk;
+
+                mig_p0_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                mig_p1_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                mig_p0_wr_data  <= p0_wr_data(31 downto 0);
+                mig_p0_wr_mask(3 downto 0)  <= p0_wr_mask(3 downto 0);
+                mig_p1_wr_data  <= p0_wr_data(63  downto  32);
+                mig_p1_wr_mask(3 downto 0)  <= p0_wr_mask(7  downto  4);     
+
+                p0_rd_empty_i       <= mig_p1_rd_empty;
+                p0_rd_data        <= (mig_p1_rd_data & mig_p0_rd_data); 
+                mig_p0_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+                mig_p1_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+
+
+                 p0_wr_count       <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
+                 p0_rd_count       <= mig_p1_rd_count;
+                 p0_wr_empty       <= mig_p1_wr_empty;
+                 p0_wr_error       <= mig_p1_wr_error or mig_p0_wr_error;  
+                 p0_wr_full_i        <= mig_p1_wr_full;
+                 p0_wr_underrun    <= mig_p1_wr_underrun or mig_p0_wr_underrun; 
+                 p0_rd_overflow    <= mig_p1_rd_overflow or mig_p0_rd_overflow; 
+                 p0_rd_error       <= mig_p1_rd_error or mig_p0_rd_error; 
+                 p0_rd_full        <= mig_p1_rd_full;
+
+end generate; 
+p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
+       
+                mig_p0_arb_en      <= '0';
+                mig_p0_cmd_clk     <= '0';
+                mig_p0_cmd_en      <= '0';
+                mig_p0_cmd_ra      <= (others => '0');
+                mig_p0_cmd_ba      <= (others => '0');
+                mig_p0_cmd_ca      <= (others => '0');
+                mig_p0_cmd_instr   <= (others => '0');
+                mig_p0_cmd_bl      <= (others => '0');
+                p0_cmd_empty       <= '0';
+                p0_cmd_full        <= '0';
+
+
+                mig_p0_wr_clk   <= '0';
+                mig_p0_rd_clk   <= '0';
+                mig_p1_wr_clk   <= '0';
+                mig_p1_rd_clk   <= '0';
+               
+                mig_p0_wr_en    <= '0';
+                mig_p1_wr_en    <= '0';
+                mig_p0_wr_data  <= (others => '0');
+                mig_p0_wr_mask  <= (others => '0');
+                mig_p1_wr_data  <= (others => '0');
+                mig_p1_wr_mask  <= (others => '0'); 
+
+                p0_rd_empty_i       <= '0';
+                p0_rd_data        <= (others => '0');
+                mig_p0_rd_en      <= '0';
+                mig_p1_rd_en      <= '0';
+ 
+ 
+                p0_wr_count       <=  (others => '0');
+                p0_rd_count       <=  (others => '0');
+                p0_wr_empty       <=  '0';
+                p0_wr_error       <=  '0';
+                p0_wr_full_i        <=  '0';
+                p0_wr_underrun    <=  '0';
+                p0_rd_overflow    <=  '0';
+                p0_rd_error       <=  '0';
+                p0_rd_full        <=  '0';
+end generate; 
+
+       
+        
+ 
+p1_c3_ena:  if (C_PORT_ENABLE(1) = '1')generate
+
+                mig_p2_arb_en      <=      p1_arb_en ;
+                mig_p2_cmd_clk     <=      p1_cmd_clk  ;
+                mig_p2_cmd_en      <=      p1_cmd_en   ;
+                mig_p2_cmd_ra      <=      p1_cmd_ra  ;
+                mig_p2_cmd_ba      <=      p1_cmd_ba   ;
+                mig_p2_cmd_ca      <=      p1_cmd_ca  ;
+                mig_p2_cmd_instr   <=      p1_cmd_instr;
+                mig_p2_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           
+
+                p1_cmd_empty       <=      mig_p2_cmd_empty;  
+                p1_cmd_full        <=      mig_p2_cmd_full;   
+
+                mig_p2_clk         <= p1_rd_clk;
+                mig_p3_clk         <= p1_wr_clk;
+
+                mig_p3_en       <= p1_wr_en;
+                mig_p3_wr_data  <= p1_wr_data(31 downto 0);
+                mig_p3_wr_mask  <= p1_wr_mask(3 downto 0);
+                mig_p2_en       <= p1_rd_en;
+
+                p1_rd_data        <= mig_p2_rd_data;
+                p1_wr_count       <= mig_p3_count;
+                p1_rd_count       <= mig_p2_count;
+                p1_wr_empty       <= mig_p3_empty;
+                p1_wr_error       <= mig_p3_error;                 
+                p1_wr_full_i        <= mig_p3_full;
+                p1_wr_underrun    <= mig_p3_underrun;
+                p1_rd_overflow    <= mig_p2_overflow; 
+                p1_rd_error       <= mig_p2_error;
+                p1_rd_full        <= mig_p2_full;
+                p1_rd_empty_i       <= mig_p2_empty;
+ end generate;
+
+p1_c3_dis:  if (C_PORT_ENABLE(1) = '0')generate
+
+                mig_p2_arb_en      <=      '0'; 
+                mig_p2_cmd_clk     <=      '0'; 
+                mig_p2_cmd_en      <=     '0'; 
+                mig_p2_cmd_ra      <=     (others => '0'); 
+                mig_p2_cmd_ba      <=     (others => '0'); 
+                mig_p2_cmd_ca      <=     (others => '0'); 
+                mig_p2_cmd_instr   <=     (others => '0'); 
+                mig_p2_cmd_bl      <=     (others => '0'); 
+                p1_cmd_empty       <=     '0'; 
+                p1_cmd_full        <=     '0'; 
+                mig_p3_en      <= '0'; 
+                mig_p3_wr_data  <= (others => '0'); 
+                mig_p3_wr_mask  <= (others => '0'); 
+                mig_p2_en      <= '0'; 
+
+                mig_p2_clk   <= '0'; 
+                mig_p3_clk   <= '0'; 
+               
+                p1_rd_data        <= (others => '0'); 
+                p1_wr_count       <= (others => '0'); 
+                p1_rd_count       <= (others => '0'); 
+                p1_wr_empty       <= '0'; 
+                p1_wr_error       <= '0';         
+                p1_wr_full_i        <= '0'; 
+                p1_wr_underrun    <= '0'; 
+                p1_rd_overflow    <= '0'; 
+                p1_rd_error       <= '0'; 
+                p1_rd_full        <=  '0'; 
+                p1_rd_empty_i       <= '0'; 
+ 
+end generate;
+       
+p2_c3_ena:  if (C_PORT_ENABLE(2) = '1')generate
+                mig_p4_arb_en      <= p2_arb_en ;
+                mig_p4_cmd_clk     <= p2_cmd_clk  ;
+                mig_p4_cmd_en      <= p2_cmd_en   ;
+                mig_p4_cmd_ra      <= p2_cmd_ra  ;
+                mig_p4_cmd_ba      <= p2_cmd_ba   ;
+                mig_p4_cmd_ca      <= p2_cmd_ca  ;
+                mig_p4_cmd_instr   <= p2_cmd_instr;
+                mig_p4_cmd_bl      <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0))  ;                           
+
+                p2_cmd_empty       <= mig_p4_cmd_empty ; 
+                p2_cmd_full        <= mig_p4_cmd_full  ; 
+                mig_p5_en          <= p2_wr_en;
+                mig_p5_wr_data     <= p2_wr_data(31 downto 0);
+                mig_p5_wr_mask     <= p2_wr_mask(3 downto 0);
+                mig_p4_en          <= p2_rd_en;
+               
+                 mig_p4_clk        <= p2_rd_clk;
+                 mig_p5_clk        <= p2_wr_clk;
+
+                 p2_rd_data        <= mig_p4_rd_data;
+                 p2_wr_count       <= mig_p5_count;
+                 p2_rd_count       <= mig_p4_count;
+                 p2_wr_empty       <= mig_p5_empty;
+                 p2_wr_full        <= mig_p5_full;
+                 p2_wr_error       <= mig_p5_error;  
+                 p2_wr_underrun    <= mig_p5_underrun;
+                 p2_rd_overflow    <= mig_p4_overflow;    
+                 p2_rd_error       <= mig_p4_error;
+                 p2_rd_full        <= mig_p4_full;
+                 p2_rd_empty       <= mig_p4_empty;
+
+end generate; 
+               
+p2_c3_dis:  if (C_PORT_ENABLE(2) = '0')generate
+
+                mig_p4_arb_en      <= '0'; 
+                mig_p4_cmd_clk     <= '0';   
+                mig_p4_cmd_en      <= '0';   
+                mig_p4_cmd_ra      <= (others => '0');   
+                mig_p4_cmd_ba      <= (others => '0');   
+                mig_p4_cmd_ca      <= (others => '0');   
+                mig_p4_cmd_instr   <= (others => '0');   
+                mig_p4_cmd_bl      <= (others => '0');   
+                p2_cmd_empty       <= '0';   
+                p2_cmd_full        <= '0'; 
+                mig_p5_en          <= '0'; 
+                mig_p5_wr_data     <= (others => '0'); 
+                mig_p5_wr_mask     <= (others => '0'); 
+                mig_p4_en          <= '0'; 
+
+                 mig_p4_clk        <= '0'; 
+                 mig_p5_clk        <= '0'; 
+
+                 p2_rd_data        <=   (others => '0');   
+                 p2_wr_count       <=   (others => '0');   
+                 p2_rd_count       <=   (others => '0');   
+                 p2_wr_empty       <=   '0'; 
+                 p2_wr_full        <=   '0';  
+                 p2_wr_error       <=   '0';   
+                 p2_wr_underrun    <=   '0';   
+                 p2_rd_overflow    <=   '0';     
+                 p2_rd_error       <=   '0'; 
+                 p2_rd_full        <=   '0'; 
+                 p2_rd_empty       <=   '0'; 
+
+end generate; 
+
+             -- MCB's port 1,3,5 is not used in this Config mode
+                mig_p1_arb_en      <=       '0';
+                mig_p1_cmd_clk      <=       '0';
+                mig_p1_cmd_en      <=       '0';
+                mig_p1_cmd_ra      <=      (others => '0');
+                mig_p1_cmd_ba      <=      (others => '0');
+                mig_p1_cmd_ca      <=      (others => '0');
+               
+                mig_p1_cmd_instr   <=      (others => '0');
+                mig_p1_cmd_bl      <=      (others => '0');
+                
+                mig_p3_arb_en    <=      '0'; 
+                mig_p3_cmd_clk      <=       '0';
+                mig_p3_cmd_en      <=       '0';
+                mig_p3_cmd_ra      <=      (others => '0');
+                mig_p3_cmd_ba      <=      (others => '0');
+                mig_p3_cmd_ca      <=      (others => '0');
+               
+                mig_p3_cmd_instr   <=      (others => '0');
+                mig_p3_cmd_bl      <=      (others => '0');
+
+                mig_p5_arb_en    <=      '0'; 
+                mig_p5_cmd_clk      <=       '0';
+                mig_p5_cmd_en      <=       '0';
+                mig_p5_cmd_ra      <=      (others => '0');
+                mig_p5_cmd_ba      <=      (others => '0');
+                mig_p5_cmd_ca      <=      (others => '0');
+               
+                mig_p5_cmd_instr   <=      (others => '0');
+                mig_p5_cmd_bl      <=      (others => '0');
+ 
+end generate;
+
+u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
+
+              -- Inputs from Application CMD Port
+
+p0_c4_ena:  if (C_PORT_ENABLE(0) = '1') generate
+               
+                        mig_p0_arb_en      <=      p0_arb_en ;
+                        mig_p1_arb_en      <=      p0_arb_en ;
+                       
+                        mig_p0_cmd_clk     <=      p0_cmd_clk  ;
+                        mig_p0_cmd_en      <=      p0_cmd_en   ;
+                        mig_p0_cmd_ra      <=      p0_cmd_ra  ;
+                        mig_p0_cmd_ba      <=      p0_cmd_ba   ;
+                        mig_p0_cmd_ca      <=      p0_cmd_ca  ;
+                        mig_p0_cmd_instr   <=      p0_cmd_instr;
+                        mig_p0_cmd_bl      <=      ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;
+
+                         mig_p0_wr_clk   <= p0_wr_clk;
+                         mig_p0_rd_clk   <= p0_rd_clk;
+                         mig_p1_wr_clk   <= p0_wr_clk;
+                         mig_p1_rd_clk   <= p0_rd_clk;
+                         mig_p0_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                         mig_p0_wr_data  <= p0_wr_data(31 downto 0);
+                         mig_p0_wr_mask(3 downto 0)  <= p0_wr_mask(3 downto 0);
+                         mig_p1_wr_data  <= p0_wr_data(63  downto  32);
+                         mig_p1_wr_mask(3 downto 0)  <= p0_wr_mask(7  downto  4);                
+                         mig_p1_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                         mig_p0_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+                         mig_p1_rd_en    <= p0_rd_en and not p0_rd_empty_i;  
+                         p0_rd_data     <= (mig_p1_rd_data & mig_p0_rd_data);
+                        
+                         p0_cmd_empty   <=     mig_p0_cmd_empty ;
+                         p0_cmd_full    <=     mig_p0_cmd_full  ;
+                         p0_wr_empty    <= mig_p1_wr_empty;      
+                         p0_wr_full_i    <= mig_p1_wr_full;
+                         p0_wr_error    <= mig_p1_wr_error or mig_p0_wr_error; 
+                         p0_wr_count    <= mig_p1_wr_count;
+                         p0_rd_count    <= mig_p1_rd_count;
+                         p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun; 
+                         p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow; 
+                         p0_rd_error    <= mig_p1_rd_error or mig_p0_rd_error; 
+                         p0_rd_full     <= mig_p1_rd_full;
+                         p0_rd_empty_i    <= mig_p1_rd_empty;
+end generate;                       
+
+p0_c4_dis:  if (C_PORT_ENABLE(0) = '0') generate
+                        mig_p0_arb_en      <=       '0';
+                        mig_p0_cmd_clk      <=       '0';
+                        mig_p0_cmd_en      <=       '0';
+                        mig_p0_cmd_ra      <=      (others => '0');
+                        mig_p0_cmd_ba      <=      (others => '0');
+                        mig_p0_cmd_ca      <=      (others => '0');
+                        mig_p0_cmd_instr   <=      (others => '0');
+                        mig_p0_cmd_bl      <=      (others => '0');
+
+                         mig_p0_wr_clk   <= '0';
+                         mig_p0_rd_clk   <= '0';
+                         mig_p1_wr_clk   <= '0';
+                         mig_p1_rd_clk   <= '0';
+                         mig_p0_wr_en    <= '0';
+                         mig_p1_wr_en    <= '0';
+                         mig_p0_wr_data  <= (others => '0');
+                         mig_p0_wr_mask  <= (others => '0');
+                         mig_p1_wr_data  <= (others => '0');
+                         mig_p1_wr_mask  <= (others => '0');            
+                  --      mig_p1_wr_en    <= (others => '0');
+                         mig_p0_rd_en    <= '0';
+                         mig_p1_rd_en    <= '0';
+                         p0_rd_data     <= (others => '0');
+
+
+                         p0_cmd_empty   <= '0';
+                         p0_cmd_full    <= '0';
+                         p0_wr_empty    <= '0';
+                         p0_wr_full_i     <= '0';
+                         p0_wr_error    <= '0';
+                         p0_wr_count    <= (others => '0');
+                         p0_rd_count    <= (others => '0');
+                         p0_wr_underrun <= '0';  
+                         p0_rd_overflow <= '0';
+                         p0_rd_error    <= '0';
+                         p0_rd_full     <= '0';
+                         p0_rd_empty_i    <= '0';
+                 
+                 
+end generate;
+      
+
+p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
+
+                        mig_p2_arb_en      <=      p1_arb_en ;
+                       
+                        mig_p2_cmd_clk     <=      p1_cmd_clk  ;
+                        mig_p2_cmd_en      <=      p1_cmd_en   ;
+                        mig_p2_cmd_ra      <=      p1_cmd_ra  ;
+                        mig_p2_cmd_ba      <=      p1_cmd_ba   ;
+                        mig_p2_cmd_ca      <=      p1_cmd_ca  ;
+                        mig_p2_cmd_instr   <=      p1_cmd_instr;
+                        mig_p2_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           
+
+
+                         mig_p2_clk     <= p1_rd_clk;
+                         mig_p3_clk     <= p1_wr_clk;
+                         mig_p4_clk     <= p1_rd_clk;
+                         mig_p5_clk     <= p1_wr_clk;
+                         mig_p3_en      <= p1_wr_en and not p1_wr_full_i;
+                         mig_p5_en      <= p1_wr_en and not p1_wr_full_i;
+                         mig_p3_wr_data  <= p1_wr_data(31 downto 0);
+                         mig_p3_wr_mask  <= p1_wr_mask(3 downto 0);
+                         mig_p5_wr_data  <= p1_wr_data(63 downto 32);
+                         mig_p5_wr_mask  <= p1_wr_mask(7 downto 4);
+                         mig_p2_en       <= p1_rd_en and not p1_rd_empty_i;
+                         mig_p4_en       <= p1_rd_en and not p1_rd_empty_i;
+                        
+                         p1_cmd_empty       <=      mig_p2_cmd_empty ;  
+                         p1_cmd_full        <=      mig_p2_cmd_full  ;
+
+                         p1_wr_count    <= mig_p5_count;
+                         p1_rd_count    <= mig_p4_count;
+                         p1_wr_full_i    <= mig_p5_full;
+                         p1_wr_error    <= mig_p5_error or mig_p5_error;
+                         p1_wr_empty    <= mig_p5_empty;
+                         p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
+                         p1_rd_overflow <= mig_p4_overflow;
+                         p1_rd_error    <= mig_p4_error;
+                         p1_rd_full     <= mig_p4_full;
+                         p1_rd_empty_i    <= mig_p4_empty;
+
+                         p1_rd_data     <= (mig_p4_rd_data & mig_p2_rd_data);
+                       
+end generate;                       
+p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
+
+                        mig_p2_arb_en      <= '0';
+                  --     mig_p3_arb_en      <= (others => '0');
+                 --      mig_p4_arb_en      <= (others => '0');
+                 --      mig_p5_arb_en      <= (others => '0');
+                       
+                        mig_p2_cmd_clk     <= '0';
+                        mig_p2_cmd_en      <= '0';
+                        mig_p2_cmd_ra      <= (others => '0');
+                        mig_p2_cmd_ba      <= (others => '0');
+                        mig_p2_cmd_ca      <= (others => '0');
+                        mig_p2_cmd_instr   <= (others => '0');
+                        mig_p2_cmd_bl      <= (others => '0');
+                        mig_p2_clk      <= '0';
+                        mig_p3_clk      <= '0';
+                        mig_p4_clk      <= '0';
+                        mig_p5_clk      <= '0';
+                        mig_p3_en      <= '0';
+                        mig_p5_en      <= '0';
+                        mig_p3_wr_data  <= (others => '0');
+                        mig_p3_wr_mask  <= (others => '0');
+                        mig_p5_wr_data  <= (others => '0');
+                        mig_p5_wr_mask  <= (others => '0'); 
+                        mig_p2_en       <= '0';
+                        mig_p4_en       <= '0';
+                        p1_cmd_empty    <= '0';  
+                        p1_cmd_full     <= '0';  
+
+                        p1_wr_count    <= (others => '0');
+                        p1_rd_count    <= (others => '0');
+                        p1_wr_full_i     <= '0';
+                        p1_wr_error    <= '0';
+                        p1_wr_empty    <= '0';
+                        p1_wr_underrun <= '0';
+                        p1_rd_overflow <= '0';
+                        p1_rd_error    <= '0'; 
+                        p1_rd_full     <= '0'; 
+                        p1_rd_empty_i    <= '0'; 
+                        p1_rd_data     <= (others => '0');
+                       
+end generate;                       
+              
+                 -- unused MCB's signals in this configuration
+                        mig_p3_arb_en      <=       '0';
+                        mig_p4_arb_en      <=       '0';
+                        mig_p5_arb_en      <=       '0';
+                       
+                        mig_p3_cmd_clk      <=       '0';
+                        mig_p3_cmd_en      <=       '0';
+                        mig_p3_cmd_ra      <=      (others => '0');
+                        mig_p3_cmd_ba      <=      (others => '0');
+                        mig_p3_cmd_ca      <=      (others => '0');
+                        mig_p3_cmd_instr   <=      (others => '0');
+
+                        mig_p4_cmd_clk      <=       '0';
+                        mig_p4_cmd_en      <=       '0';
+                        mig_p4_cmd_ra      <=      (others => '0');
+                        mig_p4_cmd_ba      <=      (others => '0');
+                        mig_p4_cmd_ca      <=      (others => '0');
+                        mig_p4_cmd_instr   <=      (others => '0');
+                        mig_p4_cmd_bl      <=      (others => '0');
+
+                        mig_p5_cmd_clk      <=       '0';
+                        mig_p5_cmd_en      <=       '0';
+                        mig_p5_cmd_ra      <=      (others => '0');
+                        mig_p5_cmd_ba      <=      (others => '0');
+                        mig_p5_cmd_ca      <=      (others => '0');                       
+                        mig_p5_cmd_instr   <=      (others => '0');
+                        mig_p5_cmd_bl      <=      (others => '0');
+
+ end generate;                       
+               
+                
+--*******************************BEGIN OF CONFIG 5 SIGNALS ********************************     
+
+u_config_5:   if(C_PORT_CONFIG = "B128" ) generate
+
+
+              -- Inputs from Application CMD Port
+               
+                mig_p0_arb_en      <=  p0_arb_en ;
+                mig_p0_cmd_clk     <=  p0_cmd_clk  ;
+                mig_p0_cmd_en      <=  p0_cmd_en   ;
+                mig_p0_cmd_ra      <=  p0_cmd_ra  ;
+                mig_p0_cmd_ba      <=  p0_cmd_ba   ;
+                mig_p0_cmd_ca      <=  p0_cmd_ca  ;
+                mig_p0_cmd_instr   <=  p0_cmd_instr;
+                mig_p0_cmd_bl      <=      ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;               
+                p0_cmd_empty       <=      mig_p0_cmd_empty ;
+                p0_cmd_full        <=      mig_p0_cmd_full  ;
+               
+ 
+ 
+               -- Inputs from Application User Port
+                
+                 mig_p0_wr_clk   <= p0_wr_clk;
+                 mig_p0_rd_clk   <= p0_rd_clk;
+                 mig_p1_wr_clk   <= p0_wr_clk;
+                 mig_p1_rd_clk   <= p0_rd_clk;
+                
+                 mig_p2_clk   <= p0_rd_clk;
+                 mig_p3_clk   <= p0_wr_clk;
+                 mig_p4_clk   <= p0_rd_clk;
+                 mig_p5_clk   <= p0_wr_clk;
+                
+                
+                
+                 mig_p0_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                 mig_p1_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                 mig_p3_en       <= p0_wr_en and not p0_wr_full_i;
+                 mig_p5_en       <= p0_wr_en and not p0_wr_full_i;
+                
+                
+                
+                 mig_p0_wr_data <= p0_wr_data(31 downto 0);
+                 mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
+                 mig_p1_wr_data <= p0_wr_data(63  downto  32);
+                 mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7  downto  4);                
+                 mig_p3_wr_data <= p0_wr_data(95  downto  64);
+                 mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11  downto  8);
+                 mig_p5_wr_data <= p0_wr_data(127  downto  96);
+                 mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15  downto  12);
+                
+                 mig_p0_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+                 mig_p1_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+                 mig_p2_en       <= p0_rd_en and not p0_rd_empty_i;
+                 mig_p4_en       <= p0_rd_en and not p0_rd_empty_i;
+                
+               -- outputs to Applications User Port
+                 p0_rd_data     <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
+                 p0_rd_empty_i    <= mig_p4_empty;
+                 p0_rd_full     <= mig_p4_full;
+                 p0_rd_error    <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;  
+                 p0_rd_overflow    <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow; 
+
+                 p0_wr_underrun    <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;      
+                 p0_wr_empty    <= mig_p5_empty;
+                 p0_wr_full_i     <= mig_p5_full;
+                 p0_wr_error    <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error; 
+                
+                 p0_wr_count    <= mig_p5_count;
+                 p0_rd_count    <= mig_p4_count;
+
+
+              -- unused MCB's siganls in this configuration
+               
+                mig_p1_arb_en      <=       '0';
+                mig_p1_cmd_clk      <=       '0';
+                mig_p1_cmd_en      <=       '0';
+                mig_p1_cmd_ra      <=      (others => '0');
+                mig_p1_cmd_ba      <=      (others => '0');
+                mig_p1_cmd_ca      <=      (others => '0');
+               
+                mig_p1_cmd_instr   <=      (others => '0');
+                mig_p1_cmd_bl      <=      (others => '0');
+               
+                mig_p2_arb_en    <=      '0';
+                mig_p2_cmd_clk      <=       '0';
+                mig_p2_cmd_en      <=       '0';
+                mig_p2_cmd_ra      <=      (others => '0');
+                mig_p2_cmd_ba      <=      (others => '0');
+                mig_p2_cmd_ca      <=      (others => '0');
+               
+                mig_p2_cmd_instr   <=      (others => '0');
+                mig_p2_cmd_bl      <=      (others => '0');
+               
+                mig_p3_arb_en    <=      '0';
+                mig_p3_cmd_clk      <=       '0';
+                mig_p3_cmd_en      <=       '0';
+                mig_p3_cmd_ra      <=      (others => '0');
+                mig_p3_cmd_ba      <=      (others => '0');
+                mig_p3_cmd_ca      <=      (others => '0');
+               
+                mig_p3_cmd_instr   <=      (others => '0');
+                mig_p3_cmd_bl      <=      (others => '0');
+               
+                mig_p4_arb_en    <=      '0';
+                mig_p4_cmd_clk      <=       '0';
+                mig_p4_cmd_en      <=       '0';
+                mig_p4_cmd_ra      <=      (others => '0');
+                mig_p4_cmd_ba      <=      (others => '0');
+                mig_p4_cmd_ca      <=      (others => '0');
+               
+                mig_p4_cmd_instr   <=      (others => '0');
+                mig_p4_cmd_bl      <=      (others => '0');
+               
+                mig_p5_arb_en    <=       '0';
+                mig_p5_cmd_clk      <=       '0';
+                mig_p5_cmd_en      <=       '0';
+                mig_p5_cmd_ra      <=      (others => '0');
+                mig_p5_cmd_ba      <=      (others => '0');
+                mig_p5_cmd_ca      <=      (others => '0');
+               
+                mig_p5_cmd_instr   <=      (others => '0');
+                mig_p5_cmd_bl      <=      (others => '0');
+                             
+--*******************************END OF CONFIG 5 SIGNALS ********************************     
+                                
+end generate;
+
+uo_cal_start <= uo_cal_start_int;
+
+
+
+samc_0:   MCB 
+   GENERIC MAP   
+     (          PORT_CONFIG             => C_PORT_CONFIG,                                   
+               MEM_WIDTH              => C_NUM_DQ_PINS    ,       
+               MEM_TYPE                => C_MEM_TYPE       ,
+               MEM_BURST_LEN            => C_MEM_BURST_LEN  , 
+               MEM_ADDR_ORDER           => C_MEM_ADDR_ORDER,              
+               MEM_CAS_LATENCY          => C_MEM_CAS_LATENCY,       
+               MEM_DDR3_CAS_LATENCY      => C_MEM_DDR3_CAS_LATENCY   ,
+               MEM_DDR2_WRT_RECOVERY     => C_MEM_DDR2_WRT_RECOVERY  ,
+               MEM_DDR3_WRT_RECOVERY     => C_MEM_DDR3_WRT_RECOVERY  ,
+               MEM_MOBILE_PA_SR          => C_MEM_MOBILE_PA_SR       ,
+               MEM_DDR1_2_ODS              => C_MEM_DDR1_2_ODS         ,
+               MEM_DDR3_ODS                => C_MEM_DDR3_ODS           ,
+               MEM_DDR2_RTT                => C_MEM_DDR2_RTT           ,
+               MEM_DDR3_RTT                => C_MEM_DDR3_RTT           ,
+               MEM_DDR3_ADD_LATENCY        => C_MEM_DDR3_ADD_LATENCY   ,
+               MEM_DDR2_ADD_LATENCY        => C_MEM_DDR2_ADD_LATENCY   ,
+               MEM_MOBILE_TC_SR            => C_MEM_MOBILE_TC_SR       ,
+               MEM_MDDR_ODS                => C_MEM_MDDR_ODS           ,
+               MEM_DDR2_DIFF_DQS_EN        => C_MEM_DDR2_DIFF_DQS_EN   ,
+               MEM_DDR2_3_PA_SR            => C_MEM_DDR2_3_PA_SR       ,
+               MEM_DDR3_CAS_WR_LATENCY    => C_MEM_DDR3_CAS_WR_LATENCY,
+               MEM_DDR3_AUTO_SR           => C_MEM_DDR3_AUTO_SR       ,
+               MEM_DDR2_3_HIGH_TEMP_SR    => C_MEM_DDR2_3_HIGH_TEMP_SR,
+               MEM_DDR3_DYN_WRT_ODT       => C_MEM_DDR3_DYN_WRT_ODT   ,
+               MEM_RA_SIZE               => C_MEM_ADDR_WIDTH            ,
+               MEM_BA_SIZE               => C_MEM_BANKADDR_WIDTH            ,
+               MEM_CA_SIZE               => C_MEM_NUM_COL_BITS            ,
+               MEM_RAS_VAL               => MEM_RAS_VAL            , 
+               MEM_RCD_VAL               => MEM_RCD_VAL            , 
+               MEM_REFI_VAL               => MEM_REFI_VAL           , 
+               MEM_RFC_VAL               => MEM_RFC_VAL            , 
+               MEM_RP_VAL                => MEM_RP_VAL             , 
+               MEM_WR_VAL                => MEM_WR_VAL             , 
+               MEM_RTP_VAL               => MEM_RTP_VAL            , 
+               MEM_WTR_VAL               => MEM_WTR_VAL            ,
+               CAL_BYPASS        => C_MC_CALIB_BYPASS,     
+               CAL_RA            => C_MC_CALIBRATION_RA,    
+               CAL_BA            => C_MC_CALIBRATION_BA ,   
+               CAL_CA            => C_MC_CALIBRATION_CA, 
+               CAL_CLK_DIV        => C_MC_CALIBRATION_CLK_DIV,      
+               CAL_DELAY         => C_MC_CALIBRATION_DELAY,
+--               CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
+               ARB_NUM_TIME_SLOTS         => C_ARB_NUM_TIME_SLOTS,
+               ARB_TIME_SLOT_0            => C_ARB_TIME_SLOT_0,        
+               ARB_TIME_SLOT_1            => C_ARB_TIME_SLOT_1,        
+               ARB_TIME_SLOT_2            => C_ARB_TIME_SLOT_2,        
+               ARB_TIME_SLOT_3            => C_ARB_TIME_SLOT_3,        
+               ARB_TIME_SLOT_4            => C_ARB_TIME_SLOT_4,        
+               ARB_TIME_SLOT_5            => C_ARB_TIME_SLOT_5,        
+               ARB_TIME_SLOT_6            => C_ARB_TIME_SLOT_6,        
+               ARB_TIME_SLOT_7            => C_ARB_TIME_SLOT_7,        
+               ARB_TIME_SLOT_8            => C_ARB_TIME_SLOT_8,        
+               ARB_TIME_SLOT_9            => C_ARB_TIME_SLOT_9,        
+               ARB_TIME_SLOT_10           => C_ARB_TIME_SLOT_10,            
+               ARB_TIME_SLOT_11           => C_ARB_TIME_SLOT_11            
+             )   PORT MAP                                                
+     (
+                                                                    
+            -- HIGH-SPEED PLL clock interface
+             
+             PLLCLK            => pllclk1,
+             PLLCE              => pllce1,
+
+             PLLLOCK           => '1',
+             
+            -- DQS CLOCK NETWork interface
+             
+             DQSIOIN           => idelay_dqs_ioi_s,
+             DQSIOIP           => idelay_dqs_ioi_m,
+             UDQSIOIN          => idelay_udqs_ioi_s,
+             UDQSIOIP          => idelay_udqs_ioi_m,
+
+
+              --DQSPIN    => in_pre_dqsp,
+               DQI       => in_dq,
+            -- RESETS - GLOBAl and local
+             SYSRST         => MCB_SYSRST ,
+   
+           -- command port 0
+             P0ARBEN            => mig_p0_arb_en,
+             P0CMDCLK           => mig_p0_cmd_clk,
+             P0CMDEN            => mig_p0_cmd_en,
+             P0CMDRA            => mig_p0_cmd_ra,
+             P0CMDBA            => mig_p0_cmd_ba,
+             P0CMDCA            => mig_p0_cmd_ca,
+             
+             P0CMDINSTR         => mig_p0_cmd_instr,
+             P0CMDBL            => mig_p0_cmd_bl,
+             P0CMDEMPTY         => mig_p0_cmd_empty,
+             P0CMDFULL          => mig_p0_cmd_full,
+             
+            -- command port 1 
+            
+             P1ARBEN            => mig_p1_arb_en,
+             P1CMDCLK           => mig_p1_cmd_clk,
+             P1CMDEN            => mig_p1_cmd_en,
+             P1CMDRA            => mig_p1_cmd_ra,
+             P1CMDBA            => mig_p1_cmd_ba,
+             P1CMDCA            => mig_p1_cmd_ca,
+             
+             P1CMDINSTR         => mig_p1_cmd_instr,
+             P1CMDBL            => mig_p1_cmd_bl,
+             P1CMDEMPTY         => mig_p1_cmd_empty,
+             P1CMDFULL          => mig_p1_cmd_full,
+
+            -- command port 2
+             
+             P2ARBEN            => mig_p2_arb_en,
+             P2CMDCLK           => mig_p2_cmd_clk,
+             P2CMDEN            => mig_p2_cmd_en,
+             P2CMDRA            => mig_p2_cmd_ra,
+             P2CMDBA            => mig_p2_cmd_ba,
+             P2CMDCA            => mig_p2_cmd_ca,
+             
+             P2CMDINSTR         => mig_p2_cmd_instr,
+             P2CMDBL            => mig_p2_cmd_bl,
+             P2CMDEMPTY         => mig_p2_cmd_empty,
+             P2CMDFULL          => mig_p2_cmd_full,
+
+            -- command port 3
+             
+             P3ARBEN            => mig_p3_arb_en,
+             P3CMDCLK           => mig_p3_cmd_clk,
+             P3CMDEN            => mig_p3_cmd_en,
+             P3CMDRA            => mig_p3_cmd_ra,
+             P3CMDBA            => mig_p3_cmd_ba,
+             P3CMDCA            => mig_p3_cmd_ca,
+                               
+             P3CMDINSTR         => mig_p3_cmd_instr,
+             P3CMDBL            => mig_p3_cmd_bl,
+             P3CMDEMPTY         => mig_p3_cmd_empty,
+             P3CMDFULL          => mig_p3_cmd_full,
+
+            -- command port 4 -- don't care in config 2
+             
+             P4ARBEN            => mig_p4_arb_en,
+             P4CMDCLK           => mig_p4_cmd_clk,
+             P4CMDEN            => mig_p4_cmd_en,
+             P4CMDRA            => mig_p4_cmd_ra,
+             P4CMDBA            => mig_p4_cmd_ba,
+             P4CMDCA            => mig_p4_cmd_ca,
+                               
+             P4CMDINSTR         => mig_p4_cmd_instr,
+             P4CMDBL            => mig_p4_cmd_bl,
+             P4CMDEMPTY         => mig_p4_cmd_empty,
+             P4CMDFULL          => mig_p4_cmd_full,
+
+            -- command port 5-- don't care in config 2
+             
+             P5ARBEN            => mig_p5_arb_en,
+             P5CMDCLK           => mig_p5_cmd_clk,
+             P5CMDEN            => mig_p5_cmd_en,
+             P5CMDRA            => mig_p5_cmd_ra,
+             P5CMDBA            => mig_p5_cmd_ba,
+             P5CMDCA            => mig_p5_cmd_ca,
+                               
+             P5CMDINSTR         => mig_p5_cmd_instr,
+             P5CMDBL            => mig_p5_cmd_bl,
+             P5CMDEMPTY         => mig_p5_cmd_empty,
+             P5CMDFULL          => mig_p5_cmd_full,
+
+              
+            -- IOI & IOB SIGNals/tristate interface
+             
+             DQIOWEN0        => dqIO_w_en_0,
+             DQSIOWEN90P     => dqsIO_w_en_90_p,
+             DQSIOWEN90N     => dqsIO_w_en_90_n,
+             
+             
+            -- IOB MEMORY INTerface signals
+             ADDR         => address_90, 
+             BA           => ba_90 ,     
+             RAS         => ras_90 ,    
+             CAS         => cas_90 ,    
+             WE          => we_90  ,    
+             CKE          => cke_90 ,    
+             ODT          => odt_90 ,    
+             RST          => rst_90 ,    
+             
+            -- CALIBRATION DRP interface
+             IOIDRPCLK           => ioi_drp_clk    ,
+             IOIDRPADDR          => ioi_drp_addr   ,
+             IOIDRPSDO           => ioi_drp_sdo    ,
+             IOIDRPSDI           => ioi_drp_sdi    ,
+             IOIDRPCS            => ioi_drp_cs     ,
+             IOIDRPADD           => ioi_drp_add    ,
+             IOIDRPBROADCAST     => ioi_drp_broadcast  ,
+             IOIDRPTRAIN         => ioi_drp_train    ,
+             IOIDRPUPDATE         => ioi_drp_update ,
+             
+            -- CALIBRATION DAtacapture interface
+            --SPECIAL COMMANDs
+             RECAL               => mcb_recal    ,
+             UIREAD               => mcb_ui_read,
+             UIADD                => mcb_ui_add    ,
+             UICS                 => mcb_ui_cs     ,
+             UICLK                => mcb_ui_clk    ,
+             UISDI                => mcb_ui_sdi    ,
+             UIADDR               => mcb_ui_addr   ,
+             UIBROADCAST          => mcb_ui_broadcast,
+             UIDRPUPDATE          => mcb_ui_drp_update,
+             UIDONECAL            => mcb_ui_done_cal,
+             UICMD                => mcb_ui_cmd,
+             UICMDIN              => mcb_ui_cmd_in,
+             UICMDEN              => mcb_ui_cmd_en,
+             UIDQCOUNT            => mcb_ui_dqcount,
+             UIDQLOWERDEC          => mcb_ui_dq_lower_dec,
+             UIDQLOWERINC          => mcb_ui_dq_lower_inc,
+             UIDQUPPERDEC          => mcb_ui_dq_upper_dec,
+             UIDQUPPERINC          => mcb_ui_dq_upper_inc,
+             UIUDQSDEC          => mcb_ui_udqs_dec,
+             UIUDQSINC          => mcb_ui_udqs_inc,
+             UILDQSDEC          => mcb_ui_ldqs_dec,
+             UILDQSINC          => mcb_ui_ldqs_inc,
+             UODATA             => uo_data_int,
+             UODATAVALID          => uo_data_valid_int,
+             UODONECAL            => hard_done_cal  ,
+             UOCMDREADYIN         => uo_cmd_ready_in_int,
+             UOREFRSHFLAG         => uo_refrsh_flag_xhdl23,
+             UOCALSTART           => uo_cal_start_int,
+             UOSDO                => uo_sdo_xhdl24,
+
+            --CONTROL SIGNALS
+              STATUS                    => status,
+              SELFREFRESHENTER          => selfrefresh_mcb_enter,
+              SELFREFRESHMODE           => selfrefresh_mcb_mode, 
+------------------------------------------------
+--MUIs
+------------------------------------------------
+            
+              P0RDDATA         =>  mig_p0_rd_data ( 31 downto 0),
+              P1RDDATA         =>  mig_p1_rd_data ( 31 downto 0),
+              P2RDDATA         =>  mig_p2_rd_data ( 31 downto 0),
+              P3RDDATA         =>  mig_p3_rd_data ( 31 downto 0),
+              P4RDDATA         =>  mig_p4_rd_data ( 31 downto 0),
+              P5RDDATA         =>  mig_p5_rd_data ( 31 downto 0),
+              LDMN             =>  dqnlm       ,
+              UDMN             =>  dqnum       ,
+              DQON             =>  dqo_n       ,
+              DQOP             =>  dqo_p       ,
+              LDMP             =>  dqplm       ,
+              UDMP             =>  dqpum       ,
+              
+              P0RDCOUNT          =>  mig_p0_rd_count ,
+              P0WRCOUNT          =>  mig_p0_wr_count ,
+              P1RDCOUNT          =>  mig_p1_rd_count ,
+              P1WRCOUNT          =>  mig_p1_wr_count ,
+              P2COUNT           =>  mig_p2_count  ,
+              P3COUNT           =>  mig_p3_count  ,
+              P4COUNT           =>  mig_p4_count  ,
+              P5COUNT           =>  mig_p5_count  ,
+              
+             -- NEW ADDED FIFo status siganls
+             -- MIG USER PORT 0
+              P0RDEMPTY        =>  mig_p0_rd_empty,
+              P0RDFULL         =>  mig_p0_rd_full,
+              P0RDOVERFLOW     =>  mig_p0_rd_overflow,
+              P0WREMPTY        =>  mig_p0_wr_empty,
+              P0WRFULL         =>  mig_p0_wr_full,
+              P0WRUNDERRUN     =>  mig_p0_wr_underrun,
+             -- MIG USER PORT 1
+              P1RDEMPTY        =>  mig_p1_rd_empty,
+              P1RDFULL         =>  mig_p1_rd_full,
+              P1RDOVERFLOW     =>  mig_p1_rd_overflow, 
+              P1WREMPTY        =>  mig_p1_wr_empty,
+              P1WRFULL         =>  mig_p1_wr_full,
+              P1WRUNDERRUN     =>  mig_p1_wr_underrun, 
+              
+             -- MIG USER PORT 2
+              P2EMPTY          =>  mig_p2_empty,
+              P2FULL           =>  mig_p2_full,
+              P2RDOVERFLOW        =>  mig_p2_overflow,
+              P2WRUNDERRUN       =>  mig_p2_underrun,
+              
+              P3EMPTY          =>  mig_p3_empty ,
+              P3FULL           =>  mig_p3_full ,
+              P3RDOVERFLOW        =>  mig_p3_overflow,
+              P3WRUNDERRUN       =>  mig_p3_underrun ,
+             -- MIG USER PORT 3
+              P4EMPTY          =>  mig_p4_empty,
+              P4FULL           =>  mig_p4_full,
+              P4RDOVERFLOW        =>  mig_p4_overflow,
+              P4WRUNDERRUN       =>  mig_p4_underrun,
+              
+              P5EMPTY          =>  mig_p5_empty ,
+              P5FULL           =>  mig_p5_full ,
+              P5RDOVERFLOW        =>  mig_p5_overflow,
+              P5WRUNDERRUN       =>  mig_p5_underrun,
+              
+             ---------------------------------------------------------
+              P0WREN        =>  mig_p0_wr_en,
+              P0RDEN        =>  mig_p0_rd_en,                        
+              P1WREN        =>  mig_p1_wr_en,
+              P1RDEN        =>  mig_p1_rd_en,
+              P2EN          =>  mig_p2_en,
+              P3EN          =>  mig_p3_en,
+              P4EN          =>  mig_p4_en,
+              P5EN          =>  mig_p5_en,
+             -- WRITE  MASK BIts connection
+              P0RWRMASK        =>  mig_p0_wr_mask(3 downto 0),
+              P1RWRMASK        =>  mig_p1_wr_mask(3 downto 0),
+              P2WRMASK        =>  mig_p2_wr_mask(3 downto 0),
+              P3WRMASK        =>  mig_p3_wr_mask(3 downto 0),
+              P4WRMASK        =>  mig_p4_wr_mask(3 downto 0),
+              P5WRMASK        =>  mig_p5_wr_mask(3 downto 0),
+             -- DATA WRITE COnnection
+              P0WRDATA      =>  mig_p0_wr_data(31 downto 0),
+              P1WRDATA      =>  mig_p1_wr_data(31 downto 0),
+              P2WRDATA      =>  mig_p2_wr_data(31 downto 0),
+              P3WRDATA      =>  mig_p3_wr_data(31 downto 0),
+              P4WRDATA      =>  mig_p4_wr_data(31 downto 0),
+              P5WRDATA      =>  mig_p5_wr_data(31 downto 0),
+              
+              P0WRERROR     => mig_p0_wr_error,
+              P1WRERROR     => mig_p1_wr_error,
+              P0RDERROR     => mig_p0_rd_error,
+              P1RDERROR     => mig_p1_rd_error,
+              
+              P2ERROR       => mig_p2_error,
+              P3ERROR       => mig_p3_error,
+              P4ERROR       => mig_p4_error,
+              P5ERROR       => mig_p5_error,
+              
+             --  USER SIDE DAta ports clock
+             --  128 BITS CONnections
+              P0WRCLK            =>  mig_p0_wr_clk  ,
+              P1WRCLK            =>  mig_p1_wr_clk  ,
+              P0RDCLK            =>  mig_p0_rd_clk  ,
+              P1RDCLK            =>  mig_p1_rd_clk  ,
+              P2CLK              =>  mig_p2_clk  ,
+              P3CLK              =>  mig_p3_clk  ,
+              P4CLK              =>  mig_p4_clk  ,
+              P5CLK              =>  mig_p5_clk 
+              );
+
+--//////////////////////////////////////////////////////
+--// Input Termination Calibration
+--//////////////////////////////////////////////////////
+             
+
+--process(ui_clk)
+--begin
+--if (ui_clk'event and ui_clk = '1') then
+--      syn1_sys_rst <= sys_rst;
+--      syn2_sys_rst <= syn1_sys_rst;
+--end if;
+--end process;
+             
+ uo_done_cal_sig <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
+                         hard_done_cal;
+
+
+   gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
+      mcb_soft_calibration_top_inst : mcb_soft_calibration_top
+      generic map (   C_MEM_TZQINIT_MAXCNT  => C_MEM_TZQINIT_MAXCNT,
+                      C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, 
+                      SKIP_IN_TERM_CAL      => C_SKIP_IN_TERM_CAL,
+                      SKIP_DYNAMIC_CAL      => C_SKIP_DYNAMIC_CAL,
+                      SKIP_DYN_IN_TERM      => C_SKIP_DYN_IN_TERM,
+                      C_SIMULATION          => C_SIMULATION,
+                      C_MEM_TYPE            => C_MEM_TYPE
+                   )
+  
+         PORT MAP (
+            UI_CLK                => ui_clk,
+            --RST                   => syn2_sys_rst,
+            RST                   => int_sys_rst,
+            IOCLK                 => ioclk0,
+            DONE_SOFTANDHARD_CAL  => DONE_SOFTANDHARD_CAL,
+            --PLL_LOCK              => pll_lock,
+            PLL_LOCK              => gated_pll_lock,
+
+            --SELFREFRESH_REQ       => selfrefresh_enter,     -- from user app
+            SELFREFRESH_REQ       => soft_cal_selfrefresh_req,     -- from user app
+            SELFREFRESH_MCB_MODE  => selfrefresh_mcb_mode,  -- from MCB
+            SELFREFRESH_MCB_REQ   => selfrefresh_mcb_enter, -- to mcb
+            SELFREFRESH_MODE      => selfrefresh_mode_sig,      -- to user app
+
+            MCB_UIADD             => mcb_ui_add,
+            MCB_UISDI             => mcb_ui_sdi,
+            MCB_UOSDO             => uo_sdo_xhdl24,
+            MCB_UODONECAL         => hard_done_cal,
+            MCB_UOREFRSHFLAG      => uo_refrsh_flag_xhdl23,
+            MCB_UICS              => mcb_ui_cs,
+            MCB_UIDRPUPDATE       => mcb_ui_drp_update,
+            MCB_UIBROADCAST       => mcb_ui_broadcast,
+            MCB_UIADDR            => mcb_ui_addr,
+            MCB_UICMDEN           => mcb_ui_cmd_en,
+            MCB_UIDONECAL         => mcb_ui_done_cal,
+            MCB_UIDQLOWERDEC      => mcb_ui_dq_lower_dec,
+            MCB_UIDQLOWERINC      => mcb_ui_dq_lower_inc,
+            MCB_UIDQUPPERDEC      => mcb_ui_dq_upper_dec,
+            MCB_UIDQUPPERINC      => mcb_ui_dq_upper_inc,
+            MCB_UILDQSDEC         => mcb_ui_ldqs_dec,
+            MCB_UILDQSINC         => mcb_ui_ldqs_inc,
+            MCB_UIREAD            => mcb_ui_read,
+            MCB_UIUDQSDEC         => mcb_ui_udqs_dec,
+            MCB_UIUDQSINC         => mcb_ui_udqs_inc,
+            MCB_RECAL             => mcb_recal,
+            MCB_SYSRST            => MCB_SYSRST,
+            MCB_UICMD             => mcb_ui_cmd,
+            MCB_UICMDIN           => mcb_ui_cmd_in,    
+            MCB_UIDQCOUNT         => mcb_ui_dqcount,     
+            MCB_UODATA            => uo_data_int,    
+            MCB_UODATAVALID       => uo_data_valid_int,    
+            MCB_UOCMDREADY        => uo_cmd_ready_in_int, 
+            MCB_UO_CAL_START      => uo_cal_start_int,
+            RZQ_PIN               => rzq,
+            ZIO_PIN               => zio,
+            CKE_Train             => cke_train
+         );
+         mcb_ui_clk <= ui_clk;
+   END GENERATE;
+
+
+   gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
+      DONE_SOFTANDHARD_CAL <= '0';
+      MCB_SYSRST <= int_sys_rst or not(wait_200us_counter(15));
+      mcb_recal <= calib_recal;
+      mcb_ui_read <= ui_read;
+      mcb_ui_add <= ui_add;
+      mcb_ui_cs <= ui_cs;
+      mcb_ui_clk <= ui_clk;
+      mcb_ui_sdi <= ui_sdi;
+      mcb_ui_addr <= ui_addr;
+      mcb_ui_broadcast <= ui_broadcast;
+      mcb_ui_drp_update <= ui_drp_update;
+      mcb_ui_done_cal <= ui_done_cal;
+      mcb_ui_cmd <= ui_cmd;
+      mcb_ui_cmd_in <= ui_cmd_in;
+      mcb_ui_cmd_en <= ui_cmd_en;
+      mcb_ui_dqcount <= ui_dqcount;
+      mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
+      mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
+      mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
+      mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
+      mcb_ui_udqs_inc <= ui_udqs_inc;
+      mcb_ui_udqs_dec <= ui_udqs_dec;
+      mcb_ui_ldqs_inc <= ui_ldqs_inc;
+      mcb_ui_ldqs_dec <= ui_ldqs_dec;
+      selfrefresh_mode_sig <= '0';
+
+      -- synthesis translate_off
+      init_sequence: if (C_SIMULATION = "FALSE") generate      
+      -- synthesis translate_on
+         process (ui_clk, int_sys_rst)
+         begin
+            if (int_sys_rst = '1') then
+               wait_200us_counter <= (others => '0');
+            elsif (ui_clk'event and ui_clk = '1') then   -- UI_CLK maximum is up to 100 MHz
+               if (wait_200us_counter(15) = '1') then
+                  wait_200us_counter <= wait_200us_counter;
+               else
+                  wait_200us_counter <= wait_200us_counter + '1';
+               end if;
+            end if;
+         end process;
+      -- synthesis translate_off
+      end generate;
+
+      init_sequence_skip: if (C_SIMULATION = "TRUE") generate
+         wait_200us_counter <= X"FFFF";
+         process
+         begin
+            report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
+            wait;
+         end process;
+      end generate;
+      -- synthesis translate_on
+ 
+      gen_cketrain_a: if (C_MEM_TYPE = "DDR2") generate
+         process (ui_clk)
+         begin
+            -- When wait_200us_[13] and wait_200us_[14] are both asserted,
+            -- 200 us wait should have been passed. 
+            if (ui_clk'event and ui_clk = '1') then
+               if ((wait_200us_counter(14) and wait_200us_counter(13)) = '1') then
+                  wait_200us_done_r1 <= '1';
+               else
+                  wait_200us_done_r1 <= '0';
+               end if;
+               wait_200us_done_r2 <= wait_200us_done_r1;
+            end if;
+         end process;
+
+         process (ui_clk, int_sys_rst)
+         begin
+            if (int_sys_rst = '1') then
+               cke_train_reg <= '0';
+            elsif (ui_clk'event and ui_clk = '1') then
+               if ((wait_200us_done_r1 and not(wait_200us_done_r2)) = '1') then
+                  cke_train_reg <= '1';
+               elsif (uo_done_cal_sig = '1') then
+                  cke_train_reg <= '0';
+               end if;
+            end if;
+         end process;
+
+         cke_train <= cke_train_reg;
+      end generate;      
+
+      gen_cketrain_b: if (NOT(C_MEM_TYPE = "DDR2")) generate
+         
+         cke_train <= '0';
+
+      end generate;
+
+   end generate;
+   
+
+
+--//////////////////////////////////////////////////////
+--//ODDRDES2 instantiations
+--//////////////////////////////////////////////////////
+
+--------
+--ADDR
+--------
+
+   gen_addr_oserdes2 : FOR addr_ioi IN 0 TO  C_MEM_ADDR_WIDTH - 1 GENERATE
+      
+      
+      ioi_addr_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2
+         )
+         PORT MAP (
+            OQ         => ioi_addr(addr_ioi),
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => t_addr(addr_ioi),
+            CLK0       => ioclk0,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => address_90(addr_ioi),
+            D2         => address_90(addr_ioi),
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_0,
+            OCE        => '1',
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => '0',
+            T2         => '0',
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => '0'
+         );
+   END GENERATE;
+
+--------
+--BA
+--------
+
+   gen_ba_oserdes2 : FOR ba_ioi IN 0 TO  C_MEM_BANKADDR_WIDTH - 1 GENERATE
+      
+      
+      ioi_ba_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2
+         )
+         PORT MAP (
+            OQ         => ioi_ba(ba_ioi),
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => t_ba(ba_ioi),
+            CLK0       => ioclk0,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => ba_90(ba_ioi),
+            D2         => ba_90(ba_ioi),
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_0,
+            OCE        => '1',
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => '0',
+            T2         => '0',
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => '0'
+         );
+   END GENERATE;
+   
+--------
+--CAS
+--------
+   ioi_cas_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ioi_cas,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => t_cas,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => cas_90,
+         D2         => cas_90,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--CKE
+--------
+   ioi_cke_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2,
+         TRAIN_PATTERN   => 15
+      )
+      PORT MAP (
+         OQ         => ioi_cke,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => t_cke,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => cke_90,
+         D2         => cke_90,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         --OCE        => '1',
+         OCE        => pll_lock,
+         RST        => '0', --int_sys_rst
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => cke_train
+      );
+--------
+--ODT
+--------
+   xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
+      
+      ioi_odt_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2
+--            TRAIN_PATTERN   => 0
+         )
+         PORT MAP (
+            OQ         => ioi_odt,
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => t_odt,
+            CLK0       => ioclk0,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => odt_90,
+            D2         => odt_90,
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_0,
+            OCE        => '1',
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => '0',
+            T2         => '0',
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => '0'
+         );
+   END GENERATE;
+
+--------
+--RAS
+--------
+   ioi_ras_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ioi_ras,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => t_ras,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => ras_90,
+         D2         => ras_90,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+--------
+--RST
+--------
+   xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
+      ioi_rst_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2
+         )
+         PORT MAP (
+            OQ         => ioi_rst,
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => t_rst,
+            CLK0       => ioclk0,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => rst_90,
+            D2         => rst_90,
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_0,
+            --OCE        => '1',
+            OCE        => pll_lock,
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => '0',
+            T2         => '0',
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => '0'
+         );
+   END GENERATE;
+--------
+--WE
+--------
+   ioi_we_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ioi_we,
+         TQ         => t_we,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => we_90,
+         D2         => we_90,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--CK
+--------
+   ioi_ck_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,                    
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ioi_ck,
+         SHIFTOUT1  => open,--ck_shiftout0_1,
+         SHIFTOUT2  => open,--ck_shiftout0_2,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => t_ck,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '0',
+         D2         => '1',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         --OCE        => '1',
+         OCE        => pll_lock,
+         RST        => '0', --int_sys_rst
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+----------
+----CKN
+----------
+--   ioi_ckn_0 : OSERDES2
+--      GENERIC MAP (
+--         BYPASS_GCLK_FF  => TRUE,
+--         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+--         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+--         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+--         SERDES_MODE     => C_OSERDES2_SERDES_MODE_SLAVE,
+--         DATA_WIDTH      => 2
+--      )
+--      PORT MAP (
+--         OQ         => ioi_ckn,
+--         SHIFTOUT1  => open,
+--         SHIFTOUT2  => open,
+--         SHIFTOUT3  => open,--ck_shiftout1_3,
+--         SHIFTOUT4  => open,--ck_shiftout1_4,
+--         TQ         => t_ckn,
+--         CLK0       => ioclk0,
+--         CLK1       => '0',
+--         CLKDIV     => '0',
+--         D1         => '1',
+--         D2         => '0',
+--         D3         => '0',
+--         D4         => '0',
+--         IOCE       => pll_ce_0,
+--         OCE        => '1',
+--         RST        => '0',
+--         SHIFTIN1   => '0',
+--         SHIFTIN2   => '0',
+--         SHIFTIN3   => '0',
+--         SHIFTIN4   => '0',
+--         T1         => '0',
+--         T2         => '0',
+--         T3         => '0',
+--         T4         => '0',
+--         TCE        => '1',
+--         TRAIN      => '0'
+--      );
+--   
+--------
+--UDM
+--------
+   
+   ioi_udm_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => udm_oq,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => udm_t,
+         CLK0       => ioclk90,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => dqpum,
+         D2         => dqnum,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_90,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => dqIO_w_en_0,
+         T2         => dqIO_w_en_0,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--LDM
+--------
+   ioi_ldm_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ldm_oq,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => ldm_t,
+         CLK0       => ioclk90,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => dqplm,
+         D2         => dqnlm,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_90,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => dqIO_w_en_0,
+         T2         => dqIO_w_en_0,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+--------
+--DQ
+--------
+   gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
+      oserdes2_dq_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2,
+            TRAIN_PATTERN   => 5
+         )
+         PORT MAP (
+            OQ         => dq_oq(dq),
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => dq_tq(dq),
+            CLK0       => ioclk90,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => dqo_p(dq),
+            D2         => dqo_n(dq),
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_90,
+            OCE        => '1',
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => dqIO_w_en_0,
+            T2         => dqIO_w_en_0,
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => ioi_drp_train
+         );
+   END GENERATE;
+
+--------
+--DQSP
+--------
+   
+   
+   oserdes2_dqsp_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+     --    TRAIN_PATTERN   => 0
+      )
+      PORT MAP (
+         OQ         => dqsp_oq,
+         SHIFTOUT1  => open,--dqs_shiftout0_1,
+         SHIFTOUT2  => open,--dqs_shiftout0_2,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => dqsp_tq,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '0',
+         D2         => '1',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',--dqs_shiftout1_3,
+         SHIFTIN4   => '0',--dqs_shiftout1_4,
+         T1         => dqsIO_w_en_90_n,
+         T2         => dqsIO_w_en_90_p,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--DQSN
+--------
+   
+   oserdes2_dqsn_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_SLAVE,
+         DATA_WIDTH      => 2
+  --       TRAIN_PATTERN   => 0
+      )
+      PORT MAP (
+         OQ         => dqsn_oq,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,--dqs_shiftout1_3,
+         SHIFTOUT4  => open,--dqs_shiftout1_4,
+         TQ         => dqsn_tq,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '1',
+         D2         => '0',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',--dqs_shiftout0_1,
+         SHIFTIN2   => '0',--dqs_shiftout0_2,
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => dqsIO_w_en_90_n,
+         T2         => dqsIO_w_en_90_p,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--UDQSP
+--------
+   
+   oserdeS2_UDQSP_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+--         TRAIN_PATTERN   => 0
+      )
+      PORT MAP (
+         OQ         => udqsp_oq,
+         SHIFTOUT1  => open,--udqs_shiftout0_1,
+         SHIFTOUT2  => open,--udqs_shiftout0_2,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => udqsp_tq,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '0',
+         D2         => '1',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',--udqs_shiftout1_3,
+         SHIFTIN4   => '0',--udqs_shiftout1_4,
+         T1         => dqsIO_w_en_90_n,
+         t2         => dqsIO_w_en_90_p,
+         T3         => '0',
+         T4         => '0',
+         tce        => '1',
+         train      => '0'
+      );
+   
+--------
+--UDQSN
+--------
+   
+   oserdes2_udqsn_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_SLAVE,
+         DATA_WIDTH      => 2
+--         TRAIN_PATTERN   => 0
+      )
+      PORT MAP (
+         OQ         => udqsn_oq,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,--udqs_shiftout1_3,
+         SHIFTOUT4  => open,--udqs_shiftout1_4,
+         TQ         => udqsn_tq,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '1',
+         D2         => '0',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',--udqs_shiftout0_1,
+         SHIFTIN2   => '0',--udqs_shiftout0_2,
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => dqsIO_w_en_90_n,
+         T2         => dqsIO_w_en_90_p,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+------------------------------------------------------
+--*********************************** OSERDES2 instantiations end *******************************************
+------------------------------------------------------
+
+------------------------------------------------
+--&&&&&&&&&&&&&&&&&&&&&&&&&&&  IODRP2 instantiations  &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
+------------------------------------------------
+---#####################################--X16 MEMORY WIDTH-#############################################
+   
+   dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
+
+--////////////////////////////////////////////////
+--DQ14
+--////////////////////////////////////////////////
+
+   iodrp2_DQ_14 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ14_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 7,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_14,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(14),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(14),
+         SDO        => open,
+         TOUT       => t_dq(14),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_15,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(14),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(14),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(14)
+      );
+
+--////////////////////////////////////////////////
+--DQ15
+--////////////////////////////////////////////////
+   
+   
+   iodrp2_dq_15 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ15_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 7,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_15,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(15),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(15),
+         SDO        => open,
+         TOUT       => t_dq(15),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => '0',
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(15),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(15),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(15)
+      );
+   
+--////////////////////////////////////////////////
+--DQ12
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_12 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ12_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 6,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_12,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(12),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(12),
+         SDO        => open,
+         TOUT       => t_dq(12),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_13,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(12),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(12),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(12)
+      );
+   
+--////////////////////////////////////////////////
+--DQ13
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_13 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ13_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 6,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_13,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(13),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(13),
+         SDO        => open,
+         TOUT       => t_dq(13),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_14,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(13),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(13),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(13)
+      );
+   
+--/////////
+--UDQSP
+--/////////
+   
+   iodrp2_UDQSP_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => UDQSP_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 14,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_udqsp,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udqs,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_udqs_ioi_m,
+         SDO        => open,
+         TOUT       => t_udqs,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_udqsn,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_udqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udqsp_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udqsp_tq
+      );
+   
+--/////////
+--UDQSN
+--/////////
+   
+   iodrp2_udqsn_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => UDQSN_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 14,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_udqsn,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udqsn,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_udqs_ioi_s,
+         SDO        => open,
+         TOUT       => t_udqsn,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_12,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_udqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udqsn_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udqsn_tq
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ10
+--////////////////////////////////////////////////   
+   iodrp2_DQ_10 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ10_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 5,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_10,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(10),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(10),
+         SDO        => open,
+         TOUT       => t_dq(10),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_11,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(10),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(10),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(10)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ11
+--////////////////////////////////////////////////   
+   
+   iodrp2_dq_11 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ11_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 5,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_11,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(11),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(11),
+         SDO        => open,
+         TOUT       => t_dq(11),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_udqsp,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(11),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(11),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(11)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ8
+--////////////////////////////////////////////////   
+   
+   iodrp2_DQ_8 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ8_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 4,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_8,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(8),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(8),
+         SDO        => open,
+         TOUT       => t_dq(8),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_9,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(8),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(8),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(8)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ9
+--////////////////////////////////////////////////   
+   
+   iodrp2_dq_9 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ9_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 4,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_9,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(9),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(9),
+         SDO        => open,
+         TOUT       => t_dq(9),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_10,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(9),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(9),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(9)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ0
+--////////////////////////////////////////////////   
+   
+   iodrp2_DQ_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ0_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_0,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(0),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(0),
+         SDO        => open,
+         TOUT       => t_dq(0),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_1,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(0),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(0),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(0)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ1
+--////////////////////////////////////////////////   
+   
+   iodrp2_dq_1 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ1_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_1,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(1),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(1),
+         SDO        => open,
+         TOUT       => t_dq(1),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_8,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(1),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(1),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(1)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ2
+--////////////////////////////////////////////////   
+   
+   iodrp2_DQ_2 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ2_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_2,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(2),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(2),
+         SDO        => open,
+         TOUT       => t_dq(2),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_3,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(2),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(2),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(2)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ3
+--////////////////////////////////////////////////   
+   
+   iodrp2_dq_3 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ3_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_3,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(3),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(3),
+         SDO        => open,
+         TOUT       => t_dq(3),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_0,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(3),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(3),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(3)
+      );
+   
+--/////////
+--//DQSP
+--/////////
+   
+   iodrp2_DQSP_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSP_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsp,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqs,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_m,
+         SDO        => open,
+         TOUT       => t_dqs,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsn,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsp_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsp_tq
+      );
+   
+--/////////
+--//DQSN
+--/////////
+   
+   iodrp2_dqsn_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSN_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsn,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqsn,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_s,
+         SDO        => open,
+         TOUT       => t_dqsn,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_2,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsn_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsn_tq
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ6
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_6 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ6_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 3,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_6,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(6),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(6),
+         SDO        => open,
+         TOUT       => t_dq(6),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_7,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(6),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(6),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(6)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ7
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_7 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ7_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 3,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_7,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(7),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(7),
+         SDO        => open,
+         TOUT       => t_dq(7),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsp,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(7),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(7),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(7)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ4
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_4 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ4_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 2,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_4,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(4),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(4),
+         SDO        => open,
+         TOUT       => t_dq(4),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_5,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(4),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(4),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(4)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ5
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_5 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ5_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 2,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_5,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(5),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(5),
+         SDO        => open,
+         TOUT       => t_dq(5),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_6,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(5),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(5),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(5)
+      );
+   
+   
+  
+   
+--/////////////////////////////////////////////////
+--//UDM
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_udm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => ioi_drp_sdi,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_udm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_ldm,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udm_t
+      );
+
+--/////////////////////////////////////////////////
+--//LDM
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_ldm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_ldm,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_ldm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_ldm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_4,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => ldm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => ldm_t
+      );
+
+end generate;
+
+---#####################################--X8 MEMORY WIDTH-#############################################
+   
+   dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
+--/////////////////////////////////////////////////
+--//DQ0
+--////////////////////////////////////////////////
+   iodrp2_DQ_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ0_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_0,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(0),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(0),
+         SDO        => open,
+         TOUT       => t_dq(0),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_1,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(0),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(0),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(0)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ1
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_1 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ1_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_1,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(1),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(1),
+         SDO        => open,
+         TOUT       => t_dq(1),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => '0',
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(1),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(1),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(1)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ2
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_2 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ2_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_2,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(2),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(2),
+         SDO        => open,
+         TOUT       => t_dq(2),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_3,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(2),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(2),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(2)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ3
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_3 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ3_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_3,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(3),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(3),
+         SDO        => open,
+         TOUT       => t_dq(3),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_0,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(3),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(3),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(3)
+      );
+   
+--/////////
+--//DQSP
+--/////////
+   
+   iodrp2_DQSP_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSP_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsp,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqs,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_m,
+         SDO        => open,
+         TOUT       => t_dqs,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsn,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsp_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsp_tq
+      );
+   
+--/////////
+--//DQSN
+--/////////   
+   iodrp2_dqsn_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSN_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsn,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqsn,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_s,
+         SDO        => open,
+         TOUT       => t_dqsn,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_2,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsn_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsn_tq
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ6
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_6 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ6_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 3,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_6,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(6),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(6),
+         SDO        => open,
+         TOUT       => t_dq(6),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_7,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(6),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(6),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(6)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ7
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_7 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ7_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 3,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_7,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(7),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(7),
+         SDO        => open,
+         TOUT       => t_dq(7),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsp,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(7),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(7),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(7)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ4
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_4 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ4_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 2,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_4,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(4),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(4),
+         SDO        => open,
+         TOUT       => t_dq(4),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_5,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(4),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(4),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(4)
+      );
+--/////////////////////////////////////////////////
+--//DQ5
+--////////////////////////////////////////////////
+   
+   
+   iodrp2_dq_5 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ5_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 2,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_5,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(5),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(5),
+         SDO        => open,
+         TOUT       => t_dq(5),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_6,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(5),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(5),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(5)
+      );
+   
+   
+   
+--NEED TO GENERATE UDM so that user won't instantiate in this location
+   
+--/////////////////////////////////////////////////
+--//UDM
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_udm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => ioi_drp_sdi,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_udm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_ldm,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udm_t
+      );
+
+--/////////////////////////////////////////////////
+--//LDM
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_ldm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_ldm,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_ldm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_ldm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_4,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => ldm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => ldm_t
+      );
+
+end generate;
+
+---#####################################--X4 MEMORY WIDTH-#############################################
+   
+   dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
+--/////////////////////////////////////////////////
+--//DQ0
+--////////////////////////////////////////////////
+
+   iodrp2_DQ_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ0_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_0,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(0),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(0),
+         SDO        => open,
+         TOUT       => t_dq(0),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_1,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(0),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(0),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(0)
+      );
+   
+ --/////////////////////////////////////////////////
+--//DQ1
+--////////////////////////////////////////////////
+  
+   iodrp2_dq_1 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ1_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_1,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(1),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(1),
+         SDO        => open,
+         TOUT       => t_dq(1),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => '0',
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(1),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(1),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(1)
+      );
+   
+ --/////////////////////////////////////////////////
+--//DQ2
+--////////////////////////////////////////////////
+  
+   iodrp2_DQ_2 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ2_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_2,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(2),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(2),
+         SDO        => open,
+         TOUT       => t_dq(2),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_3,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(2),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(2),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(2)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ3
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_3 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ3_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_3,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(3),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(3),
+         SDO        => open,
+         TOUT       => t_dq(3),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_0,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(3),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(3),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(3)
+      );
+   
+--///////////////////////////////////////////////
+--DQSP
+--///////////////////////////////////////////////
+   iodrp2_DQSP_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSP_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsp,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqs,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_m,
+         SDO        => open,
+         TOUT       => t_dqs,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsn,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsp_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsp_tq
+      );
+   
+--///////////////////////////////////////////////
+--DQSN
+--///////////////////////////////////////////////
+   
+   iodrp2_dqsn_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSN_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsn,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqsn,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_s,
+         SDO        => open,
+         TOUT       => t_dqsn,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_2,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsn_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsn_tq
+      );
+--///////////////////////////////////////////////
+--UDM
+--//////////////////////////////////////////////  
+ --NEED TO GENERATE UDM so that user won't instantiate in this location
+  
+   
+   iodrp2_dq_udm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => ioi_drp_sdi,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_udm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_ldm,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udm_t
+      );
+
+--///////////////////////////////////////////////
+--LDM
+--//////////////////////////////////////////////  
+   
+   
+   iodrp2_dq_ldm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_ldm,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_ldm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_ldm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_4,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => ldm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => ldm_t
+      );
+
+end generate;
+
+------------------------------------------------
+--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
+------------------------------------------------   
+
+ -------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ --IOBs instantiations
+ -- this part need more inputs from design team 
+ -- for now just use as listed in fpga.v
+ -----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+-- DRAM Address
+   gen_addr_obuft : FOR addr_i IN 0 TO  C_MEM_ADDR_WIDTH - 1 GENERATE
+      iob_addr_inst : OBUFT
+         PORT MAP (
+            I  => ioi_addr(addr_i),
+            T  => t_addr(addr_i),
+            O  => mcbx_dram_addr(addr_i)
+         );
+   END GENERATE;
+   
+   gen_ba_obuft : FOR ba_i IN 0 TO  C_MEM_BANKADDR_WIDTH - 1 GENERATE
+      iob_ba_inst : OBUFT
+         PORT MAP (
+            I  => ioi_ba(ba_i),
+            T  => t_ba(ba_i),
+            O  => mcbx_dram_ba(ba_i)
+         );
+   END GENERATE;
+   
+-- DRAM control
+--RAS   
+   iob_ras : OBUFT
+      PORT MAP (
+         O  => mcbx_dram_ras_n,
+         I  => ioi_ras,
+         T  => t_ras
+      );
+   
+--CAS      
+   iob_cas : OBUFT
+      PORT MAP (
+         O  => mcbx_dram_cas_n,
+         I  => ioi_cas,
+         T  => t_cas
+      );
+   
+--WE      
+   iob_we : OBUFT
+      PORT MAP (
+         O  => mcbx_dram_we_n,
+         I  => ioi_we,
+         T  => t_we
+      );
+   
+--CKE   
+   iob_cke : OBUFT
+      PORT MAP (
+         O  => mcbx_dram_cke,
+         I  => ioi_cke,
+         T  => t_cke
+      );
+
+--DDR3 RST
+   gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
+      iob_rst : OBUFT
+         PORT MAP (
+            O  => mcbx_dram_ddr3_rst,
+            I  => ioi_rst,
+            T  => t_rst
+         );
+   END GENERATE;
+
+--ODT
+   gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF"))) 
+   OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
+      iob_odt : OBUFT
+         PORT MAP (
+            O  => mcbx_dram_odt,
+            I  => ioi_odt,
+            t  => t_odt
+         );
+   END GENERATE;
+   
+--MEMORY CLOCK   
+   iob_clk : OBUFTDS
+      PORT MAP (
+         I  => ioi_ck,
+         T  => t_ck,
+         O  => mcbx_dram_clk,
+         OB => mcbx_dram_clk_n
+      );
+   
+--DQ
+   gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
+      gen_iob_dq_inst : IOBUF
+         PORT MAP (
+            IO  => mcbx_dram_dq(dq_i),
+            I   => ioi_dq(dq_i),
+            T   => t_dq(dq_i),
+            O   => in_pre_dq(dq_i)
+         );
+   END GENERATE;
+   
+-- x4 and x8
+--DQS
+gen_dqs_iobuf :   if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
+      iob_dqs : IOBUF
+      PORT MAP (
+         IO  => mcbx_dram_dqs,
+         I   => ioi_dqs,
+         T   => t_dqs,
+         O   => in_pre_dqsp
+      );
+end generate;   
+
+--DQSP/DQSN
+gen_dqs_iobufds :   if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
+   iob_dqs : IOBUFDS
+      PORT MAP (
+         IO   => mcbx_dram_dqs,
+         IOB  => mcbx_dram_dqs_n,
+         I    => ioi_dqs,
+         T    => t_dqs,
+         O    => in_pre_dqsp
+      );
+end generate;   
+
+-- x16
+--UDQS   
+gen_udqs_iobuf :   if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
+      iob_udqs : IOBUF
+      PORT MAP (
+         IO  => mcbx_dram_udqs,
+         I   => ioi_udqs,
+         T   => t_udqs,
+         O   => in_pre_udqsp
+      );
+end generate;   
+
+----UDQSP/UDQSN
+gen_udqs_iobufds :   if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
+   iob_udqs : IOBUFDS
+      PORT MAP (
+         IO   => mcbx_dram_udqs,
+         IOB  => mcbx_dram_udqs_n,
+         I    => ioi_udqs,
+         T    => t_udqs,
+         O    => in_pre_udqsp
+      );
+end generate;   
+   
+-- DQS PULLDWON
+gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate 
+dqs_pulldown : PULLDOWN  port map (O => mcbx_dram_dqs);
+end generate;
+
+gen_dqs_pullupdn_ds :   if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
+dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
+dqs_n_pullup : PULLUP port map  (O  =>  mcbx_dram_dqs_n);   
+end generate;
+
+-- DQSN PULLUP
+gen_udqs_pullupdn :   if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
+udqs_pulldown : PULLDOWN  port map (O => mcbx_dram_udqs);
+end generate;
+
+gen_udqs_pullupdn_ds :   if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and 
+                                                          (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
+udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
+udqs_n_pullup : PULLUP port map  (O  =>  mcbx_dram_udqs_n);   
+end generate;
+
+--UDM   
+gen_udm : if(C_NUM_DQ_PINS = 16) generate   
+   iob_udm : OBUFT
+      PORT MAP (
+         I  => ioi_udm,
+         T  => t_udm,
+         O  => mcbx_dram_udm
+      );
+end generate;   
+--LDM   
+   iob_ldm : OBUFT
+      PORT MAP (
+         I  => ioi_ldm,
+         T  => t_ldm,
+         O  => mcbx_dram_ldm
+      );
+   
+selfrefresh_mode <= selfrefresh_mode_sig;
+
+ end aarch;    
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_soft_calibration.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_soft_calibration.vhd
new file mode 100755
index 0000000..0e68a29
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_soft_calibration.vhd
@@ -0,0 +1,1774 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_soft_calibration.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:26 $
+-- \   \  /  \    Date Created: Mon Feb 9 2009
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR
+--Purpose:  Xilinx reference design for MCB Soft
+--           Calibration
+--Reference:
+--
+--  Revision:      Date:  Comment
+--       1.0:  2/06/09:   Initial version for MIG wrapper.
+--       1.1:  2/09/09:   moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working 
+--                          correctly)
+--       1.2:  2/12/09:   Many other changes.
+--       1.3:  2/26/09:   Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
+--                          STATE
+--       1.4:  3/02/09:   Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
+--       1.5:  3/16/09:   Added pll_lock port, and using it to gate reset.  Changing RST (except input port) to RST_reg and gating it with pll_lock.
+--       1.6:  6/05/09:   Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
+--       1.7:  6/24/09:   Gave RZQ and ZIO each their own unique ADD and SDI nets
+--       2.6:  12/15/09:  Changed STATE from 7-bit to 6-bit.  Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to 
+--                          RST_DELAY. 
+--                        Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
+--                          16 clocks.  Added PNSKEW option.
+--       2.7:  12/23/09:  Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
+--       2.8:  01/14/10:  Added functionality to allow for SUSPEND.  Changed MCB_SYSRST port from wire to reg.
+--       2.9:  02/01/10:  More changes to SUSPEND and Reset logic to handle SUSPEND properly.  Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced 
+--                          with 8bit TARGET_DQS_DELAY which
+--                        will track most recnet Max_Value.  Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
+--                          Changed DQS_COUNT* to DQS_DELAY*.
+--                        Changed MCB_SYSRST port back to wire (from reg).
+--       3.0:  02/10/10:  Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
+--       3.1:  02/23/10:  Registered the DONE_SOFTANDHARD_CAL for timing.
+--       3.2:  02/28/10:  Corrected the   WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
+--       3.3:  03/02/10:  Changed PNSKEW to default on (1'b1)
+--       3.4:  03/04/10:  Recoded the RST_Reg logic.
+--       3.5:  03/05/10:  Changed Result register to be 16-bits.  Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
+--       3.6   03/10/10:  Improvements to Reset logic.  
+--       3.7:  04/26/10:  Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
+--       3.8:  05/05/10:  Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
+--       3.9:  05/24/10:  Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
+--       3.10  10/22/10:  Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic.		
+--       3.11  2/14/11:   Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity.
+--       4.1   03/08/12:  Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that
+--                        MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. 
+--       4.2   05/10/12:  All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT
+--                        are set to 8 for LPDDR,DDR and DDR2 interface .
+--                        Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing
+--                        Premable detection until the second deassertion of MCB_SYSRST. 
+                        
+
+-- End Revision
+--**********************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+entity mcb_soft_calibration is
+   generic (
+      C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
+      SKIP_IN_TERM_CAL      : integer := 0;                 -- provides option to skip the input termination calibration
+      SKIP_DYNAMIC_CAL      : integer := 0;                 -- provides option to skip the dynamic delay calibration
+      SKIP_DYN_IN_TERM      : integer := 1;                 -- provides option to skip the input termination calibration
+      C_MC_CALIBRATION_MODE : string  := "CALIBRATION";     -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
+                                                            -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY 
+                                                            -- (Quarter, etc)
+      C_SIMULATION          : string  := "FALSE";           -- Tells us whether the design is being simulated or implemented
+      C_MEM_TYPE            : string  := "DDR"                                                             
+
+      
+   );
+   port (
+      UI_CLK                : in std_logic;         -- main clock input for logic and IODRP CLK pins.  At top level, this should also connect to IODRP2_MCB 
+                                                    --  CLK pins
+      RST                   : in std_logic;         -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
+      DONE_SOFTANDHARD_CAL  : out std_logic;        -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB 
+                                                    --  hard calib complete)
+      PLL_LOCK              : in std_logic;         -- Lock signal from PLL
+      SELFREFRESH_REQ       : in std_logic;
+      SELFREFRESH_MCB_MODE  : in std_logic;
+      SELFREFRESH_MCB_REQ   : out std_logic;
+      SELFREFRESH_MODE      : out std_logic;
+      IODRP_ADD             : out std_logic;        -- IODRP ADD port 
+      IODRP_SDI             : out std_logic;        -- IODRP SDI port
+      RZQ_IN                : in std_logic;         -- RZQ pin from board - expected to have a 2*R resistor to ground
+      RZQ_IODRP_SDO         : in std_logic;         -- RZQ IODRP's SDO port
+      RZQ_IODRP_CS          : out std_logic := '0'; -- RZQ IODRP's CS port
+      ZIO_IN                : in std_logic;         -- Z-stated IO pin - garanteed not to be driven externally
+      ZIO_IODRP_SDO         : in std_logic;         -- ZIO IODRP's SDO port
+      ZIO_IODRP_CS          : out std_logic := '0'; -- ZIO IODRP's CS port
+      MCB_UIADD             : out std_logic;        -- to MCB's UIADD port
+      MCB_UISDI             : out std_logic;        -- to MCB's UISDI port
+      MCB_UOSDO             : in std_logic;         -- from MCB's UOSDO port (User output SDO)
+      MCB_UODONECAL         : in std_logic;         -- indicates when MCB hard calibration process is complete
+      MCB_UOREFRSHFLAG      : in std_logic;         -- high during refresh cycle and time when MCB is innactive
+      MCB_UICS              : out std_logic;        -- to MCB's UICS port (User Input CS)
+      MCB_UIDRPUPDATE       : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used 
+                                                    --  during IODRP2_MCB writes).  Currently just trasnparent
+      MCB_UIBROADCAST       : out std_logic;        -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
+      MCB_UIADDR            : out std_logic_vector(4 downto 0) := "00000";  -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
+      MCB_UICMDEN           : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
+      MCB_UIDONECAL         : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
+      MCB_UIDQLOWERDEC      : out std_logic ;
+      MCB_UIDQLOWERINC      : out std_logic ;
+      MCB_UIDQUPPERDEC      : out std_logic ;
+      MCB_UIDQUPPERINC      : out std_logic ;
+      MCB_UILDQSDEC         : out std_logic := '0';
+      MCB_UILDQSINC         : out std_logic := '0';
+      MCB_UIREAD            : out std_logic;        -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in 
+                                                    --  regular IODRP2).  IODRPCTRLR_R_WB becomes don't-care.
+      MCB_UIUDQSDEC         : out std_logic := '0';
+      MCB_UIUDQSINC         : out std_logic := '0';
+      MCB_RECAL             : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
+      MCB_UICMD             : out std_logic;
+      MCB_UICMDIN           : out std_logic;
+      MCB_UIDQCOUNT         : out std_logic_vector(3 downto 0);
+      MCB_UODATA            : in std_logic_vector(7 downto 0);
+      MCB_UODATAVALID       : in std_logic;
+      MCB_UOCMDREADY        : in std_logic;
+      MCB_UO_CAL_START      : in std_logic;
+      MCB_SYSRST            : out std_logic;        -- drives the MCB's SYSRST pin - the main reset for MCB
+      Max_Value             : out std_logic_vector(7 downto 0);
+      CKE_Train             : out std_logic
+   );
+end entity mcb_soft_calibration;
+
+architecture trans of mcb_soft_calibration is
+
+   constant IOI_DQ0                   : std_logic_vector(4 downto 0) := ("0000" & '1');
+   constant IOI_DQ1                   : std_logic_vector(4 downto 0) := ("0000" & '0');
+   constant IOI_DQ2                   : std_logic_vector(4 downto 0) := ("0001" & '1');
+   constant IOI_DQ3                   : std_logic_vector(4 downto 0) := ("0001" & '0');
+   constant IOI_DQ4                   : std_logic_vector(4 downto 0) := ("0010" & '1');
+   constant IOI_DQ5                   : std_logic_vector(4 downto 0) := ("0010" & '0');
+   constant IOI_DQ6                   : std_logic_vector(4 downto 0) := ("0011" & '1');
+   constant IOI_DQ7                   : std_logic_vector(4 downto 0) := ("0011" & '0');
+   constant IOI_DQ8                   : std_logic_vector(4 downto 0) := ("0100" & '1');
+   constant IOI_DQ9                   : std_logic_vector(4 downto 0) := ("0100" & '0');
+   constant IOI_DQ10                  : std_logic_vector(4 downto 0) := ("0101" & '1');
+   constant IOI_DQ11                  : std_logic_vector(4 downto 0) := ("0101" & '0');
+   constant IOI_DQ12                  : std_logic_vector(4 downto 0) := ("0110" & '1');
+   constant IOI_DQ13                  : std_logic_vector(4 downto 0) := ("0110" & '0');
+   constant IOI_DQ14                  : std_logic_vector(4 downto 0) := ("0111" & '1');
+   constant IOI_DQ15                  : std_logic_vector(4 downto 0) := ("0111" & '0');
+   constant IOI_UDM                   : std_logic_vector(4 downto 0) := ("1000" & '1');
+   constant IOI_LDM                   : std_logic_vector(4 downto 0) := ("1000" & '0');
+   constant IOI_CK_P                  : std_logic_vector(4 downto 0) := ("1001" & '1');
+   constant IOI_CK_N                  : std_logic_vector(4 downto 0) := ("1001" & '0');
+   constant IOI_RESET                 : std_logic_vector(4 downto 0) := ("1010" & '1');
+   constant IOI_A11                   : std_logic_vector(4 downto 0) := ("1010" & '0');
+   constant IOI_WE                    : std_logic_vector(4 downto 0) := ("1011" & '1');
+   constant IOI_BA2                   : std_logic_vector(4 downto 0) := ("1011" & '0');
+   constant IOI_BA0                   : std_logic_vector(4 downto 0) := ("1100" & '1');
+   constant IOI_BA1                   : std_logic_vector(4 downto 0) := ("1100" & '0');
+   constant IOI_RASN                  : std_logic_vector(4 downto 0) := ("1101" & '1');
+   constant IOI_CASN                  : std_logic_vector(4 downto 0) := ("1101" & '0');
+   constant IOI_UDQS_CLK              : std_logic_vector(4 downto 0) := ("1110" & '1');
+   constant IOI_UDQS_PIN              : std_logic_vector(4 downto 0) := ("1110" & '0');
+   constant IOI_LDQS_CLK              : std_logic_vector(4 downto 0) := ("1111" & '1');
+   constant IOI_LDQS_PIN              : std_logic_vector(4 downto 0) := ("1111" & '0');
+
+   constant START                     : std_logic_vector(5 downto 0) := "000000";
+   constant LOAD_RZQ_NTERM            : std_logic_vector(5 downto 0) := "000001";
+   constant WAIT1                     : std_logic_vector(5 downto 0) := "000010";
+   constant LOAD_RZQ_PTERM            : std_logic_vector(5 downto 0) := "000011";
+   constant WAIT2                     : std_logic_vector(5 downto 0) := "000100";
+   constant INC_PTERM                 : std_logic_vector(5 downto 0) := "000101";
+   constant MULTIPLY_DIVIDE           : std_logic_vector(5 downto 0) := "000110";
+   constant LOAD_ZIO_PTERM            : std_logic_vector(5 downto 0) := "000111";
+   constant WAIT3                     : std_logic_vector(5 downto 0) := "001000";
+   constant LOAD_ZIO_NTERM            : std_logic_vector(5 downto 0) := "001001";
+   constant WAIT4                     : std_logic_vector(5 downto 0) := "001010";
+   constant INC_NTERM                 : std_logic_vector(5 downto 0) := "001011";
+   constant SKEW                      : std_logic_vector(5 downto 0) := "001100";
+   constant WAIT_FOR_START_BROADCAST  : std_logic_vector(5 downto 0) := "001101";
+   constant BROADCAST_PTERM           : std_logic_vector(5 downto 0) := "001110";
+   constant WAIT5                     : std_logic_vector(5 downto 0) := "001111";
+   constant BROADCAST_NTERM           : std_logic_vector(5 downto 0) := "010000";
+   constant WAIT6                     : std_logic_vector(5 downto 0) := "010001";
+
+   constant LDQS_CLK_WRITE_P_TERM     : std_logic_vector(5 downto 0) := "010010";
+   constant LDQS_CLK_P_TERM_WAIT      : std_logic_vector(5 downto 0) := "010011";
+   constant LDQS_CLK_WRITE_N_TERM     : std_logic_vector(5 downto 0) := "010100";
+   constant LDQS_CLK_N_TERM_WAIT      : std_logic_vector(5 downto 0) := "010101";
+   constant LDQS_PIN_WRITE_P_TERM     : std_logic_vector(5 downto 0) := "010110";
+   constant LDQS_PIN_P_TERM_WAIT      : std_logic_vector(5 downto 0) := "010111";
+   constant LDQS_PIN_WRITE_N_TERM     : std_logic_vector(5 downto 0) := "011000";
+   constant LDQS_PIN_N_TERM_WAIT      : std_logic_vector(5 downto 0) := "011001";
+   constant UDQS_CLK_WRITE_P_TERM     : std_logic_vector(5 downto 0) := "011010";
+   constant UDQS_CLK_P_TERM_WAIT      : std_logic_vector(5 downto 0) := "011011";
+   constant UDQS_CLK_WRITE_N_TERM     : std_logic_vector(5 downto 0) := "011100";
+   constant UDQS_CLK_N_TERM_WAIT      : std_logic_vector(5 downto 0) := "011101";
+   constant UDQS_PIN_WRITE_P_TERM     : std_logic_vector(5 downto 0) := "011110";
+   constant UDQS_PIN_P_TERM_WAIT      : std_logic_vector(5 downto 0) := "011111";
+   constant UDQS_PIN_WRITE_N_TERM     : std_logic_vector(5 downto 0) := "100000";
+   constant UDQS_PIN_N_TERM_WAIT      : std_logic_vector(5 downto 0) := "100001"; 
+   
+   constant OFF_RZQ_PTERM             : std_logic_vector(5 downto 0) := "100010";
+   constant WAIT7                     : std_logic_vector(5 downto 0) := "100011";
+   constant OFF_ZIO_NTERM             : std_logic_vector(5 downto 0) := "100100";
+   constant WAIT8                     : std_logic_vector(5 downto 0) := "100101";
+   constant RST_DELAY                 : std_logic_vector(5 downto 0) := "100110";
+   constant START_DYN_CAL_PRE         : std_logic_vector(5 downto 0) := "100111";
+   constant WAIT_FOR_UODONE           : std_logic_vector(5 downto 0) := "101000";
+   constant LDQS_WRITE_POS_INDELAY    : std_logic_vector(5 downto 0) := "101001";
+   constant LDQS_WAIT1                : std_logic_vector(5 downto 0) := "101010";
+   constant LDQS_WRITE_NEG_INDELAY    : std_logic_vector(5 downto 0) := "101011";
+   constant LDQS_WAIT2                : std_logic_vector(5 downto 0) := "101100";
+   constant UDQS_WRITE_POS_INDELAY    : std_logic_vector(5 downto 0) := "101101";
+   constant UDQS_WAIT1                : std_logic_vector(5 downto 0) := "101110";
+   constant UDQS_WRITE_NEG_INDELAY    : std_logic_vector(5 downto 0) := "101111";
+   constant UDQS_WAIT2                : std_logic_vector(5 downto 0) := "110000";
+   constant START_DYN_CAL             : std_logic_vector(5 downto 0) := "110001";
+   constant WRITE_CALIBRATE           : std_logic_vector(5 downto 0) := "110010";
+   constant WAIT9                     : std_logic_vector(5 downto 0) := "110011";
+   constant READ_MAX_VALUE            : std_logic_vector(5 downto 0) := "110100";
+   constant WAIT10                    : std_logic_vector(5 downto 0) := "110101";
+   constant ANALYZE_MAX_VALUE         : std_logic_vector(5 downto 0) := "110110";
+   constant FIRST_DYN_CAL             : std_logic_vector(5 downto 0) := "110111";
+   constant INCREMENT                 : std_logic_vector(5 downto 0) := "111000";
+   constant DECREMENT                 : std_logic_vector(5 downto 0) := "111001"; 
+   constant DONE                      : std_logic_vector(5 downto 0) := "111010";
+   --constant INCREMENT_TA             : std_logic_vector(5 downto 0) := "111011";
+
+   constant RZQ                       : std_logic_vector(1 downto 0) := "00";
+   constant ZIO                       : std_logic_vector(1 downto 0) := "01";
+   constant MCB_PORT                  : std_logic_vector(1 downto 0) := "11";
+   constant WRITE_MODE                : std_logic := '0';
+   constant READ_MODE                 : std_logic := '1';
+    
+    -- IOI Registers
+   constant NoOp                      : std_logic_vector(7 downto 0) := "00000000";
+   constant DelayControl              : std_logic_vector(7 downto 0) := "00000001";
+   constant PosEdgeInDly              : std_logic_vector(7 downto 0) := "00000010";
+   constant NegEdgeInDly              : std_logic_vector(7 downto 0) := "00000011";
+   constant PosEdgeOutDly             : std_logic_vector(7 downto 0) := "00000100";
+   constant NegEdgeOutDly             : std_logic_vector(7 downto 0) := "00000101";
+   constant MiscCtl1                  : std_logic_vector(7 downto 0) := "00000110";
+   constant MiscCtl2                  : std_logic_vector(7 downto 0) := "00000111";
+   constant MaxValue                  : std_logic_vector(7 downto 0) := "00001000";
+    
+    -- IOB Registers
+   constant PDrive                    : std_logic_vector(7 downto 0) := "10000000";
+   constant PTerm                     : std_logic_vector(7 downto 0) := "10000001";
+   constant NDrive                    : std_logic_vector(7 downto 0) := "10000010";
+   constant NTerm                     : std_logic_vector(7 downto 0) := "10000011";
+   constant SlewRateCtl               : std_logic_vector(7 downto 0) := "10000100";
+   constant LVDSControl               : std_logic_vector(7 downto 0) := "10000101";
+   constant MiscControl               : std_logic_vector(7 downto 0) := "10000110";
+   constant InputControl              : std_logic_vector(7 downto 0) := "10000111";
+   constant TestReadback              : std_logic_vector(7 downto 0) := "10001000";
+
+-- No multi/divide is required when a 55 ohm resister is used on RZQ
+-- localparam          MULT          = 1;
+-- localparam          DIV           = 1;
+-- use 7/4 scaling factor when the 100 ohm RZQ is used
+   constant MULT                      : integer := 7;
+   constant DIV                       : integer := 4;
+
+   constant PNSKEW                    : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
+   constant PNSKEWDQS                 : std_logic := '1';
+   
+   constant MULT_S                    : integer  := 9;
+   constant DIV_S                     : integer  := 8;
+   constant MULT_W                    : integer  := 7;
+   constant DIV_W                     : integer  := 8;
+
+   constant DQS_NUMERATOR             : integer  := 3;
+   constant DQS_DENOMINATOR           : integer  := 8;
+   constant INCDEC_THRESHOLD          : std_logic_vector(7 downto 0) := X"03"; 
+                                                          -- parameter for the threshold which triggers an inc/dec to occur.  2 for half, 4 for quarter, 
+                                                          -- 3 for three eighths
+
+   constant RST_CNT                   : std_logic_vector(9 downto 0) := "0000010000";
+ 
+   constant IN_TERM_PASS             : std_logic := '0';
+   constant DYN_CAL_PASS             : std_logic := '1';
+
+   function TZQINIT_MAXCNT_W return std_logic_vector is
+     variable temp : std_logic_vector(9 downto 0) := (others=>'0');
+   begin
+      if (C_MEM_TYPE = "DDR3") then
+         temp := C_MEM_TZQINIT_MAXCNT + RST_CNT;
+      else
+         temp := 8 + RST_CNT;
+      end if;
+         return temp(9 downto 0);
+   end function;
+
+   constant TZQINIT_MAXCNT            : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W;
+
+   component iodrp_mcb_controller is
+      port (
+         memcell_address           : in std_logic_vector(7 downto 0);
+         write_data                : in std_logic_vector(7 downto 0);
+         read_data                 : out std_logic_vector(7 downto 0);
+         rd_not_write              : in std_logic;
+         cmd_valid                 : in std_logic;
+         rdy_busy_n                : out std_logic;
+         use_broadcast             : in std_logic;
+         drp_ioi_addr              : in std_logic_vector(4 downto 0);
+         sync_rst                  : in std_logic;
+         DRP_CLK                   : in std_logic;
+         DRP_CS                    : out std_logic;
+         DRP_SDI                   : out std_logic;
+         DRP_ADD                   : out std_logic;
+         DRP_BKST                  : out std_logic;
+         DRP_SDO                   : in std_logic;
+         MCB_UIREAD                : out std_logic
+      );
+   end component;
+   
+   component iodrp_controller is
+      port (
+         memcell_address           : in std_logic_vector(7 downto 0);
+         write_data                : in std_logic_vector(7 downto 0);
+         read_data                 : out std_logic_vector(7 downto 0);
+         rd_not_write              : in std_logic;
+         cmd_valid                 : in std_logic;
+         rdy_busy_n                : out std_logic;
+         use_broadcast             : in std_logic;
+         sync_rst                  : in std_logic;
+         DRP_CLK                   : in std_logic;
+         DRP_CS                    : out std_logic;
+         DRP_SDI                   : out std_logic;
+         DRP_ADD                   : out std_logic;
+         DRP_BKST                  : out std_logic;
+         DRP_SDO                   : in std_logic
+      );
+   end component;
+   
+   signal P_Term                       : std_logic_vector(5 downto 0) := "000000";  
+   signal N_Term                       : std_logic_vector(6 downto 0) := "0000000";   
+   signal P_Term_s                       : std_logic_vector(5 downto 0) := "000000";  
+   signal N_Term_s                       : std_logic_vector(6 downto 0) := "0000000"; 
+   signal P_Term_w                       : std_logic_vector(5 downto 0) := "000000";  
+   signal N_Term_w                       : std_logic_vector(6 downto 0) := "0000000"; 
+   signal P_Term_Prev                  : std_logic_vector(5 downto 0) := "000000";  
+   signal N_Term_Prev                  : std_logic_vector(6 downto 0) := "0000000"; 
+
+   signal STATE                        : std_logic_vector(5 downto 0);
+   signal IODRPCTRLR_MEMCELL_ADDR      : std_logic_vector(7 downto 0);              
+   signal IODRPCTRLR_WRITE_DATA        : std_logic_vector(7 downto 0);              
+   signal Active_IODRP                 : std_logic_vector(1 downto 0);
+   signal IODRPCTRLR_R_WB              : std_logic := '0';
+   signal IODRPCTRLR_CMD_VALID         : std_logic := '0';
+   signal IODRPCTRLR_USE_BKST          : std_logic := '0';
+   signal MCB_CMD_VALID                : std_logic := '0';
+   signal MCB_USE_BKST                 : std_logic := '0';
+   signal Pre_SYSRST                   : std_logic := '1';                          -- internally generated reset which will OR with RST input to drive MCB's
+                                                                                    -- SYSRST pin (MCB_SYSRST)
+   signal IODRP_SDO                    : std_logic;
+   signal Max_Value_Previous           : std_logic_vector(7 downto 0) := "00000000";
+   signal count                        : std_logic_vector(5 downto 0) := "000000";  -- counter for adding 18 extra clock cycles after setting Calibrate bit
+   signal counter_en                   : std_logic := '0';                          -- counter enable for "count"
+   signal First_Dyn_Cal_Done           : std_logic := '0';                          -- flag - high after the very first dynamic calibration is done
+   signal START_BROADCAST              : std_logic ;                          -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - 
+                                                                                    --  state machine will wait for this to be high
+   signal DQS_DELAY_INITIAL            : std_logic_vector(7 downto 0) := "00000000";
+   signal DQS_DELAY                    : std_logic_vector(7 downto 0);              -- contains the latest values written to LDQS and UDQS Input Delays
+   signal TARGET_DQS_DELAY             : std_logic_vector(7 downto 0);              -- used to track the target for DQS input delays - only gets updated if 
+                                                                                    --  the Max Value changes by more than the threshold
+   signal counter_inc                  : std_logic_vector(7 downto 0);              -- used to delay Inc signal by several ui_clk cycles (to deal with 
+                                                                                    --  latency on UOREFRSHFLAG)
+   signal counter_dec                  : std_logic_vector(7 downto 0);              -- used to delay Dec signal by several ui_clk cycles (to deal with 
+                                                                                    --  latency on UOREFRSHFLAG)
+   signal IODRPCTRLR_READ_DATA         : std_logic_vector(7 downto 0);
+   signal IODRPCTRLR_RDY_BUSY_N        : std_logic;
+   signal IODRP_CS                     : std_logic;
+   signal MCB_READ_DATA                : std_logic_vector(7 downto 0);
+   signal RST_reg                      : std_logic;
+   signal Block_Reset                  : std_logic;
+   signal MCB_UODATAVALID_U            : std_logic;
+
+   signal Inc_Dec_REFRSH_Flag          : std_logic_vector(2 downto 0);          -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
+   signal Max_Value_Delta_Up           : std_logic_vector(7 downto 0);          -- tracks amount latest Max Value has gone up from previous Max Value read
+   signal Half_MV_DU                   : std_logic_vector(7 downto 0);          -- half of Max_Value_Delta_Up
+   signal Max_Value_Delta_Dn           : std_logic_vector(7 downto 0);          -- tracks amount latest Max Value has gone down from previous Max Value read
+   signal Half_MV_DD                   : std_logic_vector(7 downto 0);          -- half of Max_Value_Delta_Dn
+
+   signal RstCounter                   : std_logic_vector(9 downto 0) := (others => '0');
+   signal rst_tmp                      : std_logic;
+   signal LastPass_DynCal              : std_logic;
+   signal First_In_Term_Done           : std_logic;
+   signal Inc_Flag                     : std_logic;                                 -- flag to increment Dynamic Delay
+   signal Dec_Flag                     : std_logic;                                 -- flag to decrement Dynamic Delay
+
+   signal CALMODE_EQ_CALIBRATION       : std_logic;                                 -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE 
+                                                                                    --  parameter = "CALIBRATION"
+   signal DQS_DELAY_LOWER_LIMIT        : std_logic_vector(7 downto 0);              -- Lower limit for DQS input delays 
+   signal DQS_DELAY_UPPER_LIMIT        : std_logic_vector(7 downto 0);              -- Upper limit for DQS input delays
+   signal SKIP_DYN_IN_TERMINATION      : std_logic;                                 -- wire to allow skipping dynamic input termination if either the 
+                                                                                    --  one-time or dynamic parameters are 1
+   signal SKIP_DYNAMIC_DQS_CAL         : std_logic;                                 -- wire allowing skipping dynamic DQS delay calibration if either 
+                                                                                    --  SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
+   signal Quarter_Max_Value            : std_logic_vector(7 downto 0);
+   signal Half_Max_Value               : std_logic_vector(7 downto 0);
+   signal PLL_LOCK_R1                  : std_logic;
+   signal PLL_LOCK_R2                  : std_logic;
+   signal MCB_RDY_BUSY_N               : std_logic;
+   
+   signal SELFREFRESH_REQ_R1                         : std_logic;
+   signal SELFREFRESH_REQ_R2                         : std_logic;
+   signal SELFREFRESH_REQ_R3                         : std_logic;
+   signal SELFREFRESH_MCB_MODE_R1                    : std_logic;
+   signal SELFREFRESH_MCB_MODE_R2                    : std_logic;
+   signal SELFREFRESH_MCB_MODE_R3                    : std_logic;
+   signal WAIT_SELFREFRESH_EXIT_DQS_CAL              : std_logic;
+   signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH    : std_logic;
+   signal START_DYN_CAL_STATE_R1                     : std_logic;
+   signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
+
+   -- Declare intermediate signals for referenced outputs
+   signal IODRP_ADD_xilinx0            : std_logic;
+   signal IODRP_SDI_xilinx1            : std_logic;
+   signal MCB_UIADD_xilinx2            : std_logic;
+   signal MCB_UISDI_xilinx11           : std_logic;
+   signal MCB_UICS_xilinx6             : std_logic;
+   signal MCB_UIBROADCAST_xilinx4      : std_logic;
+   signal MCB_UIADDR_int           : std_logic_vector(4 downto 0);
+   signal MCB_UIDONECAL_xilinx7        : std_logic;
+   signal MCB_UIREAD_xilinx10          : std_logic;
+   signal SELFREFRESH_MODE_xilinx11    : std_logic;
+   signal Max_Value_int                : std_logic_vector(7 downto 0);
+   signal Rst_condition1               : std_logic;
+   --signal Rst_condition2               : std_logic;
+   signal non_violating_rst            : std_logic;
+   signal WAIT_200us_COUNTER           : std_logic_vector(15 downto 0);
+   signal WaitTimer                    : std_logic_vector(7 downto 0);
+   signal WarmEnough                   : std_logic;
+   signal WaitCountEnable : std_logic;
+   signal State_Start_DynCal_R1 : std_logic;
+   signal State_Start_DynCal : std_logic;
+   
+   signal pre_sysrst_minpulse_width_ok : std_logic;
+   signal pre_sysrst_cnt : std_logic_vector(3 downto 0);
+
+   -- This function multiplies by a constant MULT and then divides by the DIV constant
+   function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
+     variable Result : integer := 0;
+     variable temp   : std_logic_vector(14 downto 0) := "000000000000000"; 
+   begin
+     for count in 0 to (MULT-1) loop
+       temp := temp + ("0000000" & Input);
+     end loop;
+     Result := (to_integer(unsigned(temp))) / (DIV);
+     temp   := std_logic_vector(to_unsigned(Result,15));
+     return temp(7 downto 0);
+   end function Mult_Divide;
+
+
+
+   attribute syn_preserve : boolean;
+   attribute syn_preserve of P_Term                  : signal is TRUE;
+   attribute syn_preserve of N_Term                  : signal is TRUE;
+   attribute syn_preserve of P_Term_s                  : signal is TRUE;
+   attribute syn_preserve of N_Term_s                  : signal is TRUE;
+   attribute syn_preserve of P_Term_w                  : signal is TRUE;
+   attribute syn_preserve of N_Term_w                  : signal is TRUE;
+   
+   
+   
+   
+   attribute syn_preserve of P_Term_Prev             : signal is TRUE;
+   attribute syn_preserve of N_Term_Prev             : signal is TRUE;
+   attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
+   attribute syn_preserve of IODRPCTRLR_WRITE_DATA   : signal is TRUE;
+   attribute syn_preserve of Max_Value_Previous      : signal is TRUE;
+   attribute syn_preserve of DQS_DELAY_INITIAL       : signal is TRUE;
+
+   attribute iob          : string;
+   attribute iob of DONE_SOFTANDHARD_CAL             : signal is "FALSE";
+
+begin
+
+
+-- move the default assignment here to make FORMALITY happy.
+
+   START_BROADCAST  <= '1';
+   MCB_RECAL        <= '0';
+   MCB_UIDQLOWERDEC <= '0';
+   MCB_UIADDR       <= MCB_UIADDR_int;
+   MCB_UIDQLOWERINC <= '0';
+   MCB_UIDQUPPERDEC <= '0';
+   MCB_UIDQUPPERINC <= '0';
+  
+  
+   Max_Value        <= Max_Value_int;
+   -- Drive referenced outputs
+   IODRP_ADD        <= IODRP_ADD_xilinx0;
+   IODRP_SDI        <= IODRP_SDI_xilinx1;
+   MCB_UIADD        <= MCB_UIADD_xilinx2;
+   MCB_UISDI        <= MCB_UISDI_xilinx11;
+   MCB_UICS         <= MCB_UICS_xilinx6;
+   MCB_UIBROADCAST  <= MCB_UIBROADCAST_xilinx4;
+   MCB_UIDONECAL    <= MCB_UIDONECAL_xilinx7;
+   MCB_UIREAD       <= MCB_UIREAD_xilinx10;
+   SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
+
+   Inc_Dec_REFRSH_Flag     <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
+   Max_Value_Delta_Up      <= Max_Value_int - Max_Value_Previous;
+   Half_MV_DU              <= ('0' & Max_Value_Delta_Up(7 downto 1));
+   Max_Value_Delta_Dn      <= Max_Value_Previous - Max_Value_int;
+   Half_MV_DD              <= ('0' & Max_Value_Delta_Dn(7 downto 1));
+   CALMODE_EQ_CALIBRATION  <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
+   Half_Max_Value          <= ('0' & Max_Value_int(7 downto 1));        
+   Quarter_Max_Value       <= ("00" & Max_Value_int(7 downto 2)); 
+   DQS_DELAY_LOWER_LIMIT   <= Quarter_Max_Value;    -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
+   DQS_DELAY_UPPER_LIMIT   <= Half_Max_Value;       -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
+   SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; 
+                                                -- skip dynamic input termination if either the one-time or dynamic parameters are 1
+   SKIP_DYNAMIC_DQS_CAL    <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; 
+                                                -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then    
+            DONE_SOFTANDHARD_CAL <= MCB_UODONECAL;       -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
+         else
+            DONE_SOFTANDHARD_CAL <= '0';
+         end if;   
+      end if;
+   end process;      
+
+   iodrp_controller_inst : iodrp_controller
+      port map (
+         memcell_address  => IODRPCTRLR_MEMCELL_ADDR,
+         write_data       => IODRPCTRLR_WRITE_DATA,
+         read_data        => IODRPCTRLR_READ_DATA,
+         rd_not_write     => IODRPCTRLR_R_WB,
+         cmd_valid        => IODRPCTRLR_CMD_VALID,
+         rdy_busy_n       => IODRPCTRLR_RDY_BUSY_N,
+         use_broadcast    => '0',
+         sync_rst         => RST_reg,
+         DRP_CLK          => UI_CLK,
+         DRP_CS           => IODRP_CS,
+         DRP_SDI          => IODRP_SDI_xilinx1,
+         DRP_ADD          => IODRP_ADD_xilinx0,
+         DRP_SDO          => IODRP_SDO,
+         DRP_BKST         => open 
+      );      
+   
+   iodrp_mcb_controller_inst : iodrp_mcb_controller
+      port map (
+         memcell_address  => IODRPCTRLR_MEMCELL_ADDR,
+         write_data       => IODRPCTRLR_WRITE_DATA,
+         read_data        => MCB_READ_DATA,
+         rd_not_write     => IODRPCTRLR_R_WB,
+         cmd_valid        => MCB_CMD_VALID,
+         rdy_busy_n       => MCB_RDY_BUSY_N,
+         use_broadcast    => MCB_USE_BKST,
+         drp_ioi_addr     => MCB_UIADDR_int,
+         sync_rst         => RST_reg,
+         DRP_CLK          => UI_CLK,
+         DRP_CS           => MCB_UICS_xilinx6,
+         DRP_SDI          => MCB_UISDI_xilinx11,
+         DRP_ADD          => MCB_UIADD_xilinx2,
+         DRP_BKST         => MCB_UIBROADCAST_xilinx4,
+         DRP_SDO          => MCB_UOSDO,
+         MCB_UIREAD       => MCB_UIREAD_xilinx10
+      );
+      
+      process (UI_CLK, RST) begin
+         if (RST = '1') then
+           if (C_SIMULATION = "TRUE") then
+             WAIT_200us_COUNTER <= X"7FF0";
+           else
+             WAIT_200us_COUNTER <= (others => '0');
+           end if;
+         elsif (UI_CLK'event and UI_CLK = '1') then
+            if (WAIT_200us_COUNTER(15) = '1') then
+                 WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
+            else
+                 WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
+            end if;
+         end if;
+      end process;
+
+ --  init_sequence_skip: if (C_SIMULATION = "TRUE") generate
+ --     WAIT_200us_COUNTER <= X"FFFF";
+ --     process
+ --     begin
+ --        report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
+ --        wait;
+ --     end process;
+ --  end generate;
+            
+      
+   gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate 
+   process (UI_CLK, RST) begin
+      if (RST = '1') then
+          CKE_Train <= '0';
+      elsif (UI_CLK'event and UI_CLK = '1') then
+         if (STATE = WAIT_FOR_UODONE  and MCB_UODONECAL = '1') then
+              CKE_Train <= '0';
+         elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
+              CKE_Train <= '1';
+         else
+              CKE_Train <= '0';
+         end if;
+      end if;
+   end process;       
+   end generate  ;  
+      
+   gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate 
+   process (UI_CLK) begin
+      if (UI_CLK'event and UI_CLK = '1') then
+          CKE_Train <= '0';
+      end if;
+   end process;       
+   end generate    ;
+      
+--********************************************
+-- PLL_LOCK and RST signals
+--********************************************
+   --MCB_SYSRST <= Pre_SYSRST or RST_reg;               -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
+                                                      --  SYSRST pin (MCB_SYSRST)
+   
+   rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND 
+
+   process (UI_CLK, RST) begin
+     if (RST = '1') then
+       --Block_Reset <= '0';
+       --RstCounter  <= (others => '0');
+     --elsif (UI_CLK'event and UI_CLK = '1') then  
+       -- if (rst_tmp = '1') then                     -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3)
+          Block_Reset <= '0';
+          RstCounter  <= (others => '0');
+     elsif (UI_CLK'event and UI_CLK = '1') then  
+          Block_Reset <= '0';                      -- default to allow STATE to move out of RST_DELAY state
+          if (Pre_SYSRST = '1') then
+            RstCounter  <= RST_CNT;                -- whenever STATE wants to reset the MCB, set RstCounter to h10
+          else                                                                                                   
+            if (RstCounter < TZQINIT_MAXCNT) then  -- if RstCounter is less than d512 than this will execute
+              Block_Reset <= '1';                  -- STATE won't exit RST_DELAY state
+              RstCounter  <= RstCounter + "1";     -- and Rst_Counter increments
+            end if;
+          end if;
+        end if;
+     --end if;
+   end process;
+ 
+  -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT
+  non_violating_rst <= RST and Rst_condition1;
+  MCB_SYSRST <= Pre_SYSRST;
+
+  process (UI_CLK) begin
+    if (UI_CLK'event and UI_CLK = '1') then
+       if (RstCounter >= TZQINIT_MAXCNT) then
+          Rst_condition1 <= '1';
+       else
+          Rst_condition1 <= '0';
+       end if;
+    end if;
+  end process;
+  
+-- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3)
+-- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization  process.   
+-- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which
+--    is gated by pll's lock signal.   When the PLL locks again, the RST_reg stays asserted for at least 200 us which
+--    will cause MCB to reset and reinitialize the memory afterwards.
+-- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at 
+--    its terminal count.  The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module
+--    The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration 
+--    state machine will not reset during SUSPEND.
+-- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to 
+--    Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. 
+--    It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT 
+--    termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration.
+  
+
+   --process (UI_CLK) begin
+   -- if (UI_CLK'event and UI_CLK = '1') then
+   --  
+   --    if (RstCounter < RST_CNT) then
+   --       Rst_condition2 <= '1';
+   --    else
+   --       Rst_condition2 <= '0';
+   --    end if;
+   -- end if;
+   --end process;
+  
+   process (UI_CLK, non_violating_rst) begin
+     if (non_violating_rst = '1') then
+        RST_reg <= '1';                                  -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND 
+     elsif (UI_CLK'event and UI_CLK = '1') then 
+       if (WAIT_200us_COUNTER(15) = '0')  then
+        RST_reg <= '1';
+       else
+        --RST_reg <= Rst_condition2 or rst_tmp;                                  -- insures RST_reg is at least h10 pulses long
+        RST_reg <= rst_tmp;                                  -- insures RST_reg is at least h10 pulses long
+       end if;
+     end if;
+   end process;
+   
+--*************************************************************
+-- Stretching the pre_sysrst to satisfy the minimum pulse width
+--*************************************************************
+
+process (UI_CLK) begin
+if (UI_CLK'event and UI_CLK = '1') then 
+  if (STATE = START_DYN_CAL_PRE) then
+    pre_sysrst_cnt <= pre_sysrst_cnt + '1';
+  else
+    pre_sysrst_cnt <= (others=>'0');
+  end if;
+end if;
+end process;
+
+pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3);
+
+--********************************************
+-- SUSPEND Logic
+--********************************************
+   process (UI_CLK,RST)
+   begin
+      if (RST = '1') then
+
+         SELFREFRESH_MCB_MODE_R1 <= '0';
+         SELFREFRESH_MCB_MODE_R2 <= '0';
+         SELFREFRESH_MCB_MODE_R3 <= '0';
+
+         SELFREFRESH_REQ_R1      <= '0';
+         SELFREFRESH_REQ_R2      <= '0';
+         SELFREFRESH_REQ_R3      <= '0';
+         
+         PLL_LOCK_R1             <= '0';
+         PLL_LOCK_R2             <= '0';
+
+      elsif (UI_CLK'event and UI_CLK = '1') then
+         -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
+         SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
+         SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
+         SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
+
+         -- SELFREFRESH_REQ is clocked by user's application clock
+         SELFREFRESH_REQ_R1      <= SELFREFRESH_REQ;
+         SELFREFRESH_REQ_R2      <= SELFREFRESH_REQ_R1;
+         SELFREFRESH_REQ_R3      <= SELFREFRESH_REQ_R2;
+
+         PLL_LOCK_R1             <= PLL_LOCK;
+         PLL_LOCK_R2             <= PLL_LOCK_R1;
+         
+      end if;
+   end process;      
+              
+-- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
+-- This is to make sure MCB get a locked sys_2x_clk before exiting
+-- SELFREFRESH mode.
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            SELFREFRESH_MCB_REQ <= '0';
+         --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then
+         elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then
+            SELFREFRESH_MCB_REQ <=  '0';
+         elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then  
+            SELFREFRESH_MCB_REQ <= '1';
+         end if;
+      end if;
+   end process;
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
+         elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
+            WAIT_SELFREFRESH_EXIT_DQS_CAL <=  '1';
+         elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then  
+                                                                                                                      -- START_DYN_CAL is next state
+            WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
+         end if;
+      end if;
+   end process;
+
+-- Need to detect when SM entering START_DYN_CAL
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
+            START_DYN_CAL_STATE_R1                  <= '0';
+         else
+         -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle              
+            PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
+            if (STATE = START_DYN_CAL) then
+               START_DYN_CAL_STATE_R1   <= '1';
+            else   
+               START_DYN_CAL_STATE_R1   <= '0';
+            end if;   
+            if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
+               PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
+            elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then
+               PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
+            end if;
+         end if;
+      end if;
+   end process;      
+
+-- SELFREFRESH_MCB_MODE deasserted status is hold off
+-- until Soft_Calib has at least done one loop of DQS update.
+-- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before 
+-- deassert the status of MCB's SELFREFRESH_MODE.  This is to ensure all IOs are stable before
+-- user logic sending new commands to MCB.
+   
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            SELFREFRESH_MODE_xilinx11 <= '0';
+         elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
+            SELFREFRESH_MODE_xilinx11 <=  '1';
+         elsif (WarmEnough = '1') then
+            SELFREFRESH_MODE_xilinx11 <= '0';
+         end if;
+      end if;
+   end process;
+
+
+
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+           WaitCountEnable <= '0';
+         elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then  
+           WaitCountEnable <= '0';
+         elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then  
+           WaitCountEnable <= '1';
+         else
+           WaitCountEnable <=  WaitCountEnable;
+         end if;
+      end if;
+   end process;
+
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+           State_Start_DynCal <= '0';
+         elsif (STATE = START_DYN_CAL) then  
+           State_Start_DynCal <= '1';
+         else
+           State_Start_DynCal <= '0';
+         end if;
+       end if;
+     end process;
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+           State_Start_DynCal_R1 <= '0';
+        else 
+           State_Start_DynCal_R1 <= State_Start_DynCal;
+         end if;
+       end if;
+     end process;
+
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            WaitTimer <= (others => '0');
+            WarmEnough <= '1';
+          elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1'))  then
+            WaitTimer <= (others => '0');
+            WarmEnough <= '0';
+          elsif (WaitTimer = X"04") then 
+            WaitTimer <= WaitTimer ;
+            WarmEnough <= '1';
+          elsif (WaitCountEnable  = '1') then
+            WaitTimer <= WaitTimer + '1';
+          else
+            WaitTimer <= WaitTimer ;
+          end if;  
+        end if;
+      end process;
+
+--********************************************
+--Comparitor for Dynamic Calibration circuit
+--********************************************
+   Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
+   Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
+   
+--*********************************************************************************************
+--Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
+--*********************************************************************************************
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST_reg = '1') then
+            count <= "000000";
+         elsif (counter_en = '1') then
+            count <= count + "000001";
+         else
+            count <= "000000";
+         end if;
+      end if;
+   end process;
+   
+--*********************************************************************************************
+-- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
+--*********************************************************************************************
+   process (UI_CLK, MCB_UODATAVALID)
+   begin
+     if(MCB_UODATAVALID = '1') then
+       MCB_UODATAVALID_U <= '1';
+     elsif(UI_CLK'event and UI_CLK = '1') then
+       MCB_UODATAVALID_U <= MCB_UODATAVALID;
+     end if;
+   end process;
+   
+--**************************************************************************************************************
+--Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
+--**************************************************************************************************************
+   process (Active_IODRP,  IODRP_CS, RZQ_IODRP_SDO,  ZIO_IODRP_SDO)
+   begin
+      case Active_IODRP is
+         when RZQ =>
+            RZQ_IODRP_CS <= IODRP_CS;
+            ZIO_IODRP_CS <= '0';
+            IODRP_SDO <= RZQ_IODRP_SDO;
+         when ZIO =>
+            RZQ_IODRP_CS <= '0';
+            ZIO_IODRP_CS <= IODRP_CS;
+            IODRP_SDO <= ZIO_IODRP_SDO;
+         when MCB_PORT =>
+            RZQ_IODRP_CS <= '0';
+            ZIO_IODRP_CS <= '0';
+            IODRP_SDO <= '0';
+         when others =>
+            RZQ_IODRP_CS <= '0';
+            ZIO_IODRP_CS <= '0';
+            IODRP_SDO <= '0';
+      end case;
+   end process;
+      
+--******************************************************************
+--State Machine's Always block / Case statement for Next State Logic
+--
+--The WAIT1,2,etc states were required after every state where the
+--DRP controller was used to do a write to the IODRPs - this is because
+--there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
+--sees IODRPCTRLR_CMD_VALID go high.  OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
+--soley for the purpose of reducing power, particularly on RZQ as
+--that pin is expected to have a permanent external resistor to gnd.
+--******************************************************************
+   NEXT_STATE_LOGIC: process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST_reg = '1') then                         -- Synchronous reset
+            MCB_CMD_VALID           <= '0';
+            MCB_UIADDR_int      <= "00000";          -- take control of UI/UO port
+            MCB_UICMDEN             <= '1';              -- tells MCB that it is in Soft Cal.
+            MCB_UIDONECAL_xilinx7   <= '0';
+            MCB_USE_BKST            <= '0';
+            MCB_UIDRPUPDATE         <= '1';             
+            Pre_SYSRST              <= '1';              -- keeps MCB in reset
+            IODRPCTRLR_CMD_VALID    <= '0';
+            IODRPCTRLR_MEMCELL_ADDR <= NoOp;
+            IODRPCTRLR_WRITE_DATA   <= "00000000";
+            IODRPCTRLR_R_WB         <= WRITE_MODE;
+            IODRPCTRLR_USE_BKST     <= '0';
+            P_Term                  <= "000000";
+            N_Term                  <= "0000000";
+            P_Term_s                <= "000000";
+            N_Term_w                <= "0000000";
+            P_Term_w                <= "000000";
+            N_Term_s                <= "0000000";
+            
+            P_Term_Prev             <= "000000";
+            N_Term_Prev             <= "0000000";
+            Active_IODRP            <= RZQ;
+            MCB_UILDQSINC           <= '0';              --no inc or dec
+            MCB_UIUDQSINC           <= '0';              --no inc or dec
+            MCB_UILDQSDEC           <= '0';              --no inc or dec
+            MCB_UIUDQSDEC           <= '0';
+            counter_en              <= '0';              --flag that the First Dynamic Calibration completed
+            First_Dyn_Cal_Done      <= '0';
+            Max_Value_int           <= "00000000";
+            Max_Value_Previous      <= "00000000";
+            STATE                   <= START;
+            DQS_DELAY               <= "00000000";
+            DQS_DELAY_INITIAL       <= "00000000";
+            TARGET_DQS_DELAY        <= "00000000";
+            LastPass_DynCal         <= IN_TERM_PASS;
+            First_In_Term_Done      <= '0';
+            MCB_UICMD               <= '0';
+            MCB_UICMDIN             <= '0';
+            MCB_UIDQCOUNT           <= "0000";
+            counter_inc             <= "00000000";
+            counter_dec             <= "00000000";
+         else
+            counter_en              <= '0';
+            IODRPCTRLR_CMD_VALID    <= '0';
+            IODRPCTRLR_MEMCELL_ADDR <= NoOp;
+            IODRPCTRLR_R_WB         <= READ_MODE;
+            IODRPCTRLR_USE_BKST     <= '0';
+            MCB_CMD_VALID           <= '0';              --no inc or dec
+            MCB_UILDQSINC           <= '0';              --no inc or dec
+            MCB_UIUDQSINC           <= '0';              --no inc or dec
+            MCB_UILDQSDEC           <= '0';              --no inc or dec
+            MCB_UIUDQSDEC           <= '0';
+            MCB_USE_BKST            <= '0';
+            MCB_UICMDIN             <= '0';
+            DQS_DELAY               <= DQS_DELAY;
+            TARGET_DQS_DELAY        <= TARGET_DQS_DELAY;
+
+            case STATE is               
+               when START =>    --h00
+                  MCB_UICMDEN           <= '1';          -- take control of UI/UO port
+                  MCB_UIDONECAL_xilinx7 <= '0';          -- tells MCB that it is in Soft Cal.
+                  P_Term                <= "000000";
+                  N_Term                <= "0000000";
+                  Pre_SYSRST            <= '1';          -- keeps MCB in reset
+                  LastPass_DynCal       <= IN_TERM_PASS;
+                  if (SKIP_IN_TERM_CAL = 1) then
+                     --STATE <= WRITE_CALIBRATE;
+                     STATE <= WAIT_FOR_START_BROADCAST;
+                     P_Term                <= "000000";
+                     N_Term                <= "0000000";
+                  elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_RZQ_NTERM;
+                  else
+                     STATE <= START;
+                  end if;
+               --***************************
+               -- IOB INPUT TERMINATION CAL
+               --***************************
+               when LOAD_RZQ_NTERM =>   --h01
+                  Active_IODRP            <= RZQ;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ('0' & N_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_RZQ_NTERM;
+                  else
+                     STATE <= WAIT1;
+                  end if;
+
+               when WAIT1 =>    --h02
+                  if (IODRPCTRLR_RDY_BUSY_N = '0') then
+                     STATE <= WAIT1;
+                  else
+                     STATE <= LOAD_RZQ_PTERM;
+                  end if;
+
+               when LOAD_RZQ_PTERM =>   --h03
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ("00" & P_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_RZQ_PTERM;
+                  else
+                     STATE <= WAIT2;
+                  end if;
+
+               when WAIT2 =>    --h04
+                  if (IODRPCTRLR_RDY_BUSY_N = '0') then
+                     STATE <= WAIT2;
+                  elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
+                     STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
+                  else
+                     STATE <= INC_PTERM;
+                  end if;
+
+               when INC_PTERM =>        --h05
+                  P_Term <= P_Term + "000001";
+                  STATE <= LOAD_RZQ_PTERM;
+
+               when MULTIPLY_DIVIDE =>  -- h06 
+                  -- 13/4/2011 compensate the added sync FF
+                  P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0);
+                  STATE  <= LOAD_ZIO_PTERM;
+
+               when LOAD_ZIO_PTERM =>           --h07
+                  Active_IODRP            <= ZIO;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ("00" & P_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_ZIO_PTERM;
+                  else
+                     STATE <= WAIT3;
+                  end if;
+
+               when WAIT3 =>    --h08
+                  if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
+                     STATE <= WAIT3;
+                  else
+                     STATE <= LOAD_ZIO_NTERM;
+                  end if;
+
+               when LOAD_ZIO_NTERM =>   --h09
+                  Active_IODRP            <= ZIO;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ('0' & N_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_ZIO_NTERM;
+                  else
+                     STATE <= WAIT4;
+                  end if;
+
+               when WAIT4 =>            --h0A
+                  if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
+                     STATE <= WAIT4;
+                  elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
+                     if (PNSKEW = '1') then       
+                        STATE <= SKEW;
+                     else
+                        STATE <= WAIT_FOR_START_BROADCAST;
+                     end if;            
+                  else
+                     STATE <= INC_NTERM;
+                  end if;
+
+               when INC_NTERM =>                --h0B
+                  N_Term <= N_Term + "0000001";
+                  STATE  <= LOAD_ZIO_NTERM;             
+
+               when SKEW =>     -- h0C
+               
+                  P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
+                  N_Term_w <= Mult_Divide(('0' & (N_Term-'1')),  MULT_W, DIV_W)(6 downto 0);
+                  P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0);
+                  N_Term_s <= Mult_Divide(('0' & (N_Term-'1')),  MULT_S, DIV_S)(6 downto 0);
+                  P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
+                  N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
+                  STATE  <= WAIT_FOR_START_BROADCAST;
+
+               when WAIT_FOR_START_BROADCAST => --h0D
+                  Pre_SYSRST <= '0';       -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while 
+                                           --  keeping the MCB in calibration mode
+                  Active_IODRP <= MCB_PORT;
+                  if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
+                    if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then
+                      STATE       <= BROADCAST_PTERM;
+                      P_Term_Prev <= P_Term;
+                    elsif (N_Term /= N_Term_Prev) then
+                      N_Term_Prev <= N_Term;
+                      STATE       <= BROADCAST_NTERM;
+                    else
+                      STATE <= OFF_RZQ_PTERM;
+                    end if;
+                  else
+                     STATE <= WAIT_FOR_START_BROADCAST;
+                  end if;
+
+               when BROADCAST_PTERM =>  --h0E
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ("00" & P_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  MCB_CMD_VALID           <= '1';
+                  MCB_UIDRPUPDATE         <= not First_In_Term_Done; -- Set the update flag if this is the first time through
+                  MCB_USE_BKST            <= '1';
+                  if (MCB_RDY_BUSY_N = '1') then
+                     STATE <= BROADCAST_PTERM;
+                  else
+                     STATE <= WAIT5;
+                  end if;
+
+               when WAIT5 =>    --h0F
+                  if ((not(MCB_RDY_BUSY_N)) = '1') then
+                     STATE <= WAIT5;
+                  elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
+                     if (MCB_UOREFRSHFLAG = '1')then
+                        MCB_UIDRPUPDATE <= '1';
+                        if (N_Term /= N_Term_Prev) then
+                           N_Term_Prev <= N_Term;
+                           STATE       <= BROADCAST_NTERM;
+                        else  
+                           STATE       <= OFF_RZQ_PTERM;
+                         end if;
+                     else
+                        STATE <= WAIT5;  -- wait for a Refresh cycle
+                     end if;            
+                  else
+                     N_Term_Prev <= N_Term;
+                     STATE <= BROADCAST_NTERM;
+                  end if;
+
+               when BROADCAST_NTERM =>  -- h10
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ("0" & N_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  MCB_CMD_VALID           <= '1';
+                  MCB_USE_BKST            <= '1';
+                  MCB_UIDRPUPDATE         <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
+                  if (MCB_RDY_BUSY_N = '1') then
+                     STATE <= BROADCAST_NTERM;
+                  else
+                     STATE <= WAIT6;
+                  end if;
+
+               when WAIT6 =>    -- h11
+                  if (MCB_RDY_BUSY_N = '0') then
+                     STATE <= WAIT6;
+                  elsif (First_In_Term_Done = '1') then  -- If first time through is already set, then this must be dynamic in term
+                    if (MCB_UOREFRSHFLAG = '1')then
+                      MCB_UIDRPUPDATE <= '1';
+                      STATE           <= OFF_RZQ_PTERM;
+                    else
+                      STATE <= WAIT6;   -- wait for a Refresh cycle
+                    end if;
+                  else
+                    -- if (PNSKEWDQS = '1') then
+                       STATE <= LDQS_CLK_WRITE_P_TERM;
+                   --  else
+                   --    STATE <= OFF_RZQ_PTERM;
+                   --  end if;
+                  end if;
+
+-- *********************
+               when LDQS_CLK_WRITE_P_TERM =>    -- h12
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= "00" & P_Term_w;
+                  MCB_UIADDR_int              <= IOI_LDQS_CLK;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1') then
+                    STATE <= LDQS_CLK_WRITE_P_TERM;
+                  else
+                    STATE <= LDQS_CLK_P_TERM_WAIT;
+                  end if;
+                
+        
+               when LDQS_CLK_P_TERM_WAIT =>    --7'h13  
+                 if (MCB_RDY_BUSY_N  = '0') then
+                   STATE   <= LDQS_CLK_P_TERM_WAIT;
+                 else 
+                   STATE   <= LDQS_CLK_WRITE_N_TERM;
+                 end if;        
+        
+               when  LDQS_CLK_WRITE_N_TERM =>  --7'h14
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= '0' & N_Term_s;
+                  MCB_UIADDR_int              <= IOI_LDQS_CLK;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1') then
+                    STATE <= LDQS_CLK_WRITE_N_TERM;
+                  else
+                    STATE <= LDQS_CLK_N_TERM_WAIT;
+                  end if;
+        
+   --**     
+               when  LDQS_CLK_N_TERM_WAIT =>   --7'h15
+                  if (MCB_RDY_BUSY_N  = '0') then
+                    STATE <= LDQS_CLK_N_TERM_WAIT;
+                  else 
+                    STATE           <= LDQS_PIN_WRITE_P_TERM;
+                 end if;
+                
+                
+               when   LDQS_PIN_WRITE_P_TERM => --7'h16
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= "00" & P_Term_s;
+                  MCB_UIADDR_int              <= IOI_LDQS_PIN;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1')  then
+                    STATE <= LDQS_PIN_WRITE_P_TERM;
+                  else
+                    STATE <= LDQS_PIN_P_TERM_WAIT;
+                  end if;
+                
+                
+               when  LDQS_PIN_P_TERM_WAIT =>   --7'h17
+                  if (MCB_RDY_BUSY_N  = '0')  then
+                    STATE <= LDQS_PIN_P_TERM_WAIT;
+                  else 
+                    STATE    <= LDQS_PIN_WRITE_N_TERM;
+                  end if;
+               
+                
+                when  LDQS_PIN_WRITE_N_TERM => --7'h18
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= '0' & N_Term_w;
+                  MCB_UIADDR_int              <= IOI_LDQS_PIN;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1')  then
+                    STATE <= LDQS_PIN_WRITE_N_TERM;
+                  else
+                    STATE <= LDQS_PIN_N_TERM_WAIT;
+                  end if;
+                
+                
+               when  LDQS_PIN_N_TERM_WAIT =>  --7'h19
+                  if (MCB_RDY_BUSY_N  = '0')  then
+                    STATE <= LDQS_PIN_N_TERM_WAIT;
+                  else 
+                    STATE           <= UDQS_CLK_WRITE_P_TERM;
+                  end if;
+               
+                
+                
+               when  UDQS_CLK_WRITE_P_TERM => --7'h1A
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= "00" & P_Term_w;
+                  MCB_UIADDR_int              <= IOI_UDQS_CLK;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1')  then
+                    STATE <= UDQS_CLK_WRITE_P_TERM;
+                  else
+                    STATE <= UDQS_CLK_P_TERM_WAIT;
+                  end if;
+                
+                
+               when  UDQS_CLK_P_TERM_WAIT => --7'h1B
+                  if (MCB_RDY_BUSY_N  = '0')  then
+                    STATE <= UDQS_CLK_P_TERM_WAIT;
+                  else 
+                    STATE           <= UDQS_CLK_WRITE_N_TERM;
+                  end if;
+                
+                
+               when  UDQS_CLK_WRITE_N_TERM => --7'h1C
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= '0' & N_Term_s;
+                  MCB_UIADDR_int              <= IOI_UDQS_CLK;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1')  then
+                    STATE <= UDQS_CLK_WRITE_N_TERM;
+                  else
+                    STATE <= UDQS_CLK_N_TERM_WAIT;
+                  end if;
+                
+               when UDQS_CLK_N_TERM_WAIT => --7'h1D
+                  if (MCB_RDY_BUSY_N  = '0') then
+                    STATE <= UDQS_CLK_N_TERM_WAIT;
+                  else 
+                    STATE           <= UDQS_PIN_WRITE_P_TERM;
+                  end if;
+                
+                
+                
+                when  UDQS_PIN_WRITE_P_TERM => --7'h1E
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= "00" & P_Term_s;
+                  MCB_UIADDR_int              <= IOI_UDQS_PIN;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N = '1')  then
+                    STATE <= UDQS_PIN_WRITE_P_TERM;
+                  else
+                    STATE <= UDQS_PIN_P_TERM_WAIT;
+                  end if;
+                
+                
+               when UDQS_PIN_P_TERM_WAIT =>  --7'h1F
+                  if (MCB_RDY_BUSY_N = '0')  then
+                    STATE <= UDQS_PIN_P_TERM_WAIT;
+                  else 
+                    STATE           <= UDQS_PIN_WRITE_N_TERM;
+                  end if;
+                
+                when  UDQS_PIN_WRITE_N_TERM =>  --7'h20
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= '0' & N_Term_w;
+                  MCB_UIADDR_int              <= IOI_UDQS_PIN;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N = '1')  then
+                    STATE <= UDQS_PIN_WRITE_N_TERM;
+                  else
+                    STATE <= UDQS_PIN_N_TERM_WAIT;
+                  end if;
+                
+                
+                when  UDQS_PIN_N_TERM_WAIT =>   --7'h21
+                  if (MCB_RDY_BUSY_N = '0')  then
+                    STATE <= UDQS_PIN_N_TERM_WAIT;
+                  else 
+                    STATE           <= OFF_RZQ_PTERM;
+                  end if;
+               
+-- *********************
+
+
+               when OFF_RZQ_PTERM =>    -- h22
+                  Active_IODRP            <= RZQ;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_WRITE_DATA   <= "00000000";
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  P_Term                  <= "000000";
+                  N_Term                  <= "0000000";
+                  MCB_UIDRPUPDATE         <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= OFF_RZQ_PTERM;
+                  else
+                     STATE <= WAIT7;
+                  end if;
+
+               when WAIT7 =>    -- h23
+                  if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
+                     STATE <= WAIT7;
+                  else
+                     STATE <= OFF_ZIO_NTERM;
+                  end if;
+
+               when OFF_ZIO_NTERM =>    -- h24
+                  Active_IODRP            <= ZIO;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_WRITE_DATA   <= "00000000";
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= OFF_ZIO_NTERM;
+                  else
+                     STATE <= WAIT8;
+                  end if;
+
+               when WAIT8 =>    -- h25
+                  if (IODRPCTRLR_RDY_BUSY_N = '0') then
+                     STATE <= WAIT8;
+                  else   
+                     if (First_In_Term_Done = '1') then
+                        STATE <= START_DYN_CAL;    -- No need to reset the MCB if we are in InTerm tuning
+                     else
+                        STATE <= WRITE_CALIBRATE;  -- go read the first Max_Value_int from RZQ
+                     end if;
+                  end if;   
+
+              when RST_DELAY =>      -- h26
+                --MCB_UICMDEN <= '0';          -- release control of UI/UO port      
+                if (Block_Reset = '1') then  -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
+                 STATE <= RST_DELAY;
+               else 
+                 STATE <= START_DYN_CAL_PRE;
+               end if;
+
+--***************************
+--DYNAMIC CALIBRATION PORTION
+--***************************
+               when START_DYN_CAL_PRE =>        -- h27
+                  LastPass_DynCal       <= IN_TERM_PASS;
+                  MCB_UICMDEN           <= '0';          -- release UICMDEN
+                  MCB_UIDONECAL_xilinx7 <= '1';          -- release UIDONECAL - MCB will now initialize.
+                  Pre_SYSRST            <= '1';          -- SYSRST pulse
+                  if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
+                    STATE       <= START_DYN_CAL;        -- we'll skip setting the DQS delays manually
+                  elsif (pre_sysrst_minpulse_width_ok = '1') then
+                    STATE       <= WAIT_FOR_UODONE;
+                  end if;
+
+               when WAIT_FOR_UODONE =>          -- h28
+                 Pre_SYSRST    <= '0';                   -- SYSRST pulse
+                 if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
+                   MCB_UICMDEN         <= '1';           -- grab UICMDEN
+                   DQS_DELAY_INITIAL   <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
+                   STATE               <= LDQS_WRITE_POS_INDELAY;
+                 else
+                   STATE               <= WAIT_FOR_UODONE;
+                 end if;
+
+               when LDQS_WRITE_POS_INDELAY =>   -- h29 
+                 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
+                 IODRPCTRLR_R_WB         <= WRITE_MODE;
+                 IODRPCTRLR_WRITE_DATA   <= DQS_DELAY_INITIAL;
+                 MCB_UIADDR_int     <= IOI_LDQS_CLK;
+                 MCB_CMD_VALID           <= '1';
+                 if (MCB_RDY_BUSY_N = '1') then 
+                   STATE <= LDQS_WRITE_POS_INDELAY;
+                 else
+                   STATE <= LDQS_WAIT1;
+                 end if;
+
+               when LDQS_WAIT1 =>       -- h2A
+                 if (MCB_RDY_BUSY_N = '0')then
+                   STATE <= LDQS_WAIT1;
+                 else
+                   STATE <= LDQS_WRITE_NEG_INDELAY;      
+                 end if;
+
+              when LDQS_WRITE_NEG_INDELAY =>    -- h2B
+                IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
+                IODRPCTRLR_R_WB         <= WRITE_MODE;
+                IODRPCTRLR_WRITE_DATA   <= DQS_DELAY_INITIAL;
+                MCB_UIADDR_int      <= IOI_LDQS_CLK;
+                MCB_CMD_VALID           <= '1';
+                if (MCB_RDY_BUSY_N = '1')then 
+                  STATE <= LDQS_WRITE_NEG_INDELAY;
+                else
+                  STATE <= LDQS_WAIT2;
+                end if;
+
+               when LDQS_WAIT2 =>           -- 7'h2C
+                 if(MCB_RDY_BUSY_N = '0')then
+                   STATE <= LDQS_WAIT2;
+                 else
+                   STATE <= UDQS_WRITE_POS_INDELAY;
+                 end if;
+
+               when  UDQS_WRITE_POS_INDELAY =>  -- 7'h2D
+                 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
+                 IODRPCTRLR_R_WB         <= WRITE_MODE;
+                 IODRPCTRLR_WRITE_DATA   <= DQS_DELAY_INITIAL;
+                 MCB_UIADDR_int      <= IOI_UDQS_CLK;
+                 MCB_CMD_VALID           <= '1';
+                 if (MCB_RDY_BUSY_N = '1')then
+                   STATE <= UDQS_WRITE_POS_INDELAY;
+                 else
+                   STATE <= UDQS_WAIT1;
+                 end if;
+
+               when UDQS_WAIT1 =>           -- 7'h2E
+                 if (MCB_RDY_BUSY_N = '0')then
+                   STATE <= UDQS_WAIT1;
+                 else 
+                   STATE <= UDQS_WRITE_NEG_INDELAY;
+                 end if;
+
+               when UDQS_WRITE_NEG_INDELAY => -- 7'h2F
+                 IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
+                 IODRPCTRLR_R_WB         <= WRITE_MODE;
+                 IODRPCTRLR_WRITE_DATA   <= DQS_DELAY_INITIAL;
+                 MCB_UIADDR_int     <= IOI_UDQS_CLK;
+                 MCB_CMD_VALID           <= '1';
+                 if (MCB_RDY_BUSY_N = '1')then
+                   STATE <= UDQS_WRITE_NEG_INDELAY;
+                else
+                  STATE <= UDQS_WAIT2;
+                end if;
+
+               when UDQS_WAIT2 => -- 7'h30
+                 if (MCB_RDY_BUSY_N = '0')then
+                   STATE <= UDQS_WAIT2;
+                 else 
+                    DQS_DELAY         <= DQS_DELAY_INITIAL;
+                    TARGET_DQS_DELAY  <= DQS_DELAY_INITIAL;
+                    STATE             <= START_DYN_CAL;
+                end if;
+
+               when START_DYN_CAL =>    -- h31
+                  Pre_SYSRST  <= '0';                    -- SYSRST not driven
+                  counter_inc <= (others => '0');
+                  counter_dec <= (others => '0');
+                  if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
+                     STATE <= DONE;                      --if we're skipping both dynamic algorythms, go directly to DONE
+                  elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
+                                                         --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
+                     -- Alternate between Dynamic Input Termination and Dynamic Tuning routines           
+                     if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then       
+                        LastPass_DynCal <= IN_TERM_PASS;
+                        STATE           <= LOAD_RZQ_NTERM;
+                     else 
+                        LastPass_DynCal <= DYN_CAL_PASS;
+                        STATE           <= WRITE_CALIBRATE;
+                     end if;
+                  else
+                     STATE     <= START_DYN_CAL;
+                  end if;
+
+               when WRITE_CALIBRATE =>          -- h32
+                  Pre_SYSRST              <= '0';
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
+                  IODRPCTRLR_WRITE_DATA   <= "00100000";
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  Active_IODRP            <= RZQ;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= WRITE_CALIBRATE;
+                  else
+                     STATE <= WAIT9;
+                  end if;               
+
+               when WAIT9 =>    -- h33
+                  counter_en <= '1';
+                  if (count < "100110") then             -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
+                     STATE <= WAIT9;
+                  else
+                     STATE <= READ_MAX_VALUE;
+                  end if;
+
+               when READ_MAX_VALUE =>           -- h34
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
+                  IODRPCTRLR_R_WB         <= READ_MODE;
+                  Max_Value_Previous      <= Max_Value_int;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= READ_MAX_VALUE;
+                  else
+                     STATE <= WAIT10;
+                  end if;               
+
+               when WAIT10 =>           -- h35   
+                  if (IODRPCTRLR_RDY_BUSY_N = '0') then
+                     STATE <= WAIT10;
+                  else
+                     Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
+                    if (First_In_Term_Done = '0') then
+                      STATE               <= RST_DELAY;
+                      First_In_Term_Done  <= '1';
+                    else 
+                     STATE                <= ANALYZE_MAX_VALUE;
+                    end if;
+                  end if;
+
+               when ANALYZE_MAX_VALUE =>        -- h36      only do a Inc or Dec during a REFRESH cycle.
+                 if (First_Dyn_Cal_Done = '0')then
+                   STATE <= FIRST_DYN_CAL;
+                 elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
+                    STATE            <= DECREMENT;       -- May need to Decrement
+                    TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
+                                                         -- DQS_COUNT_VIRTUAL updated (could be negative value)
+                 elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
+                    STATE            <= INCREMENT;       -- May need to Increment
+                    TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
+                 else 
+                    Max_Value_int    <= Max_Value_Previous;
+                    STATE            <= START_DYN_CAL;
+                 end if; 
+
+               when FIRST_DYN_CAL =>            -- h37
+                  First_Dyn_Cal_Done <= '1';             -- set flag that the First Dynamic Calibration has been completed
+                  STATE              <= START_DYN_CAL;
+
+               when INCREMENT =>        -- h38
+                  STATE         <= START_DYN_CAL;        -- Default case: Inc is not high or no longer in REFRSH
+                  MCB_UILDQSINC <= '0';                  -- Default case: no inc or dec
+                  MCB_UIUDQSINC <= '0';                  -- Default case: no inc or dec
+                  MCB_UILDQSDEC <= '0';                  -- Default case: no inc or dec
+                  MCB_UIUDQSDEC <= '0';                  -- Default case: no inc or dec
+                  case Inc_Dec_REFRSH_Flag is            -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
+                     when "101" =>
+                       counter_inc    <= counter_inc + '1';
+                       STATE          <= INCREMENT;      -- Increment is still high, still in REFRSH cycle      
+                       if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then 
+                                                         -- if not at the upper limit yet, and you've waited 4 clks, increment
+                          MCB_UILDQSINC <= '1';
+                          MCB_UIUDQSINC <= '1';
+                          DQS_DELAY     <= DQS_DELAY + '1';
+                       end if;
+                     when "100" =>
+                      if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
+                        STATE         <= INCREMENT;      -- Increment is still high, REFRESH ended - wait for next REFRESH
+                      end if; 
+                     when others =>
+                        STATE         <= START_DYN_CAL;
+                  end case;
+
+               when DECREMENT =>                -- h39
+                  STATE         <= START_DYN_CAL;        -- Default case: Dec is not high or no longer in REFRSH
+                  MCB_UILDQSINC <= '0';                  -- Default case: no inc or dec
+                  MCB_UIUDQSINC <= '0';                  -- Default case: no inc or dec
+                  MCB_UILDQSDEC <= '0';                  -- Default case: no inc or dec
+                  MCB_UIUDQSDEC <= '0';                  -- Default case: no inc or dec
+                  if (DQS_DELAY /= "00000000") then
+                     case Inc_Dec_REFRSH_Flag is         -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
+                        when "011" =>
+                           counter_dec    <= counter_dec + '1';
+                           STATE          <= DECREMENT;  -- Decrement is still high, still in REFRSH cycle      
+                           if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then 
+                                                         -- if not at the lower limit, and you've waited 4 clks, decrement
+                              MCB_UILDQSDEC <= '1';      -- decrement
+                              MCB_UIUDQSDEC <= '1';      -- decrement
+                              DQS_DELAY     <= DQS_DELAY - '1'; -- SBS
+                          end if;
+                        when "010" =>
+                          if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then  --if not at the lower limit, decrement
+                            STATE           <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
+                          end if;
+                        when others =>
+                           STATE            <= START_DYN_CAL;
+                     end case;
+                  end if;
+
+               when DONE =>     -- h3A
+                  Pre_SYSRST  <= '0';                    -- SYSRST cleared
+                  MCB_UICMDEN <= '0';                    -- release UICMDEN
+                  STATE       <= DONE;
+
+               when others =>
+                  MCB_UICMDEN             <= '0';        -- release UICMDEN
+                  MCB_UIDONECAL_xilinx7   <= '1';        -- release UIDONECAL - MCB will now initialize.
+                  Pre_SYSRST              <= '0';        -- SYSRST not driven
+                  IODRPCTRLR_CMD_VALID    <= '0';
+                  IODRPCTRLR_MEMCELL_ADDR <= "00000000";
+                  IODRPCTRLR_WRITE_DATA   <= "00000000";
+                  IODRPCTRLR_R_WB         <= '0';
+                  IODRPCTRLR_USE_BKST     <= '0';
+                  P_Term                  <= "000000";
+                  N_Term                  <= "0000000";
+                  Active_IODRP            <= ZIO;
+                  Max_Value_Previous      <= "00000000";
+                  MCB_UILDQSINC           <= '0';        -- no inc or dec
+                  MCB_UIUDQSINC           <= '0';        -- no inc or dec
+                  MCB_UILDQSDEC           <= '0';        -- no inc or dec
+                  MCB_UIUDQSDEC           <= '0';        -- no inc or dec
+                  counter_en              <= '0';
+                  First_Dyn_Cal_Done      <= '0';        -- flag that the First Dynamic Calibration completed
+                  Max_Value_int           <= Max_Value_int;
+                  STATE                   <= START;
+            end case;
+         end if;
+      end if;
+   end process;
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_soft_calibration_top.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_soft_calibration_top.vhd
new file mode 100755
index 0000000..10aebb4
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/mcb_soft_calibration_top.vhd
@@ -0,0 +1,428 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_soft_calibration_top.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:26 $
+-- \   \  /  \    Date Created: Mon Feb 9 2009
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR
+--Purpose:  Xilinx reference design top-level simulation
+--           wrapper file for input termination calibration
+--Reference:
+--
+--  Revision:      Date:  Comment
+--     1.0:  2/06/09:  Initial version for MIG wrapper.
+--     1.1:  3/16/09: Added pll_lock port, for using it to gate reset
+--     1.2: 6/06/09:  Removed MCB_UIDQCOUNT.
+--     1.3: 6/18/09:  corrected/changed MCB_SYSRST to be an output port
+--     1.4: 6/24/09:  gave RZQ and ZIO each their own unique ADD and SDI nets
+--     1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
+--     1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
+--     1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
+--     1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
+-- End Revision
+--**********************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+library unisim;
+use unisim.vcomponents.all;
+
+entity mcb_soft_calibration_top is
+   generic (
+      C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets 
+      C_MC_CALIBRATION_MODE : string :=  "CALIBRATION";  -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
+                                                         --  and does dynamic recal,
+                                                         -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* 
+                                                         --  no dynamic recal will be done 
+      SKIP_IN_TERM_CAL      : integer := 0;             -- provides option to skip the input termination calibration
+      SKIP_DYNAMIC_CAL      : integer := 0;             -- provides option to skip the dynamic delay calibration
+      SKIP_DYN_IN_TERM      : integer := 0;             -- provides option to skip the dynamic delay calibration
+      C_SIMULATION          : string  := "FALSE";       -- Tells us whether the design is being simulated or implemented
+      C_MEM_TYPE            : string  := "DDR"          -- provides the memory device used for the design
+
+   );
+   port (
+      UI_CLK                : in std_logic;             -- Input - global clock to be used for input_term_tuner and IODRP clock
+      RST                   : in std_logic;             -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for 
+                                                        --  IODRP (sub)controller
+      IOCLK                 : in std_logic;             -- Input - IOCLK input to the IODRP's
+      DONE_SOFTANDHARD_CAL  : out std_logic;            -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
+                                                        --  (MCB hard calib complete)
+      PLL_LOCK              : in std_logic;             -- Lock signal from PLL
+      SELFREFRESH_REQ       : in std_logic;             
+      SELFREFRESH_MCB_MODE  : in std_logic;             
+      SELFREFRESH_MCB_REQ   : out std_logic;            
+      SELFREFRESH_MODE      : out std_logic;            
+      MCB_UIADD             : out std_logic;            -- to MCB's UIADD port
+      MCB_UISDI             : out std_logic;            -- to MCB's UISDI port
+      MCB_UOSDO             : in std_logic;
+      MCB_UODONECAL         : in std_logic;
+      MCB_UOREFRSHFLAG      : in std_logic;
+      MCB_UICS              : out std_logic;
+      MCB_UIDRPUPDATE       : out std_logic;
+      MCB_UIBROADCAST       : out std_logic;
+      MCB_UIADDR            : out std_logic_vector(4 downto 0);
+      MCB_UICMDEN           : out std_logic;
+      MCB_UIDONECAL         : out std_logic;
+      MCB_UIDQLOWERDEC      : out std_logic;
+      MCB_UIDQLOWERINC      : out std_logic;
+      MCB_UIDQUPPERDEC      : out std_logic;
+      MCB_UIDQUPPERINC      : out std_logic;
+      MCB_UILDQSDEC         : out std_logic;
+      MCB_UILDQSINC         : out std_logic;
+      MCB_UIREAD            : out std_logic;
+      MCB_UIUDQSDEC         : out std_logic;
+      MCB_UIUDQSINC         : out std_logic;
+      MCB_RECAL             : out std_logic;
+      MCB_SYSRST            : out std_logic;
+
+      MCB_UICMD             : out std_logic;
+      MCB_UICMDIN           : out std_logic;
+      MCB_UIDQCOUNT         : out std_logic_vector(3 downto 0);
+      MCB_UODATA            : in std_logic_vector(7 downto 0);
+      MCB_UODATAVALID       : in std_logic;
+      MCB_UOCMDREADY        : in std_logic;
+      MCB_UO_CAL_START      : in std_logic;
+      RZQ_PIN               : inout std_logic;
+      ZIO_PIN               : inout std_logic;
+      CKE_Train             : out std_logic
+      
+   );
+end entity mcb_soft_calibration_top;
+
+architecture trans of mcb_soft_calibration_top is
+   
+component mcb_soft_calibration is
+   generic (
+      C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
+      SKIP_IN_TERM_CAL      : integer := 0;                 -- provides option to skip the input termination calibration
+      SKIP_DYNAMIC_CAL      : integer := 0;                 -- provides option to skip the dynamic delay calibration
+      SKIP_DYN_IN_TERM      : integer := 1;                 -- provides option to skip the input termination calibration
+      C_MC_CALIBRATION_MODE : string  := "CALIBRATION";      -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
+                                                            -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY 
+                                                            -- (Quarter, etc)
+
+      C_SIMULATION          : string  := "FALSE";           -- Tells us whether the design is being simulated or implemented
+      C_MEM_TYPE            : string  := "DDR"
+   );
+   port (
+      UI_CLK                : in std_logic;         -- main clock input for logic and IODRP CLK pins.  At top level, this should also connect to IODRP2_MCB 
+                                                    --  CLK pins
+      RST                   : in std_logic;         -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
+      DONE_SOFTANDHARD_CAL  : out std_logic;        -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB 
+                                                    --  hard calib complete)
+      PLL_LOCK              : in std_logic;         -- Lock signal from PLL
+      SELFREFRESH_REQ       : in std_logic;
+      SELFREFRESH_MCB_MODE  : in std_logic;
+      SELFREFRESH_MCB_REQ   : out std_logic;
+      SELFREFRESH_MODE      : out std_logic;
+      IODRP_ADD             : out std_logic;        -- IODRP ADD port 
+      IODRP_SDI             : out std_logic;        -- IODRP SDI port
+      RZQ_IN                : in std_logic;         -- RZQ pin from board - expected to have a 2*R resistor to ground
+      RZQ_IODRP_SDO         : in std_logic;         -- RZQ IODRP's SDO port
+      RZQ_IODRP_CS          : out std_logic := '0'; -- RZQ IODRP's CS port
+      ZIO_IN                : in std_logic;         -- Z-stated IO pin - garanteed not to be driven externally
+      ZIO_IODRP_SDO         : in std_logic;         -- ZIO IODRP's SDO port
+      ZIO_IODRP_CS          : out std_logic := '0'; -- ZIO IODRP's CS port
+      MCB_UIADD             : out std_logic;        -- to MCB's UIADD port
+      MCB_UISDI             : out std_logic;        -- to MCB's UISDI port
+      MCB_UOSDO             : in std_logic;         -- from MCB's UOSDO port (User output SDO)
+      MCB_UODONECAL         : in std_logic;         -- indicates when MCB hard calibration process is complete
+      MCB_UOREFRSHFLAG      : in std_logic;         -- high during refresh cycle and time when MCB is innactive
+      MCB_UICS              : out std_logic;        -- to MCB's UICS port (User Input CS)
+      MCB_UIDRPUPDATE       : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used 
+                                                    --  during IODRP2_MCB writes).  Currently just trasnparent
+      MCB_UIBROADCAST       : out std_logic;        -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
+      MCB_UIADDR            : out std_logic_vector(4 downto 0) := "00000";  -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
+      MCB_UICMDEN           : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
+      MCB_UIDONECAL         : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
+      MCB_UIDQLOWERDEC      : out std_logic := '0';
+      MCB_UIDQLOWERINC      : out std_logic := '0';
+      MCB_UIDQUPPERDEC      : out std_logic := '0';
+      MCB_UIDQUPPERINC      : out std_logic := '0';
+      MCB_UILDQSDEC         : out std_logic := '0';
+      MCB_UILDQSINC         : out std_logic := '0';
+      MCB_UIREAD            : out std_logic;        -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in 
+                                                    --  regular IODRP2).  IODRPCTRLR_R_WB becomes don't-care.
+      MCB_UIUDQSDEC         : out std_logic := '0';
+      MCB_UIUDQSINC         : out std_logic := '0';
+      MCB_RECAL             : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
+      MCB_UICMD             : out std_logic;
+      MCB_UICMDIN           : out std_logic;
+      MCB_UIDQCOUNT         : out std_logic_vector(3 downto 0);
+      MCB_UODATA            : in std_logic_vector(7 downto 0);
+      MCB_UODATAVALID       : in std_logic;
+      MCB_UOCMDREADY        : in std_logic;
+      MCB_UO_CAL_START      : in std_logic;
+      MCB_SYSRST            : out std_logic;        -- drives the MCB's SYSRST pin - the main reset for MCB
+      Max_Value             : out std_logic_vector(7 downto 0);
+      CKE_Train             : out std_logic
+      
+   );
+end component;
+
+   signal IODRP_ADD                    : std_logic;
+   signal IODRP_SDI                    : std_logic;
+   signal RZQ_IODRP_SDO                : std_logic;
+   signal RZQ_IODRP_CS                 : std_logic;
+   signal ZIO_IODRP_SDO                : std_logic;
+   signal ZIO_IODRP_CS                 : std_logic;
+   signal IODRP_SDO                    : std_logic;
+   signal IODRP_CS                     : std_logic;
+   signal IODRP_BKST                   : std_logic;
+   signal RZQ_ZIO_ODATAIN              : std_logic;
+   signal RZQ_ZIO_TRISTATE             : std_logic;
+   signal RZQ_TOUT                     : std_logic;
+   signal ZIO_TOUT                     : std_logic;
+   signal Max_Value                    : std_logic_vector(7 downto 0);
+   
+   signal RZQ_IN                       : std_logic;             -- RZQ pin from board - expected to have a 2*R resistor to ground
+   signal RZQ_IN_R1                    : std_logic;             -- RZQ pin from board - expected to have a 2*R resistor to ground
+   signal RZQ_IN_R2                    : std_logic;             -- RZQ pin from board - expected to have a 2*R resistor to ground
+   signal ZIO_IN                       : std_logic;             -- Z-stated IO pin - garanteed not to be driven externally
+   signal ZIO_IN_R1                    : std_logic;             -- Z-stated IO pin - garanteed not to be driven externally
+   signal ZIO_IN_R2                    : std_logic;             -- Z-stated IO pin - garanteed not to be driven externally
+   signal RZQ_OUT                      : std_logic;
+   signal ZIO_OUT                      : std_logic;
+   
+   -- Declare intermediate signals for referenced outputs
+   signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
+   signal MCB_UIADD_xilinx3            : std_logic;
+   signal MCB_UISDI_xilinx17           : std_logic;
+   signal MCB_UICS_xilinx7             : std_logic;
+   signal MCB_UIDRPUPDATE_xilinx13     : std_logic;
+   signal MCB_UIBROADCAST_xilinx5      : std_logic;
+   signal MCB_UIADDR_xilinx4           : std_logic_vector(4 downto 0);
+   signal MCB_UICMDEN_xilinx6          : std_logic;
+   signal MCB_UIDONECAL_xilinx8        : std_logic;
+   signal MCB_UIDQLOWERDEC_xilinx9     : std_logic;
+   signal MCB_UIDQLOWERINC_xilinx10    : std_logic;
+   signal MCB_UIDQUPPERDEC_xilinx11    : std_logic;
+   signal MCB_UIDQUPPERINC_xilinx12    : std_logic;
+   signal MCB_UILDQSDEC_xilinx14       : std_logic;
+   signal MCB_UILDQSINC_xilinx15       : std_logic;
+   signal MCB_UIREAD_xilinx16          : std_logic;
+   signal MCB_UIUDQSDEC_xilinx18       : std_logic;
+   signal MCB_UIUDQSINC_xilinx19       : std_logic;
+   signal MCB_RECAL_xilinx1            : std_logic;
+   signal MCB_SYSRST_xilinx2           : std_logic;
+begin
+   -- Drive referenced outputs
+   DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
+   MCB_UIADD <= MCB_UIADD_xilinx3;
+   MCB_UISDI <= MCB_UISDI_xilinx17;
+   MCB_UICS <= MCB_UICS_xilinx7;
+   MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
+   MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
+   MCB_UIADDR <= MCB_UIADDR_xilinx4;
+   MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
+   MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
+   MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
+   MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
+   MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
+   MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
+   MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
+   MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
+   MCB_UIREAD <= MCB_UIREAD_xilinx16;
+   MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
+   MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
+   MCB_RECAL <= MCB_RECAL_xilinx1;
+   MCB_SYSRST <= MCB_SYSRST_xilinx2;
+   
+   RZQ_ZIO_ODATAIN  <= not(RST);
+   RZQ_ZIO_TRISTATE <= not(RST);
+   IODRP_BKST       <= '0';                -- future hook for possible BKST to ZIO and RZQ
+   
+   
+   mcb_soft_calibration_inst : mcb_soft_calibration
+      generic map (
+         C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
+         C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, 
+         SKIP_IN_TERM_CAL     => SKIP_IN_TERM_CAL,
+         SKIP_DYNAMIC_CAL     => SKIP_DYNAMIC_CAL,
+         SKIP_DYN_IN_TERM     => SKIP_DYN_IN_TERM,
+	 C_SIMULATION         => C_SIMULATION,
+         C_MEM_TYPE           => C_MEM_TYPE
+
+      )
+      port map (
+         UI_CLK                => UI_CLK,
+         RST                   => RST,
+         PLL_LOCK              => PLL_LOCK,
+         SELFREFRESH_REQ       => SELFREFRESH_REQ,
+         SELFREFRESH_MCB_MODE  => SELFREFRESH_MCB_MODE,
+         SELFREFRESH_MCB_REQ   => SELFREFRESH_MCB_REQ,
+         SELFREFRESH_MODE      => SELFREFRESH_MODE,
+         DONE_SOFTANDHARD_CAL  => DONE_SOFTANDHARD_CAL_xilinx0,
+         IODRP_ADD             => IODRP_ADD,
+         IODRP_SDI             => IODRP_SDI,
+         RZQ_IN                => RZQ_IN_R2,
+         RZQ_IODRP_SDO         => RZQ_IODRP_SDO,
+         RZQ_IODRP_CS          => RZQ_IODRP_CS,
+         ZIO_IN                => ZIO_IN_R2,
+         ZIO_IODRP_SDO         => ZIO_IODRP_SDO,
+         ZIO_IODRP_CS          => ZIO_IODRP_CS,
+         MCB_UIADD             => MCB_UIADD_xilinx3,
+         MCB_UISDI             => MCB_UISDI_xilinx17,
+         MCB_UOSDO             => MCB_UOSDO,
+         MCB_UODONECAL         => MCB_UODONECAL,
+         MCB_UOREFRSHFLAG      => MCB_UOREFRSHFLAG,
+         MCB_UICS              => MCB_UICS_xilinx7,
+         MCB_UIDRPUPDATE       => MCB_UIDRPUPDATE_xilinx13,
+         MCB_UIBROADCAST       => MCB_UIBROADCAST_xilinx5,
+         MCB_UIADDR            => MCB_UIADDR_xilinx4,
+         MCB_UICMDEN           => MCB_UICMDEN_xilinx6,
+         MCB_UIDONECAL         => MCB_UIDONECAL_xilinx8,
+         MCB_UIDQLOWERDEC      => MCB_UIDQLOWERDEC_xilinx9,
+         MCB_UIDQLOWERINC      => MCB_UIDQLOWERINC_xilinx10,
+         MCB_UIDQUPPERDEC      => MCB_UIDQUPPERDEC_xilinx11,
+         MCB_UIDQUPPERINC      => MCB_UIDQUPPERINC_xilinx12,
+         MCB_UILDQSDEC         => MCB_UILDQSDEC_xilinx14,
+         MCB_UILDQSINC         => MCB_UILDQSINC_xilinx15,
+         MCB_UIREAD            => MCB_UIREAD_xilinx16,
+         MCB_UIUDQSDEC         => MCB_UIUDQSDEC_xilinx18,
+         MCB_UIUDQSINC         => MCB_UIUDQSINC_xilinx19,
+         MCB_RECAL             => MCB_RECAL_xilinx1,
+         MCB_UICMD             => MCB_UICMD,
+         MCB_UICMDIN           => MCB_UICMDIN,    
+         MCB_UIDQCOUNT         => MCB_UIDQCOUNT,     
+         MCB_UODATA            => MCB_UODATA,    
+         MCB_UODATAVALID       => MCB_UODATAVALID,    
+         MCB_UOCMDREADY        => MCB_UOCMDREADY,    
+         MCB_UO_CAL_START      => MCB_UO_CAL_START,
+         mcb_sysrst            => MCB_SYSRST_xilinx2,
+         Max_Value             => Max_Value,
+         CKE_Train             => CKE_Train
+      );
+   
+   process(UI_CLK,RST)
+   begin
+     if (RST = '1') then 
+        ZIO_IN_R1 <= '0'; 
+        ZIO_IN_R2 <= '0';
+        RZQ_IN_R1 <= '0'; 
+        RZQ_IN_R2 <= '0';          
+      elsif (UI_CLK'event and UI_CLK = '1') then
+        ZIO_IN_R1 <= ZIO_IN;
+        ZIO_IN_R2 <= ZIO_IN_R1;
+        RZQ_IN_R1 <= RZQ_IN;
+        RZQ_IN_R2 <= RZQ_IN_R1;
+      end if;
+   end process;
+
+   IOBUF_RZQ : IOBUF
+      port map (
+         o   => RZQ_IN,
+         io  => RZQ_PIN,
+         i   => RZQ_OUT,
+         t   => RZQ_TOUT
+      );
+   
+   IODRP2_RZQ : IODRP2
+      port map (
+         dataout   => open,
+         dataout2  => open,
+         dout      => RZQ_OUT,
+         sdo       => RZQ_IODRP_SDO,
+         tout      => RZQ_TOUT,
+         add       => IODRP_ADD,
+         bkst      => IODRP_BKST,
+         clk       => UI_CLK,
+         cs        => RZQ_IODRP_CS,
+         idatain   => RZQ_IN,
+         ioclk0    => IOCLK,
+         ioclk1    => '1',
+         odatain   => RZQ_ZIO_ODATAIN,
+         sdi       => IODRP_SDI,
+         t         => RZQ_ZIO_TRISTATE
+      );
+   
+  
+   gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
+                 (SKIP_IN_TERM_CAL = 0)) generate
+
+      IOBUF_ZIO : IOBUF
+         port map (
+            o   => ZIO_IN,
+            io  => ZIO_PIN,
+            i   => ZIO_OUT,
+            t   => ZIO_TOUT
+         );
+      
+      IODRP2_ZIO : IODRP2
+         port map (
+            dataout   => open,
+            dataout2  => open,
+            dout      => ZIO_OUT,
+            sdo       => ZIO_IODRP_SDO,
+            tout      => ZIO_TOUT,
+            add       => IODRP_ADD,
+            bkst      => IODRP_BKST,
+            clk       => UI_CLK,
+            cs        => ZIO_IODRP_CS,
+            idatain   => ZIO_IN,
+            ioclk0    => IOCLK,
+            ioclk1    => '1',
+            odatain   => RZQ_ZIO_ODATAIN,
+            sdi       => IODRP_SDI,
+            t         => RZQ_ZIO_TRISTATE
+         );
+   end generate;         
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_infrastructure.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_infrastructure.vhd
new file mode 100644
index 0000000..6f5a97f
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_infrastructure.vhd
@@ -0,0 +1,334 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : 3.92
+--  \   \         Application        : MIG
+--  /   /         Filename           : memc3_infrastructure.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:56 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+--Device           : Spartan-6
+--Design Name      : DDR/DDR2/DDR3/LPDDR
+--Purpose          : Clock generation/distribution and reset synchronization
+--Reference        :
+--Revision History :
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+library unisim;
+use unisim.vcomponents.all;
+
+entity memc3_infrastructure is
+generic
+  (
+    C_INCLK_PERIOD     : integer := 2500;
+    C_RST_ACT_LOW      : integer := 1;
+    C_INPUT_CLK_TYPE   : string  := "DIFFERENTIAL";
+    C_CLKOUT0_DIVIDE   : integer := 1;
+    C_CLKOUT1_DIVIDE   : integer := 1;
+    C_CLKOUT2_DIVIDE   : integer := 16;
+    C_CLKOUT3_DIVIDE   : integer := 8;
+    C_CLKFBOUT_MULT   : integer := 2;
+    C_DIVCLK_DIVIDE   : integer := 1
+
+  );
+port
+(
+    sys_clk_p       : in std_logic;
+    sys_clk_n       : in std_logic;
+    sys_clk       : in std_logic;
+    sys_rst_i       : in std_logic;
+    clk0            : out std_logic;
+    rst0            : out std_logic;
+    async_rst       : out std_logic;
+    sysclk_2x       : out std_logic;
+    sysclk_2x_180   : out std_logic;
+    mcb_drp_clk     : out std_logic;
+    pll_ce_0        : out std_logic;
+    pll_ce_90       : out std_logic;
+    pll_lock        : out std_logic
+  
+);
+end entity;
+architecture syn of memc3_infrastructure is
+
+  -- # of clock cycles to delay deassertion of reset. Needs to be a fairly
+  -- high number not so much for metastability protection, but to give time
+  -- for reset (i.e. stable clock cycles) to propagate through all state
+  -- machines and to all control signals (i.e. not all control signals have
+  -- resets, instead they rely on base state logic being reset, and the effect
+  -- of that reset propagating through the logic). Need this because we may not
+  -- be getting stable clock cycles while reset asserted (i.e. since reset
+  -- depends on PLL/DCM lock status)
+
+  constant RST_SYNC_NUM   : integer := 25;
+  constant CLK_PERIOD_NS  : real := (real(C_INCLK_PERIOD)) / 1000.0;
+  constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
+
+
+  signal   clk_2x_0            : std_logic;
+  signal   clk_2x_180          : std_logic;
+  signal   clk0_bufg           : std_logic;
+  signal   clk0_bufg_in        : std_logic;
+  signal   mcb_drp_clk_bufg_in : std_logic;
+  signal   clkfbout_clkfbin    : std_logic;
+  signal   rst_tmp             : std_logic;
+  signal   sys_clk_ibufg       : std_logic;
+  signal   sys_rst             : std_logic;
+  signal   rst0_sync_r         : std_logic_vector(RST_SYNC_NUM-1 downto 0);
+  signal   powerup_pll_locked  : std_logic;
+  signal   syn_clk0_powerup_pll_locked : std_logic;
+  signal   locked              : std_logic;
+  signal   bufpll_mcb_locked   : std_logic;
+  signal   mcb_drp_clk_sig     : std_logic;
+
+  attribute max_fanout : string;
+  attribute syn_maxfan : integer;
+  attribute KEEP : string; 
+  attribute max_fanout of rst0_sync_r : signal is "10";
+  attribute syn_maxfan of rst0_sync_r : signal is 10;
+  attribute KEEP of sys_clk_ibufg     : signal is "TRUE";
+
+begin 
+
+  sys_rst  <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
+  clk0     <= clk0_bufg;
+  pll_lock <= bufpll_mcb_locked;
+  mcb_drp_clk <= mcb_drp_clk_sig;
+
+  diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate   
+      --***********************************************************************
+      -- Differential input clock input buffers
+      --***********************************************************************
+      u_ibufg_sys_clk : IBUFGDS
+        generic map (
+          DIFF_TERM => TRUE		    
+        )
+        port map (
+          I  => sys_clk_p,
+          IB => sys_clk_n,
+          O  => sys_clk_ibufg
+          );
+  end generate;   
+  
+  
+  se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate   
+      --***********************************************************************
+      -- SINGLE_ENDED input clock input buffers
+      --***********************************************************************
+      u_ibufg_sys_clk : IBUFG
+        port map (
+          I  => sys_clk,
+          O  => sys_clk_ibufg
+          );
+  end generate;   
+
+  --***************************************************************************
+  -- Global clock generation and distribution
+  --***************************************************************************
+
+    u_pll_adv : PLL_ADV 
+    generic map 
+        (
+         BANDWIDTH          => "OPTIMIZED",
+         CLKIN1_PERIOD      => CLK_PERIOD_NS,
+         CLKIN2_PERIOD      => CLK_PERIOD_NS,
+         CLKOUT0_DIVIDE     => C_CLKOUT0_DIVIDE,
+         CLKOUT1_DIVIDE     => C_CLKOUT1_DIVIDE,
+         CLKOUT2_DIVIDE     => C_CLKOUT2_DIVIDE,
+         CLKOUT3_DIVIDE     => C_CLKOUT3_DIVIDE,
+         CLKOUT4_DIVIDE     => 1,
+         CLKOUT5_DIVIDE     => 1,
+         CLKOUT0_PHASE      => 0.000,
+         CLKOUT1_PHASE      => 180.000,
+         CLKOUT2_PHASE      => 0.000,
+         CLKOUT3_PHASE      => 0.000,
+         CLKOUT4_PHASE      => 0.000,
+         CLKOUT5_PHASE      => 0.000,
+         CLKOUT0_DUTY_CYCLE => 0.500,
+         CLKOUT1_DUTY_CYCLE => 0.500,
+         CLKOUT2_DUTY_CYCLE => 0.500,
+         CLKOUT3_DUTY_CYCLE => 0.500,
+         CLKOUT4_DUTY_CYCLE => 0.500,
+         CLKOUT5_DUTY_CYCLE => 0.500,
+	 SIM_DEVICE         => "SPARTAN6",
+         COMPENSATION       => "INTERNAL",
+         DIVCLK_DIVIDE      => C_DIVCLK_DIVIDE,
+         CLKFBOUT_MULT      => C_CLKFBOUT_MULT,
+         CLKFBOUT_PHASE     => 0.0,
+         REF_JITTER         => 0.005000
+         )
+        port map
+          (
+           CLKFBIN          => clkfbout_clkfbin,
+           CLKINSEL         => '1',
+           CLKIN1           => sys_clk_ibufg,
+           CLKIN2           => '0',
+           DADDR            => (others => '0'),
+           DCLK             => '0',
+           DEN              => '0',
+           DI               => (others => '0'),
+           DWE              => '0',
+           REL              => '0',
+           RST              => sys_rst,
+           CLKFBDCM         => open,
+           CLKFBOUT         => clkfbout_clkfbin,
+           CLKOUTDCM0       => open,
+           CLKOUTDCM1       => open,
+           CLKOUTDCM2       => open,
+           CLKOUTDCM3       => open,
+           CLKOUTDCM4       => open,
+           CLKOUTDCM5       => open,
+           CLKOUT0          => clk_2x_0,
+           CLKOUT1          => clk_2x_180,
+           CLKOUT2          => clk0_bufg_in,
+           CLKOUT3          => mcb_drp_clk_bufg_in,
+           CLKOUT4          => open,
+           CLKOUT5          => open,
+           DO               => open,
+           DRDY             => open,
+           LOCKED           => locked
+           );
+
+    U_BUFG_CLK0 : BUFG
+    port map
+    (
+     O => clk0_bufg,
+     I => clk0_bufg_in
+     );
+
+   --U_BUFG_CLK1 : BUFG 
+   -- port map (  
+   --  O => mcb_drp_clk_sig,
+   --  I => mcb_drp_clk_bufg_in
+   --  );
+
+   U_BUFG_CLK1 : BUFGCE 
+    port map (  
+     O => mcb_drp_clk_sig,
+     I => mcb_drp_clk_bufg_in,
+     CE => locked
+     );
+
+   process (mcb_drp_clk_sig, sys_rst)
+   begin
+      if(sys_rst = '1') then
+         powerup_pll_locked <= '0';
+      elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
+         if (bufpll_mcb_locked = '1') then
+            powerup_pll_locked <= '1';
+         end if;
+      end if;
+   end process;      
+
+
+   process (clk0_bufg, sys_rst)
+   begin
+      if(sys_rst = '1') then
+         syn_clk0_powerup_pll_locked <= '0';
+      elsif (clk0_bufg'event and clk0_bufg = '1') then
+         if (bufpll_mcb_locked = '1') then
+            syn_clk0_powerup_pll_locked <= '1';
+         end if;
+      end if;
+   end process;      
+
+
+   --***************************************************************************
+   -- Reset synchronization
+   -- NOTES:
+   --   1. shut down the whole operation if the PLL hasn't yet locked (and
+   --      by inference, this means that external sys_rst has been asserted -
+   --      PLL deasserts LOCKED as soon as sys_rst asserted)
+   --   2. asynchronously assert reset. This was we can assert reset even if
+   --      there is no clock (needed for things like 3-stating output buffers).
+   --      reset deassertion is synchronous.
+   --   3. asynchronous reset only look at pll_lock from PLL during power up. After
+   --      power up and pll_lock is asserted, the powerup_pll_locked will be asserted
+   --      forever until sys_rst is asserted again. PLL will lose lock when FPGA 
+   --      enters suspend mode. We don't want reset to MCB get
+   --      asserted in the application that needs suspend feature.
+   --***************************************************************************
+
+
+  async_rst <= sys_rst or not(powerup_pll_locked);
+  -- async_rst <= rst_tmp;
+  rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
+  -- rst_tmp <= sys_rst or not(powerup_pll_locked);
+
+process (clk0_bufg, rst_tmp)
+  begin
+    if (rst_tmp = '1') then
+      rst0_sync_r <= (others => '1');
+    elsif (rising_edge(clk0_bufg)) then      
+      rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0';  -- logical left shift by one (pads with 0)
+    end if;
+  end process;
+
+  rst0    <= rst0_sync_r(RST_SYNC_NUM-1);
+
+
+BUFPLL_MCB_INST : BUFPLL_MCB
+port map
+( IOCLK0         => sysclk_2x,	
+  IOCLK1         => sysclk_2x_180, 
+  LOCKED         => locked,
+  GCLK           => mcb_drp_clk_sig,
+  SERDESSTROBE0  => pll_ce_0, 
+  SERDESSTROBE1  => pll_ce_90, 
+  PLLIN0         => clk_2x_0,  
+  PLLIN1         => clk_2x_180,
+  LOCK           => bufpll_mcb_locked 
+  );
+
+end architecture syn;
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_tb_top.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_tb_top.vhd
new file mode 100644
index 0000000..6cb946b
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_tb_top.vhd
@@ -0,0 +1,1070 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : 3.92
+--  \   \         Application        : MIG
+--  /   /         Filename           : memc3_tb_top.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:56 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+--Device           : Spartan-6
+--Design Name      : DDR/DDR2/DDR3/LPDDR
+--Purpose          : This is top level module for test bench. which instantiates 
+--                   init_mem_pattern_ctr and mcb_traffic_gen modules for each user
+--                   port.
+--Reference        :
+--Revision History :
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity memc3_tb_top is
+generic
+  (
+      C_P0_MASK_SIZE                   : integer := 4;
+      C_P0_DATA_PORT_SIZE              : integer := 32;
+      C_P1_MASK_SIZE                   : integer := 4;
+      C_P1_DATA_PORT_SIZE              : integer := 32;
+      C_MEM_BURST_LEN                  : integer := 8;
+      C_SIMULATION                     : string  := "FALSE";
+      C_MEM_NUM_COL_BITS               : integer := 11;
+      C_NUM_DQ_PINS                    : integer := 8;
+      C_SMALL_DEVICE                   : string := "FALSE";
+            C_p0_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000100";
+      C_p0_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p0_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000002ff";
+      C_p0_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffffc00";
+      C_p0_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000100";
+      C_p1_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000300";
+      C_p1_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p1_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000004ff";
+      C_p1_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff800";
+      C_p1_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000300";
+      C_p2_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000500";
+      C_p2_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p2_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000006ff";
+      C_p2_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff800";
+      C_p2_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000500";
+      C_p3_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000700";
+      C_p3_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p3_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000008ff";
+      C_p3_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff000";
+      C_p3_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000700"
+  );
+port
+(
+   clk0            : in std_logic;
+   rst0            : in std_logic;
+   calib_done      : in std_logic;
+      p0_mcb_cmd_en_o                           : out std_logic;
+      p0_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p0_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p0_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p0_mcb_cmd_full_i                         : in std_logic;
+
+      p0_mcb_wr_en_o                            : out std_logic;
+      p0_mcb_wr_mask_o                          : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+      p0_mcb_wr_data_o                          : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_mcb_wr_full_i                          : in std_logic;
+      p0_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p0_mcb_rd_en_o                            : out std_logic;
+      p0_mcb_rd_data_i                          : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_mcb_rd_empty_i                         : in std_logic;
+      p0_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p1_mcb_cmd_en_o                           : out std_logic;
+      p1_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p1_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p1_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p1_mcb_cmd_full_i                         : in std_logic;
+
+      p1_mcb_wr_en_o                            : out std_logic;
+      p1_mcb_wr_mask_o                          : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+      p1_mcb_wr_data_o                          : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_mcb_wr_full_i                          : in std_logic;
+      p1_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p1_mcb_rd_en_o                            : out std_logic;
+      p1_mcb_rd_data_i                          : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_mcb_rd_empty_i                         : in std_logic;
+      p1_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p2_mcb_cmd_en_o                           : out std_logic;
+      p2_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p2_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p2_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p2_mcb_cmd_full_i                         : in std_logic;
+
+      p2_mcb_wr_en_o                            : out std_logic;
+      p2_mcb_wr_mask_o                          : out std_logic_vector(3 downto 0);
+      p2_mcb_wr_data_o                          : out std_logic_vector(31 downto 0);
+      p2_mcb_wr_full_i                          : in std_logic;
+      p2_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p2_mcb_rd_en_o                            : out std_logic;
+      p2_mcb_rd_data_i                          : in std_logic_vector(31 downto 0);
+      p2_mcb_rd_empty_i                         : in std_logic;
+      p2_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p3_mcb_cmd_en_o                           : out std_logic;
+      p3_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p3_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p3_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p3_mcb_cmd_full_i                         : in std_logic;
+
+      p3_mcb_wr_en_o                            : out std_logic;
+      p3_mcb_wr_mask_o                          : out std_logic_vector(3 downto 0);
+      p3_mcb_wr_data_o                          : out std_logic_vector(31 downto 0);
+      p3_mcb_wr_full_i                          : in std_logic;
+      p3_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p3_mcb_rd_en_o                            : out std_logic;
+      p3_mcb_rd_data_i                          : in std_logic_vector(31 downto 0);
+      p3_mcb_rd_empty_i                         : in std_logic;
+      p3_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+
+
+   vio_modify_enable   : in std_logic;
+   vio_data_mode_value : in std_logic_vector(2 downto 0);
+   vio_addr_mode_value : in std_logic_vector(2 downto 0);
+   cmp_error       : out std_logic;
+   cmp_data        : out std_logic_vector(31 downto 0);
+   cmp_data_valid  : out std_logic;
+   error           : out std_logic;
+   error_status    : out std_logic_vector(127 downto 0)
+);
+end memc3_tb_top;
+
+architecture arc of memc3_tb_top is
+
+function ERROR_DQWIDTH (val_i : integer) return integer is
+begin
+  if (val_i = 4) then
+    return 1;
+  else
+    return val_i/8;
+  end if;
+end function ERROR_DQWIDTH;
+
+constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
+
+component init_mem_pattern_ctr IS
+   generic (
+      FAMILY                         : string;
+      BEGIN_ADDRESS                  : std_logic_vector(31 downto 0);
+      END_ADDRESS                    : std_logic_vector(31 downto 0);
+      DWIDTH                         : integer;
+      CMD_SEED_VALUE                 : std_logic_vector(31 downto 0);
+      DATA_SEED_VALUE                : std_logic_vector(31 downto 0);
+      DATA_MODE                      : std_logic_vector(3 downto 0);
+      PORT_MODE                      : string
+   );
+   PORT (
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic;
+      mcb_cmd_bl_i                   : in std_logic_vector(5 downto 0);
+      mcb_cmd_en_i                   : in std_logic;
+      mcb_cmd_instr_i                : in std_logic_vector(2 downto 0);
+      mcb_init_done_i                : in std_logic;
+      mcb_wr_en_i                    : in std_logic;
+      vio_modify_enable              : in std_logic;
+      vio_data_mode_value            : in std_logic_vector(2 downto 0);
+      vio_addr_mode_value            : in std_logic_vector(2 downto 0);
+      vio_bl_mode_value              : in STD_LOGIC_VECTOR(1 downto 0);
+      vio_fixed_bl_value             : in STD_LOGIC_VECTOR(5 downto 0);
+      cmp_error                      : in std_logic;
+      run_traffic_o                  : out std_logic;
+      start_addr_o                   : out std_logic_vector(31 downto 0);
+      end_addr_o                     : out std_logic_vector(31 downto 0);
+      cmd_seed_o                     : out std_logic_vector(31 downto 0);
+      data_seed_o                    : out std_logic_vector(31 downto 0);
+      load_seed_o                    : out std_logic;
+      addr_mode_o                    : out std_logic_vector(2 downto 0);
+      instr_mode_o                   : out std_logic_vector(3 downto 0);
+      bl_mode_o                      : out std_logic_vector(1 downto 0);
+      data_mode_o                    : out std_logic_vector(3 downto 0);
+      mode_load_o                    : out std_logic;
+      fixed_bl_o                     : out std_logic_vector(5 downto 0);
+      fixed_instr_o                  : out std_logic_vector(2 downto 0);
+      fixed_addr_o                   : out std_logic_vector(31 downto 0)
+   );
+end component;
+
+component mcb_traffic_gen is
+   generic (
+
+      FAMILY                         : string;
+      SIMULATION                     : string;
+      MEM_BURST_LEN                  : integer;
+      PORT_MODE                      : string;
+      DATA_PATTERN                   : string;
+      CMD_PATTERN                    : string;
+      ADDR_WIDTH                     : integer;
+      CMP_DATA_PIPE_STAGES           : integer;
+      MEM_COL_WIDTH                  : integer;
+      NUM_DQ_PINS                    : integer;
+      DQ_ERROR_WIDTH                 : integer;
+      DWIDTH                         : integer;
+      PRBS_EADDR_MASK_POS            : std_logic_vector(31 downto 0);
+      PRBS_SADDR_MASK_POS            : std_logic_vector(31 downto 0);
+      PRBS_EADDR                     : std_logic_vector(31 downto 0);
+      PRBS_SADDR                     : std_logic_vector(31 downto 0)
+   );
+   port (
+
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic;
+      run_traffic_i                  : in std_logic;
+      manual_clear_error             : in std_logic;
+      -- *** runtime parameter ***
+      start_addr_i                   : in std_logic_vector(31 downto 0);
+      end_addr_i                     : in std_logic_vector(31 downto 0);
+      cmd_seed_i                     : in std_logic_vector(31 downto 0);
+      data_seed_i                    : in std_logic_vector(31 downto 0);
+      load_seed_i                    : in std_logic;
+
+      addr_mode_i                    : in std_logic_vector(2 downto 0);
+      instr_mode_i                   : in std_logic_vector(3 downto 0);
+      bl_mode_i                      : in std_logic_vector(1 downto 0);
+      data_mode_i                    : in std_logic_vector(3 downto 0);
+      mode_load_i                    : in std_logic;
+
+      -- fixed pattern inputs interface
+      fixed_bl_i                     : in std_logic_vector(5 downto 0);
+      fixed_instr_i                  : in std_logic_vector(2 downto 0);
+      fixed_addr_i                   : in std_logic_vector(31 downto 0);
+      fixed_data_i                   : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
+
+      bram_cmd_i                     : in std_logic_vector(38 downto 0);
+      bram_valid_i                   : in std_logic;
+      bram_rdy_o                     : out std_logic;
+
+      --///////////////////////////////////////////////////////////////////////////
+      --  MCB INTERFACE
+      -- interface to mcb command port
+      mcb_cmd_en_o                   : out std_logic;
+      mcb_cmd_instr_o                : out std_logic_vector(2 downto 0);
+      mcb_cmd_addr_o                 : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      mcb_cmd_bl_o                   : out std_logic_vector(5 downto 0);
+      mcb_cmd_full_i                 : in std_logic;
+      -- interface to mcb wr data port
+      mcb_wr_en_o                    : out std_logic;
+      mcb_wr_data_o                  : out std_logic_vector(DWIDTH - 1 downto 0);
+      mcb_wr_mask_o                  : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
+      mcb_wr_data_end_o              : OUT std_logic;
+
+      mcb_wr_full_i                  : in std_logic;
+      mcb_wr_fifo_counts             : in std_logic_vector(6 downto 0);
+
+      -- interface to mcb rd data port
+      mcb_rd_en_o                    : out std_logic;
+      mcb_rd_data_i                  : in std_logic_vector(DWIDTH - 1 downto 0);
+      mcb_rd_empty_i                 : in std_logic;
+      mcb_rd_fifo_counts             : in std_logic_vector(6 downto 0);
+      --///////////////////////////////////////////////////////////////////////////
+      -- status feedback
+      counts_rst                     : in std_logic;
+      wr_data_counts                 : out std_logic_vector(47 downto 0);
+      rd_data_counts                 : out std_logic_vector(47 downto 0);
+      cmp_data                       : out std_logic_vector(DWIDTH - 1 downto 0);
+      cmp_data_valid                 : out std_logic;
+      cmp_error			     : out std_logic;
+      error                          : out std_logic;
+      error_status                   : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
+      mem_rd_data                    : out std_logic_vector(DWIDTH - 1 downto 0);
+      dq_error_bytelane_cmp          : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
+      cumlative_dq_lane_error        : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)      
+
+   );
+end component;
+
+   -- Function to determine the number of data patterns to be generated
+   function DATA_PATTERN_CALC return string is
+   begin
+      if (C_SMALL_DEVICE = "FALSE") then
+         return "DGEN_ALL";
+      else
+         return "DGEN_ADDR";
+      end if;
+   end function;
+
+   constant FAMILY                        : string := "SPARTAN6";
+   constant DATA_PATTERN                  : string := DATA_PATTERN_CALC;
+   constant CMD_PATTERN                   : string := "CGEN_ALL";
+   constant ADDR_WIDTH                    : integer := 30;
+   constant CMP_DATA_PIPE_STAGES          : integer := 0;
+   constant PRBS_SADDR_MASK_POS           : std_logic_vector(31 downto 0)  := X"00007000";
+   constant PRBS_EADDR_MASK_POS           : std_logic_vector(31 downto 0)  := X"FFFF8000";
+   constant PRBS_SADDR                    : std_logic_vector(31 downto 0)  := X"00005000";
+   constant PRBS_EADDR                    : std_logic_vector(31 downto 0)  := X"00007fff";
+   constant BEGIN_ADDRESS                 : std_logic_vector(31 downto 0)  := X"00000000";
+   constant END_ADDRESS                   : std_logic_vector(31 downto 0)  := X"00000fff";
+   constant DATA_MODE                     : std_logic_vector(3 downto 0) := "0010";
+
+
+       
+    
+
+  
+   constant p0_DWIDTH : integer := 32;
+ 
+   constant p1_DWIDTH : integer := 32;
+ 
+   constant p2_DWIDTH : integer := 32;
+ 
+   constant p3_DWIDTH : integer := 32;
+
+  
+   constant p0_PORT_MODE                  : string := "BI_MODE";           
+  
+   constant p1_PORT_MODE                  : string := "BI_MODE";           
+ 
+   constant p2_PORT_MODE                  : string := "BI_MODE";           
+  
+   constant p3_PORT_MODE                  : string := "BI_MODE";           
+
+
+    
+     
+
+   
+    
+
+  
+  
+
+  
+
+
+	
+--p0 Signal declarations
+signal p0_tg_run_traffic           : std_logic;
+signal p0_tg_start_addr            : std_logic_vector(31 downto 0);
+signal p0_tg_end_addr              : std_logic_vector(31 downto 0);
+signal p0_tg_cmd_seed              : std_logic_vector(31 downto 0);
+signal p0_tg_data_seed             : std_logic_vector(31 downto 0);
+signal p0_tg_load_seed             : std_logic;
+signal p0_tg_addr_mode             : std_logic_vector(2 downto 0);
+signal p0_tg_instr_mode            : std_logic_vector(3 downto 0);
+signal p0_tg_bl_mode               : std_logic_vector(1 downto 0);
+signal p0_tg_data_mode             : std_logic_vector(3 downto 0);
+signal p0_tg_mode_load             : std_logic;
+signal p0_tg_fixed_bl              : std_logic_vector(5 downto 0);
+signal p0_tg_fixed_instr           : std_logic_vector(2 downto 0);
+signal p0_tg_fixed_addr            : std_logic_vector(31 downto 0);
+signal p0_error_status             : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
+signal p0_error                    : std_logic;
+signal p0_cmp_error                : std_logic;
+signal p0_cmp_data                 : std_logic_vector(p0_DWIDTH-1 downto 0);  
+signal p0_cmp_data_valid           : std_logic;  
+
+signal p0_mcb_cmd_en_o_int         : std_logic;
+signal p0_mcb_cmd_instr_o_int      : std_logic_vector(2 downto 0);
+signal p0_mcb_cmd_bl_o_int         : std_logic_vector(5 downto 0);
+signal p0_mcb_cmd_addr_o_int       : std_logic_vector(29 downto 0);
+signal p0_mcb_wr_en_o_int          : std_logic;
+
+	
+--p1 Signal declarations
+signal p1_tg_run_traffic           : std_logic;
+signal p1_tg_start_addr            : std_logic_vector(31 downto 0);
+signal p1_tg_end_addr              : std_logic_vector(31 downto 0);
+signal p1_tg_cmd_seed              : std_logic_vector(31 downto 0);
+signal p1_tg_data_seed             : std_logic_vector(31 downto 0);
+signal p1_tg_load_seed             : std_logic;
+signal p1_tg_addr_mode             : std_logic_vector(2 downto 0);
+signal p1_tg_instr_mode            : std_logic_vector(3 downto 0);
+signal p1_tg_bl_mode               : std_logic_vector(1 downto 0);
+signal p1_tg_data_mode             : std_logic_vector(3 downto 0);
+signal p1_tg_mode_load             : std_logic;
+signal p1_tg_fixed_bl              : std_logic_vector(5 downto 0);
+signal p1_tg_fixed_instr           : std_logic_vector(2 downto 0);
+signal p1_tg_fixed_addr            : std_logic_vector(31 downto 0);
+signal p1_error_status             : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
+signal p1_error                    : std_logic;
+signal p1_cmp_error                : std_logic;
+signal p1_cmp_data                 : std_logic_vector(p1_DWIDTH-1 downto 0);  
+signal p1_cmp_data_valid           : std_logic;  
+
+signal p1_mcb_cmd_en_o_int         : std_logic;
+signal p1_mcb_cmd_instr_o_int      : std_logic_vector(2 downto 0);
+signal p1_mcb_cmd_bl_o_int         : std_logic_vector(5 downto 0);
+signal p1_mcb_cmd_addr_o_int       : std_logic_vector(29 downto 0);
+signal p1_mcb_wr_en_o_int          : std_logic;
+
+	
+--p2 Signal declarations
+signal p2_tg_run_traffic           : std_logic;
+signal p2_tg_start_addr            : std_logic_vector(31 downto 0);
+signal p2_tg_end_addr              : std_logic_vector(31 downto 0);
+signal p2_tg_cmd_seed              : std_logic_vector(31 downto 0);
+signal p2_tg_data_seed             : std_logic_vector(31 downto 0);
+signal p2_tg_load_seed             : std_logic;
+signal p2_tg_addr_mode             : std_logic_vector(2 downto 0);
+signal p2_tg_instr_mode            : std_logic_vector(3 downto 0);
+signal p2_tg_bl_mode               : std_logic_vector(1 downto 0);
+signal p2_tg_data_mode             : std_logic_vector(3 downto 0);
+signal p2_tg_mode_load             : std_logic;
+signal p2_tg_fixed_bl              : std_logic_vector(5 downto 0);
+signal p2_tg_fixed_instr           : std_logic_vector(2 downto 0);
+signal p2_tg_fixed_addr            : std_logic_vector(31 downto 0);
+signal p2_error_status             : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
+signal p2_error                    : std_logic;
+signal p2_cmp_error                : std_logic;
+signal p2_cmp_data                 : std_logic_vector(p2_DWIDTH-1 downto 0);  
+signal p2_cmp_data_valid           : std_logic;  
+
+signal p2_mcb_cmd_en_o_int         : std_logic;
+signal p2_mcb_cmd_instr_o_int      : std_logic_vector(2 downto 0);
+signal p2_mcb_cmd_bl_o_int         : std_logic_vector(5 downto 0);
+signal p2_mcb_cmd_addr_o_int       : std_logic_vector(29 downto 0);
+signal p2_mcb_wr_en_o_int          : std_logic;
+
+	
+--p3 Signal declarations
+signal p3_tg_run_traffic           : std_logic;
+signal p3_tg_start_addr            : std_logic_vector(31 downto 0);
+signal p3_tg_end_addr              : std_logic_vector(31 downto 0);
+signal p3_tg_cmd_seed              : std_logic_vector(31 downto 0);
+signal p3_tg_data_seed             : std_logic_vector(31 downto 0);
+signal p3_tg_load_seed             : std_logic;
+signal p3_tg_addr_mode             : std_logic_vector(2 downto 0);
+signal p3_tg_instr_mode            : std_logic_vector(3 downto 0);
+signal p3_tg_bl_mode               : std_logic_vector(1 downto 0);
+signal p3_tg_data_mode             : std_logic_vector(3 downto 0);
+signal p3_tg_mode_load             : std_logic;
+signal p3_tg_fixed_bl              : std_logic_vector(5 downto 0);
+signal p3_tg_fixed_instr           : std_logic_vector(2 downto 0);
+signal p3_tg_fixed_addr            : std_logic_vector(31 downto 0);
+signal p3_error_status             : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
+signal p3_error                    : std_logic;
+signal p3_cmp_error                : std_logic;
+signal p3_cmp_data                 : std_logic_vector(p3_DWIDTH-1 downto 0);  
+signal p3_cmp_data_valid           : std_logic;  
+
+signal p3_mcb_cmd_en_o_int         : std_logic;
+signal p3_mcb_cmd_instr_o_int      : std_logic_vector(2 downto 0);
+signal p3_mcb_cmd_bl_o_int         : std_logic_vector(5 downto 0);
+signal p3_mcb_cmd_addr_o_int       : std_logic_vector(29 downto 0);
+signal p3_mcb_wr_en_o_int          : std_logic;
+
+
+
+
+
+
+
+
+
+--signal cmp_data : std_logic_vector(31 downto 0);
+begin
+
+   cmp_error       <= p0_cmp_error or p1_cmp_error or p2_cmp_error or p3_cmp_error;
+   error           <= p0_error or p1_error or p2_error or p3_error;
+   error_status    <= p0_error_status;
+   cmp_data        <= p0_cmp_data(31 downto 0);
+   cmp_data_valid  <= p0_cmp_data_valid;
+
+
+p0_mcb_cmd_en_o     <= p0_mcb_cmd_en_o_int;
+p0_mcb_cmd_instr_o  <= p0_mcb_cmd_instr_o_int;
+p0_mcb_cmd_bl_o     <= p0_mcb_cmd_bl_o_int;
+p0_mcb_cmd_addr_o   <= p0_mcb_cmd_addr_o_int;
+p0_mcb_wr_en_o     <= p0_mcb_wr_en_o_int;
+
+ init_mem_pattern_ctr_p0 :init_mem_pattern_ctr 
+ generic map
+ 	 (
+    DWIDTH            =>    p0_DWIDTH,
+    FAMILY            =>    FAMILY,
+    BEGIN_ADDRESS     =>    C_p0_BEGIN_ADDRESS,
+    END_ADDRESS       =>    C_p0_END_ADDRESS,
+    CMD_SEED_VALUE    =>    X"56456783",
+    DATA_SEED_VALUE   =>    X"12345678",
+    DATA_MODE         =>    C_p0_DATA_MODE,
+    PORT_MODE         =>    p0_PORT_MODE
+	
+   )
+ port map
+    (
+    clk_i              =>   clk0,
+    rst_i              =>   rst0,
+                       
+    mcb_cmd_en_i       =>   p0_mcb_cmd_en_o_int,
+    mcb_cmd_instr_i    =>   p0_mcb_cmd_instr_o_int,
+    mcb_cmd_bl_i       =>   p0_mcb_cmd_bl_o_int,
+    mcb_wr_en_i        =>   p0_mcb_wr_en_o_int,
+
+    vio_modify_enable  =>	vio_modify_enable,
+    vio_data_mode_value =>  vio_data_mode_value,
+    vio_addr_mode_value =>  vio_addr_mode_value,
+    vio_bl_mode_value	=>  "10",--vio_bl_mode_value,
+    vio_fixed_bl_value	=>  "000000",--vio_fixed_bl_value,  
+                       
+    mcb_init_done_i    =>   calib_done,
+    cmp_error          =>   p0_error,
+    run_traffic_o      =>   p0_tg_run_traffic, 
+    start_addr_o       =>   p0_tg_start_addr,
+    end_addr_o         =>   p0_tg_end_addr   ,
+    cmd_seed_o         =>   p0_tg_cmd_seed   , 
+    data_seed_o        =>   p0_tg_data_seed  ,
+    load_seed_o        =>   p0_tg_load_seed  ,
+    addr_mode_o        =>   p0_tg_addr_mode  ,
+    instr_mode_o       =>   p0_tg_instr_mode ,
+    bl_mode_o          =>   p0_tg_bl_mode    ,
+    data_mode_o        =>   p0_tg_data_mode  ,
+    mode_load_o        =>   p0_tg_mode_load  ,
+    fixed_bl_o         =>   p0_tg_fixed_bl   ,
+    fixed_instr_o      =>   p0_tg_fixed_instr,
+    fixed_addr_o       =>   p0_tg_fixed_addr 
+  );
+
+ m_traffic_gen_p0 :  mcb_traffic_gen 
+ generic map(  
+    MEM_BURST_LEN        => C_MEM_BURST_LEN, 
+    MEM_COL_WIDTH        => C_MEM_NUM_COL_BITS,
+    NUM_DQ_PINS          => C_NUM_DQ_PINS,
+    DQ_ERROR_WIDTH       => DQ_ERROR_WIDTH,
+                         
+    PORT_MODE            => p0_PORT_MODE,    
+    DWIDTH               => p0_DWIDTH,
+    CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,                     
+    FAMILY               => FAMILY,
+    SIMULATION           => "FALSE",
+    DATA_PATTERN         => DATA_PATTERN,  
+    CMD_PATTERN          => "CGEN_ALL",
+    ADDR_WIDTH           => 30,
+    PRBS_SADDR_MASK_POS  => C_p0_PRBS_SADDR_MASK_POS,
+    PRBS_EADDR_MASK_POS  => C_p0_PRBS_EADDR_MASK_POS,
+    PRBS_SADDR           => C_p0_BEGIN_ADDRESS,
+    PRBS_EADDR           => C_p0_END_ADDRESS
+  )  
+ port map
+  (  
+    clk_i                =>  clk0,
+    rst_i                =>  rst0,
+    run_traffic_i        =>  p0_tg_run_traffic,
+    manual_clear_error   =>  rst0,
+   -- runtime parameter  
+    start_addr_i         =>  p0_tg_start_addr ,
+    end_addr_i           =>  p0_tg_end_addr   ,
+    cmd_seed_i           =>  p0_tg_cmd_seed   ,
+    data_seed_i          =>  p0_tg_data_seed  ,
+    load_seed_i          =>  p0_tg_load_seed,
+    addr_mode_i          =>  p0_tg_addr_mode,
+                         
+    instr_mode_i         =>  p0_tg_instr_mode ,
+    bl_mode_i            =>  p0_tg_bl_mode    ,
+    data_mode_i          =>  p0_tg_data_mode  ,
+    mode_load_i          =>  p0_tg_mode_load  ,
+    
+    -- fixed pattern inputs interface  
+    fixed_bl_i           =>  p0_tg_fixed_bl,      
+    fixed_instr_i        =>  p0_tg_fixed_instr,   
+    fixed_addr_i         =>  p0_tg_fixed_addr,
+    fixed_data_i         =>  (others => '0'),
+    -- BRAM interface. 
+    bram_cmd_i           =>  (others => '0'),
+    bram_valid_i         =>  '0',
+    bram_rdy_o           =>  open, 
+    
+    --  MCB INTERFACE  
+    mcb_cmd_en_o	 =>  p0_mcb_cmd_en_o_int, 
+    mcb_cmd_instr_o	 =>  p0_mcb_cmd_instr_o_int, 
+    mcb_cmd_bl_o	 =>  p0_mcb_cmd_bl_o_int, 
+    mcb_cmd_addr_o	 =>  p0_mcb_cmd_addr_o_int, 
+    mcb_cmd_full_i	 =>  p0_mcb_cmd_full_i, 
+    
+    mcb_wr_en_o		 =>  p0_mcb_wr_en_o_int, 
+    mcb_wr_mask_o	 =>  p0_mcb_wr_mask_o, 
+    mcb_wr_data_o	 =>  p0_mcb_wr_data_o, 
+    mcb_wr_data_end_o    =>  open, 
+    mcb_wr_full_i	 =>  p0_mcb_wr_full_i, 
+    mcb_wr_fifo_counts	 =>  p0_mcb_wr_fifo_counts, 
+    
+    mcb_rd_en_o		 =>  p0_mcb_rd_en_o, 
+    mcb_rd_data_i	 =>  p0_mcb_rd_data_i, 
+    mcb_rd_empty_i	 =>  p0_mcb_rd_empty_i, 
+    mcb_rd_fifo_counts	 =>  p0_mcb_rd_fifo_counts, 
+
+    -- status feedback   
+    counts_rst           =>  rst0,
+    wr_data_counts       =>  open,
+    rd_data_counts       =>  open,
+    cmp_data             =>  p0_cmp_data,      
+    cmp_data_valid       =>  p0_cmp_data_valid,      
+    cmp_error            =>  p0_cmp_error,        
+    error                =>  p0_error,        
+    error_status         =>  p0_error_status,
+    mem_rd_data          =>  open,
+    dq_error_bytelane_cmp   => open,
+    cumlative_dq_lane_error => open
+  );         
+
+
+
+p1_mcb_cmd_en_o     <= p1_mcb_cmd_en_o_int;
+p1_mcb_cmd_instr_o  <= p1_mcb_cmd_instr_o_int;
+p1_mcb_cmd_bl_o     <= p1_mcb_cmd_bl_o_int;
+p1_mcb_cmd_addr_o   <= p1_mcb_cmd_addr_o_int;
+p1_mcb_wr_en_o     <= p1_mcb_wr_en_o_int;
+
+ init_mem_pattern_ctr_p1 :init_mem_pattern_ctr 
+ generic map
+ 	 (
+    DWIDTH            =>    p1_DWIDTH,
+    FAMILY            =>    FAMILY,
+    BEGIN_ADDRESS     =>    C_p1_BEGIN_ADDRESS,
+    END_ADDRESS       =>    C_p1_END_ADDRESS,
+    CMD_SEED_VALUE    =>    X"56456783",
+    DATA_SEED_VALUE   =>    X"12345678",
+    DATA_MODE         =>    C_p1_DATA_MODE,
+    PORT_MODE         =>    p1_PORT_MODE
+	
+   )
+ port map
+    (
+    clk_i              =>   clk0,
+    rst_i              =>   rst0,
+                       
+    mcb_cmd_en_i       =>   p1_mcb_cmd_en_o_int,
+    mcb_cmd_instr_i    =>   p1_mcb_cmd_instr_o_int,
+    mcb_cmd_bl_i       =>   p1_mcb_cmd_bl_o_int,
+    mcb_wr_en_i        =>   p1_mcb_wr_en_o_int,
+
+    vio_modify_enable  =>	vio_modify_enable,
+    vio_data_mode_value =>  vio_data_mode_value,
+    vio_addr_mode_value =>  vio_addr_mode_value,
+    vio_bl_mode_value	=>  "10",--vio_bl_mode_value,
+    vio_fixed_bl_value	=>  "000000",--vio_fixed_bl_value,  
+                       
+    mcb_init_done_i    =>   calib_done,
+    cmp_error          =>   p1_error,
+    run_traffic_o      =>   p1_tg_run_traffic, 
+    start_addr_o       =>   p1_tg_start_addr,
+    end_addr_o         =>   p1_tg_end_addr   ,
+    cmd_seed_o         =>   p1_tg_cmd_seed   , 
+    data_seed_o        =>   p1_tg_data_seed  ,
+    load_seed_o        =>   p1_tg_load_seed  ,
+    addr_mode_o        =>   p1_tg_addr_mode  ,
+    instr_mode_o       =>   p1_tg_instr_mode ,
+    bl_mode_o          =>   p1_tg_bl_mode    ,
+    data_mode_o        =>   p1_tg_data_mode  ,
+    mode_load_o        =>   p1_tg_mode_load  ,
+    fixed_bl_o         =>   p1_tg_fixed_bl   ,
+    fixed_instr_o      =>   p1_tg_fixed_instr,
+    fixed_addr_o       =>   p1_tg_fixed_addr 
+  );
+
+ m_traffic_gen_p1 :  mcb_traffic_gen 
+ generic map(  
+    MEM_BURST_LEN        => C_MEM_BURST_LEN, 
+    MEM_COL_WIDTH        => C_MEM_NUM_COL_BITS,
+    NUM_DQ_PINS          => C_NUM_DQ_PINS,
+    DQ_ERROR_WIDTH       => DQ_ERROR_WIDTH,
+                         
+    PORT_MODE            => p1_PORT_MODE,    
+    DWIDTH               => p1_DWIDTH,
+    CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,                     
+    FAMILY               => FAMILY,
+    SIMULATION           => "FALSE",
+    DATA_PATTERN         => DATA_PATTERN,  
+    CMD_PATTERN          => "CGEN_ALL",
+    ADDR_WIDTH           => 30,
+    PRBS_SADDR_MASK_POS  => C_p1_PRBS_SADDR_MASK_POS,
+    PRBS_EADDR_MASK_POS  => C_p1_PRBS_EADDR_MASK_POS,
+    PRBS_SADDR           => C_p1_BEGIN_ADDRESS,
+    PRBS_EADDR           => C_p1_END_ADDRESS
+  )  
+ port map
+  (  
+    clk_i                =>  clk0,
+    rst_i                =>  rst0,
+    run_traffic_i        =>  p1_tg_run_traffic,
+    manual_clear_error   =>  rst0,
+   -- runtime parameter  
+    start_addr_i         =>  p1_tg_start_addr ,
+    end_addr_i           =>  p1_tg_end_addr   ,
+    cmd_seed_i           =>  p1_tg_cmd_seed   ,
+    data_seed_i          =>  p1_tg_data_seed  ,
+    load_seed_i          =>  p1_tg_load_seed,
+    addr_mode_i          =>  p1_tg_addr_mode,
+                         
+    instr_mode_i         =>  p1_tg_instr_mode ,
+    bl_mode_i            =>  p1_tg_bl_mode    ,
+    data_mode_i          =>  p1_tg_data_mode  ,
+    mode_load_i          =>  p1_tg_mode_load  ,
+    
+    -- fixed pattern inputs interface  
+    fixed_bl_i           =>  p1_tg_fixed_bl,      
+    fixed_instr_i        =>  p1_tg_fixed_instr,   
+    fixed_addr_i         =>  p1_tg_fixed_addr,
+    fixed_data_i         =>  (others => '0'),
+    -- BRAM interface. 
+    bram_cmd_i           =>  (others => '0'),
+    bram_valid_i         =>  '0',
+    bram_rdy_o           =>  open, 
+    
+    --  MCB INTERFACE  
+    mcb_cmd_en_o	 =>  p1_mcb_cmd_en_o_int, 
+    mcb_cmd_instr_o	 =>  p1_mcb_cmd_instr_o_int, 
+    mcb_cmd_bl_o	 =>  p1_mcb_cmd_bl_o_int, 
+    mcb_cmd_addr_o	 =>  p1_mcb_cmd_addr_o_int, 
+    mcb_cmd_full_i	 =>  p1_mcb_cmd_full_i, 
+    
+    mcb_wr_en_o		 =>  p1_mcb_wr_en_o_int, 
+    mcb_wr_mask_o	 =>  p1_mcb_wr_mask_o, 
+    mcb_wr_data_o	 =>  p1_mcb_wr_data_o, 
+    mcb_wr_data_end_o    =>  open, 
+    mcb_wr_full_i	 =>  p1_mcb_wr_full_i, 
+    mcb_wr_fifo_counts	 =>  p1_mcb_wr_fifo_counts, 
+    
+    mcb_rd_en_o		 =>  p1_mcb_rd_en_o, 
+    mcb_rd_data_i	 =>  p1_mcb_rd_data_i, 
+    mcb_rd_empty_i	 =>  p1_mcb_rd_empty_i, 
+    mcb_rd_fifo_counts	 =>  p1_mcb_rd_fifo_counts, 
+
+    -- status feedback   
+    counts_rst           =>  rst0,
+    wr_data_counts       =>  open,
+    rd_data_counts       =>  open,
+    cmp_data             =>  p1_cmp_data,      
+    cmp_data_valid       =>  p1_cmp_data_valid,      
+    cmp_error            =>  p1_cmp_error,        
+    error                =>  p1_error,        
+    error_status         =>  p1_error_status,
+    mem_rd_data          =>  open,
+    dq_error_bytelane_cmp   => open,
+    cumlative_dq_lane_error => open
+  );         
+
+
+
+p2_mcb_cmd_en_o     <= p2_mcb_cmd_en_o_int;
+p2_mcb_cmd_instr_o  <= p2_mcb_cmd_instr_o_int;
+p2_mcb_cmd_bl_o     <= p2_mcb_cmd_bl_o_int;
+p2_mcb_cmd_addr_o   <= p2_mcb_cmd_addr_o_int;
+p2_mcb_wr_en_o     <= p2_mcb_wr_en_o_int;
+
+ init_mem_pattern_ctr_p2 :init_mem_pattern_ctr 
+ generic map
+ 	 (
+    DWIDTH            =>    p2_DWIDTH,
+    FAMILY            =>    FAMILY,
+    BEGIN_ADDRESS     =>    C_p2_BEGIN_ADDRESS,
+    END_ADDRESS       =>    C_p2_END_ADDRESS,
+    CMD_SEED_VALUE    =>    X"56456783",
+    DATA_SEED_VALUE   =>    X"12345678",
+    DATA_MODE         =>    C_p2_DATA_MODE,
+    PORT_MODE         =>    p2_PORT_MODE
+	
+   )
+ port map
+    (
+    clk_i              =>   clk0,
+    rst_i              =>   rst0,
+                       
+    mcb_cmd_en_i       =>   p2_mcb_cmd_en_o_int,
+    mcb_cmd_instr_i    =>   p2_mcb_cmd_instr_o_int,
+    mcb_cmd_bl_i       =>   p2_mcb_cmd_bl_o_int,
+    mcb_wr_en_i        =>   p2_mcb_wr_en_o_int,
+
+    vio_modify_enable  =>	vio_modify_enable,
+    vio_data_mode_value =>  vio_data_mode_value,
+    vio_addr_mode_value =>  vio_addr_mode_value,
+    vio_bl_mode_value	=>  "10",--vio_bl_mode_value,
+    vio_fixed_bl_value	=>  "000000",--vio_fixed_bl_value,  
+                       
+    mcb_init_done_i    =>   calib_done,
+    cmp_error          =>   p2_error,
+    run_traffic_o      =>   p2_tg_run_traffic, 
+    start_addr_o       =>   p2_tg_start_addr,
+    end_addr_o         =>   p2_tg_end_addr   ,
+    cmd_seed_o         =>   p2_tg_cmd_seed   , 
+    data_seed_o        =>   p2_tg_data_seed  ,
+    load_seed_o        =>   p2_tg_load_seed  ,
+    addr_mode_o        =>   p2_tg_addr_mode  ,
+    instr_mode_o       =>   p2_tg_instr_mode ,
+    bl_mode_o          =>   p2_tg_bl_mode    ,
+    data_mode_o        =>   p2_tg_data_mode  ,
+    mode_load_o        =>   p2_tg_mode_load  ,
+    fixed_bl_o         =>   p2_tg_fixed_bl   ,
+    fixed_instr_o      =>   p2_tg_fixed_instr,
+    fixed_addr_o       =>   p2_tg_fixed_addr 
+  );
+
+ m_traffic_gen_p2 :  mcb_traffic_gen 
+ generic map(  
+    MEM_BURST_LEN        => C_MEM_BURST_LEN, 
+    MEM_COL_WIDTH        => C_MEM_NUM_COL_BITS,
+    NUM_DQ_PINS          => C_NUM_DQ_PINS,
+    DQ_ERROR_WIDTH       => DQ_ERROR_WIDTH,
+                         
+    PORT_MODE            => p2_PORT_MODE,    
+    DWIDTH               => p2_DWIDTH,
+    CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,                     
+    FAMILY               => FAMILY,
+    SIMULATION           => "FALSE",
+    DATA_PATTERN         => DATA_PATTERN,  
+    CMD_PATTERN          => "CGEN_ALL",
+    ADDR_WIDTH           => 30,
+    PRBS_SADDR_MASK_POS  => C_p2_PRBS_SADDR_MASK_POS,
+    PRBS_EADDR_MASK_POS  => C_p2_PRBS_EADDR_MASK_POS,
+    PRBS_SADDR           => C_p2_BEGIN_ADDRESS,
+    PRBS_EADDR           => C_p2_END_ADDRESS
+  )  
+ port map
+  (  
+    clk_i                =>  clk0,
+    rst_i                =>  rst0,
+    run_traffic_i        =>  p2_tg_run_traffic,
+    manual_clear_error   =>  rst0,
+   -- runtime parameter  
+    start_addr_i         =>  p2_tg_start_addr ,
+    end_addr_i           =>  p2_tg_end_addr   ,
+    cmd_seed_i           =>  p2_tg_cmd_seed   ,
+    data_seed_i          =>  p2_tg_data_seed  ,
+    load_seed_i          =>  p2_tg_load_seed,
+    addr_mode_i          =>  p2_tg_addr_mode,
+                         
+    instr_mode_i         =>  p2_tg_instr_mode ,
+    bl_mode_i            =>  p2_tg_bl_mode    ,
+    data_mode_i          =>  p2_tg_data_mode  ,
+    mode_load_i          =>  p2_tg_mode_load  ,
+    
+    -- fixed pattern inputs interface  
+    fixed_bl_i           =>  p2_tg_fixed_bl,      
+    fixed_instr_i        =>  p2_tg_fixed_instr,   
+    fixed_addr_i         =>  p2_tg_fixed_addr,
+    fixed_data_i         =>  (others => '0'),
+    -- BRAM interface. 
+    bram_cmd_i           =>  (others => '0'),
+    bram_valid_i         =>  '0',
+    bram_rdy_o           =>  open, 
+    
+    --  MCB INTERFACE  
+    mcb_cmd_en_o	 =>  p2_mcb_cmd_en_o_int, 
+    mcb_cmd_instr_o	 =>  p2_mcb_cmd_instr_o_int, 
+    mcb_cmd_bl_o	 =>  p2_mcb_cmd_bl_o_int, 
+    mcb_cmd_addr_o	 =>  p2_mcb_cmd_addr_o_int, 
+    mcb_cmd_full_i	 =>  p2_mcb_cmd_full_i, 
+    
+    mcb_wr_en_o		 =>  p2_mcb_wr_en_o_int, 
+    mcb_wr_mask_o	 =>  p2_mcb_wr_mask_o, 
+    mcb_wr_data_o	 =>  p2_mcb_wr_data_o, 
+    mcb_wr_data_end_o    =>  open, 
+    mcb_wr_full_i	 =>  p2_mcb_wr_full_i, 
+    mcb_wr_fifo_counts	 =>  p2_mcb_wr_fifo_counts, 
+    
+    mcb_rd_en_o		 =>  p2_mcb_rd_en_o, 
+    mcb_rd_data_i	 =>  p2_mcb_rd_data_i, 
+    mcb_rd_empty_i	 =>  p2_mcb_rd_empty_i, 
+    mcb_rd_fifo_counts	 =>  p2_mcb_rd_fifo_counts, 
+
+    -- status feedback   
+    counts_rst           =>  rst0,
+    wr_data_counts       =>  open,
+    rd_data_counts       =>  open,
+    cmp_data             =>  p2_cmp_data,      
+    cmp_data_valid       =>  p2_cmp_data_valid,      
+    cmp_error            =>  p2_cmp_error,        
+    error                =>  p2_error,        
+    error_status         =>  p2_error_status,
+    mem_rd_data          =>  open,
+    dq_error_bytelane_cmp   => open,
+    cumlative_dq_lane_error => open
+  );         
+
+
+
+p3_mcb_cmd_en_o     <= p3_mcb_cmd_en_o_int;
+p3_mcb_cmd_instr_o  <= p3_mcb_cmd_instr_o_int;
+p3_mcb_cmd_bl_o     <= p3_mcb_cmd_bl_o_int;
+p3_mcb_cmd_addr_o   <= p3_mcb_cmd_addr_o_int;
+p3_mcb_wr_en_o     <= p3_mcb_wr_en_o_int;
+
+ init_mem_pattern_ctr_p3 :init_mem_pattern_ctr 
+ generic map
+ 	 (
+    DWIDTH            =>    p3_DWIDTH,
+    FAMILY            =>    FAMILY,
+    BEGIN_ADDRESS     =>    C_p3_BEGIN_ADDRESS,
+    END_ADDRESS       =>    C_p3_END_ADDRESS,
+    CMD_SEED_VALUE    =>    X"56456783",
+    DATA_SEED_VALUE   =>    X"12345678",
+    DATA_MODE         =>    C_p3_DATA_MODE,
+    PORT_MODE         =>    p3_PORT_MODE
+	
+   )
+ port map
+    (
+    clk_i              =>   clk0,
+    rst_i              =>   rst0,
+                       
+    mcb_cmd_en_i       =>   p3_mcb_cmd_en_o_int,
+    mcb_cmd_instr_i    =>   p3_mcb_cmd_instr_o_int,
+    mcb_cmd_bl_i       =>   p3_mcb_cmd_bl_o_int,
+    mcb_wr_en_i        =>   p3_mcb_wr_en_o_int,
+
+    vio_modify_enable  =>	vio_modify_enable,
+    vio_data_mode_value =>  vio_data_mode_value,
+    vio_addr_mode_value =>  vio_addr_mode_value,
+    vio_bl_mode_value	=>  "10",--vio_bl_mode_value,
+    vio_fixed_bl_value	=>  "000000",--vio_fixed_bl_value,  
+                       
+    mcb_init_done_i    =>   calib_done,
+    cmp_error          =>   p3_error,
+    run_traffic_o      =>   p3_tg_run_traffic, 
+    start_addr_o       =>   p3_tg_start_addr,
+    end_addr_o         =>   p3_tg_end_addr   ,
+    cmd_seed_o         =>   p3_tg_cmd_seed   , 
+    data_seed_o        =>   p3_tg_data_seed  ,
+    load_seed_o        =>   p3_tg_load_seed  ,
+    addr_mode_o        =>   p3_tg_addr_mode  ,
+    instr_mode_o       =>   p3_tg_instr_mode ,
+    bl_mode_o          =>   p3_tg_bl_mode    ,
+    data_mode_o        =>   p3_tg_data_mode  ,
+    mode_load_o        =>   p3_tg_mode_load  ,
+    fixed_bl_o         =>   p3_tg_fixed_bl   ,
+    fixed_instr_o      =>   p3_tg_fixed_instr,
+    fixed_addr_o       =>   p3_tg_fixed_addr 
+  );
+
+ m_traffic_gen_p3 :  mcb_traffic_gen 
+ generic map(  
+    MEM_BURST_LEN        => C_MEM_BURST_LEN, 
+    MEM_COL_WIDTH        => C_MEM_NUM_COL_BITS,
+    NUM_DQ_PINS          => C_NUM_DQ_PINS,
+    DQ_ERROR_WIDTH       => DQ_ERROR_WIDTH,
+                         
+    PORT_MODE            => p3_PORT_MODE,    
+    DWIDTH               => p3_DWIDTH,
+    CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,                     
+    FAMILY               => FAMILY,
+    SIMULATION           => "FALSE",
+    DATA_PATTERN         => DATA_PATTERN,  
+    CMD_PATTERN          => "CGEN_ALL",
+    ADDR_WIDTH           => 30,
+    PRBS_SADDR_MASK_POS  => C_p3_PRBS_SADDR_MASK_POS,
+    PRBS_EADDR_MASK_POS  => C_p3_PRBS_EADDR_MASK_POS,
+    PRBS_SADDR           => C_p3_BEGIN_ADDRESS,
+    PRBS_EADDR           => C_p3_END_ADDRESS
+  )  
+ port map
+  (  
+    clk_i                =>  clk0,
+    rst_i                =>  rst0,
+    run_traffic_i        =>  p3_tg_run_traffic,
+    manual_clear_error   =>  rst0,
+   -- runtime parameter  
+    start_addr_i         =>  p3_tg_start_addr ,
+    end_addr_i           =>  p3_tg_end_addr   ,
+    cmd_seed_i           =>  p3_tg_cmd_seed   ,
+    data_seed_i          =>  p3_tg_data_seed  ,
+    load_seed_i          =>  p3_tg_load_seed,
+    addr_mode_i          =>  p3_tg_addr_mode,
+                         
+    instr_mode_i         =>  p3_tg_instr_mode ,
+    bl_mode_i            =>  p3_tg_bl_mode    ,
+    data_mode_i          =>  p3_tg_data_mode  ,
+    mode_load_i          =>  p3_tg_mode_load  ,
+    
+    -- fixed pattern inputs interface  
+    fixed_bl_i           =>  p3_tg_fixed_bl,      
+    fixed_instr_i        =>  p3_tg_fixed_instr,   
+    fixed_addr_i         =>  p3_tg_fixed_addr,
+    fixed_data_i         =>  (others => '0'),
+    -- BRAM interface. 
+    bram_cmd_i           =>  (others => '0'),
+    bram_valid_i         =>  '0',
+    bram_rdy_o           =>  open, 
+    
+    --  MCB INTERFACE  
+    mcb_cmd_en_o	 =>  p3_mcb_cmd_en_o_int, 
+    mcb_cmd_instr_o	 =>  p3_mcb_cmd_instr_o_int, 
+    mcb_cmd_bl_o	 =>  p3_mcb_cmd_bl_o_int, 
+    mcb_cmd_addr_o	 =>  p3_mcb_cmd_addr_o_int, 
+    mcb_cmd_full_i	 =>  p3_mcb_cmd_full_i, 
+    
+    mcb_wr_en_o		 =>  p3_mcb_wr_en_o_int, 
+    mcb_wr_mask_o	 =>  p3_mcb_wr_mask_o, 
+    mcb_wr_data_o	 =>  p3_mcb_wr_data_o, 
+    mcb_wr_data_end_o    =>  open, 
+    mcb_wr_full_i	 =>  p3_mcb_wr_full_i, 
+    mcb_wr_fifo_counts	 =>  p3_mcb_wr_fifo_counts, 
+    
+    mcb_rd_en_o		 =>  p3_mcb_rd_en_o, 
+    mcb_rd_data_i	 =>  p3_mcb_rd_data_i, 
+    mcb_rd_empty_i	 =>  p3_mcb_rd_empty_i, 
+    mcb_rd_fifo_counts	 =>  p3_mcb_rd_fifo_counts, 
+
+    -- status feedback   
+    counts_rst           =>  rst0,
+    wr_data_counts       =>  open,
+    rd_data_counts       =>  open,
+    cmp_data             =>  p3_cmp_data,      
+    cmp_data_valid       =>  p3_cmp_data_valid,      
+    cmp_error            =>  p3_cmp_error,        
+    error                =>  p3_error,        
+    error_status         =>  p3_error_status,
+    mem_rd_data          =>  open,
+    dq_error_bytelane_cmp   => open,
+    cumlative_dq_lane_error => open
+  );         
+
+
+end architecture;
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_wrapper.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_wrapper.vhd
new file mode 100644
index 0000000..f0d77ea
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/memc3_wrapper.vhd
@@ -0,0 +1,1013 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : 3.92
+--  \   \         Application        : MIG
+--  /   /         Filename           : memc3_wrapper.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:57 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+--Device           : Spartan-6
+--Design Name      : DDR/DDR2/DDR3/LPDDR
+--Purpose          : This module instantiates mcb_raw_wrapper module.
+--Reference        :
+--Revision History :
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity memc3_wrapper is
+generic (
+
+      C_MEMCLK_PERIOD             : integer := 2500;
+      C_P0_MASK_SIZE              : integer := 4;
+      C_P0_DATA_PORT_SIZE         : integer := 32;
+      C_P1_MASK_SIZE              : integer := 4;
+      C_P1_DATA_PORT_SIZE         : integer := 32;
+
+      C_ARB_NUM_TIME_SLOTS        : integer := 12;
+      C_ARB_TIME_SLOT_0           : bit_vector := "000";
+      C_ARB_TIME_SLOT_1           : bit_vector := "000";
+      C_ARB_TIME_SLOT_2           : bit_vector := "000";
+      C_ARB_TIME_SLOT_3           : bit_vector := "000";
+      C_ARB_TIME_SLOT_4           : bit_vector := "000";
+      C_ARB_TIME_SLOT_5           : bit_vector := "000";
+      C_ARB_TIME_SLOT_6           : bit_vector := "000";
+      C_ARB_TIME_SLOT_7           : bit_vector := "000";
+      C_ARB_TIME_SLOT_8           : bit_vector := "000";
+      C_ARB_TIME_SLOT_9           : bit_vector := "000";
+      C_ARB_TIME_SLOT_10          : bit_vector := "000";
+      C_ARB_TIME_SLOT_11          : bit_vector := "000";
+
+      C_MEM_TRAS               : integer := 45000;
+      C_MEM_TRCD               : integer := 12500;
+      C_MEM_TREFI              : integer := 7800000;
+      C_MEM_TRFC               : integer := 127500;
+      C_MEM_TRP                : integer := 12500;
+      C_MEM_TWR                : integer := 15000;
+      C_MEM_TRTP               : integer := 7500;
+      C_MEM_TWTR               : integer := 7500;
+
+      C_MEM_ADDR_ORDER         : string :="ROW_BANK_COLUMN";
+      C_MEM_TYPE               : string :="DDR2";
+      C_MEM_DENSITY            : string :="1Gb";
+      C_NUM_DQ_PINS            : integer := 4;
+      C_MEM_BURST_LEN          : integer := 8;
+      C_MEM_CAS_LATENCY        : integer := 5;
+      C_MEM_ADDR_WIDTH         : integer := 14;
+      C_MEM_BANKADDR_WIDTH     : integer := 3;
+      C_MEM_NUM_COL_BITS       : integer := 11;
+
+      C_MEM_DDR1_2_ODS          : string := "FULL";
+      C_MEM_DDR2_RTT            : string := "50OHMS";
+      C_MEM_DDR2_DIFF_DQS_EN    : string := "YES";
+      C_MEM_DDR2_3_PA_SR        : string := "FULL";
+      C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
+
+      C_MEM_DDR3_CAS_LATENCY    : integer:= 7;
+      C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
+      C_MEM_DDR3_ODS            : string := "DIV6";
+      C_MEM_DDR3_RTT            : string := "DIV2";
+      C_MEM_DDR3_AUTO_SR        : string := "ENABLED";
+      C_MEM_DDR3_DYN_WRT_ODT    : string := "OFF";
+      C_MEM_MOBILE_PA_SR        : string := "FULL";
+      C_MEM_MDDR_ODS            : string := "FULL";
+      C_MC_CALIB_BYPASS         : string := "NO";
+      C_LDQSP_TAP_DELAY_VAL		: integer := 0;
+      C_UDQSP_TAP_DELAY_VAL		: integer := 0;
+      C_LDQSN_TAP_DELAY_VAL		: integer := 0;
+      C_UDQSN_TAP_DELAY_VAL		: integer := 0;
+      C_DQ0_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ1_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ2_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ3_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ4_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ5_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ6_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ7_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ8_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ9_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ10_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ11_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ12_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ13_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ14_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ15_TAP_DELAY_VAL                : integer := 0;  
+
+
+      C_SKIP_IN_TERM_CAL                 : integer := 0;  
+      C_SKIP_DYNAMIC_CAL                 : integer := 0;  
+
+      C_SIMULATION              : string  := "FALSE";  
+      C_MC_CALIBRATION_MODE     : string := "CALIBRATION";
+      C_MC_CALIBRATION_DELAY    : string := "QUARTER";
+      C_CALIB_SOFT_IP           : string := "TRUE"
+
+
+      );
+    port
+    (
+
+      -- high-speed PLL clock interface
+      sysclk_2x       : in std_logic;
+      sysclk_2x_180   : in std_logic;
+      pll_ce_0        : in std_logic;
+      pll_ce_90       : in std_logic;
+      pll_lock        : in std_logic;
+      async_rst       : in std_logic;
+
+      --User Port0 Interface Signals
+
+      p0_cmd_clk                            : in std_logic;
+      p0_cmd_en                             : in std_logic;
+      p0_cmd_instr                          : in std_logic_vector(2 downto 0) ;
+      p0_cmd_bl                             : in std_logic_vector(5 downto 0) ;
+      p0_cmd_byte_addr                      : in std_logic_vector(29 downto 0) ;
+      p0_cmd_empty                          : out std_logic;
+      p0_cmd_full                           : out std_logic;
+
+      -- Data Wr Port signals
+      p0_wr_clk                             : in std_logic;
+      p0_wr_en                              : in std_logic;
+      p0_wr_mask                            : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
+      p0_wr_data                            : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
+      p0_wr_full                            : out std_logic;
+      p0_wr_empty                           : out std_logic;
+      p0_wr_count                           : out std_logic_vector(6 downto 0) ;
+      p0_wr_underrun                        : out std_logic;
+      p0_wr_error                           : out std_logic;
+
+      --Data Rd Port signals
+      p0_rd_clk                             : in std_logic;
+      p0_rd_en                              : in std_logic;
+      p0_rd_data                            : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
+      p0_rd_full                            : out std_logic;
+      p0_rd_empty                           : out std_logic;
+      p0_rd_count                           : out std_logic_vector(6 downto 0) ;
+      p0_rd_overflow                        : out std_logic;
+      p0_rd_error                           : out std_logic;
+
+      --User Port1 Interface Signals
+
+      p1_cmd_clk                            : in std_logic;
+      p1_cmd_en                             : in std_logic;
+      p1_cmd_instr                          : in std_logic_vector(2 downto 0) ;
+      p1_cmd_bl                             : in std_logic_vector(5 downto 0) ;
+      p1_cmd_byte_addr                      : in std_logic_vector(29 downto 0) ;
+      p1_cmd_empty                          : out std_logic;
+      p1_cmd_full                           : out std_logic;
+
+      -- Data Wr Port signals
+      p1_wr_clk                             : in std_logic;
+      p1_wr_en                              : in std_logic;
+      p1_wr_mask                            : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
+      p1_wr_data                            : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
+      p1_wr_full                            : out std_logic;
+      p1_wr_empty                           : out std_logic;
+      p1_wr_count                           : out std_logic_vector(6 downto 0) ;
+      p1_wr_underrun                        : out std_logic;
+      p1_wr_error                           : out std_logic;
+
+      --Data Rd Port signals
+      p1_rd_clk                             : in std_logic;
+      p1_rd_en                              : in std_logic;
+      p1_rd_data                            : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
+      p1_rd_full                            : out std_logic;
+      p1_rd_empty                           : out std_logic;
+      p1_rd_count                           : out std_logic_vector(6 downto 0) ;
+      p1_rd_overflow                        : out std_logic;
+      p1_rd_error                           : out std_logic;
+
+      --User Port2 Interface Signals
+
+      p2_cmd_clk                            : in std_logic;
+      p2_cmd_en                             : in std_logic;
+      p2_cmd_instr                          : in std_logic_vector(2 downto 0) ;
+      p2_cmd_bl                             : in std_logic_vector(5 downto 0) ;
+      p2_cmd_byte_addr                      : in std_logic_vector(29 downto 0) ;
+      p2_cmd_empty                          : out std_logic;
+      p2_cmd_full                           : out std_logic;
+
+      -- Data Wr Port signals
+      p2_wr_clk                             : in std_logic;
+      p2_wr_en                              : in std_logic;
+      p2_wr_mask                            : in std_logic_vector(3 downto 0) ;
+      p2_wr_data                            : in std_logic_vector(31 downto 0) ;
+      p2_wr_full                            : out std_logic;
+      p2_wr_empty                           : out std_logic;
+      p2_wr_count                           : out std_logic_vector(6 downto 0) ;
+      p2_wr_underrun                        : out std_logic;
+      p2_wr_error                           : out std_logic;
+
+      --Data Rd Port signals
+      p2_rd_clk                             : in std_logic;
+      p2_rd_en                              : in std_logic;
+      p2_rd_data                            : out std_logic_vector(31 downto 0) ;
+      p2_rd_full                            : out std_logic;
+      p2_rd_empty                           : out std_logic;
+      p2_rd_count                           : out std_logic_vector(6 downto 0) ;
+      p2_rd_overflow                        : out std_logic;
+      p2_rd_error                           : out std_logic;
+
+      --User Port3 Interface Signals
+
+      p3_cmd_clk                            : in std_logic;
+      p3_cmd_en                             : in std_logic;
+      p3_cmd_instr                          : in std_logic_vector(2 downto 0) ;
+      p3_cmd_bl                             : in std_logic_vector(5 downto 0) ;
+      p3_cmd_byte_addr                      : in std_logic_vector(29 downto 0) ;
+      p3_cmd_empty                          : out std_logic;
+      p3_cmd_full                           : out std_logic;
+
+      -- Data Wr Port signals
+      p3_wr_clk                             : in std_logic;
+      p3_wr_en                              : in std_logic;
+      p3_wr_mask                            : in std_logic_vector(3 downto 0) ;
+      p3_wr_data                            : in std_logic_vector(31 downto 0) ;
+      p3_wr_full                            : out std_logic;
+      p3_wr_empty                           : out std_logic;
+      p3_wr_count                           : out std_logic_vector(6 downto 0) ;
+      p3_wr_underrun                        : out std_logic;
+      p3_wr_error                           : out std_logic;
+
+      --Data Rd Port signals
+      p3_rd_clk                             : in std_logic;
+      p3_rd_en                              : in std_logic;
+      p3_rd_data                            : out std_logic_vector(31 downto 0) ;
+      p3_rd_full                            : out std_logic;
+      p3_rd_empty                           : out std_logic;
+      p3_rd_count                           : out std_logic_vector(6 downto 0) ;
+      p3_rd_overflow                        : out std_logic;
+      p3_rd_error                           : out std_logic;
+
+
+
+      -- memory interface signals
+      mcb3_dram_ck          : out std_logic;
+      mcb3_dram_ck_n        : out std_logic;
+      mcb3_dram_a           : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
+      mcb3_dram_ba          : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
+      mcb3_dram_ras_n       : out std_logic;
+      mcb3_dram_cas_n       : out std_logic;
+      mcb3_dram_we_n        : out std_logic;
+      mcb3_dram_odt         : out std_logic;
+--      mcb3_dram_odt         : out std_logic;
+      mcb3_dram_cke         : out std_logic;
+      mcb3_dram_dq          : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+      mcb3_dram_dqs         : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+
+
+mcb3_dram_udqs   : inout std_logic;
+mcb3_dram_udm    : out std_logic; 
+
+
+ mcb3_dram_udqs_n : inout std_logic;
+
+
+
+mcb3_dram_dm : out std_logic;
+
+      mcb3_rzq                             : inout std_logic;
+      mcb3_zio                              : inout std_logic;
+
+      -- Calibration signals
+      mcb_drp_clk            : in std_logic;
+      calib_done           : out std_logic;
+      selfrefresh_enter    : in std_logic;
+      selfrefresh_mode     : out std_logic
+
+    );
+end entity;
+architecture acch of memc3_wrapper is
+component mcb_raw_wrapper IS
+   GENERIC (
+
+      C_MEMCLK_PERIOD                  : integer;
+      C_PORT_ENABLE                    : std_logic_vector(5 downto 0);
+      C_MEM_ADDR_ORDER                 : string;
+      C_ARB_NUM_TIME_SLOTS             : integer;
+      C_ARB_TIME_SLOT_0                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_1                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_2                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_3                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_4                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_5                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_6                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_7                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_8                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_9                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_10               : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_11               : bit_vector(17 downto 0);
+      C_PORT_CONFIG                    : string;
+
+
+      C_MEM_TRAS                       : integer;
+      C_MEM_TRCD                       : integer;
+      C_MEM_TREFI                      : integer;
+      C_MEM_TRFC                       : integer;
+      C_MEM_TRP                        : integer;
+      C_MEM_TWR                        : integer;
+      C_MEM_TRTP                       : integer;
+      C_MEM_TWTR                       : integer;
+
+      C_NUM_DQ_PINS                    : integer;
+      C_MEM_TYPE                       : string;
+      C_MEM_DENSITY                    : string;
+      C_MEM_BURST_LEN                  : integer;
+
+      C_MEM_CAS_LATENCY                : integer;
+      C_MEM_ADDR_WIDTH                 : integer;
+      C_MEM_BANKADDR_WIDTH             : integer;
+      C_MEM_NUM_COL_BITS               : integer;
+
+      C_MEM_DDR3_CAS_LATENCY           : integer;
+      C_MEM_MOBILE_PA_SR               : string;
+      C_MEM_DDR1_2_ODS                 : string;
+      C_MEM_DDR3_ODS                   : string;
+      C_MEM_DDR2_RTT                   : string;
+      C_MEM_DDR3_RTT                   : string;
+      C_MEM_MDDR_ODS                   : string;
+
+      C_MEM_DDR2_DIFF_DQS_EN           : string;
+      C_MEM_DDR2_3_PA_SR               : string;
+      C_MEM_DDR3_CAS_WR_LATENCY        : integer;
+
+      C_MEM_DDR3_AUTO_SR               : string;
+      C_MEM_DDR2_3_HIGH_TEMP_SR        : string;
+      C_MEM_DDR3_DYN_WRT_ODT           : string;
+
+      C_MC_CALIB_BYPASS                : string;
+      C_MC_CALIBRATION_RA              : bit_vector(15 DOWNTO 0);
+      C_MC_CALIBRATION_BA              : bit_vector(2 DOWNTO 0);
+      C_CALIB_SOFT_IP                  : string;
+      C_MC_CALIBRATION_CA              : bit_vector(11 DOWNTO 0);
+      C_MC_CALIBRATION_CLK_DIV         : integer;
+      C_MC_CALIBRATION_MODE            : string;
+      C_MC_CALIBRATION_DELAY           : string;
+
+     LDQSP_TAP_DELAY_VAL		: integer;
+     UDQSP_TAP_DELAY_VAL		: integer;
+     LDQSN_TAP_DELAY_VAL		: integer;
+     UDQSN_TAP_DELAY_VAL		: integer;
+     DQ0_TAP_DELAY_VAL                  : integer;  
+     DQ1_TAP_DELAY_VAL                  : integer;  
+     DQ2_TAP_DELAY_VAL                  : integer;  
+     DQ3_TAP_DELAY_VAL                  : integer;  
+     DQ4_TAP_DELAY_VAL                  : integer;  
+     DQ5_TAP_DELAY_VAL                  : integer;  
+     DQ6_TAP_DELAY_VAL                  : integer;  
+     DQ7_TAP_DELAY_VAL                  : integer;  
+     DQ8_TAP_DELAY_VAL                  : integer;  
+     DQ9_TAP_DELAY_VAL                  : integer;  
+     DQ10_TAP_DELAY_VAL                  : integer;  
+     DQ11_TAP_DELAY_VAL                  : integer;  
+     DQ12_TAP_DELAY_VAL                  : integer;  
+     DQ13_TAP_DELAY_VAL                  : integer;  
+     DQ14_TAP_DELAY_VAL                  : integer;  
+     DQ15_TAP_DELAY_VAL                  : integer;  
+
+      C_P0_MASK_SIZE                   : integer;
+      C_P0_DATA_PORT_SIZE              : integer;
+      C_P1_MASK_SIZE                   : integer;
+      C_P1_DATA_PORT_SIZE              : integer;
+
+      C_SIMULATION                       : string ;  
+      C_SKIP_IN_TERM_CAL                 : integer; 
+      C_SKIP_DYNAMIC_CAL                 : integer; 
+      C_SKIP_DYN_IN_TERM                 : integer; 
+
+      C_MEM_TZQINIT_MAXCNT              : std_logic_vector(9 downto 0)
+   );
+   PORT (
+      -- HIGH-SPEED PLL clock interface
+
+      sysclk_2x                        : in std_logic;
+      sysclk_2x_180                    : in std_logic;
+      pll_ce_0                         : in std_logic;
+      pll_ce_90                        : in std_logic;
+      pll_lock                         : in std_logic;
+      sys_rst                          : in std_logic;
+
+      p0_arb_en                        : in std_logic;
+      p0_cmd_clk                       : in std_logic;
+      p0_cmd_en                        : in std_logic;
+      p0_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p0_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p0_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p0_cmd_empty                     : out std_logic;
+      p0_cmd_full                      : out std_logic;
+      p0_wr_clk                        : in std_logic;
+      p0_wr_en                         : in std_logic;
+      p0_wr_mask                       : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
+      p0_wr_data                       : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
+      p0_wr_full                       : out std_logic;
+      p0_wr_empty                      : out std_logic;
+      p0_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p0_wr_underrun                   : out std_logic;
+      p0_wr_error                      : out std_logic;
+      p0_rd_clk                        : in std_logic;
+      p0_rd_en                         : in std_logic;
+      p0_rd_data                       : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
+      p0_rd_full                       : out std_logic;
+      p0_rd_empty                      : out std_logic;
+      p0_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p0_rd_overflow                   : out std_logic;
+      p0_rd_error                      : out std_logic;
+      p1_arb_en                        : in std_logic;
+      p1_cmd_clk                       : in std_logic;
+      p1_cmd_en                        : in std_logic;
+      p1_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p1_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p1_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p1_cmd_empty                     : out std_logic;
+      p1_cmd_full                      : out std_logic;
+      p1_wr_clk                        : in std_logic;
+      p1_wr_en                         : in std_logic;
+      p1_wr_mask                       : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
+      p1_wr_data                       : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
+      p1_wr_full                       : out std_logic;
+      p1_wr_empty                      : out std_logic;
+      p1_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p1_wr_underrun                   : out std_logic;
+      p1_wr_error                      : out std_logic;
+      p1_rd_clk                        : in std_logic;
+      p1_rd_en                         : in std_logic;
+      p1_rd_data                       : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
+      p1_rd_full                       : out std_logic;
+      p1_rd_empty                      : out std_logic;
+      p1_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p1_rd_overflow                   : out std_logic;
+      p1_rd_error                      : out std_logic;
+      p2_arb_en                        : in std_logic;
+      p2_cmd_clk                       : in std_logic;
+      p2_cmd_en                        : in std_logic;
+      p2_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p2_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p2_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p2_cmd_empty                     : out std_logic;
+      p2_cmd_full                      : out std_logic;
+      p2_wr_clk                        : in std_logic;
+      p2_wr_en                         : in std_logic;
+      p2_wr_mask                       : in std_logic_vector(3 DOWNTO 0);
+      p2_wr_data                       : in std_logic_vector(31 DOWNTO 0);
+      p2_wr_full                       : out std_logic;
+      p2_wr_empty                      : out std_logic;
+      p2_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p2_wr_underrun                   : out std_logic;
+      p2_wr_error                      : out std_logic;
+      p2_rd_clk                        : in std_logic;
+      p2_rd_en                         : in std_logic;
+      p2_rd_data                       : out std_logic_vector(31 DOWNTO 0);
+      p2_rd_full                       : out std_logic;
+      p2_rd_empty                      : out std_logic;
+      p2_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p2_rd_overflow                   : out std_logic;
+      p2_rd_error                      : out std_logic;
+      p3_arb_en                        : in std_logic;
+      p3_cmd_clk                       : in std_logic;
+      p3_cmd_en                        : in std_logic;
+      p3_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p3_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p3_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p3_cmd_empty                     : out std_logic;
+      p3_cmd_full                      : out std_logic;
+      p3_wr_clk                        : in std_logic;
+      p3_wr_en                         : in std_logic;
+      p3_wr_mask                       : in std_logic_vector(3 DOWNTO 0);
+      p3_wr_data                       : in std_logic_vector(31 DOWNTO 0);
+      p3_wr_full                       : out std_logic;
+      p3_wr_empty                      : out std_logic;
+      p3_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p3_wr_underrun                   : out std_logic;
+      p3_wr_error                      : out std_logic;
+      p3_rd_clk                        : in std_logic;
+      p3_rd_en                         : in std_logic;
+      p3_rd_data                       : out std_logic_vector(31 DOWNTO 0);
+      p3_rd_full                       : out std_logic;
+      p3_rd_empty                      : out std_logic;
+      p3_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p3_rd_overflow                   : out std_logic;
+      p3_rd_error                      : out std_logic;
+      p4_arb_en                        : in std_logic;
+      p4_cmd_clk                       : in std_logic;
+      p4_cmd_en                        : in std_logic;
+      p4_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p4_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p4_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p4_cmd_empty                     : out std_logic;
+      p4_cmd_full                      : out std_logic;
+      p4_wr_clk                        : in std_logic;
+      p4_wr_en                         : in std_logic;
+      p4_wr_mask                       : in std_logic_vector(3 DOWNTO 0);
+      p4_wr_data                       : in std_logic_vector(31 DOWNTO 0);
+      p4_wr_full                       : out std_logic;
+      p4_wr_empty                      : out std_logic;
+      p4_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p4_wr_underrun                   : out std_logic;
+      p4_wr_error                      : out std_logic;
+      p4_rd_clk                        : in std_logic;
+      p4_rd_en                         : in std_logic;
+      p4_rd_data                       : out std_logic_vector(31 DOWNTO 0);
+      p4_rd_full                       : out std_logic;
+      p4_rd_empty                      : out std_logic;
+      p4_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p4_rd_overflow                   : out std_logic;
+      p4_rd_error                      : out std_logic;
+      p5_arb_en                        : in std_logic;
+      p5_cmd_clk                       : in std_logic;
+      p5_cmd_en                        : in std_logic;
+      p5_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p5_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p5_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p5_cmd_empty                     : out std_logic;
+      p5_cmd_full                      : out std_logic;
+      p5_wr_clk                        : in std_logic;
+      p5_wr_en                         : in std_logic;
+      p5_wr_mask                       : in std_logic_vector(3 DOWNTO 0);
+      p5_wr_data                       : in std_logic_vector(31 DOWNTO 0);
+      p5_wr_full                       : out std_logic;
+      p5_wr_empty                      : out std_logic;
+      p5_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p5_wr_underrun                   : out std_logic;
+      p5_wr_error                      : out std_logic;
+      p5_rd_clk                        : in std_logic;
+      p5_rd_en                         : in std_logic;
+      p5_rd_data                       : out std_logic_vector(31 DOWNTO 0);
+      p5_rd_full                       : out std_logic;
+      p5_rd_empty                      : out std_logic;
+      p5_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p5_rd_overflow                   : out std_logic;
+      p5_rd_error                      : out std_logic;
+
+      mcbx_dram_addr                   : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
+      mcbx_dram_ba                     : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
+      mcbx_dram_ras_n                  : out std_logic;
+      mcbx_dram_cas_n                  : out std_logic;
+      mcbx_dram_we_n                   : out std_logic;
+      mcbx_dram_cke                    : out std_logic;
+      mcbx_dram_clk                    : out std_logic;
+      mcbx_dram_clk_n                  : out std_logic;
+      mcbx_dram_dq                     : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
+      mcbx_dram_dqs                    : inout std_logic;
+      mcbx_dram_dqs_n                  : inout std_logic;
+      mcbx_dram_udqs                   : inout std_logic;
+      mcbx_dram_udqs_n                 : inout std_logic;
+      mcbx_dram_udm                    : out std_logic;
+      mcbx_dram_ldm                    : out std_logic;
+      mcbx_dram_odt                    : out std_logic;
+      mcbx_dram_ddr3_rst               : out std_logic;
+      calib_recal                      : in std_logic;
+      rzq                              : inout std_logic;
+      zio                              : inout std_logic;
+      ui_read                          : in std_logic;
+      ui_add                           : in std_logic;
+      ui_cs                            : in std_logic;
+      ui_clk                           : in std_logic;
+      ui_sdi                           : in std_logic;
+      ui_addr                          : in std_logic_vector(4 DOWNTO 0);
+      ui_broadcast                     : in std_logic;
+      ui_drp_update                    : in std_logic;
+      ui_done_cal                      : in std_logic;
+      ui_cmd                           : in std_logic;
+      ui_cmd_in                        : in std_logic;
+      ui_cmd_en                        : in std_logic;
+      ui_dqcount                       : in std_logic_vector(3 DOWNTO 0);
+      ui_dq_lower_dec                  : in std_logic;
+      ui_dq_lower_inc                  : in std_logic;
+      ui_dq_upper_dec                  : in std_logic;
+      ui_dq_upper_inc                  : in std_logic;
+      ui_udqs_inc                      : in std_logic;
+      ui_udqs_dec                      : in std_logic;
+      ui_ldqs_inc                      : in std_logic;
+      ui_ldqs_dec                      : in std_logic;
+      uo_data                          : out std_logic_vector(7 DOWNTO 0);
+      uo_data_valid                    : out std_logic;
+      uo_done_cal                      : out std_logic;
+      uo_cmd_ready_in                  : out std_logic;
+      uo_refrsh_flag                   : out std_logic;
+      uo_cal_start                     : out std_logic;
+      uo_sdo                           : out std_logic;
+      status                           : out std_logic_vector(31 DOWNTO 0);
+      selfrefresh_enter                : in std_logic;
+      selfrefresh_mode                 : out std_logic
+   );
+end component;
+
+signal uo_data : std_logic_vector(7 downto 0);
+
+ constant C_PORT_ENABLE              : std_logic_vector(5 downto 0) := "001111";
+
+constant C_PORT_CONFIG             : string :=  "B32_B32_B32_B32";
+
+
+constant ARB_TIME_SLOT_0    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_0(11 downto 9) & C_ARB_TIME_SLOT_0(8 downto 6) & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
+constant ARB_TIME_SLOT_1    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_1(11 downto 9) & C_ARB_TIME_SLOT_1(8 downto 6) & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
+constant ARB_TIME_SLOT_2    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_2(11 downto 9) & C_ARB_TIME_SLOT_2(8 downto 6) & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
+constant ARB_TIME_SLOT_3    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_3(11 downto 9) & C_ARB_TIME_SLOT_3(8 downto 6) & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
+constant ARB_TIME_SLOT_4    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_4(11 downto 9) & C_ARB_TIME_SLOT_4(8 downto 6) & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
+constant ARB_TIME_SLOT_5    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_5(11 downto 9) & C_ARB_TIME_SLOT_5(8 downto 6) & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
+constant ARB_TIME_SLOT_6    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_6(11 downto 9) & C_ARB_TIME_SLOT_6(8 downto 6) & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
+constant ARB_TIME_SLOT_7    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_7(11 downto 9) & C_ARB_TIME_SLOT_7(8 downto 6) & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
+constant ARB_TIME_SLOT_8    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_8(11 downto 9) & C_ARB_TIME_SLOT_8(8 downto 6) & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
+constant ARB_TIME_SLOT_9    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_9(11 downto 9) & C_ARB_TIME_SLOT_9(8 downto 6) & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
+constant ARB_TIME_SLOT_10   : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_10(11 downto 9) & C_ARB_TIME_SLOT_10(8 downto 6) & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
+constant ARB_TIME_SLOT_11   : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_11(11 downto 9) & C_ARB_TIME_SLOT_11(8 downto 6) & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
+
+
+constant C_MC_CALIBRATION_CLK_DIV  : integer  := 1;
+constant C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000" + "0000010000";   -- 16 cycles are added to avoid trfc violations
+constant C_SKIP_DYN_IN_TERM : integer := 1;	  
+
+constant C_MC_CALIBRATION_RA    : bit_vector(15 downto 0) := X"0000"; 
+constant C_MC_CALIBRATION_BA    : bit_vector(2 downto 0) := o"0"; 
+constant C_MC_CALIBRATION_CA    : bit_vector(11 downto 0) := X"000"; 
+
+signal status          : std_logic_vector(31 downto 0);
+signal uo_data_valid   : std_logic;
+signal uo_cmd_ready_in : std_logic;
+signal uo_refrsh_flag  : std_logic;
+signal uo_cal_start    : std_logic;
+signal uo_sdo          : std_logic;
+
+
+
+
+
+
+
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of acch : architecture IS
+  "mig_v3_92_ddr2_s6, Coregen 14.2";
+
+attribute CORE_GENERATION_INFO : string;
+attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE,  NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Four 32-bit bi-directional ports, MEM_ADDR_ORDER=BANK_ROW_COLUMN, PORT_ENABLE=Port0_Port1_Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
+
+begin
+
+
+memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
+generic map
+ (
+   C_MEMCLK_PERIOD            => C_MEMCLK_PERIOD,
+   C_P0_MASK_SIZE             => C_P0_MASK_SIZE,
+   C_P0_DATA_PORT_SIZE        => C_P0_DATA_PORT_SIZE,
+   C_P1_MASK_SIZE             => C_P1_MASK_SIZE,
+   C_P1_DATA_PORT_SIZE        => C_P1_DATA_PORT_SIZE,
+
+   C_ARB_NUM_TIME_SLOTS       => C_ARB_NUM_TIME_SLOTS,
+   C_ARB_TIME_SLOT_0          => ARB_TIME_SLOT_0,
+   C_ARB_TIME_SLOT_1          => ARB_TIME_SLOT_1,
+   C_ARB_TIME_SLOT_2          => ARB_TIME_SLOT_2,
+   C_ARB_TIME_SLOT_3          => ARB_TIME_SLOT_3,
+   C_ARB_TIME_SLOT_4          => ARB_TIME_SLOT_4,
+   C_ARB_TIME_SLOT_5          => ARB_TIME_SLOT_5,
+   C_ARB_TIME_SLOT_6          => ARB_TIME_SLOT_6,
+   C_ARB_TIME_SLOT_7          => ARB_TIME_SLOT_7,
+   C_ARB_TIME_SLOT_8          => ARB_TIME_SLOT_8,
+   C_ARB_TIME_SLOT_9          => ARB_TIME_SLOT_9,
+   C_ARB_TIME_SLOT_10         => ARB_TIME_SLOT_10,
+   C_ARB_TIME_SLOT_11         => ARB_TIME_SLOT_11,
+
+   C_PORT_CONFIG              => C_PORT_CONFIG,
+   C_PORT_ENABLE              => C_PORT_ENABLE,
+
+   C_MEM_TRAS                 => C_MEM_TRAS,
+   C_MEM_TRCD                 => C_MEM_TRCD,
+   C_MEM_TREFI                => C_MEM_TREFI,
+   C_MEM_TRFC                 => C_MEM_TRFC,
+   C_MEM_TRP                  => C_MEM_TRP,
+   C_MEM_TWR                  => C_MEM_TWR,
+   C_MEM_TRTP                 => C_MEM_TRTP,
+   C_MEM_TWTR                 => C_MEM_TWTR,
+
+   C_MEM_ADDR_ORDER           => C_MEM_ADDR_ORDER,
+   C_NUM_DQ_PINS              => C_NUM_DQ_PINS,
+   C_MEM_TYPE                 => C_MEM_TYPE,
+   C_MEM_DENSITY              => C_MEM_DENSITY,
+   C_MEM_BURST_LEN            => C_MEM_BURST_LEN,
+   C_MEM_CAS_LATENCY          => C_MEM_CAS_LATENCY,
+   C_MEM_ADDR_WIDTH           => C_MEM_ADDR_WIDTH,
+   C_MEM_BANKADDR_WIDTH       => C_MEM_BANKADDR_WIDTH,
+   C_MEM_NUM_COL_BITS         => C_MEM_NUM_COL_BITS,
+
+   C_MEM_DDR1_2_ODS           => C_MEM_DDR1_2_ODS,
+   C_MEM_DDR2_RTT             => C_MEM_DDR2_RTT,
+   C_MEM_DDR2_DIFF_DQS_EN     => C_MEM_DDR2_DIFF_DQS_EN,
+   C_MEM_DDR2_3_PA_SR         => C_MEM_DDR2_3_PA_SR,
+   C_MEM_DDR2_3_HIGH_TEMP_SR  => C_MEM_DDR2_3_HIGH_TEMP_SR,
+
+   C_MEM_DDR3_CAS_LATENCY     => C_MEM_DDR3_CAS_LATENCY,
+   C_MEM_DDR3_ODS             => C_MEM_DDR3_ODS,
+   C_MEM_DDR3_RTT             => C_MEM_DDR3_RTT,
+   C_MEM_DDR3_CAS_WR_LATENCY  => C_MEM_DDR3_CAS_WR_LATENCY,
+   C_MEM_DDR3_AUTO_SR         => C_MEM_DDR3_AUTO_SR,
+   C_MEM_DDR3_DYN_WRT_ODT     => C_MEM_DDR3_DYN_WRT_ODT,
+   C_MEM_MOBILE_PA_SR         => C_MEM_MOBILE_PA_SR,
+   C_MEM_MDDR_ODS             => C_MEM_MDDR_ODS,
+   C_MC_CALIBRATION_CLK_DIV   => C_MC_CALIBRATION_CLK_DIV,
+   C_MC_CALIBRATION_MODE      => C_MC_CALIBRATION_MODE,
+   C_MC_CALIBRATION_DELAY     => C_MC_CALIBRATION_DELAY,
+
+   C_MC_CALIB_BYPASS          => C_MC_CALIB_BYPASS,
+   C_MC_CALIBRATION_RA        => C_MC_CALIBRATION_RA,
+   C_MC_CALIBRATION_BA        => C_MC_CALIBRATION_BA,
+   C_MC_CALIBRATION_CA        => C_MC_CALIBRATION_CA,
+   C_CALIB_SOFT_IP            => C_CALIB_SOFT_IP,
+
+   C_SIMULATION               => C_SIMULATION,
+   C_SKIP_IN_TERM_CAL         => C_SKIP_IN_TERM_CAL,
+   C_SKIP_DYNAMIC_CAL         => C_SKIP_DYNAMIC_CAL,
+   C_SKIP_DYN_IN_TERM         => C_SKIP_DYN_IN_TERM, 
+   C_MEM_TZQINIT_MAXCNT       => C_MEM_TZQINIT_MAXCNT,
+
+   LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,  
+   UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,  
+   LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,  
+   UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,  
+   DQ0_TAP_DELAY_VAL   => C_DQ0_TAP_DELAY_VAL, 
+   DQ1_TAP_DELAY_VAL  => C_DQ1_TAP_DELAY_VAL,  
+   DQ2_TAP_DELAY_VAL  => C_DQ2_TAP_DELAY_VAL,  
+   DQ3_TAP_DELAY_VAL  => C_DQ3_TAP_DELAY_VAL,  
+   DQ4_TAP_DELAY_VAL  => C_DQ4_TAP_DELAY_VAL,  
+   DQ5_TAP_DELAY_VAL  => C_DQ5_TAP_DELAY_VAL,  
+   DQ6_TAP_DELAY_VAL  => C_DQ6_TAP_DELAY_VAL,  
+   DQ7_TAP_DELAY_VAL  => C_DQ7_TAP_DELAY_VAL,  
+   DQ8_TAP_DELAY_VAL  => C_DQ8_TAP_DELAY_VAL,  
+   DQ9_TAP_DELAY_VAL  => C_DQ9_TAP_DELAY_VAL,  
+   DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL, 
+   DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL, 
+   DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL, 
+   DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL, 
+   DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL, 
+   DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
+   )
+
+port map
+(
+   sys_rst                    =>  async_rst,
+   sysclk_2x                  =>  sysclk_2x,
+   sysclk_2x_180              =>  sysclk_2x_180,
+   pll_ce_0                   =>  pll_ce_0,
+   pll_ce_90                  =>  pll_ce_90,
+   pll_lock                   =>  pll_lock,
+   mcbx_dram_addr             =>  mcb3_dram_a,
+   mcbx_dram_ba               =>  mcb3_dram_ba,
+   mcbx_dram_ras_n            =>  mcb3_dram_ras_n,
+   mcbx_dram_cas_n            =>  mcb3_dram_cas_n,
+   mcbx_dram_we_n             =>  mcb3_dram_we_n,
+   mcbx_dram_cke              =>  mcb3_dram_cke,
+   mcbx_dram_clk              =>  mcb3_dram_ck,
+   mcbx_dram_clk_n            =>  mcb3_dram_ck_n,
+   mcbx_dram_dq               =>  mcb3_dram_dq,
+   mcbx_dram_odt              =>  mcb3_dram_odt,
+   mcbx_dram_ldm              =>  mcb3_dram_dm,
+   mcbx_dram_udm              =>  mcb3_dram_udm,
+   mcbx_dram_dqs              =>  mcb3_dram_dqs,
+   mcbx_dram_dqs_n            =>  mcb3_dram_dqs_n,
+   mcbx_dram_udqs             =>  mcb3_dram_udqs,
+   mcbx_dram_udqs_n           =>  mcb3_dram_udqs_n,
+   mcbx_dram_ddr3_rst         =>  open,
+   calib_recal                =>  '0',
+   rzq                        =>  mcb3_rzq,
+   zio                        =>  mcb3_zio,
+   ui_read                    =>  '0',
+   ui_add                     =>  '0',
+   ui_cs                      =>  '0',
+   ui_clk                     =>  mcb_drp_clk,
+   ui_sdi                     =>  '0',
+   ui_addr                    =>  (others => '0'),
+   ui_broadcast               =>  '0',
+   ui_drp_update              =>  '0',
+   ui_done_cal                =>  '1',
+   ui_cmd                     =>  '0',
+   ui_cmd_in                  =>  '0',
+   ui_cmd_en                  =>  '0',
+   ui_dqcount                 =>  (others => '0'),
+   ui_dq_lower_dec            =>  '0',
+   ui_dq_lower_inc            =>  '0',
+   ui_dq_upper_dec            =>  '0',
+   ui_dq_upper_inc            =>  '0',
+   ui_udqs_inc                =>  '0',
+   ui_udqs_dec                =>  '0',
+   ui_ldqs_inc                =>  '0',
+   ui_ldqs_dec                =>  '0',
+   uo_data                    =>  uo_data,
+   uo_data_valid              =>  uo_data_valid,
+   uo_done_cal                =>  calib_done,
+   uo_cmd_ready_in            =>  uo_cmd_ready_in,
+   uo_refrsh_flag             =>  uo_refrsh_flag,
+   uo_cal_start               =>  uo_cal_start,
+   uo_sdo                     =>  uo_sdo,
+   status                     =>  status,
+   selfrefresh_enter          =>  '0',
+   selfrefresh_mode           =>  selfrefresh_mode,
+
+
+      p0_arb_en                            =>  '1',
+   p0_cmd_clk                           =>  p0_cmd_clk,
+   p0_cmd_en                            =>  p0_cmd_en,
+   p0_cmd_instr                         =>  p0_cmd_instr,
+   p0_cmd_bl                            =>  p0_cmd_bl,
+   p0_cmd_byte_addr                     =>  p0_cmd_byte_addr,
+   p0_cmd_empty                         =>  p0_cmd_empty,
+   p0_cmd_full                          =>  p0_cmd_full,
+   p0_wr_clk                            =>  p0_wr_clk,
+   p0_wr_en                             =>  p0_wr_en,
+   p0_wr_mask                           =>  p0_wr_mask,
+   p0_wr_data                           =>  p0_wr_data,
+   p0_wr_full                           =>  p0_wr_full,
+   p0_wr_empty                          =>  p0_wr_empty,
+   p0_wr_count                          =>  p0_wr_count,
+   p0_wr_underrun                       =>  p0_wr_underrun,
+   p0_wr_error                          =>  p0_wr_error,
+   p0_rd_clk                            =>  p0_rd_clk,
+   p0_rd_en                             =>  p0_rd_en,
+   p0_rd_data                           =>  p0_rd_data,
+   p0_rd_full                           =>  p0_rd_full,
+   p0_rd_empty                          =>  p0_rd_empty,
+   p0_rd_count                          =>  p0_rd_count,
+   p0_rd_overflow                       =>  p0_rd_overflow,
+   p0_rd_error                          =>  p0_rd_error,
+   p1_arb_en                            =>  '1',
+   p1_cmd_clk                           =>  p1_cmd_clk,
+   p1_cmd_en                            =>  p1_cmd_en,
+   p1_cmd_instr                         =>  p1_cmd_instr,
+   p1_cmd_bl                            =>  p1_cmd_bl,
+   p1_cmd_byte_addr                     =>  p1_cmd_byte_addr,
+   p1_cmd_empty                         =>  p1_cmd_empty,
+   p1_cmd_full                          =>  p1_cmd_full,
+   p1_wr_clk                            =>  p1_wr_clk,
+   p1_wr_en                             =>  p1_wr_en,
+   p1_wr_mask                           =>  p1_wr_mask,
+   p1_wr_data                           =>  p1_wr_data,
+   p1_wr_full                           =>  p1_wr_full,
+   p1_wr_empty                          =>  p1_wr_empty,
+   p1_wr_count                          =>  p1_wr_count,
+   p1_wr_underrun                       =>  p1_wr_underrun,
+   p1_wr_error                          =>  p1_wr_error,
+   p1_rd_clk                            =>  p1_rd_clk,
+   p1_rd_en                             =>  p1_rd_en,
+   p1_rd_data                           =>  p1_rd_data,
+   p1_rd_full                           =>  p1_rd_full,
+   p1_rd_empty                          =>  p1_rd_empty,
+   p1_rd_count                          =>  p1_rd_count,
+   p1_rd_overflow                       =>  p1_rd_overflow,
+   p1_rd_error                          =>  p1_rd_error,
+   p2_arb_en                            =>  '1',
+   p2_cmd_clk                           =>  p2_cmd_clk,
+   p2_cmd_en                            =>  p2_cmd_en,
+   p2_cmd_instr                         =>  p2_cmd_instr,
+   p2_cmd_bl                            =>  p2_cmd_bl,
+   p2_cmd_byte_addr                     =>  p2_cmd_byte_addr,
+   p2_cmd_empty                         =>  p2_cmd_empty,
+   p2_cmd_full                          =>  p2_cmd_full,
+   p2_wr_clk                            =>  p2_wr_clk,
+   p2_wr_en                             =>  p2_wr_en,
+   p2_wr_mask                           =>  p2_wr_mask,
+   p2_wr_data                           =>  p2_wr_data,
+   p2_wr_full                           =>  p2_wr_full,
+   p2_wr_empty                          =>  p2_wr_empty,
+   p2_wr_count                          =>  p2_wr_count,
+   p2_wr_underrun                       =>  p2_wr_underrun,
+   p2_wr_error                          =>  p2_wr_error,
+   p2_rd_clk                            =>  p2_rd_clk,
+   p2_rd_en                             =>  p2_rd_en,
+   p2_rd_data                           =>  p2_rd_data,
+   p2_rd_full                           =>  p2_rd_full,
+   p2_rd_empty                          =>  p2_rd_empty,
+   p2_rd_count                          =>  p2_rd_count,
+   p2_rd_overflow                       =>  p2_rd_overflow,
+   p2_rd_error                          =>  p2_rd_error,
+   p3_arb_en                            =>  '1',
+   p3_cmd_clk                           =>  p3_cmd_clk,
+   p3_cmd_en                            =>  p3_cmd_en,
+   p3_cmd_instr                         =>  p3_cmd_instr,
+   p3_cmd_bl                            =>  p3_cmd_bl,
+   p3_cmd_byte_addr                     =>  p3_cmd_byte_addr,
+   p3_cmd_empty                         =>  p3_cmd_empty,
+   p3_cmd_full                          =>  p3_cmd_full,
+   p3_wr_clk                            =>  p3_wr_clk,
+   p3_wr_en                             =>  p3_wr_en,
+   p3_wr_mask                           =>  p3_wr_mask,
+   p3_wr_data                           =>  p3_wr_data,
+   p3_wr_full                           =>  p3_wr_full,
+   p3_wr_empty                          =>  p3_wr_empty,
+   p3_wr_count                          =>  p3_wr_count,
+   p3_wr_underrun                       =>  p3_wr_underrun,
+   p3_wr_error                          =>  p3_wr_error,
+   p3_rd_clk                            =>  p3_rd_clk,
+   p3_rd_en                             =>  p3_rd_en,
+   p3_rd_data                           =>  p3_rd_data,
+   p3_rd_full                           =>  p3_rd_full,
+   p3_rd_empty                          =>  p3_rd_empty,
+   p3_rd_count                          =>  p3_rd_count,
+   p3_rd_overflow                       =>  p3_rd_overflow,
+   p3_rd_error                          =>  p3_rd_error,
+   p4_arb_en                            =>  '0',
+   p4_cmd_clk                           =>  '0',
+   p4_cmd_en                            =>  '0',
+   p4_cmd_instr                         =>  (others => '0'),
+   p4_cmd_bl                            =>  (others => '0'),
+   p4_cmd_byte_addr                     =>  (others => '0'),
+   p4_cmd_empty                         =>  open,
+   p4_cmd_full                          =>  open,
+   p4_rd_clk                            =>  '0',
+   p4_rd_en                             =>  '0',
+   p4_rd_data                           =>  open,
+   p4_rd_full                           =>  open,
+   p4_rd_empty                          =>  open,
+   p4_rd_count                          =>  open,
+   p4_rd_overflow                       =>  open,
+   p4_rd_error                          =>  open,
+   p4_wr_clk                            =>  '0',
+   p4_wr_en                             =>  '0',
+   p4_wr_mask                           =>  (others => '0'),
+   p4_wr_data                           =>  (others => '0'),
+   p4_wr_full                           =>  open,
+   p4_wr_empty                          =>  open,
+   p4_wr_count                          =>  open,
+   p4_wr_underrun                       =>  open,
+   p4_wr_error                          =>  open,
+   p5_arb_en                            =>  '0',
+   p5_cmd_clk                           =>  '0',
+   p5_cmd_en                            =>  '0',
+   p5_cmd_instr                         =>  (others => '0'),
+   p5_cmd_bl                            =>  (others => '0'),
+   p5_cmd_byte_addr                     =>  (others => '0'),
+   p5_cmd_empty                         =>  open,
+   p5_cmd_full                          =>  open,
+   p5_rd_clk                            =>  '0',
+   p5_rd_en                             =>  '0',
+   p5_rd_data                           =>  open,
+   p5_rd_full                           =>  open,
+   p5_rd_empty                          =>  open,
+   p5_rd_count                          =>  open,
+   p5_rd_overflow                       =>  open,
+   p5_rd_error                          =>  open,
+   p5_wr_clk                            =>  '0',
+   p5_wr_en                             =>  '0',
+   p5_wr_mask                           =>  (others => '0'),
+   p5_wr_data                           =>  (others => '0'),
+   p5_wr_full                           =>  open,
+   p5_wr_empty                          =>  open,
+   p5_wr_count                          =>  open,
+   p5_wr_underrun                       =>  open,
+   p5_wr_error                          =>  open
+);
+
+
+
+end architecture;
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/afifo.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/afifo.vhd
new file mode 100755
index 0000000..5924354
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/afifo.vhd
@@ -0,0 +1,280 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.	   
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: afifo.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:34 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:  A generic synchronous fifo.
+-- Reference:
+-- Revision History: 2009/01/09  corrected signal "buf_avail" and "almost_full" equation.
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   use ieee.numeric_std.all;
+
+
+
+ENTITY afifo IS
+   GENERIC (
+      TCQ         : TIME   := 100 ps;
+      DSIZE       : INTEGER := 32;
+      FIFO_DEPTH  : INTEGER := 16;
+      ASIZE       : INTEGER := 4;
+      SYNC        : INTEGER := 1
+   );
+   PORT (
+      wr_clk      : IN STD_LOGIC;
+      rst         : IN STD_LOGIC;
+      wr_en       : IN STD_LOGIC;
+      wr_data     : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      rd_en       : IN STD_LOGIC;
+      rd_clk      : IN STD_LOGIC;
+      rd_data     : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      full        : OUT STD_LOGIC;
+      empty       : OUT STD_LOGIC;
+      almost_full : OUT STD_LOGIC
+   );
+END afifo;
+
+ARCHITECTURE trans OF afifo IS
+   TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+
+   
+   
+   SIGNAL mem                     : mem_array;
+   
+   SIGNAL rd_gray_nxt             : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL rd_gray                 : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL rd_capture_ptr          : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL rd_capture_gray_ptr     : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wr_gray                 : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wr_gray_nxt             : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   
+   SIGNAL wr_capture_ptr          : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wr_capture_gray_ptr     : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL buf_avail               : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL buf_filled              : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wr_addr                 : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
+   SIGNAL rd_addr                 : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
+   
+   SIGNAL wr_ptr                  : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL rd_ptr                  : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL i                       : INTEGER;
+   SIGNAL j                       : INTEGER;
+   SIGNAL k                       : INTEGER;
+   
+   SIGNAL rd_strobe               : STD_LOGIC;
+   
+   SIGNAL n                       : INTEGER;
+   SIGNAL rd_ptr_tmp              : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   
+   SIGNAL wbin                    : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wgraynext               : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wbinnext                : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL ZERO                    : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL ONE                     : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL full_xhdl1              : STD_LOGIC;
+   SIGNAL almost_full_int             : STD_LOGIC;
+   SIGNAL empty_xhdl0             : STD_LOGIC;
+BEGIN
+   -- Drive referenced outputs
+   ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
+   ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
+
+   full <= full_xhdl1;
+   empty <= empty_xhdl0;
+   xhdl3 : IF (SYNC = 1) GENERATE
+      PROCESS (rd_ptr)
+      BEGIN
+         rd_capture_ptr <= rd_ptr;
+      END PROCESS;      
+   END GENERATE;
+
+
+
+
+   xhdl4 : IF (SYNC = 1) GENERATE
+      PROCESS (wr_ptr)
+      BEGIN
+         wr_capture_ptr <= wr_ptr;
+      END PROCESS;      
+   END GENERATE;
+
+   wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
+   rd_data <= mem(conv_integer(rd_addr));
+
+
+
+   PROCESS (wr_clk)
+   BEGIN
+      IF (wr_clk'EVENT AND wr_clk = '1') THEN
+         IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
+            mem(to_integer(unsigned(wr_addr))) <= wr_data;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
+   rd_strobe <= rd_en AND NOT(empty_xhdl0);
+   PROCESS (rd_ptr)
+   BEGIN
+      rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
+      FOR n IN 0 TO  ASIZE - 1 LOOP
+         rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
+      END LOOP;
+   END PROCESS;
+   
+   PROCESS (rd_clk)
+   BEGIN
+      IF (rd_clk'EVENT AND rd_clk = '1') THEN
+         IF (rst = '1') THEN
+            rd_ptr <= (others=> '0');
+            rd_gray <= (others=> '0');
+         ELSE
+            IF (rd_strobe = '1') THEN
+               rd_ptr <= rd_ptr + 1;
+            END IF;
+            rd_ptr_tmp <= rd_ptr;
+            rd_gray <= rd_gray_nxt;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   buf_filled <= wr_capture_ptr - rd_ptr;
+   PROCESS (rd_clk)
+   BEGIN
+      IF (rd_clk'EVENT AND rd_clk = '1') THEN
+         IF (rst = '1') THEN
+            empty_xhdl0 <= '1';
+         ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
+            empty_xhdl0 <= '1';
+         ELSE
+            empty_xhdl0 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (rd_clk)
+   BEGIN
+      IF (rd_clk'EVENT AND rd_clk = '1') THEN
+         IF (rst = '1') THEN
+            wr_ptr <= (others => '0');
+            wr_gray <= (others => '0');
+         ELSE
+            IF (wr_en = '1') THEN
+               
+               wr_ptr <= wr_ptr + 1;
+            END IF;
+            wr_gray <= wr_gray_nxt;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (wr_ptr)
+   BEGIN
+      wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
+      FOR n IN 0 TO  ASIZE - 1 LOOP
+         wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
+      END LOOP;
+   END PROCESS;
+   
+   buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
+  
+   
+   PROCESS (wr_clk)
+   BEGIN
+      IF (wr_clk'EVENT AND wr_clk = '1') THEN
+         IF (rst = '1') THEN
+            full_xhdl1 <= '0';
+         ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
+            full_xhdl1 <= '1';
+         ELSE
+            full_xhdl1 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   almost_full <= almost_full_int;
+   PROCESS (wr_clk)
+   BEGIN
+      IF (wr_clk'EVENT AND wr_clk = '1') THEN
+         IF (rst = '1') THEN
+            almost_full_int <= '0';
+
+         ELSIF (buf_avail <=  3 AND wr_en = '1') THEN  --FIFO_DEPTH
+         
+            almost_full_int <= '1';
+         ELSE
+            almost_full_int <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+
+   
+END trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/cmd_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/cmd_gen.vhd
new file mode 100755
index 0000000..17ee620
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/cmd_gen.vhd
@@ -0,0 +1,1077 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: cmd_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:27 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR
+-- Purpose:  This module genreates different type of commands, address,
+--          burst_length to mcb_flow_control module.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+
+ENTITY cmd_gen IS
+   GENERIC (
+      FAMILY               : STRING := "SPARTAN6";
+      MEM_BURST_LEN        : INTEGER := 8;
+      TCQ                  : TIME := 100 ps;
+      PORT_MODE            : STRING  := "BI_MODE";
+      NUM_DQ_PINS          : INTEGER := 8;
+      DATA_PATTERN         : STRING := "DGEN_ALL";
+      CMD_PATTERN          : STRING := "CGEN_ALL";
+      ADDR_WIDTH           : INTEGER := 30;
+      DWIDTH               : INTEGER := 32;
+      PIPE_STAGES          : INTEGER := 0;
+      MEM_COL_WIDTH        : INTEGER := 10;
+      PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+      PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00002000"
+   );
+   PORT (
+      clk_i                : IN STD_LOGIC;
+      rst_i                : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      run_traffic_i        : IN STD_LOGIC;
+      rd_buff_avail_i      : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      force_wrcmd_gen_i    : IN STD_LOGIC;
+      start_addr_i         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      end_addr_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmd_seed_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      data_seed_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      load_seed_i          : IN STD_LOGIC;
+      addr_mode_i          : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      data_mode_i          : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      instr_mode_i         : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      bl_mode_i            : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      mode_load_i          : IN STD_LOGIC;
+      fixed_bl_i           : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      fixed_instr_i        : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      fixed_addr_i         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bram_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bram_instr_i         : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      bram_bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      bram_valid_i         : IN STD_LOGIC;
+      bram_rdy_o           : OUT STD_LOGIC;
+      reading_rd_data_i    : IN STD_LOGIC;
+      rdy_i                : IN STD_LOGIC;
+      addr_o               : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      instr_o              : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      bl_o                 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+--      m_addr_o             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmd_o_vld            : OUT STD_LOGIC
+   );
+END cmd_gen;
+
+ARCHITECTURE trans OF cmd_gen IS
+    constant  PRBS_ADDR_WIDTH      : INTEGER := 32;
+    constant  INSTR_PRBS_WIDTH     : INTEGER := 16;
+    constant  BL_PRBS_WIDTH        : INTEGER := 16;
+
+    constant  BRAM_DATAL_MODE      : std_logic_vector(3 downto 0)  := "0000";
+    constant  FIXED_DATA_MODE      : std_logic_vector(3 downto 0)  := "0001";
+    constant  ADDR_DATA_MODE       : std_logic_vector(3 downto 0)  := "0010";
+    constant  HAMMER_DATA_MODE     : std_logic_vector(3 downto 0)  := "0011";
+    constant  NEIGHBOR_DATA_MODE   : std_logic_vector(3 downto 0)  := "0100";
+    constant  WALKING1_DATA_MODE   : std_logic_vector(3 downto 0)  := "0101";
+    constant  WALKING0_DATA_MODE   : std_logic_vector(3 downto 0)  := "0110";
+    constant  PRBS_DATA_MODE       : std_logic_vector(3 downto 0)  := "0111";
+COMPONENT pipeline_inserter IS
+   GENERIC (
+      DATA_WIDTH            : INTEGER := 32;
+      PIPE_STAGES           : INTEGER := 1
+   );
+   PORT (
+      data_i                : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
+      clk_i                 : IN STD_LOGIC;
+      en_i                  : IN STD_LOGIC;
+
+      data_o                : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
+   );
+END COMPONENT;
+
+COMPONENT cmd_prbs_gen IS
+   GENERIC (
+      TCQ                  : time := 100 ps;
+      FAMILY               : STRING := "SPARTAN6";
+      ADDR_WIDTH           : INTEGER := 29;
+      DWIDTH               : INTEGER := 32;
+      PRBS_CMD             : STRING := "ADDRESS";
+      PRBS_WIDTH           : INTEGER := 64;
+      SEED_WIDTH           : INTEGER := 32;
+      PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+      PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00002000"
+   );
+   PORT (
+
+      clk_i                : IN STD_LOGIC;
+      prbs_seed_init       : IN STD_LOGIC;
+      clk_en               : IN STD_LOGIC;
+      prbs_seed_i          : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
+
+      prbs_o               : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
+   );
+END COMPONENT;
+
+function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
+begin
+   if A = true then
+       return '1';
+   else
+       return '0';
+   end if;
+end function BOOLEAN_TO_STD_LOGIC;
+
+   SIGNAL INC_COUNTS                    : STD_LOGIC_VECTOR(10 DOWNTO 0);
+   SIGNAL addr_mode_reg                 : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL bl_mode_reg                   : STD_LOGIC_VECTOR(1 DOWNTO 0);
+   SIGNAL addr_counts                   : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL prbs_bl                       : STD_LOGIC_VECTOR(14 DOWNTO 0);
+   SIGNAL instr_out                     : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL prbs_instr_a                  : STD_LOGIC_VECTOR(14 DOWNTO 0);
+   SIGNAL prbs_instr_b                  : STD_LOGIC_VECTOR(14 DOWNTO 0);
+   SIGNAL prbs_brlen                    : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL prbs_addr                     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL seq_addr                      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL fixed_addr                    : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL addr_out                      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL bl_out                        : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL bl_out_reg                    : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL mode_load_d1                  : STD_LOGIC;
+   SIGNAL mode_load_d2                  : STD_LOGIC;
+   SIGNAL mode_load_pulse               : STD_LOGIC;
+   SIGNAL pipe_data_o                   : STD_LOGIC_VECTOR(41 DOWNTO 0);
+   SIGNAL cmd_clk_en                    : STD_LOGIC;
+   SIGNAL pipe_out_vld                  : STD_LOGIC;
+   SIGNAL end_addr_range                : STD_LOGIC_VECTOR(15 DOWNTO 0);
+   SIGNAL force_bl1                     : STD_LOGIC;
+   SIGNAL A0_G_E0                       : STD_LOGIC;
+   SIGNAL A1_G_E1                       : STD_LOGIC;
+   SIGNAL A2_G_E2                       : STD_LOGIC;
+   SIGNAL A3_G_E3                       : STD_LOGIC;
+   SIGNAL AC3_G_E3                      : STD_LOGIC;
+   SIGNAL AC2_G_E2                      : STD_LOGIC;
+   SIGNAL AC1_G_E1                      : STD_LOGIC;
+   SIGNAL bl_out_clk_en                 : STD_LOGIC;
+   SIGNAL pipe_data_in                  : STD_LOGIC_VECTOR(41 DOWNTO 0);
+   SIGNAL instr_vld                     : STD_LOGIC;
+   SIGNAL bl_out_vld                    : STD_LOGIC;
+   SIGNAL cmd_vld                       : STD_LOGIC;
+   SIGNAL run_traffic_r                 : STD_LOGIC;
+   SIGNAL run_traffic_pulse             : STD_LOGIC;
+
+   SIGNAL pipe_data_in_vld              : STD_LOGIC;
+   SIGNAL gen_addr_larger               : STD_LOGIC;
+   SIGNAL buf_avail_r                   : STD_LOGIC_VECTOR(6 DOWNTO 0);
+   SIGNAL rd_data_received_counts       : STD_LOGIC_VECTOR(6 DOWNTO 0);
+   SIGNAL rd_data_counts_asked          : STD_LOGIC_VECTOR(6 DOWNTO 0);
+   SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
+   SIGNAL instr_vld_dly1                : STD_LOGIC;
+   SIGNAL first_load_pulse              : STD_LOGIC;
+   SIGNAL mem_init_done                 : STD_LOGIC;
+   SIGNAL i                             : INTEGER;
+   SIGNAL force_wrcmd_gen               : STD_LOGIC;
+   SIGNAL force_smallvalue              : STD_LOGIC;
+
+   SIGNAL end_addr_r                    : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+   SIGNAL force_rd_counts               : STD_LOGIC_VECTOR(9 DOWNTO 0);
+   SIGNAL force_rd                      : STD_LOGIC;
+   SIGNAL addr_counts_next_r            : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL refresh_cmd_en                : STD_LOGIC;
+   SIGNAL refresh_timer                 : STD_LOGIC_VECTOR(9 DOWNTO 0);
+   SIGNAL refresh_prbs                  : STD_LOGIC;
+   SIGNAL cmd_clk_en_r                  : STD_LOGIC;
+
+   signal instr_mode_reg                : std_logic_vector(3 downto 0);
+
+
+   -- X-HDL generated signals
+
+   SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
+   SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL bl_o_xhdl0                    : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL mode_load_pulse_r1            : STD_LOGIC;
+
+BEGIN
+   -- Drive referenced outputs
+   bl_o       <= bl_o_xhdl0;
+   addr_o     <= pipe_data_o(31 DOWNTO 0);
+   instr_o    <= pipe_data_o(34 DOWNTO 32);
+   bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
+   cmd_o_vld  <= pipe_data_o(41) AND run_traffic_r;
+   pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
+   pipe_data_o <= pipe_data_in;
+
+
+   cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+           cmd_vld <= cmd_clk_en;
+      END IF;
+   END PROCESS;
+   END GENERATE;
+
+   cv3 : IF (CMD_PATTERN = "CGEN_PRBS"  OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+           cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
+      END IF;
+   END PROCESS;
+   END GENERATE;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+            run_traffic_r <=  run_traffic_i ;
+          IF (  run_traffic_i= '1' AND   run_traffic_r = '0' ) THEN
+               run_traffic_pulse <= '1'  ;
+          ELSE
+               run_traffic_pulse <= '0' ;
+          END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
+         bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
+         bl_out_vld <= bl_out_clk_en ;
+         pipe_data_in_vld <= instr_vld ;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0) = '1') THEN
+            first_load_pulse <= '1' ;
+         ELSIF (mode_load_pulse = '1') THEN
+            first_load_pulse <= '0' ;
+         ELSE
+            first_load_pulse <= first_load_pulse ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+
+   cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i)  OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
+
+   pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF ((rst_i(0)) = '1') THEN
+               pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
+            ELSIF (instr_vld = '1') THEN
+               IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
+
+                 IF (DWIDTH = 32) THEN
+                   pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
+                 ELSIF (DWIDTH = 64) THEN
+                   pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
+                 ELSE
+                   pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
+                 END IF;
+
+               ELSE
+                  IF (DWIDTH = 32) THEN
+                     pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
+                  ELSIF (DWIDTH = 64) THEN
+                     pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
+                  ELSIF (DWIDTH = 128) THEN
+                     pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
+                  END IF;
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+   END GENERATE;
+   pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF ((rst_i(1)) = '1') THEN
+               pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
+            ELSIF (instr_vld = '1') THEN
+               IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
+                  pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
+
+               ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
+                  END IF;
+
+               ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
+
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
+                  END IF;
+
+               ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
+                  END IF;
+
+               ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
+                  pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
+                  END IF;
+               ELSIF (NUM_DQ_PINS = 8)  THEN
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
+                  END IF;
+
+
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+   END GENERATE;
+--   pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
+--      PROCESS (clk_i)
+--      BEGIN
+--         IF (clk_i'EVENT AND clk_i = '1') THEN
+--            IF ((rst_i(1)) = '1') THEN
+--               m_addr_o(31 DOWNTO 0) <= start_addr_i ;
+--            ELSIF (instr_vld = '1') THEN
+--               IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
+--                  m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
+--
+--               ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
+--                  m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
+--
+--               ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
+--                  m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
+--               ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
+--                  m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
+--               ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
+--                  m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
+--               ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
+--                  m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
+--               END IF;
+--            END IF;
+--         END IF;
+--      END PROCESS;
+--
+--   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0) = '1') THEN
+            force_wrcmd_gen <= '0' ;
+         ELSIF (buf_avail_r = "0111111") THEN
+            force_wrcmd_gen <= '0' ;
+         ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
+            force_wrcmd_gen <= '1' ;
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         instr_mode_reg <= instr_mode_i ;
+
+      END IF;
+   END PROCESS;
+            -- **********************************************
+
+   PROCESS (clk_i) BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(2)) = '1') THEN
+            pipe_data_in(40 DOWNTO 32) <= "000000000";
+            force_smallvalue <= '0';
+         ELSIF (instr_vld = '1') THEN
+
+            IF (instr_mode_reg = 0) THEN
+               pipe_data_in(34 DOWNTO 32) <= instr_out ;
+
+            ELSIF (instr_out(2) = '1') THEN
+
+               pipe_data_in(34 DOWNTO 32) <= "100" ;
+
+
+            ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
+
+               pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
+
+            ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
+                  pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
+            ELSE
+                  pipe_data_in(34 DOWNTO 32) <= instr_out;
+
+            END IF;
+   ----********* condition the generated bl value except if TG is programmed for BRAM interface'
+   ---- if the generated address is close to end address range, the bl_out will be altered to 1.
+     --
+           IF (bl_mode_i = 0) THEN
+               pipe_data_in(40 DOWNTO 35) <= bl_out ;
+         ELSIF ( FAMILY = "VIRTEX6") THEN
+             pipe_data_in(40 DOWNTO 35)  <=  bl_out ;
+         ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
+
+            pipe_data_in(40 DOWNTO 35) <= "000001"  ;
+
+
+         -- **********************************************
+
+      ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
+         IF (bl_mode_reg = "10") THEN
+             force_smallvalue <= NOT(force_smallvalue) ;
+          END IF;
+          IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
+             pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
+          ELSE
+             pipe_data_in(40 DOWNTO 35) <= bl_out ;
+          END IF;
+      ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
+         IF (FAMILY = "SPARTAN6") THEN
+           pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
+        ELSE
+           pipe_data_in(40 DOWNTO 35) <= bl_out ;
+         END IF;
+         END IF; --IF (bl_mode_i = 0) THEN
+       END IF;  --IF ((rst_i(2)) = '1') THEN
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(2)) = '1') THEN
+            pipe_data_in(41) <= '0' ;
+         ELSIF (cmd_vld = '1') THEN
+            pipe_data_in(41) <= instr_vld ;
+         ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
+            pipe_data_in(41) <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         instr_vld_dly1 <= instr_vld;
+      END IF;
+   END PROCESS;
+
+
+
+ PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0) = '1') THEN
+            rd_data_counts_asked <= (others => '0') ;
+         ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
+            IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
+               rd_data_counts_asked <= rd_data_counts_asked + 64 ;
+
+            ELSE
+               rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
+
+            END IF;
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF  (rst_i(0) = '1') THEN
+            rd_data_received_counts <= (others => '0');
+            rd_data_received_counts_total <= (others => '0');
+         ELSIF (reading_rd_data_i = '1') THEN
+            rd_data_received_counts <= rd_data_received_counts + '1';
+            rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(3)) = '1') THEN
+           IF (CMD_PATTERN = "CGEN_BRAM") THEN
+             addr_mode_reg <= "000";
+           ELSE
+             addr_mode_reg <= "011";
+           END IF;
+         ELSIF (mode_load_pulse = '1') THEN
+            addr_mode_reg <= addr_mode_i;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (mode_load_pulse = '1') THEN
+            bl_mode_reg <= bl_mode_i;
+         END IF;
+         mode_load_d1 <= mode_load_i;
+         mode_load_d2 <= mode_load_d1;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
+      END IF;
+   END PROCESS;
+
+   xhdl4 <= addr_mode_reg;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(3)) = '1') THEN
+            addr_out <= start_addr_i;
+         ELSE
+            CASE xhdl4 IS
+               WHEN "000" =>
+                  addr_out <= bram_addr_i;
+               WHEN "001" =>
+                  addr_out <= fixed_addr;
+               WHEN "010" =>
+                  addr_out <= prbs_addr;
+               WHEN "011" =>
+                  addr_out <= ("00" & seq_addr(29 DOWNTO 0));
+               WHEN "100" =>
+--                  addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
+                  addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
+               WHEN "101" =>
+                  addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
+  --                addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
+               WHEN OTHERS =>
+                  addr_out <= (others => '0');--"00000000000000000000000000000000";
+            END CASE;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+
+
+      addr_prbs_gen : cmd_prbs_gen
+         GENERIC MAP (
+            family               => FAMILY,
+            addr_width           => 32,
+            dwidth               => DWIDTH,
+            prbs_width           => 32,
+            seed_width           => 32,
+            prbs_eaddr_mask_pos  => PRBS_EADDR_MASK_POS,
+            prbs_saddr_mask_pos  => PRBS_SADDR_MASK_POS,
+            prbs_eaddr           => PRBS_EADDR,
+            prbs_saddr           => PRBS_SADDR
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            clk_en          => cmd_clk_en,
+            prbs_seed_init  => mode_load_pulse,
+            prbs_seed_i     => cmd_seed_i(31 DOWNTO 0),
+            prbs_o          => prbs_addr
+         );
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
+            gen_addr_larger <= '1';
+         ELSE
+            gen_addr_larger <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+   xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (mem_init_done = '1') THEN
+               INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
+            ELSE
+               IF (fixed_bl_i = "000000") THEN
+                  INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
+               ELSE
+                  INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+   END GENERATE;
+   xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
+         
+            ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
+            ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
+            ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
+            ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
+            END IF;
+         END IF;
+      END PROCESS;
+
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+            end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
+            AC3_G_E3 <= '1';
+         ELSE
+            AC3_G_E3 <= '0';
+         END IF;
+         IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
+            AC2_G_E2 <= '1';
+         ELSE
+            AC2_G_E2 <= '0';
+         END IF;
+         IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
+            AC1_G_E1 <= '1';
+         ELSE
+            AC1_G_E1 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+--   xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+      seq_addr <= addr_counts;
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            mode_load_pulse_r1 <= mode_load_pulse;
+         END IF;
+      END PROCESS;
+
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+               end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
+         END IF;
+      END PROCESS;
+
+      PROCESS (clk_i)
+      BEGIN
+        IF (clk_i'EVENT AND clk_i = '1') THEN
+              addr_counts_next_r <=   addr_counts + (INC_COUNTS);
+
+        END IF;
+      END PROCESS;
+
+      PROCESS (clk_i)
+      BEGIN
+        IF (clk_i'EVENT AND clk_i = '1') THEN
+              cmd_clk_en_r <= cmd_clk_en;
+        END IF;
+      END PROCESS;
+
+
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF ((rst_i(4)) = '1') THEN
+               addr_counts <= start_addr_i;
+               mem_init_done <= '0';
+            ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
+--               IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
+            IF (addr_counts_next_r >= end_addr_i) THEN
+                  addr_counts <= start_addr_i;
+                  mem_init_done <= '1';
+               ELSIF (addr_counts < end_addr_r) THEN
+                  addr_counts <= addr_counts + INC_COUNTS;
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+   --END GENERATE;
+   
+   xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+      fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
+                    (fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
+                    (fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
+                    (fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
+                    (fixed_addr_i(31 DOWNTO 6) & "000000");
+   END GENERATE;
+   xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+      bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(4)) = '1') THEN
+            force_rd_counts <= (others => '0');--"0000000000";
+         ELSIF (instr_vld = '1') THEN
+            force_rd_counts <= force_rd_counts + "0000000001";
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(4)) = '1') THEN
+            force_rd <= '0';
+         ELSIF ((force_rd_counts(3)) = '1') THEN
+            force_rd <= '1';
+         ELSE
+            force_rd <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+
+-- adding refresh timer to limit the amount of issuing refresh command.
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(4)) = '1') THEN
+            refresh_timer <= (others => '0');
+         ELSE
+            refresh_timer <= refresh_timer + 1;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(4)) = '1') THEN
+            refresh_cmd_en <= '0';
+         ELSIF (refresh_timer = "1111111111") THEN
+            refresh_cmd_en <= '1';
+         ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
+            refresh_cmd_en <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (FAMILY = "SPARTAN6") THEN
+            refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
+         ELSE
+            refresh_prbs <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+  --synthesis translate_off
+   PROCESS (instr_mode_i)
+   BEGIN
+     IF ((instr_mode_i  > "0010") and (FAMILY = "VIRTEX6")) THEN
+       report "Error ! Not valid instruction mode";
+     END IF;
+   END PROCESS;
+  --synthesis translate_on
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         CASE instr_mode_i IS
+            WHEN "0000" =>
+               instr_out <= bram_instr_i;
+            WHEN "0001" =>
+               instr_out <= fixed_instr_i;
+            WHEN "0010" =>
+               instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
+            WHEN "0011" =>
+               instr_out <= ("00" & prbs_instr_a(0));
+            WHEN "0100" =>
+               instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
+
+            WHEN "0101" =>
+               instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
+            WHEN OTHERS =>
+               instr_out <= ("00" & prbs_instr_a(0));
+         END CASE;
+      END IF;
+   END PROCESS;
+
+
+   xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+
+
+
+
+      instr_prbs_gen_a : cmd_prbs_gen
+         GENERIC MAP (
+            prbs_cmd    => "INSTR",
+            family      => FAMILY,
+            addr_width  => 32,
+            seed_width  => 15,
+            prbs_width  => 20
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            clk_en          => cmd_clk_en,
+            prbs_seed_init  => load_seed_i,
+            prbs_seed_i     => cmd_seed_i(14 DOWNTO 0),
+            prbs_o          => prbs_instr_a
+         );
+
+
+
+      instr_prbs_gen_b : cmd_prbs_gen
+         GENERIC MAP (
+            prbs_cmd    => "INSTR",
+            family      => FAMILY,
+            seed_width  => 15,
+            prbs_width  => 20
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            clk_en          => cmd_clk_en,
+            prbs_seed_init  => load_seed_i,
+            prbs_seed_i     => cmd_seed_i(16 DOWNTO 2),
+            prbs_o          => prbs_instr_b
+         );
+
+   END GENERATE;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
+            A3_G_E3 <= '1' ;
+         ELSE
+
+            A3_G_E3 <= '0' ;
+         END IF;
+         IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
+            A2_G_E2 <= '1' ;
+         ELSE
+
+            A2_G_E2 <= '0' ;
+         END IF;
+         IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
+            A1_G_E1 <= '1' ;
+         ELSE
+
+            A1_G_E1 <= '0' ;
+                 END IF;
+         IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1')  ) THEN      -- OK
+
+
+
+
+
+            A0_G_E0 <= '1' ;
+         ELSE
+
+            A0_G_E0 <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+
+--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
+
+   PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
+   BEGIN
+      IF ((rst_i(5)) = '1') THEN
+         force_bl1 <= '0';
+
+
+      ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i)  OR
+            (buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
+         force_bl1 <= '1' ;
+      ELSE
+         force_bl1 <= '0' ;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(6)) = '1') THEN
+            bl_out_reg <= fixed_bl_i;
+         ELSIF (bl_out_vld = '1') THEN
+
+            bl_out_reg <= bl_out;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   xhdl12 <= bl_mode_reg;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (mode_load_pulse = '1') THEN
+            bl_out <= fixed_bl_i;
+         ELSIF (cmd_clk_en = '1') THEN
+            CASE xhdl12 IS
+               WHEN "00" =>
+                  bl_out <= bram_bl_i;
+               WHEN "01" =>
+                  bl_out <= fixed_bl_i;
+               WHEN "10" =>
+                  bl_out <= prbs_brlen;
+               WHEN OTHERS =>
+                  bl_out <= "000001";
+            END CASE;
+         END IF;
+      END IF;
+   END PROCESS;
+
+  --synthesis translate_off
+   PROCESS (bl_out)
+   BEGIN
+      IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
+         report "Error ! Not valid burst length"; --severity ERROR;
+      END IF;
+   END PROCESS;
+  --synthesis translate_on
+
+   xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+
+
+
+
+      bl_prbs_gen : cmd_prbs_gen
+         GENERIC MAP (
+            TCQ         => TCQ,
+            family      => FAMILY,
+            prbs_cmd    => "BLEN",
+            addr_width  => 32,
+            seed_width  => 15,
+            prbs_width  => 20
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            clk_en          => cmd_clk_en,
+
+            prbs_seed_init  => load_seed_i,
+            prbs_seed_i     => cmd_seed_i(16 DOWNTO 2),
+            prbs_o          => prbs_bl
+         );
+
+   END GENERATE;
+--   xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
+   PROCESS (prbs_bl) BEGIN
+      IF (FAMILY = "SPARTAN6") THEN
+         if (prbs_bl(5 DOWNTO 0) = "000000") then
+--         prbs_brlen <= xhdl14;
+           prbs_brlen <= "000001";
+         else
+           prbs_brlen <= prbs_bl(5 DOWNTO 0);
+         end if;
+      ELSE
+         prbs_brlen <= "000010";
+      END IF;
+   END PROCESS;
+   
+   
+
+END trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/cmd_prbs_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/cmd_prbs_gen.vhd
new file mode 100755
index 0000000..ddba6fc
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/cmd_prbs_gen.vhd
@@ -0,0 +1,247 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: cmd_prbs_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:37 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:  This moduel use LFSR to generate random address, isntructions 
+--          or burst_length.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+
+ENTITY cmd_prbs_gen IS
+   GENERIC (
+      TCQ                  : time := 100 ps;   
+      FAMILY               : STRING := "SPARTAN6";
+      ADDR_WIDTH           : INTEGER := 29;
+      DWIDTH               : INTEGER := 32;
+      PRBS_CMD             : STRING := "ADDRESS";
+      PRBS_WIDTH           : INTEGER := 64;
+      SEED_WIDTH           : INTEGER := 32;      
+
+      PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+      PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00002000"
+   );
+   PORT (
+      
+      clk_i                : IN STD_LOGIC;
+      prbs_seed_init       : IN STD_LOGIC;
+      clk_en               : IN STD_LOGIC;
+      prbs_seed_i          : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
+      
+      prbs_o               : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
+   );
+END cmd_prbs_gen;
+
+ARCHITECTURE trans OF cmd_prbs_gen IS
+   SIGNAL ZEROS  : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+   SIGNAL prbs   : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
+   SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
+
+ function logb2 (val : integer) return integer is
+  variable vec_con : integer;
+  variable rtn : integer := 1;
+  begin
+    vec_con  := val;
+    for index in 0 to 31 loop
+      if(vec_con = 1) then
+        rtn := rtn + 1;
+        return(rtn);
+      end if;
+      vec_con := vec_con/2;
+      rtn := rtn + 1;
+    end loop;
+  end function logb2;
+
+
+BEGIN
+   
+   ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
+   
+   xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
+      
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (prbs_seed_init = '1') THEN
+               lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
+            ELSIF (clk_en = '1') THEN
+               lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
+               lfsr_q(63) <= lfsr_q(62) ;
+               lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
+               
+               lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
+               
+               lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
+               lfsr_q(1) <= lfsr_q(64) ;
+            END IF;
+         END IF;
+      END PROCESS;
+      
+      
+      PROCESS (lfsr_q(32 DOWNTO 1))
+      BEGIN
+         prbs <= lfsr_q(32 DOWNTO 1);
+      END PROCESS;
+      
+   END GENERATE;
+   
+   
+   xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
+      
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (prbs_seed_init = '1') THEN
+               lfsr_q <= prbs_seed_i ;
+            ELSIF (clk_en = '1') THEN
+               
+               lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
+               lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
+               lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
+               
+               lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
+               lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
+               lfsr_q(2) <= lfsr_q(1) ;
+               
+               lfsr_q(1) <= lfsr_q(32) ;
+            END IF;
+         END IF;
+      END PROCESS;
+      
+      
+      
+      PROCESS (lfsr_q(32 DOWNTO 1))
+      BEGIN
+
+        IF (FAMILY = "SPARTAN6") THEN
+          FOR i IN (logb2(DWIDTH) + 1) TO  SEED_WIDTH - 1 LOOP
+            IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
+                          prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
+            ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
+                          prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
+            ELSE
+              prbs(i) <= lfsr_q(i + 1);
+            END IF;
+          END LOOP;
+          prbs(logb2(DWIDTH) downto 0) <= (others => '0');
+        ELSE 
+          FOR i IN (logb2(DWIDTH) - 4) TO  SEED_WIDTH - 1 LOOP
+            IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
+                          prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
+            ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
+                          prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
+            ELSE
+              prbs(i) <= lfsr_q(i + 1);
+            END IF;
+          END LOOP;
+         prbs(logb2(DWIDTH) downto 0) <= (others => '0');
+        END IF;
+
+      END PROCESS;
+      
+      
+   END GENERATE;
+   
+   
+   xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
+      
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (prbs_seed_init = '1') THEN
+               lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
+            ELSIF (clk_en = '1') THEN
+               
+               lfsr_q(20) <= lfsr_q(19) ;
+               
+               lfsr_q(19) <= lfsr_q(18) ;
+               
+               lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
+               lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
+               
+               lfsr_q(1) <= lfsr_q(20) ;
+            END IF;
+         END IF;
+      END PROCESS;
+      
+      
+      PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
+      BEGIN
+            prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
+      END PROCESS;
+      
+      
+   END GENERATE;
+   
+   prbs_o <= prbs;
+   
+END trans;
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/data_prbs_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/data_prbs_gen.vhd
new file mode 100755
index 0000000..b372d7a
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/data_prbs_gen.vhd
@@ -0,0 +1,135 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: data_prbs_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:39 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:  This module is used LFSR to generate random data for memory 
+--          data write or memory data read comparison.The first data is 
+--          seeded by the input prbs_seed_i which is connected to memory address.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+
+ENTITY data_prbs_gen IS
+   GENERIC (
+      EYE_TEST        : STRING := "FALSE";
+      PRBS_WIDTH      : INTEGER := 32;
+      SEED_WIDTH      : INTEGER := 32
+--      TAPS            : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      clk_en          : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      prbs_seed_init  : IN STD_LOGIC;
+      prbs_seed_i     : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
+      
+      prbs_o          : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
+   );
+END data_prbs_gen;
+
+ARCHITECTURE trans OF data_prbs_gen IS
+   
+   SIGNAL prbs   : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
+   SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
+   SIGNAL i      : INTEGER;
+BEGIN
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
+            
+            
+            lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
+         ELSIF (clk_en = '1') THEN
+            
+            lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
+            lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
+            lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
+            
+            lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
+            lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
+            lfsr_q(2) <= lfsr_q(1);
+            
+            lfsr_q(1) <= lfsr_q(32);
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
+   BEGIN
+      prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
+   END PROCESS;
+   
+   
+   prbs_o <= prbs;
+   
+END trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/init_mem_pattern_ctr.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/init_mem_pattern_ctr.vhd
new file mode 100755
index 0000000..49d24e3
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/init_mem_pattern_ctr.vhd
@@ -0,0 +1,620 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: init_mem_pattern_ctr.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:39 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This moduel has a small FSM to control the operation of 
+--         mcb_traffic_gen module.It first fill up the memory with a selected 
+--         DATA pattern and then starts the memory testing state.
+-- Reference:
+-- Revision History:  1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
+--                      and the fixed_bl_o is fixed at 64 if data_mode_o == PRBS and FAMILY == "SPARTAN6"
+--                      The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
+--                    1.2  05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
+--                                    "OTF" Burst Mode and TG will only generate BL 8 traffic.
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+
+ENTITY init_mem_pattern_ctr IS
+   GENERIC (
+      FAMILY                         : STRING := "SPARTAN6";
+      TST_MEM_INSTR_MODE             : STRING := "R_W_INSTR_MODE";
+      MEM_BURST_LEN                  : INTEGER := 8;
+      CMD_PATTERN                    : STRING := "CGEN_ALL";
+      BEGIN_ADDRESS                  : std_logic_vector(31 downto 0) := X"00000000";
+      END_ADDRESS                    : std_logic_vector(31 downto 0) := X"00000fff";
+      ADDR_WIDTH                     : INTEGER := 30;
+      DWIDTH                         : INTEGER := 32;
+      CMD_SEED_VALUE                 : std_logic_vector(31 downto 0) := X"12345678";
+      DATA_SEED_VALUE                : std_logic_vector(31 downto 0) := X"ca345675";
+      DATA_MODE                      : std_logic_vector(3 downto 0) := "0010";
+      PORT_MODE                      : STRING := "BI_MODE";
+      EYE_TEST                       : STRING := "FALSE"
+      
+   );
+   PORT (
+      clk_i                          : IN STD_LOGIC;
+      rst_i                          : IN STD_LOGIC;
+      mcb_cmd_bl_i                   : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      mcb_cmd_en_i                   : IN STD_LOGIC;
+      mcb_cmd_instr_i                : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      mcb_wr_en_i                    : IN STD_LOGIC;
+      vio_modify_enable              : IN STD_LOGIC;
+      vio_data_mode_value            : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      vio_addr_mode_value            : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      vio_bl_mode_value              : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      vio_fixed_bl_value             : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      mcb_init_done_i                : IN STD_LOGIC;
+      cmp_error                      : IN STD_LOGIC;
+      run_traffic_o                  : OUT STD_LOGIC;
+      start_addr_o                   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      end_addr_o                     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmd_seed_o                     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      data_seed_o                    : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      load_seed_o                    : OUT STD_LOGIC;
+      addr_mode_o                    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      instr_mode_o                   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      bl_mode_o                      : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      data_mode_o                    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      mode_load_o                    : OUT STD_LOGIC;
+      fixed_bl_o                     : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+      fixed_instr_o                  : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      fixed_addr_o                   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+   );
+END init_mem_pattern_ctr;
+
+ARCHITECTURE trans OF init_mem_pattern_ctr IS
+
+      constant IDLE                           : std_logic_vector(4 downto 0)  := "00001";
+      constant INIT_MEM_WRITE                 : std_logic_vector(4 downto 0)  := "00010";
+      constant INIT_MEM_READ                  : std_logic_vector(4 downto 0)  := "00100";
+      constant TEST_MEM                       : std_logic_vector(4 downto 0)  := "01000";
+      constant CMP_ERROR1                     : std_logic_vector(4 downto 0)  := "10000";
+
+      constant BRAM_ADDR                      : std_logic_vector(1 downto 0)  := "00";
+      constant FIXED_ADDR                     : std_logic_vector(2 downto 0)  := "001";
+      constant PRBS_ADDR                      : std_logic_vector(2 downto 0)  := "010";
+      constant SEQUENTIAL_ADDR                : std_logic_vector(2 downto 0)  := "011";
+
+      constant BRAM_INSTR_MODE                : std_logic_vector(3 downto 0)  := "0000";
+      constant FIXED_INSTR_MODE               : std_logic_vector(3 downto 0)  := "0001";
+      constant FIXED_INSTR_MODE_WITH_REFRESH  : std_logic_vector(3 downto 0)  := "0110";
+
+      constant R_W_INSTR_MODE                 : std_logic_vector(3 downto 0)  := "0010";
+      constant RP_WP_INSTR_MODE               : std_logic_vector(3 downto 0)  := "0011";
+      constant R_RP_W_WP_INSTR_MODE           : std_logic_vector(3 downto 0)  := "0100";
+      constant R_RP_W_WP_REF_INSTR_MODE       : std_logic_vector(3 downto 0)  := "0101";
+
+      constant BRAM_BL_MODE                   : std_logic_vector(1 downto 0)  := "00";
+      constant FIXED_BL_MODE                  : std_logic_vector(1 downto 0)  := "01";
+      constant PRBS_BL_MODE                   : std_logic_vector(1 downto 0)  := "10";
+          
+      constant BRAM_DATAL_MODE                : std_logic_vector(3 downto 0)  := "0000";
+      constant FIXED_DATA_MODE                : std_logic_vector(3 downto 0)  := "0001";
+      constant ADDR_DATA_MODE                 : std_logic_vector(3 downto 0)  := "0010";
+      constant HAMMER_DATA_MODE               : std_logic_vector(3 downto 0)  := "0011";
+      constant NEIGHBOR_DATA_MODE             : std_logic_vector(3 downto 0)  := "0100";
+      constant WALKING1_DATA_MODE             : std_logic_vector(3 downto 0)  := "0101";
+      constant WALKING0_DATA_MODE             : std_logic_vector(3 downto 0)  := "0110";
+      constant PRBS_DATA_MODE                 : std_logic_vector(3 downto 0)  := "0111";
+
+      constant RD_INSTR                       : std_logic_vector(2 downto 0)  := "001";
+      constant RDP_INSTR                      : std_logic_vector(2 downto 0)  := "011";
+      constant WR_INSTR                       : std_logic_vector(2 downto 0)  := "000";
+      
+      constant WRP_INSTR                      : std_logic_vector(2 downto 0)  := "010";
+      constant REFRESH_INSTR                  : std_logic_vector(2 downto 0)  := "100";
+      constant NOP_WR_INSTR                   : std_logic_vector(2 downto 0)  := "101";
+   
+   SIGNAL current_state            : STD_LOGIC_VECTOR(4 DOWNTO 0);
+   SIGNAL next_state               : STD_LOGIC_VECTOR(4 DOWNTO 0);
+   SIGNAL mcb_init_done_reg        : STD_LOGIC;
+   SIGNAL mcb_init_done_reg1        : STD_LOGIC;
+   SIGNAL AC2_G_E2                 : STD_LOGIC;
+   SIGNAL AC1_G_E1                 : STD_LOGIC;
+   SIGNAL AC3_G_E3                 : STD_LOGIC;
+   SIGNAL upper_end_matched        : STD_LOGIC;
+   SIGNAL end_boundary_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   
+   SIGNAL mcb_cmd_en_r             : STD_LOGIC;
+   SIGNAL mcb_cmd_bl_r             : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL lower_end_matched        : STD_LOGIC;
+   SIGNAL end_addr_reached         : STD_LOGIC;
+   SIGNAL run_traffic              : STD_LOGIC;
+   SIGNAL current_address          : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL fix_bl_value             : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL data_mode_sel            : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL addr_mode_sel            : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL bl_mode_sel              : STD_LOGIC_VECTOR(1 DOWNTO 0);
+   SIGNAL addr_mode                : STD_LOGIC_VECTOR(2 DOWNTO 0);
+--   SIGNAL data_mode1                : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL INC_COUNTS               : STD_LOGIC_VECTOR(10 DOWNTO 0);
+   SIGNAL FIXEDBL                  : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL  FIXED_BL_VALUE           : STD_LOGIC_VECTOR(6 DOWNTO 0);
+   
+   SIGNAL bram_mode_enable         : STD_LOGIC;
+   SIGNAL syn1_vio_data_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL syn1_vio_addr_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL test_mem_instr_mode      : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL bl_mode_o_xhdl0          : STD_LOGIC_VECTOR(1 DOWNTO 0);
+   SIGNAL data_mode_reg          : STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+BEGIN
+
+
+test_mem_instr_mode <= "0000" when TST_MEM_INSTR_MODE = "BRAM_INSTR_MODE" else
+                       "0001" when (TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") OR
+                                   (TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") else
+                       "0010" when TST_MEM_INSTR_MODE = "R_W_INSTR_MODE" else
+                       "0011" when (TST_MEM_INSTR_MODE = "RP_WP_INSTR_MODE" AND
+                                   FAMILY = "SPARTAN6") else
+                       "0100" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_INSTR_MODE" AND
+                                   FAMILY = "SPARTAN6")else
+                       "0101" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_REF_INSTR_MODE"AND
+                                   FAMILY = "SPARTAN6") else
+                       "0010" ;
+   -- Drive referenced outputs
+   bl_mode_o <= bl_mode_o_xhdl0;
+   FIXEDBL <= "000000";
+   xhdl1 : IF (FAMILY = "SPARTAN6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            INC_COUNTS <= std_logic_vector(to_unsigned(DWIDTH/8,11));
+         END IF;
+      END PROCESS;
+      
+   END GENERATE;
+   xhdl2 : IF (FAMILY = "VIRTEX6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (DWIDTH >= 256 AND DWIDTH <= 576) THEN
+               INC_COUNTS <= "00000100000";
+            ELSIF ((DWIDTH >= 128) AND (DWIDTH <= 224)) THEN
+               INC_COUNTS <= "00000010000";
+            ELSIF ((DWIDTH = 64) OR (DWIDTH = 96)) THEN
+               INC_COUNTS <= "00000001000";
+            ELSIF (DWIDTH = 32) THEN
+               INC_COUNTS <= "00000000100";
+            END IF;
+         END IF;
+      END PROCESS;
+      
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            current_address <= BEGIN_ADDRESS;
+         ELSIF (
+--                ((mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND ((PORT_MODE = "WR_MODE") OR (PORT_MODE = "BI_MODE")))) OR
+                 (mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE"))) OR
+
+                 (mcb_wr_en_i = '1' AND (current_state = IDLE AND PORT_MODE = "RD_MODE" ))
+               ) THEN
+            current_address <= current_address + ("000000000000000000000" & INC_COUNTS);
+         ELSE
+            current_address <= current_address;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (current_address(29 DOWNTO 24) >= end_boundary_addr(29 DOWNTO 24)) THEN
+            AC3_G_E3 <= '1';
+         ELSE
+            AC3_G_E3 <= '0';
+         END IF;
+         IF (current_address(23 DOWNTO 16) >= end_boundary_addr(23 DOWNTO 16)) THEN
+            AC2_G_E2 <= '1';
+         ELSE
+            AC2_G_E2 <= '0';
+         END IF;
+         IF (current_address(15 DOWNTO 8) >= end_boundary_addr(15 DOWNTO 8)) THEN
+            AC1_G_E1 <= '1';
+         ELSE
+            AC1_G_E1 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            upper_end_matched <= '0'; 
+         ELSIF (mcb_cmd_en_i = '1') THEN
+            upper_end_matched <= AC3_G_E3 AND AC2_G_E2 AND AC1_G_E1;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   FIXED_BL_VALUE <= "0000010" WHEN ((FAMILY = "VIRTEX6") AND ((MEM_BURST_LEN = 8) OR (MEM_BURST_LEN = 0))) ELSE 
+                     "0000001" WHEN ((FAMILY = "VIRTEX6") AND (MEM_BURST_LEN = 4)) ELSE
+                     ('0' & FIXEDBL);
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         end_boundary_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(END_ADDRESS)) - (DWIDTH / 8) + 1),32));
+
+
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (current_address(7 DOWNTO 0) >= end_boundary_addr(7 DOWNTO 0)) THEN
+            lower_end_matched <= '1';
+         ELSE
+            lower_end_matched <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (mcb_cmd_en_i = '1') THEN
+            mcb_cmd_bl_r <= mcb_cmd_bl_i;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 32)) OR   
+             ((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 64)) OR 
+             (upper_end_matched = '1' AND DWIDTH = 128 AND FAMILY = "SPARTAN6") OR
+             ((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "VIRTEX6")) THEN
+            end_addr_reached <= '1';
+         ELSE
+            end_addr_reached <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   fixed_addr_o <= "00000000000000000001001000110100";
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         mcb_init_done_reg1 <= mcb_init_done_i;
+         mcb_init_done_reg <= mcb_init_done_reg1;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         run_traffic_o <= run_traffic;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            current_state <= "00001";
+         ELSE
+            current_state <= next_state;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   start_addr_o <= BEGIN_ADDRESS;
+   end_addr_o <= END_ADDRESS;
+   cmd_seed_o <= CMD_SEED_VALUE;
+   data_seed_o <= DATA_SEED_VALUE;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            syn1_vio_data_mode_value <= "011";
+            syn1_vio_addr_mode_value <= "011";
+         ELSIF (vio_modify_enable = '1') THEN
+            syn1_vio_data_mode_value <= vio_data_mode_value;
+            syn1_vio_addr_mode_value <= vio_addr_mode_value;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            data_mode_sel <= DATA_MODE; --"0101" ADDR_DATA_MODE;
+            addr_mode_sel <= "011";
+         ELSIF (vio_modify_enable = '1') THEN
+            data_mode_sel <= '0' & syn1_vio_data_mode_value(2 DOWNTO 0);
+            addr_mode_sel <= vio_addr_mode_value;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i = '1') OR (FAMILY = "VIRTEX6")) THEN
+            fix_bl_value <= FIXED_BL_VALUE(5 DOWNTO 0);
+         ELSIF (vio_modify_enable = '1') THEN
+            fix_bl_value <= vio_fixed_bl_value;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1' OR (FAMILY = "VIRTEX6")) THEN
+            IF (FAMILY = "VIRTEX6") THEN
+               bl_mode_sel <= FIXED_BL_MODE;
+            ELSE
+               bl_mode_sel <= PRBS_BL_MODE;
+            END IF;
+         ELSIF (vio_modify_enable = '1') THEN
+            bl_mode_sel <= vio_bl_mode_value;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   data_mode_o <= data_mode_reg;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         data_mode_reg <=  data_mode_sel;
+         addr_mode_o <= addr_mode;
+         IF (syn1_vio_addr_mode_value = 0 AND vio_modify_enable = '1') THEN
+             bram_mode_enable <=  '1';
+         ELSE
+             bram_mode_enable <=  '0';
+         END IF;
+        
+         
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (FIXED_BL_VALUE,fix_bl_value,bram_mode_enable,test_mem_instr_mode, current_state, mcb_init_done_reg, end_addr_reached, cmp_error, bl_mode_sel, addr_mode_sel, data_mode_reg,bl_mode_o_xhdl0)
+   BEGIN
+      load_seed_o <= '0';
+      IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
+          addr_mode <= (others => '0');
+      ELSE
+          addr_mode <= SEQUENTIAL_ADDR;
+      END IF;
+      
+      IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
+          instr_mode_o <= (others => '0');
+      ELSE
+          instr_mode_o <= FIXED_INSTR_MODE;
+      END IF;
+      
+      
+      IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
+          bl_mode_o_xhdl0 <= (others => '0');
+      ELSE
+          bl_mode_o_xhdl0 <= FIXED_BL_MODE;
+      END IF;
+--      data_mode1 <= WALKING1_DATA_MODE;
+
+      IF (FAMILY = "VIRTEX6") THEN
+        fixed_bl_o <= FIXED_BL_VALUE(5 downto 0); --"000010"; --2
+        -- PRBS mode
+      else if (data_mode_reg(2 downto 0) = "111" and FAMILY = "SPARTAN6") then
+             fixed_bl_o <= "000000";-- 64  Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
+           else
+             fixed_bl_o <= fix_bl_value;
+           end if;
+      end if;
+
+      mode_load_o <= '0';
+      run_traffic <= '0';
+      
+      next_state <= IDLE;
+      IF (PORT_MODE = "RD_MODE") THEN
+         fixed_instr_o <= RD_INSTR;
+      ELSIF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
+         fixed_instr_o <= WR_INSTR;
+      END IF;
+      
+      CASE current_state IS
+         
+         WHEN IDLE =>
+            IF (mcb_init_done_reg = '1') THEN
+               IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
+                  next_state <= INIT_MEM_WRITE;
+                  mode_load_o <= '1';
+                  run_traffic <= '0';
+                  load_seed_o <= '1';
+               ELSIF (PORT_MODE = "RD_MODE" AND end_addr_reached = '1') THEN
+                  next_state <= TEST_MEM;
+                  mode_load_o <= '1';
+                  run_traffic <= '1';
+                  load_seed_o <= '1';
+               END IF;
+            ELSE
+               next_state <= IDLE;
+               run_traffic <= '0';
+               load_seed_o <= '0';
+            END IF;
+         
+         WHEN INIT_MEM_WRITE =>
+            IF (end_addr_reached = '1' AND EYE_TEST = "FALSE") THEN
+               next_state <= TEST_MEM;
+               mode_load_o <= '1';
+               load_seed_o <= '1';
+               run_traffic <= '1';
+            ELSE
+               next_state <= INIT_MEM_WRITE;
+               run_traffic <= '1';
+               mode_load_o <= '0';
+               load_seed_o <= '0';
+               IF (EYE_TEST = "TRUE") THEN
+                  addr_mode <= FIXED_ADDR;
+               ELSIF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
+                  addr_mode <= "000";
+               ELSE
+                  addr_mode <= SEQUENTIAL_ADDR;
+               END IF;
+            END IF;
+         
+         WHEN INIT_MEM_READ =>
+            IF (end_addr_reached = '1') THEN
+               next_state <= TEST_MEM;
+               mode_load_o <= '1';
+               load_seed_o <= '1';
+            ELSE
+               next_state <= INIT_MEM_READ;
+               run_traffic <= '0';
+               mode_load_o <= '0';
+               load_seed_o <= '0';
+            END IF;
+         
+         WHEN TEST_MEM =>
+            IF (cmp_error = '1') THEN
+               next_state <= CMP_ERROR1;
+            ELSE
+               next_state <= TEST_MEM;
+            END IF;
+
+            run_traffic <= '1';
+
+
+            IF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") THEN
+               fixed_instr_o <= WR_INSTR;
+            ELSIF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") THEN
+               fixed_instr_o <= RD_INSTR;
+               
+            ELSIF (PORT_MODE = "RD_MODE") THEN
+               fixed_instr_o <= RD_INSTR;
+            ELSIF (PORT_MODE = "WR_MODE") THEN
+               fixed_instr_o <= WR_INSTR;
+            END IF;
+
+            if (FAMILY = "VIRTEX6") then
+              fixed_bl_o <= fix_bl_value; --"000010"; 2
+            else if ((data_mode_reg = "0111") and (FAMILY = "SPARTAN6")) then
+                   fixed_bl_o <= "000000";  -- 64  Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
+                 else
+                   fixed_bl_o <= fix_bl_value;
+                 end if; 
+            end if;
+
+            bl_mode_o_xhdl0 <= bl_mode_sel;
+            IF (bl_mode_o_xhdl0 = PRBS_BL_MODE) THEN
+               addr_mode <= PRBS_ADDR;
+            ELSE
+               addr_mode <= addr_mode_sel;
+            END IF;
+
+            IF (PORT_MODE = "BI_MODE") THEN
+               IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
+                  instr_mode_o <= BRAM_INSTR_MODE;
+               ELSE
+                  instr_mode_o  <= test_mem_instr_mode;
+                  --R_RP_W_WP_REF_INSTR_MODE;--FIXED_INSTR_MODE;--R_W_INSTR_MODE;--R_RP_W_WP_INSTR_MODE;--R_W_INSTR_MODE;
+                  --R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
+               END IF;      
+            ELSIF (PORT_MODE = "RD_MODE" OR PORT_MODE = "WR_MODE") THEN
+               instr_mode_o <= FIXED_INSTR_MODE;
+            END IF;
+         
+         WHEN CMP_ERROR1 =>
+            next_state <= CMP_ERROR1;
+            bl_mode_o_xhdl0 <= bl_mode_sel;
+            fixed_instr_o <= RD_INSTR;
+            addr_mode <= SEQUENTIAL_ADDR;
+            IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
+                  instr_mode_o <= BRAM_INSTR_MODE;
+            ELSE
+                  instr_mode_o  <= test_mem_instr_mode;
+               --R_W_INSTR_MODE;--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
+            END IF;
+            run_traffic <= '1';
+         
+         WHEN OTHERS =>
+            next_state <= IDLE;
+      END CASE;
+   END PROCESS;
+   
+   
+END trans;
+
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_flow_control.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_flow_control.vhd
new file mode 100755
index 0000000..123ba93
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_flow_control.vhd
@@ -0,0 +1,539 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_flow_control.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:40 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This module is the main flow control between cmd_gen.v, 
+--         write_data_path and read_data_path modules.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+
+ENTITY mcb_flow_control IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+      FAMILY          : STRING := "SPARTAN6"
+   );
+   PORT (
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      cmd_rdy_o       : OUT STD_LOGIC;
+      cmd_valid_i     : IN STD_LOGIC;
+      cmd_i           : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      mcb_cmd_full    : IN STD_LOGIC;
+      cmd_o           : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      addr_o          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bl_o            : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+      cmd_en_o        : OUT STD_LOGIC;
+      last_word_wr_i  : IN STD_LOGIC;
+      wdp_rdy_i       : IN STD_LOGIC;
+      wdp_valid_o     : OUT STD_LOGIC;
+      wdp_validB_o    : OUT STD_LOGIC;
+      wdp_validC_o    : OUT STD_LOGIC;
+      wr_addr_o       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      wr_bl_o         : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+      last_word_rd_i  : IN STD_LOGIC;
+      rdp_rdy_i       : IN STD_LOGIC;
+      rdp_valid_o     : OUT STD_LOGIC;
+      rd_addr_o       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      rd_bl_o         : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+   );
+END mcb_flow_control;
+
+ARCHITECTURE trans OF mcb_flow_control IS
+
+   constant    READY           : std_logic_vector(4 downto 0)  := "00001";
+   constant    READ            : std_logic_vector(4 downto 0)  := "00010";
+   constant    WRITE           : std_logic_vector(4 downto 0)  := "00100";
+   constant    CMD_WAIT        : std_logic_vector(4 downto 0)  := "01000";
+   constant    REFRESH_ST      : std_logic_vector(4 downto 0)  := "10000";
+      
+   constant    RD              : std_logic_vector(2 downto 0)  := "001";
+   constant    RDP             : std_logic_vector(2 downto 0)  := "011";
+   constant    WR              : std_logic_vector(2 downto 0)  := "000";
+   constant    WRP             : std_logic_vector(2 downto 0)  := "010";
+   constant    REFRESH         : std_logic_vector(2 downto 0)  := "100";
+   constant    NOP             : std_logic_vector(2 downto 0)  := "101";
+   
+   SIGNAL cmd_fifo_rdy      : STD_LOGIC;
+   SIGNAL cmd_rd            : STD_LOGIC;
+   SIGNAL cmd_wr            : STD_LOGIC;
+   SIGNAL cmd_others        : STD_LOGIC;
+   SIGNAL push_cmd          : STD_LOGIC;
+   SIGNAL xfer_cmd          : STD_LOGIC;
+   SIGNAL rd_vld            : STD_LOGIC;
+   SIGNAL wr_vld            : STD_LOGIC;
+   SIGNAL cmd_rdy           : STD_LOGIC;
+   SIGNAL cmd_reg           : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL addr_reg          : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL bl_reg            : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   
+   SIGNAL rdp_valid         : STD_LOGIC;
+   SIGNAL wdp_valid         : STD_LOGIC;
+   SIGNAL wdp_validB        : STD_LOGIC;
+   SIGNAL wdp_validC        : STD_LOGIC;
+   
+   SIGNAL current_state     : STD_LOGIC_VECTOR(4 DOWNTO 0);
+   SIGNAL next_state        : STD_LOGIC_VECTOR(4 DOWNTO 0);
+   SIGNAL tstpointA         : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL push_cmd_r        : STD_LOGIC;
+   SIGNAL wait_done         : STD_LOGIC;
+   SIGNAL cmd_en_r1         : STD_LOGIC;
+   SIGNAL wr_in_progress    : STD_LOGIC;
+   SIGNAL tst_cmd_rdy_o     : STD_LOGIC;
+   
+   SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
+   SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
+   
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL cmd_rdy_o_xhdl0   : STD_LOGIC;
+BEGIN
+   -- Drive referenced outputs
+   cmd_rdy_o <= cmd_rdy_o_xhdl0;
+   cmd_en_o <= cmd_en_r1;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         cmd_rdy_o_xhdl0 <= cmd_rdy;
+         tst_cmd_rdy_o <= cmd_rdy;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(8)) = '1') THEN
+            cmd_en_r1 <= '0' ;
+         ELSIF (xfer_cmd = '1') THEN
+            cmd_en_r1 <= '1' ;
+         ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
+            cmd_en_r1 <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(9)) = '1') THEN
+            cmd_fifo_rdy <= '1';
+         ELSIF (xfer_cmd = '1') THEN
+            cmd_fifo_rdy <= '0';
+         ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
+            cmd_fifo_rdy <= '1';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(9)) = '1') THEN
+            addr_o <= (others => '0');
+            cmd_o <= (others => '0');
+            bl_o <= (others => '0');
+         ELSIF (xfer_cmd = '1') THEN
+            addr_o <= addr_reg;
+            IF (FAMILY = "SPARTAN6") THEN
+               cmd_o <= cmd_reg;
+            ELSE
+               cmd_o <= ("00" & cmd_reg(0));
+            END IF;
+            bl_o <= bl_reg;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   wr_addr_o <= addr_i;
+   rd_addr_o <= addr_i;
+   rd_bl_o <= bl_i;
+   wr_bl_o <= bl_i;
+   wdp_valid_o <= wdp_valid;
+   wdp_validB_o <= wdp_validB;
+   wdp_validC_o <= wdp_validC;
+   rdp_valid_o <= rdp_valid;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(8)) = '1') THEN
+            wait_done <= '1' ;
+         ELSIF (push_cmd_r = '1') THEN
+            wait_done <= '1' ;
+         ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
+            wait_done <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         push_cmd_r <= push_cmd ;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (push_cmd = '1') THEN
+            cmd_reg <= cmd_i ;
+            addr_reg <= addr_i ;
+            bl_reg <= bl_i - "000001" ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
+             '0';                        
+   cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
+             '0';
+   cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
+                 '0';
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0)= '1') THEN
+            
+            cmd_wr_pending_r1 <= '0' ;
+         ELSIF (last_word_wr_i = '1') THEN
+            
+            cmd_wr_pending_r1 <= '1' ;
+         ELSIF (push_cmd = '1') THEN
+            cmd_wr_pending_r1 <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((cmd_rd AND push_cmd) = '1') THEN
+            cmd_rd_pending_r1 <= '1' ;
+         ELSIF (xfer_cmd = '1') THEN
+            
+            cmd_rd_pending_r1 <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0)= '1') THEN
+            wr_in_progress <= '0';
+         ELSIF (last_word_wr_i = '1') THEN
+            wr_in_progress <= '0';
+         ELSIF (current_state = WRITE) THEN
+            
+            wr_in_progress <= '1';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0)= '1') THEN
+            current_state <= "00001" ;
+         ELSE
+            current_state <= next_state ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
+   BEGIN
+      push_cmd <= '0';
+      
+      xfer_cmd <= '0';
+      wdp_valid <= '0';
+      wdp_validB <= '0';
+      
+      wdp_validC <= '0';
+      rdp_valid <= '0';
+      cmd_rdy <= '0';
+      next_state <= current_state;
+      CASE current_state IS
+         
+         WHEN READY =>
+            IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               xfer_cmd <= '0';
+               rdp_valid <= '1';
+
+            ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
+               next_state <= WRITE;
+               push_cmd <= '1';
+               wdp_valid <= '1';
+               wdp_validB <= '1';
+               wdp_validC <= '1';
+
+            ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
+               next_state <= REFRESH_ST;
+               push_cmd <= '1';
+               xfer_cmd <= '0';
+
+            ELSE
+               next_state <= READY;
+               push_cmd <= '0';
+            END IF;
+
+            IF (cmd_fifo_rdy = '1') THEN
+               cmd_rdy <= '1';
+            ELSE
+               cmd_rdy <= '0';
+            END IF;
+
+         WHEN REFRESH_ST =>
+            IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               rdp_valid <= '1';
+               wdp_valid <= '0';
+               xfer_cmd <= '1';
+               
+            ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
+               next_state <= WRITE;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               
+               wdp_valid     <= '1';
+               wdp_validB    <= '1';
+               wdp_validC    <= '1';               
+             
+            ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+
+            ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
+               next_state <= CMD_WAIT;
+               tstpointA  <= "1001";
+
+            ELSE
+               next_state <= READ; 
+
+            END IF;
+               
+            IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
+              cmd_rdy <= '1';
+            ELSE 
+              cmd_rdy <= '0';
+            END IF;
+
+         WHEN READ =>
+            IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               rdp_valid <= '1';
+               wdp_valid <= '0';
+               xfer_cmd <= '1';
+               tstpointA <= "0101";
+            ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
+               next_state <= WRITE;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               wdp_valid <= '1';
+               wdp_validB <= '1';
+               wdp_validC <= '1';
+               tstpointA <= "0110";
+            ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '0';
+               xfer_cmd <= '0';
+               tstpointA <= "0111";
+               wdp_valid <= '0';
+               wdp_validB <= '0';
+               wdp_validC <= '0';
+               rdp_valid <= '0';
+            ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
+               next_state <= REFRESH_ST;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               wdp_valid <= '0';
+               wdp_validB <= '0';
+               wdp_validC <= '0';
+               rdp_valid <= '0';
+               tstpointA <= "1000";
+            ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
+               next_state <= CMD_WAIT;
+               tstpointA <= "1001";
+            ELSE
+               next_state <= READ;
+            END IF;
+
+            IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
+             cmd_rdy <= wait_done; --'1';
+            ELSE
+               cmd_rdy <= '0';
+            END IF;
+         
+         WHEN WRITE =>
+            IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               rdp_valid <= '1';
+               tstpointA <= "0000";
+            ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
+               next_state <= WRITE;
+               tstpointA <= "0001";
+               IF ((cmd_wr AND last_word_wr_i) = '1') THEN
+                  wdp_valid <= '1';
+                  wdp_validB <= '1';
+                  wdp_validC <= '1';
+               ELSE
+                  wdp_valid <= '0';
+                  wdp_validB <= '0';
+                  wdp_validC <= '0';
+               END IF;
+               IF (last_word_wr_i = '1') THEN
+                  push_cmd <= '1';
+                  xfer_cmd <= '1';
+               ELSE
+                  push_cmd <= '0';
+                  xfer_cmd <= '0';
+               END IF;
+            ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
+               next_state <= REFRESH_ST;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               tstpointA <= "0010";
+               wdp_valid <= '0';
+               wdp_validB <= '0';
+               wdp_validC <= '0';
+               rdp_valid <= '0';
+            ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
+               next_state <= CMD_WAIT;
+               push_cmd <= '0';
+               xfer_cmd <= '0';
+               tstpointA <= "0011";
+            ELSE
+               next_state <= WRITE;
+               tstpointA <= "0100";
+            END IF;
+            IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
+               cmd_rdy <= wait_done;
+            ELSE
+               cmd_rdy <= '0';
+            END IF;
+         
+         WHEN CMD_WAIT =>
+            IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
+               next_state <= CMD_WAIT;
+               cmd_rdy <= '0';
+               tstpointA <= "1010";
+            ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               cmd_rdy <= '1';
+               rdp_valid <= '1';
+               tstpointA <= "1011";
+            ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
+               next_state <= WRITE;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               wdp_valid <= '1';
+               wdp_validB <= '1';
+               wdp_validC <= '1';
+               cmd_rdy <= '1';
+               tstpointA <= "1100";
+            ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
+               next_state <= REFRESH_ST;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               tstpointA <= "1101";
+               cmd_rdy <= '1';
+            ELSE
+               next_state <= CMD_WAIT;
+               tstpointA <= "1110";
+               IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
+                  cmd_rdy <= '1';
+               ELSE
+                  cmd_rdy <= '0';
+               END IF;
+            END IF;
+         
+         WHEN OTHERS =>
+            push_cmd <= '0';
+            xfer_cmd <= '0';
+            wdp_valid <= '0';
+            wdp_validB <= '0';
+            wdp_validC <= '0';
+            next_state <= READY;
+      END CASE;
+   END PROCESS;
+   
+   
+END trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd
new file mode 100755
index 0000000..bb23d62
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd
@@ -0,0 +1,1001 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_traffic_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR
+-- Purpose: This is top level module of memory traffic generator which can
+--         generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
+--         hard memory controller core.
+-- Reference:
+-- Revision History:      2009      Brought out internal signals cmp_data and cmp_error as outputs.
+--                        2010/01/09  Removed the rd_mdata_afull_set term in signal rdpath_data_valid_i .
+--                        2010/05/03  Removed local generated version of  mcb_rd_empty and mcb_wr_full in TG.
+--                        2010/05/20  If MEM_BURST_LEN value is passed with value of zero, it is treated as
+--                                    "OTF" Burst Mode and TG will only generate BL 8 traffic.
+
+--*****************************************************************************
+
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+ENTITY mcb_traffic_gen IS
+   GENERIC (
+      TCQ                   : TIME := 100 ps;
+      FAMILY                : STRING := "SPARTAN6";
+      SIMULATION            : STRING := "FALSE";
+      MEM_BURST_LEN         : INTEGER := 8;
+      PORT_MODE             : STRING := "BI_MODE";
+      DATA_PATTERN          : STRING := "DGEN_ADDR";
+      CMD_PATTERN           : STRING := "CGEN_ALL";
+
+      ADDR_WIDTH            : INTEGER := 30;
+
+      CMP_DATA_PIPE_STAGES  : INTEGER := 0;
+
+      MEM_COL_WIDTH         : INTEGER := 10;
+      NUM_DQ_PINS           : INTEGER := 16;
+      DQ_ERROR_WIDTH        : integer := 1;
+
+      SEL_VICTIM_LINE       : INTEGER := 3;
+      DWIDTH                : INTEGER := 32;
+
+      EYE_TEST              : STRING  := "FALSE";
+
+
+      PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+      PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00005000"
+   );
+   PORT (
+
+      clk_i                 : IN STD_LOGIC;
+      rst_i                 : IN STD_LOGIC;
+      run_traffic_i         : IN STD_LOGIC;
+      manual_clear_error    : IN STD_LOGIC;
+      start_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      end_addr_i            : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmd_seed_i            : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      data_seed_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      load_seed_i           : IN STD_LOGIC;
+
+      addr_mode_i           : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+
+      instr_mode_i          : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+      bl_mode_i             : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+      data_mode_i           : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+      mode_load_i           : IN STD_LOGIC;
+
+      fixed_bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      fixed_instr_i         : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+
+      fixed_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      fixed_data_i          : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0) := (others => '0');
+      bram_cmd_i            : IN STD_LOGIC_VECTOR(38 DOWNTO 0);
+      bram_valid_i          : IN STD_LOGIC;
+      bram_rdy_o            : OUT STD_LOGIC;
+
+      mcb_cmd_en_o          : OUT STD_LOGIC;
+      mcb_cmd_instr_o       : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      mcb_cmd_addr_o        : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      mcb_cmd_bl_o          : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+      mcb_cmd_full_i        : IN STD_LOGIC;
+
+      mcb_wr_en_o           : OUT STD_LOGIC;
+      mcb_wr_data_o         : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      mcb_wr_data_end_o     : OUT STD_LOGIC;
+      mcb_wr_mask_o         : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
+
+      mcb_wr_full_i         : IN STD_LOGIC;
+      mcb_wr_fifo_counts    : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+      mcb_rd_en_o           : OUT STD_LOGIC;
+      mcb_rd_data_i         : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      mcb_rd_empty_i        : IN STD_LOGIC;
+      mcb_rd_fifo_counts    : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      counts_rst            : IN STD_LOGIC;
+      wr_data_counts        : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+      rd_data_counts        : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+
+      error                 : OUT STD_LOGIC;
+      cmp_data_valid        : OUT STD_LOGIC;
+
+      error_status          : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
+      cmp_error             : out std_logic;
+      cmp_data              : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
+      mem_rd_data           : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
+      dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
+      cumlative_dq_lane_error  :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
+
+
+   );
+END mcb_traffic_gen;
+
+ARCHITECTURE trans OF mcb_traffic_gen IS
+   COMPONENT mcb_flow_control IS
+     GENERIC (
+         TCQ             : TIME   := 100 ps;
+         FAMILY                         : string := "SPARTAN6"
+      );
+      PORT (
+         clk_i                 : IN STD_LOGIC;
+         rst_i                 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+         cmd_rdy_o             : OUT STD_LOGIC;
+         cmd_valid_i           : IN STD_LOGIC;
+         cmd_i                 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         addr_i                : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         bl_i                  : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+         mcb_cmd_full          : IN STD_LOGIC;
+         cmd_o                 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+         addr_o                : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         bl_o                  : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+         cmd_en_o              : OUT STD_LOGIC;
+         last_word_wr_i        : IN STD_LOGIC;
+         wdp_rdy_i             : IN STD_LOGIC;
+         wdp_valid_o           : OUT STD_LOGIC;
+         wdp_validB_o          : OUT STD_LOGIC;
+         wdp_validC_o          : OUT STD_LOGIC;
+         wr_addr_o             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         wr_bl_o               : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+         last_word_rd_i        : IN STD_LOGIC;
+         rdp_rdy_i             : IN STD_LOGIC;
+         rdp_valid_o           : OUT STD_LOGIC;
+         rd_addr_o             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         rd_bl_o               : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+      );
+   END COMPONENT;
+
+   COMPONENT cmd_gen IS
+      GENERIC (
+         TCQ             : TIME   := 100 ps;
+         PORT_MODE            : STRING  := "BI_MODE";
+         FAMILY                : STRING := "SPARTAN6";
+         MEM_BURST_LEN         : INTEGER := 8;
+         NUM_DQ_PINS           : INTEGER := 8;
+         DATA_PATTERN          : STRING := "DGEN_PRBS";
+         CMD_PATTERN           : STRING := "CGEN_ALL";
+         ADDR_WIDTH            : INTEGER := 30;
+         DWIDTH                : INTEGER := 32;
+         PIPE_STAGES           : INTEGER := 0;
+         MEM_COL_WIDTH         : INTEGER := 10;
+         PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+         PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+         PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+         PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00005000"
+      );
+      PORT (
+         clk_i                 : IN STD_LOGIC;
+         rst_i                 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+         run_traffic_i         : IN STD_LOGIC;
+         rd_buff_avail_i       : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+         force_wrcmd_gen_i     : IN STD_LOGIC;
+         start_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         end_addr_i            : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         cmd_seed_i            : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         data_seed_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         load_seed_i           : IN STD_LOGIC;
+         addr_mode_i           : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         data_mode_i           : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+         instr_mode_i          : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+         bl_mode_i             : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+         mode_load_i           : IN STD_LOGIC;
+         fixed_bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+         fixed_instr_i         : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         fixed_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         bram_addr_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         bram_instr_i          : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         bram_bl_i             : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+         bram_valid_i          : IN STD_LOGIC;
+         bram_rdy_o            : OUT STD_LOGIC;
+         reading_rd_data_i     : IN STD_LOGIC;
+         rdy_i                 : IN STD_LOGIC;
+         addr_o                : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         instr_o               : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+         bl_o                  : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+--         m_addr_o              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         cmd_o_vld             : OUT STD_LOGIC
+      );
+   END COMPONENT;
+
+
+   component afifo IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+      DSIZE       : INTEGER := 32;
+      FIFO_DEPTH  : INTEGER := 16;
+      ASIZE       : INTEGER := 4;
+      SYNC        : INTEGER := 1
+   );
+   PORT (
+      wr_clk      : IN STD_LOGIC;
+      rst         : IN STD_LOGIC;
+      wr_en       : IN STD_LOGIC;
+      wr_data     : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      rd_en       : IN STD_LOGIC;
+      rd_clk      : IN STD_LOGIC;
+      rd_data     : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      full        : OUT STD_LOGIC;
+      almost_full : OUT STD_LOGIC;
+      empty       : OUT STD_LOGIC
+   );
+END component;
+
+component read_data_path IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+
+      FAMILY                : STRING := "SPARTAN6";
+      MEM_BURST_LEN         : INTEGER := 8;
+      ADDR_WIDTH            : INTEGER := 32;
+      CMP_DATA_PIPE_STAGES  : INTEGER := 3;
+      DWIDTH                : INTEGER := 32;
+      DATA_PATTERN          : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
+      NUM_DQ_PINS           : INTEGER := 8;
+      DQ_ERROR_WIDTH        : INTEGER := 1;
+      SEL_VICTIM_LINE       : integer := 3;
+      MEM_COL_WIDTH         : INTEGER := 10
+   );
+   PORT (
+
+      clk_i                 : IN STD_LOGIC;
+      rst_i                 : in std_logic_vector(9 downto 0);
+      manual_clear_error    : IN STD_LOGIC;
+      cmd_rdy_o             : OUT STD_LOGIC;
+      cmd_valid_i           : IN STD_LOGIC;
+      prbs_fseed_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+      data_mode_i           : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      cmd_sent              : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      bl_sent               : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      cmd_en_i              : IN STD_LOGIC;
+--      m_addr_i              : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      fixed_data_i          : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
+
+      addr_i                : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bl_i                  : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+      data_rdy_o            : OUT STD_LOGIC;
+      data_valid_i          : IN STD_LOGIC;
+      data_i                : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      last_word_rd_o        : OUT STD_LOGIC;
+      data_error_o          : OUT STD_LOGIC;
+      cmp_data_o            : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      rd_mdata_o            : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      cmp_data_valid        : OUT STD_LOGIC;
+      cmp_addr_o            : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+      cmp_bl_o              : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+      force_wrcmd_gen_o              : out std_logic;
+      rd_buff_avail_o                : out std_logic_vector(6 downto 0);
+      dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
+      cumlative_dq_lane_error_r  :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
+
+
+   );
+END component;
+
+component write_data_path IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+      FAMILY          : STRING := "SPARTAN6";
+      MEM_BURST_LEN   : INTEGER := 8;
+      ADDR_WIDTH      : INTEGER := 32;
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_ALL";
+      NUM_DQ_PINS     : INTEGER := 8;
+      SEL_VICTIM_LINE : INTEGER := 3;
+      MEM_COL_WIDTH   : INTEGER := 10;
+      EYE_TEST        : string := "FALSE"
+   );
+   PORT (
+
+      clk_i           : IN STD_LOGIC;
+      rst_i           : in std_logic_vector(9 downto 0);
+      cmd_rdy_o       : OUT STD_LOGIC;
+      cmd_valid_i     : IN STD_LOGIC;
+      cmd_validB_i    : IN STD_LOGIC;
+      cmd_validC_i    : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+--      m_addr_i        : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      fixed_data_i          : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
+
+      addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      data_valid_o    : OUT STD_LOGIC;
+      last_word_wr_o  : OUT STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      data_mask_o     : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
+      data_wr_end_o   : out std_logic
+   );
+END component;
+
+component tg_status IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+      DWIDTH          : INTEGER := 32
+   );
+   PORT (
+
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      manual_clear_error : IN STD_LOGIC;
+      data_error_i    : IN STD_LOGIC;
+      cmp_data_i      : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      rd_data_i       : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      cmp_addr_i      : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmp_bl_i        : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      mcb_cmd_full_i  : IN STD_LOGIC;
+      mcb_wr_full_i   : IN STD_LOGIC;
+      mcb_rd_empty_i  : IN STD_LOGIC;
+      error_status    : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
+      error           : OUT STD_LOGIC
+   );
+
+
+END component;
+
+   attribute KEEP                 : STRING;
+   attribute MAX_FANOUT           : STRING;
+
+
+function MEM_BLENGTH return integer is
+  begin
+    if (MEM_BURST_LEN = 4) then
+      return 4;
+    elsif (MEM_BURST_LEN = 8) then
+      return 8;
+    else
+      return 8;
+    end if;
+  end function MEM_BLENGTH;
+
+   
+   constant MEM_BLEN : INTEGER := MEM_BLENGTH;
+
+   SIGNAL mcb_wr_en               : STD_LOGIC;
+   SIGNAL cmd2flow_valid          : STD_LOGIC;
+   SIGNAL cmd2flow_cmd            : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL cmd2flow_addr           : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL cmd2flow_bl             : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL last_word_rd            : STD_LOGIC;
+   SIGNAL last_word_wr            : STD_LOGIC;
+   SIGNAL flow2cmd_rdy            : STD_LOGIC;
+   SIGNAL wr_addr                 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL rd_addr                 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL wr_bl                   : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL rd_bl                   : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL run_traffic_reg         : STD_LOGIC;
+   SIGNAL wr_validB               : STD_LOGIC;
+   SIGNAL wr_valid                : STD_LOGIC;
+   SIGNAL wr_validC               : STD_LOGIC;
+   SIGNAL bram_addr_i             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL bram_instr_i            : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL bram_bl_i               : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL AC2_G_E2                : STD_LOGIC;
+   SIGNAL AC1_G_E1                : STD_LOGIC;
+   SIGNAL AC3_G_E3                : STD_LOGIC;
+   SIGNAL upper_end_matched       : STD_LOGIC;
+   SIGNAL end_boundary_addr       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+   SIGNAL lower_end_matched       : STD_LOGIC;
+   SIGNAL addr_o                  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--   SIGNAL m_addr                  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL dcount_rst              : STD_LOGIC;
+   SIGNAL rd_addr_error           : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL rd_rdy                  : STD_LOGIC;
+   SIGNAL cmp_error_int               : STD_LOGIC;
+   SIGNAL cmd_full                : STD_LOGIC;
+
+   SIGNAL cmp_data_int                : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+   SIGNAL mem_rd_data_i             : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+   SIGNAL cmp_addr                : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL cmp_bl                  : STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+   SIGNAL rst_ra                  : STD_LOGIC_VECTOR(9 DOWNTO 0);
+   SIGNAL rst_rb                  : STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+   SIGNAL mcb_wr_full_r1          : STD_LOGIC;
+   SIGNAL mcb_wr_full_r2          : STD_LOGIC;
+   SIGNAL mcb_rd_empty_r          : STD_LOGIC;
+   SIGNAL force_wrcmd_gen         : STD_LOGIC;
+   SIGNAL rd_buff_avail           : STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+   SIGNAL data_mode_r_a           : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL data_mode_r_b           : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL data_mode_r_c           : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL tmp_address             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL error_access_range      : STD_LOGIC ;
+
+   SIGNAL mcb_rd_empty            : STD_LOGIC;
+
+   SIGNAL mcb_wr_full             : STD_LOGIC;
+
+   SIGNAL end_addr_r              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+   SIGNAL wr_rdy                  : STD_LOGIC;
+
+   SIGNAL rd_valid                : STD_LOGIC;
+
+   SIGNAL cmd_rd_en               : STD_LOGIC;
+   -- X-HDL generated signals
+
+   SIGNAL xhdl14 : STD_LOGIC_VECTOR(37 DOWNTO 0);
+   SIGNAL xhdl15 : STD_LOGIC_VECTOR(32 DOWNTO 0);
+   SIGNAL xhdl17 : STD_LOGIC;
+   SIGNAL xhdl19 : STD_LOGIC;
+   SIGNAL ZEROS  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL bram_rdy_o_xhdl0        : STD_LOGIC;
+   SIGNAL mcb_cmd_en_o_xhdl5      : STD_LOGIC;
+   SIGNAL mcb_cmd_instr_o_xhdl6   : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL mcb_cmd_addr_o_xhdl3    : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+   SIGNAL mcb_cmd_bl_o_xhdl4      : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL mcb_wr_data_o_xhdl9     : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+   SIGNAL mcb_wr_data_end_o_xhdl8 : STD_LOGIC;
+   SIGNAL mcb_wr_mask_o_xhdl10    : STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
+   SIGNAL mcb_rd_en       : STD_LOGIC;
+   SIGNAL wr_data_counts_xhdl12   : STD_LOGIC_VECTOR(47 DOWNTO 0);
+   SIGNAL rd_data_counts_xhdl11   : STD_LOGIC_VECTOR(47 DOWNTO 0);
+   SIGNAL error_xhdl1             : STD_LOGIC;
+   SIGNAL error_status_xhdl2      : STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
+
+   SIGNAL cmd_fifo_wr             : STD_LOGIC;
+   SIGNAL xfer_addr               : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL fifo_error              : STD_LOGIC;
+   SIGNAL cmd_fifo_rd             : STD_LOGIC;
+   SIGNAL cmd_fifo_empty          : STD_LOGIC;
+   SIGNAL xfer_cmd_bl             : STD_LOGIC;
+   SIGNAL cmd_fifo_full           : STD_LOGIC;
+   SIGNAL rd_mdata_afull_set      :  STD_LOGIC;
+   SIGNAL rd_mdata_fifo_afull     :  STD_LOGIC;
+   SIGNAL rdpath_data_valid_i : STD_LOGIC;
+   SIGNAL rdpath_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+    SIGNAL rd_mdata_fifo_empty : STD_LOGIC;
+   SIGNAL rd_v6_mdata             : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+   SIGNAL mdata_wren              : STD_LOGIC;
+   attribute KEEP            of rst_ra : signal is "TRUE";
+   attribute KEEP            of rst_rb : signal is "TRUE";
+   attribute KEEP            of mcb_wr_full_r1 : signal is "TRUE";
+   attribute KEEP            of mcb_wr_full_r2 : signal is "TRUE";
+   attribute MAX_FANOUT      of rst_ra : signal is "20";
+   attribute MAX_FANOUT      of rst_rb : signal is "20";
+
+
+BEGIN
+
+
+   mem_rd_data <= mem_rd_data_i;
+   ZEROS <= (others => '0');
+
+   cmp_data <= cmp_data_int;
+   cmp_error <= cmp_error_int;
+   -- Drive referenced outputs
+   bram_rdy_o <= bram_rdy_o_xhdl0;
+   mcb_cmd_en_o <= mcb_cmd_en_o_xhdl5;
+   mcb_cmd_instr_o <= mcb_cmd_instr_o_xhdl6;
+   mcb_cmd_addr_o <= mcb_cmd_addr_o_xhdl3;
+   mcb_cmd_bl_o <= mcb_cmd_bl_o_xhdl4;
+   mcb_wr_data_o <= mcb_wr_data_o_xhdl9;
+   mcb_wr_data_end_o <= mcb_wr_data_end_o_xhdl8;
+   mcb_wr_mask_o <= mcb_wr_mask_o_xhdl10;
+   mcb_rd_en_o <= mcb_rd_en;
+   wr_data_counts <= wr_data_counts_xhdl12;
+   rd_data_counts <= std_logic_vector(rd_data_counts_xhdl11);
+   error <= error_xhdl1;
+   error_status <= error_status_xhdl2;
+   tmp_address <= std_logic_vector(to_unsigned((to_integer(unsigned(mcb_cmd_addr_o_xhdl3)) + to_integer(unsigned(mcb_cmd_bl_o_xhdl4)) * (DWIDTH / 8)),32));
+--   tmp_address <= ("00" & mcb_cmd_addr_o_xhdl3 + ("000000000000000000000000" & mcb_cmd_bl_o_xhdl4 * to_stdlogicvector(DWIDTH, 6) / "001000"));
+
+--synthesis translate_off
+   PROCESS
+   BEGIN
+     IF ((MEM_BURST_LEN /= 4) AND (MEM_BURST_LEN /= 8)) THEN
+       report "Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!";
+       report "If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic.";
+       
+     END IF;
+     WAIT;
+   END PROCESS;
+
+   PROCESS (mcb_cmd_en_o_xhdl5, mcb_cmd_addr_o_xhdl3, mcb_cmd_bl_o_xhdl4, end_addr_i,tmp_address)
+   BEGIN
+      IF (mcb_cmd_en_o_xhdl5 = '1' AND (tmp_address > end_addr_i)) THEN
+         report "Error ! Data access beyond address range"; -- severity ERROR;
+         error_access_range <= '1';
+         -- $stop();
+      END IF;
+   END PROCESS;
+--synthesis translate_on
+
+    mcb_rd_empty <= mcb_rd_empty_i;
+
+    mcb_wr_full <= mcb_wr_full_i;
+
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         data_mode_r_a <= data_mode_i;
+         data_mode_r_b <= data_mode_i;
+         data_mode_r_c <= data_mode_i;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_ra(0)) = '1') THEN
+            mcb_wr_full_r1 <= '0';
+         ELSIF (mcb_wr_fifo_counts >= "0111111") THEN
+            mcb_wr_full_r1 <= '1';
+            mcb_wr_full_r2 <= '1';
+         ELSE
+            mcb_wr_full_r1 <= '0';
+            mcb_wr_full_r2 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_ra(0)) = '1') THEN
+            mcb_rd_empty_r <= '1';
+         ELSIF (mcb_rd_fifo_counts <= "0000001") THEN
+            mcb_rd_empty_r <= '1';
+         ELSE
+            mcb_rd_empty_r <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         rst_ra <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
+         rst_rb <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         run_traffic_reg <= run_traffic_i;
+      END IF;
+   END PROCESS;
+
+   bram_addr_i <= (bram_cmd_i(29 DOWNTO 0) & "00");
+   bram_instr_i <= bram_cmd_i(32 DOWNTO 30);
+   bram_bl_i(5 DOWNTO 0) <= bram_cmd_i(38 DOWNTO 33);
+   dcount_rst <= counts_rst OR rst_ra(0);
+
+
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') then
+      IF (dcount_rst = '1') THEN
+         wr_data_counts_xhdl12 <= (OTHERS => '0');
+      ELSIF (mcb_wr_en = '1') THEN
+            wr_data_counts_xhdl12 <= wr_data_counts_xhdl12 + std_logic_vector(to_unsigned(DWIDTH/8,48));
+      END IF;
+      end if;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+     IF (clk_i'EVENT AND clk_i = '1') then
+      IF (dcount_rst = '1') THEN
+         rd_data_counts_xhdl11 <= (others => '0');
+      ELSIF (mcb_rd_en = '1') THEN
+            rd_data_counts_xhdl11 <= rd_data_counts_xhdl11 + std_logic_vector(to_unsigned(DWIDTH/8,48));
+      END IF;
+    end if;
+   END PROCESS;
+
+   xhdl13 : IF (SIMULATION = "TRUE") GENERATE
+      cmd_fifo_wr <= flow2cmd_rdy AND cmd2flow_valid;
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (mcb_cmd_en_o_xhdl5 = '1') THEN
+                       if (xfer_addr /= (ZEROS(31 downto ADDR_WIDTH) & mcb_cmd_addr_o_xhdl3)) then
+                  fifo_error <= '1';
+               ELSE
+                  fifo_error <= '0';
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+      cmd_fifo_rd <= mcb_cmd_en_o_xhdl5 AND NOT(mcb_cmd_full_i) AND NOT(cmd_fifo_empty);
+
+
+      xhdl14 <= (cmd2flow_bl & cmd2flow_addr);
+      xfer_cmd_bl <= xhdl15(32);
+           xfer_addr  <= xhdl15(31 downto 0);
+      cmd_fifo : afifo
+         GENERIC MAP (
+            TCQ                   => TCQ,
+            DSIZE       => 38,
+            FIFO_DEPTH  => 16,
+            ASIZE       => 4,
+            SYNC        => 1
+         )
+         PORT MAP (
+            wr_clk   => clk_i,
+            rst      => rst_ra(0),
+            wr_en    => cmd_fifo_wr,
+            wr_data  => xhdl14,
+            rd_en    => cmd_fifo_rd,
+            rd_clk   => clk_i,
+            rd_data  => xhdl15,
+            full     => cmd_fifo_full,
+            almost_full => open,
+            empty    => cmd_fifo_empty
+         );
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            end_addr_r <= end_addr_i;
+         END IF;
+   END PROCESS;
+
+
+
+   u_c_gen : cmd_gen
+      GENERIC MAP (
+         TCQ                   => TCQ,
+         FAMILY               => FAMILY,
+         PORT_MODE            => PORT_MODE,
+         MEM_BURST_LEN        => MEM_BLEN,
+         NUM_DQ_PINS          => NUM_DQ_PINS,
+         DATA_PATTERN         => DATA_PATTERN,
+         CMD_PATTERN          => CMD_PATTERN,
+         ADDR_WIDTH           => ADDR_WIDTH,
+         DWIDTH               => DWIDTH,
+         MEM_COL_WIDTH        => MEM_COL_WIDTH,
+         PRBS_EADDR_MASK_POS  => PRBS_EADDR_MASK_POS,
+         PRBS_SADDR_MASK_POS  => PRBS_SADDR_MASK_POS,
+         PRBS_EADDR           => PRBS_EADDR,
+         PRBS_SADDR           => PRBS_SADDR
+      )
+      PORT MAP (
+         clk_i              => clk_i,
+         rst_i              => rst_ra,
+         rd_buff_avail_i    => rd_buff_avail,
+         reading_rd_data_i  => mcb_rd_en,
+         force_wrcmd_gen_i  => force_wrcmd_gen,
+         run_traffic_i      => run_traffic_reg,
+         start_addr_i       => start_addr_i,
+         end_addr_i         => end_addr_r,
+         cmd_seed_i         => cmd_seed_i,
+         data_seed_i        => data_seed_i,
+         load_seed_i        => load_seed_i,
+         addr_mode_i        => addr_mode_i,
+         data_mode_i        => data_mode_r_a,
+         instr_mode_i       => instr_mode_i,
+         bl_mode_i          => bl_mode_i,
+         mode_load_i        => mode_load_i,
+         fixed_bl_i         => fixed_bl_i,
+         fixed_addr_i       => fixed_addr_i,
+         fixed_instr_i      => fixed_instr_i,
+         bram_addr_i        => bram_addr_i,
+         bram_instr_i       => bram_instr_i,
+         bram_bl_i          => bram_bl_i,
+         bram_valid_i       => bram_valid_i,
+         bram_rdy_o         => bram_rdy_o_xhdl0,
+         rdy_i              => flow2cmd_rdy,
+         instr_o            => cmd2flow_cmd,
+         addr_o             => cmd2flow_addr,
+         bl_o               => cmd2flow_bl,
+--         m_addr_o           => m_addr,
+         cmd_o_vld          => cmd2flow_valid
+      );
+   mcb_cmd_addr_o_xhdl3 <= addr_o(ADDR_WIDTH - 1 DOWNTO 0);
+   cmd_full <= mcb_cmd_full_i;
+
+
+   mcb_control : mcb_flow_control
+      GENERIC MAP (
+         TCQ                   => TCQ,
+         FAMILY  => FAMILY
+      )
+      PORT MAP (
+         clk_i           => clk_i,
+         rst_i           => rst_ra,
+         cmd_rdy_o       => flow2cmd_rdy,
+         cmd_valid_i     => cmd2flow_valid,
+         cmd_i           => cmd2flow_cmd,
+         addr_i          => cmd2flow_addr,
+         bl_i            => cmd2flow_bl,
+         mcb_cmd_full    => cmd_full,
+         cmd_o           => mcb_cmd_instr_o_xhdl6,
+         addr_o          => addr_o,
+         bl_o            => mcb_cmd_bl_o_xhdl4,
+         cmd_en_o        => mcb_cmd_en_o_xhdl5,
+         last_word_wr_i  => last_word_wr,
+         wdp_rdy_i       => wr_rdy,
+         wdp_valid_o     => wr_valid,
+         wdp_validB_o    => wr_validB,
+         wdp_validC_o    => wr_validC,
+         wr_addr_o       => wr_addr,
+         wr_bl_o         => wr_bl,
+         last_word_rd_i  => last_word_rd,
+         rdp_rdy_i       => rd_rdy,
+         rdp_valid_o     => rd_valid,
+         rd_addr_o       => rd_addr,
+         rd_bl_o         => rd_bl
+      );
+
+     mdata_wren <= not mcb_rd_empty; 
+
+      rd_mdata_fifo : afifo
+         GENERIC MAP (
+            TCQ                   => TCQ,
+            DSIZE       => DWIDTH,
+            FIFO_DEPTH  => 32,
+            ASIZE       => 5,
+            SYNC        => 1
+         )
+         PORT MAP (
+            wr_clk   => clk_i,
+            rst      => rst_rb(0),
+            wr_en    => mdata_wren,
+            wr_data  => mcb_rd_data_i,
+            rd_en    => mcb_rd_en,
+            rd_clk   => clk_i,
+            rd_data  => rd_v6_mdata,
+            full     => open,
+            almost_full => open,
+            empty    => rd_mdata_fifo_empty
+         );
+
+
+
+   cmd_rd_en <= NOT(mcb_cmd_full_i) AND mcb_cmd_en_o_xhdl5;
+
+  PROCESS (clk_i)
+  BEGIN
+  IF (clk_i'EVENT AND clk_i = '1') THEN  
+   IF (rst_rb(0) = '1') THEN
+       rd_mdata_afull_set <= '0';
+    ELSIF (rd_mdata_fifo_afull = '1') THEN
+       rd_mdata_afull_set <= '1';
+    END IF;
+  END IF;
+  END PROCESS;
+
+
+  PROCESS(rd_mdata_fifo_empty,rd_mdata_afull_set,mcb_rd_empty)
+  BEGIN
+  
+  IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
+       rdpath_data_valid_i <= not(rd_mdata_fifo_empty);
+  ELSE
+       rdpath_data_valid_i <= not(mcb_rd_empty);
+  
+  END IF;
+  END PROCESS;
+  
+  PROCESS(rd_v6_mdata,mcb_rd_data_i)
+  BEGIN
+  
+  IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
+       rdpath_rd_data_i <= rd_v6_mdata;
+  ELSE
+       rdpath_rd_data_i <= mcb_rd_data_i;
+  
+  END IF;
+  END PROCESS;
+
+   RD_PATH : IF (PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE") GENERATE
+
+      xhdl17 <= NOT(mcb_rd_empty);
+      read_data_path_inst : read_data_path
+         GENERIC MAP (
+            TCQ                   => TCQ,
+            family                => FAMILY,
+            MEM_BURST_LEN         => MEM_BLEN,
+            cmp_data_pipe_stages  => CMP_DATA_PIPE_STAGES,
+            addr_width            => ADDR_WIDTH,
+            sel_victim_line       => SEL_VICTIM_LINE,
+            data_pattern          => DATA_PATTERN,
+            dwidth                => DWIDTH,
+            num_dq_pins           => NUM_DQ_PINS,
+            DQ_ERROR_WIDTH        => DQ_ERROR_WIDTH,
+            mem_col_width         => MEM_COL_WIDTH
+         )
+         PORT MAP (
+            clk_i              => clk_i,
+            rst_i              => rst_rb,
+            manual_clear_error => manual_clear_error,
+            cmd_rdy_o          => rd_rdy,
+            cmd_valid_i        => rd_valid,
+            prbs_fseed_i       => data_seed_i,
+            cmd_sent           => mcb_cmd_instr_o_xhdl6,
+            bl_sent            => mcb_cmd_bl_o_xhdl4,
+            cmd_en_i           => cmd_rd_en,
+            data_mode_i        => data_mode_r_b,
+            last_word_rd_o     => last_word_rd,
+--            m_addr_i           => m_addr,
+            fixed_data_i       => fixed_data_i,
+
+            addr_i             => rd_addr,
+            bl_i               => rd_bl,
+            data_rdy_o         => mcb_rd_en,
+            data_valid_i       => rdpath_data_valid_i,
+            data_i             => rdpath_rd_data_i,
+            data_error_o       => cmp_error_int,
+            cmp_data_o         => cmp_data_int,
+            rd_mdata_o         => mem_rd_data_i,
+            cmp_data_valid     => cmp_data_valid,
+            cmp_addr_o         => cmp_addr,
+            cmp_bl_o           => cmp_bl,
+            force_wrcmd_gen_o  => force_wrcmd_gen,
+            rd_buff_avail_o    => rd_buff_avail,
+            dq_error_bytelane_cmp      => dq_error_bytelane_cmp,
+            cumlative_dq_lane_error_r  => cumlative_dq_lane_error
+         );
+   END GENERATE;
+  
+   write_only_path_inst: IF ( NOT(PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE")) GENERATE
+
+      cmp_error_int <= '0';
+   END GENERATE;
+
+   xhdl18 : IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") GENERATE
+
+      xhdl19        <= NOT(mcb_wr_full);
+      write_data_path_inst : write_data_path
+         GENERIC MAP (
+            TCQ                   => TCQ,
+            family           => FAMILY,
+            MEM_BURST_LEN    => MEM_BLEN,
+            
+            addr_width       => ADDR_WIDTH,
+            data_pattern     => DATA_PATTERN,
+            dwidth           => DWIDTH,
+            num_dq_pins      => NUM_DQ_PINS,
+            sel_victim_line  => SEL_VICTIM_LINE,
+            mem_col_width    => MEM_COL_WIDTH,
+            eye_test         => EYE_TEST
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            rst_i           => rst_rb,
+            cmd_rdy_o       => wr_rdy,
+            cmd_valid_i     => wr_valid,
+            cmd_validb_i    => wr_validB,
+            cmd_validc_i    => wr_validC,
+            prbs_fseed_i    => data_seed_i,
+            data_mode_i     => data_mode_r_c,
+            last_word_wr_o  => last_word_wr,
+--            m_addr_i        => m_addr,
+            fixed_data_i       => fixed_data_i,
+
+            addr_i          => wr_addr,
+            bl_i            => wr_bl,
+            data_rdy_i      => xhdl19,
+            data_valid_o    => mcb_wr_en,
+            data_o          => mcb_wr_data_o_xhdl9,
+            data_mask_o     => mcb_wr_mask_o_xhdl10,
+            data_wr_end_o   => mcb_wr_data_end_o_xhdl8
+--            tpt_hdata       =>
+         );
+
+   END GENERATE;
+
+   mcb_wr_en_o <= mcb_wr_en;
+
+
+
+   tg_status_inst : tg_status
+      GENERIC MAP (
+         dwidth  => DWIDTH
+      )
+      PORT MAP (
+         clk_i               => clk_i,
+         rst_i               => rst_ra(2),
+         manual_clear_error  => manual_clear_error,
+         data_error_i        => cmp_error_int,
+         cmp_data_i          => cmp_data_int,
+         rd_data_i           => mem_rd_data_i,
+         cmp_addr_i          => cmp_addr,
+         cmp_bl_i            => cmp_bl,
+         mcb_cmd_full_i      => mcb_cmd_full_i,
+         mcb_wr_full_i       => mcb_wr_full,
+         mcb_rd_empty_i      => mcb_rd_empty,
+         error_status        => error_status_xhdl2,
+         error               => error_xhdl1
+      );
+
+END trans;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/rd_data_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/rd_data_gen.vhd
new file mode 100755
index 0000000..5559ade
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/rd_data_gen.vhd
@@ -0,0 +1,434 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: rd_data_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This module has all the timing control for generating "compare data" 
+--         to compare the read data from memory.
+-- Reference:
+-- Revision History: 2010/01/09  parameter MEM_BURST_LEN is missing in v6_data_gen instance module.
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+entity rd_data_gen is
+   generic (
+      
+      FAMILY                         : string := "SPARTAN6";            -- "SPARTAN6", "VIRTEX6"
+      MEM_BURST_LEN                  : integer := 8;
+      ADDR_WIDTH                     : integer := 32;
+      BL_WIDTH                       : integer := 6;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_PRBS";           --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      SEL_VICTIM_LINE                : integer := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+      
+      COLUMN_WIDTH                   : integer := 10
+   );
+   port (
+      
+      clk_i                          : in std_logic;            --
+      rst_i                          : in std_logic_vector(4 downto 0);
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      data_mode_i                    : in std_logic_vector(3 downto 0);         -- "00" = bram; 
+      rd_mdata_en                    :  in std_logic;
+      
+      cmd_rdy_o                      : out std_logic;           -- ready to receive command. It should assert when data_port is ready at the                                        // beginning and will be deasserted once see the cmd_valid_i is asserted. 
+      -- And then it should reasserted when 
+      -- it is generating the last_word.
+      cmd_valid_i                    : in std_logic;            -- when both cmd_valid_i and cmd_rdy_o is high, the command  is valid.
+      last_word_o                    : out std_logic;
+      
+--      m_addr_i                       : in std_logic_vector(ADDR_WIDTH - 1 downto 0);            -- generated address used to determine data pattern.
+      fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);
+      
+      addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);            -- generated address used to determine data pattern.
+      bl_i                           : in std_logic_vector(BL_WIDTH - 1 downto 0);              -- generated burst length for control the burst data
+      user_bl_cnt_is_1_o             : out std_logic;
+      data_rdy_i                     : in std_logic;            -- connect from mcb_wr_full when used as wr_data_gen in sp6
+      -- connect from mcb_rd_empty when used as rd_data_gen in sp6
+      -- connect from rd_data_valid in v6
+      -- When both data_rdy and data_valid is asserted, the ouput data is valid.
+      data_valid_o                   : out std_logic;           -- connect to wr_en or rd_en and is asserted whenever the 
+      -- pattern is available.
+      data_o                         : out std_logic_vector(DWIDTH - 1 downto 0)                -- generated data pattern   
+   );
+end entity rd_data_gen;
+
+ARCHITECTURE trans OF rd_data_gen IS
+
+COMPONENT sp6_data_gen IS
+   GENERIC (
+      
+      ADDR_WIDTH      : INTEGER := 32;
+      BL_WIDTH        : INTEGER := 6;
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_PRBS";
+      NUM_DQ_PINS     : INTEGER := 8;
+      COLUMN_WIDTH    : INTEGER := 10
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      cmd_startA      : IN STD_LOGIC;
+      cmd_startB      : IN STD_LOGIC;
+      cmd_startC      : IN STD_LOGIC;
+      cmd_startD      : IN STD_LOGIC;
+      cmd_startE      : IN STD_LOGIC;
+      fixed_data_i    : in std_logic_vector(DWIDTH - 1 downto 0);  
+      addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      user_burst_cnt  : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
+      
+      fifo_rdy_i      : IN STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
+   );
+END COMPONENT;      
+
+COMPONENT v6_data_gen IS
+   GENERIC (
+      
+      ADDR_WIDTH      : INTEGER := 32;
+      MEM_BURST_LEN   : integer := 8;
+      
+      BL_WIDTH        : INTEGER := 6;
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_ALL";
+      NUM_DQ_PINS     : INTEGER := 8;
+      SEL_VICTIM_LINE : INTEGER := 3;
+      COLUMN_WIDTH    : INTEGER := 10
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      cmd_startA      : IN STD_LOGIC;
+      cmd_startB      : IN STD_LOGIC;
+      cmd_startC      : IN STD_LOGIC;
+      cmd_startD      : IN STD_LOGIC;
+      cmd_startE      : IN STD_LOGIC;
+      fixed_data_i    : in std_logic_vector(DWIDTH - 1 downto 0);  
+      
+      m_addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      user_burst_cnt  : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
+      
+      fifo_rdy_i      : IN STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
+   );
+END COMPONENT;      
+
+
+   SIGNAL prbs_data          : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL cmd_start          : STD_LOGIC;
+   SIGNAL adata              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL hdata              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL ndata              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL w1data             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL v6_w1data          : STD_LOGIC_VECTOR(NUM_DQ_PINS * 4 - 1 DOWNTO 0);
+   
+   signal w0data                        : std_logic_vector(31 downto 0);
+   signal data                          : std_logic_vector(DWIDTH - 1 downto 0);
+   signal cmd_rdy                       : std_logic;
+   signal data_valid                    : std_logic;
+   signal user_burst_cnt                : std_logic_vector(6 downto 0);
+   signal data_rdy_r1                   : std_logic;
+   signal data_rdy_r2                   : std_logic;
+   signal next_count_is_one             : std_logic;
+   signal cmd_valid_r1                  : std_logic;
+   signal w3data                        : std_logic_vector(31 downto 0);
+   
+   signal data_port_fifo_rdy            : std_logic;
+   
+   --assign cmd_start = cmd_valid_i & cmd_rdy ;
+   
+   signal user_bl_cnt_is_1              : std_logic;
+   
+   signal cmd_start_b                   : std_logic;
+   
+   --  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
+   --  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
+   
+   -- counter to count user burst length
+   
+   signal u_bcount_2                    : std_logic;
+   
+   -- Declare intermediate signals for referenced outputs
+   signal last_word_o_xhdl1             : std_logic;
+   signal data_o_xhdl0                  : std_logic_vector(DWIDTH - 1 downto 0);
+begin
+   -- Drive referenced outputs
+   last_word_o <= last_word_o_xhdl1;
+   data_port_fifo_rdy <= data_rdy_i;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         data_rdy_r1 <= data_rdy_i;
+         data_rdy_r2 <= data_rdy_r1;
+         cmd_valid_r1 <= cmd_valid_i;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (user_burst_cnt = "0000010" and data_rdy_i = '1') then
+            next_count_is_one <= '1';
+         else
+            next_count_is_one <= '0';
+         end if;
+      end if;
+   end process;
+   
+   user_bl_cnt_is_1_o <= user_bl_cnt_is_1;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "SPARTAN6") or
+         (user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "VIRTEX6") ) then
+            user_bl_cnt_is_1 <= '1';
+         else
+            user_bl_cnt_is_1 <= '0';
+         end if;
+      end if;
+   end process;
+   
+   process (cmd_valid_i, cmd_valid_r1, cmd_rdy, user_bl_cnt_is_1, rd_mdata_en)
+   begin
+      if (FAMILY = "SPARTAN6") then
+         cmd_start <= cmd_valid_i and cmd_rdy;
+         cmd_start_b <= cmd_valid_i and cmd_rdy;
+      else
+        if (MEM_BURST_LEN = 4) then 
+          cmd_start <= rd_mdata_en;
+        else
+          cmd_start <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
+          cmd_start_b <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
+        end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            user_burst_cnt <= "0000000";
+         elsif (cmd_start = '1') then
+            if (bl_i = "000000") then
+               user_burst_cnt <= "1000000" ;
+            else
+               user_burst_cnt <= ('0' & bl_i) ;
+            end if;
+         elsif (data_port_fifo_rdy = '1') then
+            if (user_burst_cnt /= "0000000") then
+               user_burst_cnt <= user_burst_cnt - "0000001";
+            else
+               user_burst_cnt <= "0000000";
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((user_burst_cnt = "0000010" and data_rdy_i = '1') or (cmd_start = '1' and bl_i = "000001")) then
+            u_bcount_2 <= '1';
+         elsif (last_word_o_xhdl1 = '1') then
+            u_bcount_2 <= '0';
+         end if;
+      end if;
+   end process;
+   
+   
+   last_word_o_xhdl1 <= u_bcount_2 and data_rdy_i;
+   
+   -- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
+   -- is assert and reassert during the last data
+   
+   --data_valid_o logic
+   
+   cmd_rdy_o <= cmd_rdy;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdy <= '1';
+         elsif (cmd_start = '1') then
+            cmd_rdy <= '0';
+         elsif (data_port_fifo_rdy = '1' and user_burst_cnt = "0000001") then
+            
+            cmd_rdy <= '1';
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            data_valid <= '0';
+         elsif (user_burst_cnt = "0000001" and data_port_fifo_rdy = '1') then
+            data_valid <= '0';
+         elsif ((user_burst_cnt >= "0000001") or cmd_start = '1') then
+            data_valid <= '1';
+         end if;
+      end if;
+   end process;
+   
+   
+   process (data_valid, data_port_fifo_rdy)
+   begin
+      if (FAMILY = "SPARTAN6") then
+         data_valid_o <= data_valid;
+      else
+         
+         data_valid_o <= data_port_fifo_rdy;
+      end if;
+   end process;
+   
+   xhdl2 : if (FAMILY = "SPARTAN6") generate
+      
+      
+      
+      sp6_data_gen_inst : sp6_data_gen
+         generic map (
+            ADDR_WIDTH    => 32,
+            BL_WIDTH      => BL_WIDTH,
+            DWIDTH        => DWIDTH,
+            DATA_PATTERN  => DATA_PATTERN,
+            NUM_DQ_PINS   => NUM_DQ_PINS,
+            COLUMN_WIDTH  => COLUMN_WIDTH
+         )
+         port map (
+            clk_i           => clk_i,
+            rst_i           => rst_i(1),
+            data_rdy_i      => data_rdy_i,
+            prbs_fseed_i    => prbs_fseed_i,
+            
+            data_mode_i     => data_mode_i,
+            cmd_startA      => cmd_start,
+            cmd_startB      => cmd_start,
+            cmd_startC      => cmd_start,
+            cmd_startD      => cmd_start,
+            cmd_startE      => cmd_start,
+            fixed_data_i    => fixed_data_i,
+            
+            addr_i          => addr_i,
+            user_burst_cnt  => user_burst_cnt,
+            fifo_rdy_i      => data_port_fifo_rdy,
+            data_o          => data_o
+         );
+      
+   end generate;
+   xhdl3 : if (FAMILY = "VIRTEX6") generate
+      
+      
+      
+      v6_data_gen_inst : v6_data_gen
+         generic map (
+            ADDR_WIDTH       => 32,
+            BL_WIDTH         => BL_WIDTH,
+            MEM_BURST_LEN    => MEM_BURST_LEN,
+            
+            DWIDTH           => DWIDTH,
+            DATA_PATTERN     => DATA_PATTERN,
+            NUM_DQ_PINS      => NUM_DQ_PINS,
+            SEL_VICTIM_LINE  => SEL_VICTIM_LINE,
+            COLUMN_WIDTH     => COLUMN_WIDTH
+         )
+         port map (
+            clk_i           => clk_i,
+            rst_i           => rst_i(1),
+            data_rdy_i      => data_rdy_i,
+            prbs_fseed_i    => prbs_fseed_i,
+            
+            data_mode_i     => data_mode_i,
+            cmd_startA      => cmd_start,
+            cmd_startB      => cmd_start,
+            cmd_startC      => cmd_start,
+            cmd_startD      => cmd_start,
+            cmd_startE      => cmd_start,
+            fixed_data_i    => fixed_data_i,
+            
+            m_addr_i        => addr_i,          --(m_addr_i        ),          
+            addr_i          => addr_i,
+            user_burst_cnt  => user_burst_cnt,
+            fifo_rdy_i      => data_port_fifo_rdy,
+            data_o          => data_o
+         );
+      
+   end generate;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_data_path.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_data_path.vhd
new file mode 100755
index 0000000..0e21887
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_data_path.vhd
@@ -0,0 +1,638 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: read_data_path.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This is top level of read path and also consist of comparison logic
+--         for read data. 
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+entity read_data_path is
+   generic (
+      TCQ                            : time := 100 ps;      
+      FAMILY                         : string := "VIRTEX6";
+      MEM_BURST_LEN                  : integer := 8;
+      ADDR_WIDTH                     : integer := 32;
+      CMP_DATA_PIPE_STAGES           : integer := 3;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_ALL";           --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      DQ_ERROR_WIDTH                 : integer := 1;
+      SEL_VICTIM_LINE                : integer := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+      
+      MEM_COL_WIDTH                  : integer := 10
+   );
+   port (
+      
+      clk_i                          : in std_logic;
+      manual_clear_error             : in std_logic;
+      rst_i                          : in std_logic_vector(9 downto 0);
+      cmd_rdy_o                      : out std_logic;
+      cmd_valid_i                    : in std_logic;
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      
+      data_mode_i                    : in std_logic_vector(3 downto 0);
+      cmd_sent                       : in std_logic_vector(2 downto 0);
+      bl_sent                        : in std_logic_vector(5 downto 0);
+      cmd_en_i                       : in std_logic;
+--      m_addr_i                       : in std_logic_vector(31 downto 0);
+      fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);
+      
+      addr_i                         : in std_logic_vector(31 downto 0);
+      bl_i                           : in std_logic_vector(5 downto 0);
+      --   input [5:0]            port_data_counts_i,// connect to data port fifo counts
+      
+      data_rdy_o                     : out std_logic;
+      data_valid_i                   : in std_logic;
+      data_i                         : in std_logic_vector(DWIDTH - 1 downto 0);
+      last_word_rd_o                 : out std_logic;
+      data_error_o                   : out std_logic;
+      cmp_data_o                     : out std_logic_vector(DWIDTH - 1 downto 0);
+      rd_mdata_o                     : out std_logic_vector(DWIDTH - 1 downto 0);
+      cmp_data_valid                 : out std_logic;
+      cmp_addr_o                     : out std_logic_vector(31 downto 0);
+      cmp_bl_o                       : out std_logic_vector(5 downto 0);
+      force_wrcmd_gen_o              : out std_logic;
+      
+      rd_buff_avail_o                : out std_logic_vector(6 downto 0);
+      dq_error_bytelane_cmp          : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
+       cumlative_dq_lane_error_r     : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
+
+      
+      
+   );
+end entity read_data_path;
+
+architecture trans of read_data_path is
+
+function REDUCTION_OR( A: in std_logic_vector) return std_logic is
+  variable tmp : std_logic := '0';
+begin
+  for i in A'range loop
+       tmp := tmp or A(i);
+  end loop;
+  return tmp;
+end function REDUCTION_OR;
+
+   COMPONENT read_posted_fifo IS
+      GENERIC (
+         TCQ                   : time   := 100 ps;
+         MEM_BURST_LEN         : integer := 4;
+         FAMILY                : STRING := "SPARTAN6";
+         ADDR_WIDTH            : INTEGER := 32;
+         BL_WIDTH              : INTEGER := 6
+      );
+      PORT (
+         clk_i                 : IN STD_LOGIC;
+         rst_i                 : IN STD_LOGIC;
+         cmd_rdy_o             : OUT STD_LOGIC;
+         cmd_valid_i           : IN STD_LOGIC;
+         data_valid_i          : IN STD_LOGIC;
+         addr_i                : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+         bl_i                  : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
+         user_bl_cnt_is_1      : IN STD_LOGIC;
+         cmd_sent              : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         bl_sent               : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+         cmd_en_i              : IN STD_LOGIC;
+         gen_rdy_i             : IN STD_LOGIC;
+         gen_valid_o           : OUT STD_LOGIC;
+         gen_addr_o            : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+         gen_bl_o              : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
+         rd_buff_avail_o       : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
+         rd_mdata_fifo_empty   : IN STD_LOGIC;
+         rd_mdata_en           : OUT STD_LOGIC   
+      );
+   END COMPONENT;
+
+   component rd_data_gen is
+      generic (
+         FAMILY                         : string := "SPARTAN6";
+         MEM_BURST_LEN                  : integer := 8;
+         ADDR_WIDTH                     : integer := 32;
+         BL_WIDTH                       : integer := 6;
+         DWIDTH                         : integer := 32;
+         DATA_PATTERN                   : string := "DGEN_PRBS";
+         NUM_DQ_PINS                    : integer := 8;
+         SEL_VICTIM_LINE                : integer := 3;
+         COLUMN_WIDTH                   : integer := 10
+      );
+      port (
+         clk_i                          : in std_logic;
+         rst_i                          : in std_logic_vector(4 downto 0);
+         prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+         rd_mdata_en                    : in std_logic;
+         data_mode_i                    : in std_logic_vector(3 downto 0);
+         cmd_rdy_o                      : out std_logic;
+         cmd_valid_i                    : in std_logic;
+         last_word_o                    : out std_logic;
+--         m_addr_i                       : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+         fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);  
+         
+         addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+         bl_i                           : in std_logic_vector(BL_WIDTH - 1 downto 0);
+         user_bl_cnt_is_1_o             : out std_logic;
+         data_rdy_i                     : in std_logic;
+         data_valid_o                   : out std_logic;
+         data_o                         : out std_logic_vector(DWIDTH - 1 downto 0)
+      );
+   end component;
+
+   component afifo IS
+   GENERIC (
+      DSIZE       : INTEGER := 32;
+      FIFO_DEPTH  : INTEGER := 16;
+      ASIZE       : INTEGER := 5;
+      SYNC        : INTEGER := 1
+   );
+   PORT (
+      wr_clk      : IN STD_LOGIC;
+      rst         : IN STD_LOGIC;
+      wr_en       : IN STD_LOGIC;
+      wr_data     : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      rd_en       : IN STD_LOGIC;
+      rd_clk      : IN STD_LOGIC;
+      rd_data     : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      almost_full : OUT STD_LOGIC;
+      full        : OUT STD_LOGIC;
+      empty       : OUT STD_LOGIC
+   );
+END component;
+   
+   signal gen_rdy                  : std_logic;
+   signal gen_valid                : std_logic;
+   signal gen_addr                 : std_logic_vector(31 downto 0);
+   signal gen_bl                   : std_logic_vector(5 downto 0);
+   
+   signal cmp_rdy                  : std_logic;
+   signal cmp_valid                : std_logic;
+   signal cmp_addr                 : std_logic_vector(31 downto 0);
+   signal cmp_bl                   : std_logic_vector(5 downto 0);
+   
+   signal data_error               : std_logic;
+   signal cmp_data                 : std_logic_vector(DWIDTH - 1 downto 0);
+   signal last_word_rd             : std_logic;
+   signal bl_counter               : std_logic_vector(5 downto 0);
+   signal cmd_rdy                  : std_logic;
+   signal user_bl_cnt_is_1         : std_logic;
+   signal data_rdy                 : std_logic;
+   signal delayed_data             : std_logic_vector(DWIDTH downto 0);
+--   signal cmp_data_piped           : std_logic_vector(DWIDTH downto 0);
+   signal cmp_data_r               : std_logic_vector(DWIDTH-1 downto 0);    
+   signal rd_mdata_en              : std_logic;   
+   signal rd_data_r                : std_logic_vector(DWIDTH - 1 downto 0);
+   signal force_wrcmd_gen          : std_logic;
+   signal wait_bl_end              : std_logic;
+   signal wait_bl_end_r1           : std_logic;
+
+   signal v6_data_cmp_valid        : std_logic;
+   signal rd_v6_mdata              : std_logic_vector(DWIDTH-1 downto 0);    
+   signal cmpdata_r                : std_logic_vector(DWIDTH-1 downto 0);    
+   signal rd_mdata                 : std_logic_vector(DWIDTH-1 downto 0);    
+   signal l_data_error             : std_logic;
+   signal u_data_error             : std_logic;
+   signal cmp_data_en              : std_logic;
+   
+   signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
+
+   signal error_byte               : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
+   signal error_byte_r1             : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
+   signal dq_lane_error            : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal dq_lane_error_r1         : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal dq_lane_error_r2         : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal cum_dq_lane_error_mask   : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal cumlative_dq_lane_error_reg  : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal cumlative_dq_lane_error_c     : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
+  signal  rd_mdata_fifo_empty      : std_logic;
+   signal data_valid_r             : std_logic;
+   -- Declare intermediate signals for referenced outputs
+--   SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
+--   SIGNAL tmp_sig : STD_LOGIC;
+   signal last_word_rd_o_xhdl0     : std_logic;
+   signal rd_buff_avail_o_xhdl1    : std_logic_vector(6 downto 0);
+begin
+   -- Drive referenced outputs
+   last_word_rd_o <= last_word_rd_o_xhdl0;
+   rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         wait_bl_end_r1 <= wait_bl_end;
+         rd_data_r <= data_i;
+      end if;
+   end process;
+   
+   force_wrcmd_gen_o <= force_wrcmd_gen;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i(0) = '1') then
+            force_wrcmd_gen <= '0';
+         elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
+            force_wrcmd_gen <= '0';
+         elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
+            force_wrcmd_gen <= '1';
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i(0) = '1') then
+            force_wrcmd_timeout_cnts <= "00000000";
+         elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
+            force_wrcmd_timeout_cnts <= "00000000";
+         elsif (force_wrcmd_gen = '1') then
+            force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i(0) = '1') then
+            wait_bl_end <= '0';
+         elsif (force_wrcmd_timeout_cnts = "11111111") then
+            wait_bl_end <= '0';
+         elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
+            wait_bl_end <= '1';
+         elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
+            wait_bl_end <= '0';
+         end if;
+      end if;
+   end process;
+   
+   cmd_rdy_o <= cmd_rdy;
+   
+   
+   read_postedfifo : read_posted_fifo
+      GENERIC MAP (
+         TCQ         => TCQ,
+         FAMILY      => FAMILY,
+         MEM_BURST_LEN => MEM_BURST_LEN,
+         ADDR_WIDTH  => 32,
+         BL_WIDTH    => 6
+      )
+      port map (
+         clk_i             => clk_i,
+         rst_i             => rst_i(0),
+         cmd_rdy_o         => cmd_rdy,
+         cmd_valid_i       => cmd_valid_i,
+         data_valid_i      => data_rdy,
+         addr_i            => addr_i,
+         bl_i              => bl_i,
+         cmd_sent          => cmd_sent,
+         bl_sent           => bl_sent,
+         cmd_en_i          => cmd_en_i,
+         user_bl_cnt_is_1  => user_bl_cnt_is_1,
+         gen_rdy_i         => gen_rdy,
+         gen_valid_o       => gen_valid,
+         gen_addr_o        => gen_addr,
+         gen_bl_o          => gen_bl,
+         rd_buff_avail_o   => rd_buff_avail_o_xhdl1,
+         rd_mdata_fifo_empty => rd_mdata_fifo_empty,
+         rd_mdata_en       => rd_mdata_en
+      );
+   
+   
+   rd_datagen : rd_data_gen
+      generic map (
+         FAMILY           => FAMILY,
+         MEM_BURST_LEN    => MEM_BURST_LEN,
+         NUM_DQ_PINS      => NUM_DQ_PINS,
+         SEL_VICTIM_LINE  => SEL_VICTIM_LINE,
+         DATA_PATTERN     => DATA_PATTERN,
+         DWIDTH           => DWIDTH,
+         COLUMN_WIDTH     => MEM_COL_WIDTH
+      )
+      port map (
+         clk_i               => clk_i,
+         rst_i               => rst_i(4 downto 0),
+         prbs_fseed_i        => prbs_fseed_i,
+         data_mode_i         => data_mode_i,
+         cmd_rdy_o           => gen_rdy,
+         cmd_valid_i         => gen_valid,
+         last_word_o         => last_word_rd_o_xhdl0,
+--         m_addr_i            => m_addr_i,
+         fixed_data_i        => fixed_data_i,
+         addr_i              => gen_addr,
+         bl_i                => gen_bl,
+         user_bl_cnt_is_1_o  => user_bl_cnt_is_1,
+         data_rdy_i          => data_valid_i,
+         data_valid_o        => cmp_valid,
+         data_o              => cmp_data,
+         rd_mdata_en         => rd_mdata_en
+      );
+
+      rd_mdata_fifo : afifo
+         GENERIC MAP (
+            DSIZE       => DWIDTH,
+            FIFO_DEPTH  => 32,
+            ASIZE       => 5,
+            SYNC        => 1
+         )
+         PORT MAP (
+            wr_clk   => clk_i,
+            rst      => rst_i(0),
+            wr_en    => data_valid_i,
+            wr_data  => data_i,
+            rd_en    => rd_mdata_en,
+            rd_clk   => clk_i,
+            rd_data  => rd_v6_mdata,
+            full     => open,
+            empty    => rd_mdata_fifo_empty,
+            almost_full => open
+         );
+  
+--  tmp_sig <= cmp_valid AND data_valid_i; 
+--   xhdl2 <= ( tmp_sig & cmp_data);
+ 
+  process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+--         delayed_data <= (tmp_sig & cmp_data);
+         cmp_data_r <= cmp_data;
+      end if;
+   end process;
+   
+   rd_mdata_o <= rd_mdata;
+
+   rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata 
+               WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
+
+   cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid 
+               WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
+
+
+   cmp_data_o <= cmp_data_r;
+   cmp_addr_o <= gen_addr;
+   cmp_bl_o <= gen_bl;
+
+--   xhdl4 : if (FAMILY = "SPARTAN6") generate
+--      rd_data_o <= rd_data_r;
+--   end generate;
+--   xhdl5 : if (FAMILY /= "SPARTAN6") generate
+--      rd_data_o <= data_i;
+--   end generate;
+
+   data_rdy_o <= data_rdy;
+   data_rdy <= cmp_valid and data_valid_i;
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         v6_data_cmp_valid <= rd_mdata_en;
+      end if;
+   end process;
+    
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         cmp_data_en <= data_rdy;
+      end if;
+   end process;
+   
+   xhdl6 : if (FAMILY = "SPARTAN6") generate
+      process (clk_i)
+      begin
+         if (clk_i'event and clk_i = '1') then
+            if (cmp_data_en = '1') then
+              IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
+                l_data_error <= '1' ;
+              ELSE 
+                l_data_error <= '0' ;
+              END IF; 
+            else
+               l_data_error <= '0' ;
+            end if;
+            if (cmp_data_en = '1') then
+              IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
+                u_data_error <= '1' ;
+              ELSE
+                u_data_error <= '0' ;
+              END IF;
+            else
+               u_data_error <= '0' ;
+            end if;
+            data_error <= l_data_error or u_data_error;
+            --synthesis translate_off
+            if (data_error = '1') then
+              report ("DATA ERROR");
+            end if;
+            --synthesis translate_on
+
+         end if;
+      end process;
+      
+   end generate;
+   
+   gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
+      
+      
+      gen_cmp : FOR i IN 0 TO  NUM_DQ_PINS / 2 - 1 GENERATE
+         error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
+         
+      end generate;
+      process (clk_i)
+      begin
+         if (clk_i'event and clk_i = '1') then
+             IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
+                 error_byte_r1 <= (others => '0');
+                 data_error    <= '0';
+             ELSE
+             
+              error_byte_r1 <= error_byte;
+           -- FOR i IN 0 TO  DWIDTH - 1 LOOP
+              data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
+           -- END LOOP;
+        
+            
+            END IF;
+         end if;
+      end process;
+      
+
+      process (data_error)
+      begin
+         
+         --synthesis translate_off   
+            IF (data_error = '1') THEN               
+               
+               report "DATA ERROR"; -- severity ERROR;
+            END IF;
+         --synthesis translate_on
+      end process;
+      
+      
+      gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
+         dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
+                              error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR 
+                              error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
+                              
+         cumlative_dq_lane_error_c(i) <=  cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
+      end  generate;
+      
+     
+      process (clk_i)
+      begin
+         IF (clk_i'event and clk_i = '1') then
+             IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
+                
+               dq_lane_error_r1 <=  (others => '0');
+               dq_lane_error_r2 <=  (others => '0');
+               data_valid_r <=  '0';
+               cumlative_dq_lane_error_reg <=  (others => '0');
+               
+             ELSE 
+               data_valid_r <=  data_valid_i;
+             
+               dq_lane_error_r1 <=  dq_lane_error;
+               cumlative_dq_lane_error_reg <=  cumlative_dq_lane_error_c;
+             END IF;
+           
+      
+         END IF;
+      end process;
+      
+      
+      
+   end generate;
+
+   xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
+      
+      gen_cmp_8 : FOR i IN 0 TO  NUM_DQ_PINS / 2 - 1 GENERATE
+         error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
+      end generate;
+
+      process (clk_i)
+      begin
+         if (clk_i'event and clk_i = '1') then
+             IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
+                    error_byte_r1 <= (others => '0');
+                    data_error    <= '0';
+             ELSE
+         
+                    error_byte_r1 <= error_byte;
+                    --FOR i IN 0 TO  DWIDTH - 1 LOOP
+                    --  data_error <= error_byte_r1(i) OR data_error;
+                    --END LOOP;
+                    data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
+                
+                         --synthesis translate_off   
+                    IF (data_error = '1') THEN               
+                       
+                       report "DATA ERROR"; -- severity ERROR;
+                    end if;
+                 --synthesis translate_on
+             END IF;
+         end if;
+      end process;
+      
+      
+      gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
+         dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
+                              error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR 
+                              error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
+                              
+         cumlative_dq_lane_error_c(i) <=  cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
+      end  generate;
+      
+      process (clk_i)
+      begin
+         IF (clk_i'event and clk_i = '1') then
+             IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
+                
+               dq_lane_error_r1 <=  (others => '0');
+               dq_lane_error_r2 <=  (others => '0');
+               data_valid_r <=  '0';
+               cumlative_dq_lane_error_reg <=  (others => '0');
+               
+             ELSE 
+               data_valid_r <=  data_valid_i;
+             
+               dq_lane_error_r1 <=  dq_lane_error;
+               cumlative_dq_lane_error_reg <=  cumlative_dq_lane_error_c;
+             END IF;
+           
+      
+         END IF;
+      end process;
+            
+   end generate;
+   cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
+   
+   dq_error_bytelane_cmp <= dq_lane_error_r1;     
+
+   data_error_o <= data_error;
+   
+end architecture trans;
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_posted_fifo.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_posted_fifo.vhd
new file mode 100755
index 0000000..694ed0d
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_posted_fifo.vhd
@@ -0,0 +1,339 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: read_posted_fifo.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:40 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This module instantiated by read_data_path module and sits between 
+--         mcb_flow_control module and read_data_gen module to buffer up the 
+--         commands that has sent to memory controller.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+entity read_posted_fifo is
+   generic (
+      TCQ                            : time := 100 ps;
+      MEM_BURST_LEN                  : integer := 4;
+      FAMILY                         : string := "SPARTAN6";
+      ADDR_WIDTH                     : integer := 32;
+      BL_WIDTH                       : integer := 6
+   );
+   port (
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic;
+      cmd_rdy_o                      : out std_logic;
+      cmd_valid_i                    : in std_logic;
+      data_valid_i                   : in std_logic;
+      addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      bl_i                           : in std_logic_vector(BL_WIDTH - 1 downto 0);
+      user_bl_cnt_is_1               : in std_logic;
+      cmd_sent                       : in std_logic_vector(2 downto 0);
+      bl_sent                        : in std_logic_vector(5 downto 0);
+      cmd_en_i                       : in std_logic;
+      
+      gen_rdy_i                      : in std_logic;
+      gen_valid_o                    : out std_logic;
+      gen_addr_o                     : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      gen_bl_o                       : out std_logic_vector(BL_WIDTH - 1 downto 0);
+      
+      rd_buff_avail_o                : out std_logic_vector(6 downto 0);
+      rd_mdata_fifo_empty            : in  std_logic;
+      rd_mdata_en                    : out std_logic
+   );
+end entity read_posted_fifo;
+
+architecture trans of read_posted_fifo is
+   component afifo is
+      generic (
+         DSIZE                          : integer := 32;
+         FIFO_DEPTH                     : integer := 16;
+         ASIZE                          : integer := 4;
+         SYNC                           : integer := 1
+      );
+      port (
+         wr_clk                         : in std_logic;
+         rst                            : in std_logic;
+         wr_en                          : in std_logic;
+         wr_data                        : in std_logic_vector(DSIZE - 1 downto 0);
+         rd_en                          : in std_logic;
+         rd_clk                         : in std_logic;
+         rd_data                        : out std_logic_vector(DSIZE - 1 downto 0);
+         full                           : out std_logic;
+         empty                          : out std_logic;
+         almost_full                    : out std_logic
+      );
+   end component;
+   
+   
+   signal full                          : std_logic;
+   signal empty                         : std_logic;
+   signal wr_en                         : std_logic;
+   signal rd_en                         : std_logic;
+   signal data_valid_r                  : std_logic;
+   signal user_bl_cnt_not_1             : std_logic;
+   signal buf_avail_r                   : std_logic_vector(6 downto 0);
+   signal rd_data_received_counts       : std_logic_vector(6 downto 0);
+   signal rd_data_counts_asked          : std_logic_vector(6 downto 0);
+   
+   signal dfifo_has_enough_room         : std_logic;
+   signal wait_cnt                      : std_logic_vector(1 downto 0);
+   signal wait_done                     : std_logic;
+   
+   signal dfifo_has_enough_room_d1      : std_logic;
+   signal empty_r                       : std_logic;
+   signal rd_first_data                 : std_logic;
+   -- current count is 1 and data_is_valie, then next cycle is not 1
+   
+   -- calculate how many buf still available
+   -- assign buf_avail = 64 - (rd_data_counts_asked - rd_data_received_counts);
+   
+--   signal tmp_buf_avil                  : std_logic_vector(5 downto 0);
+   -- X-HDL generated signals
+
+   signal xhdl3 : std_logic;
+   signal xhdl4 : std_logic;
+   signal xhdl5 : std_logic_vector(37 downto 0);
+   signal xhdl6 : std_logic_vector(37 downto 0);
+   
+   -- Declare intermediate signals for referenced outputs
+   signal cmd_rdy_o_xhdl0               : std_logic;
+   signal gen_addr_o_xhdl1              : std_logic_vector(ADDR_WIDTH - 1 downto 0);
+   signal gen_bl_o_xhdl2                : std_logic_vector(BL_WIDTH - 1 downto 0);
+begin
+   -- Drive referenced outputs
+   cmd_rdy_o <= cmd_rdy_o_xhdl0;
+--   gen_addr_o <= gen_addr_o_xhdl1;
+--   gen_bl_o <= gen_bl_o_xhdl2;
+
+   gen_bl_o <= xhdl6(BL_WIDTH+ADDR_WIDTH-1 downto ADDR_WIDTH);
+   gen_addr_o <= xhdl6(ADDR_WIDTH-1 downto 0);
+   
+   rd_mdata_en <= rd_en;
+   rd_buff_avail_o <= buf_avail_r;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         cmd_rdy_o_xhdl0 <= not(full) and dfifo_has_enough_room and wait_done;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i = '1') then
+            wait_cnt <= "00";
+         elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
+            wait_cnt <= "10";
+         elsif (wait_cnt > "00") then
+            wait_cnt <= wait_cnt - "01";
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i = '1') then
+            wait_done <= '1';
+         elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
+            wait_done <= '0';
+         elsif (wait_cnt = "00") then
+            wait_done <= '1';
+         else
+            wait_done <= '0';
+         end if;
+      end if;
+   end process;
+   
+   xhdl3 <= '1' when (buf_avail_r >= "0111110") else
+            '0';
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         dfifo_has_enough_room <= xhdl3;
+         dfifo_has_enough_room_d1 <= dfifo_has_enough_room;
+      end if;
+   end process;
+   
+   wr_en <= cmd_valid_i and not(full) and dfifo_has_enough_room_d1 and wait_done;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         data_valid_r <= data_valid_i;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((data_valid_i and user_bl_cnt_is_1) = '1') then
+            user_bl_cnt_not_1 <= '1';
+         else
+            user_bl_cnt_not_1 <= '0';
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i = '1') then
+            rd_data_counts_asked <= (others => '0');
+         elsif (cmd_en_i = '1' and cmd_sent(0) = '1') then
+           rd_data_counts_asked <= rd_data_counts_asked +  (bl_sent + "0000001" );
+
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i = '1') then
+            rd_data_received_counts <= "0000000";
+         elsif (data_valid_i = '1') then
+            rd_data_received_counts <= rd_data_received_counts + "0000001";
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         buf_avail_r <= "1000000" - (rd_data_counts_asked - rd_data_received_counts);
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         empty_r <= empty;
+      end if;
+   end process;
+   
+  process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+   
+         if (rst_i = '1') then
+            rd_first_data <= '0';
+         elsif ( empty = '0' AND empty_r = '1') then
+            rd_first_data <= '1';
+         end if;
+      end if;
+   end process;   
+   
+   process (gen_rdy_i, empty,empty_r, data_valid_i, data_valid_r, user_bl_cnt_not_1,rd_mdata_fifo_empty,rd_first_data)
+   begin
+      if (FAMILY = "SPARTAN6") then
+         rd_en <= gen_rdy_i and not(empty);
+      else
+         IF (MEM_BURST_LEN = 4) then
+             rd_en <= (not(empty) and empty_r and not(rd_first_data)) or (not(rd_mdata_fifo_empty) and not(empty)) or
+                     (user_bl_cnt_not_1 and data_valid_i);
+         ELSE
+             rd_en <= (data_valid_i and not(data_valid_r)) or (user_bl_cnt_not_1 and data_valid_i);
+         END IF;
+      end if;
+   end process;
+   
+   
+   
+   
+   gen_valid_o <= not(empty);
+   -- set the SYNC to 1 because rd_clk = wr_clk to reduce latency 
+   
+   
+--   xhdl4 <= to_integer(to_stdlogic(BL_WIDTH) + to_stdlogic(ADDR_WIDTH));
+   
+   xhdl5 <= (bl_i & addr_i);
+--   (gen_bl_o_xhdl2, gen_addr_o_xhdl1) <= xhdl6;
+
+   rd_fifo : afifo
+      GENERIC MAP (
+         DSIZE       => (BL_WIDTH + ADDR_WIDTH),--xhdl4,
+         FIFO_DEPTH  => 16,
+         ASIZE       => 4,
+         SYNC        => 1
+      )
+      port map (
+         wr_clk   => clk_i,
+         rst      => rst_i,
+         wr_en    => wr_en,
+         wr_data  => xhdl5,
+         rd_en    => rd_en,
+         rd_clk   => clk_i,
+         rd_data  => xhdl6,
+         full     => full,
+         empty    => empty,
+         almost_full => open
+      );
+   
+end architecture trans;
+
+
+
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/sp6_data_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/sp6_data_gen.vhd
new file mode 100755
index 0000000..d85e41b
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/sp6_data_gen.vhd
@@ -0,0 +1,793 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: sp6_data_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:40 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This module generates different data pattern as described in 
+--         parameter DATA_PATTERN and is set up for Spartan 6 family.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+entity sp6_data_gen is
+   generic (
+      
+      ADDR_WIDTH                     : integer := 32;
+      BL_WIDTH                       : integer := 6;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_ALL";           --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      COLUMN_WIDTH                   : integer := 10
+   );
+   port (
+      
+      clk_i                          : in std_logic;            --
+      rst_i                          : in std_logic;
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      
+      data_mode_i                    : in std_logic_vector(3 downto 0);         -- "00" = bram; 
+      data_rdy_i                     : in std_logic;
+      cmd_startA                     : in std_logic;
+      cmd_startB                     : in std_logic;
+      cmd_startC                     : in std_logic;
+      cmd_startD                     : in std_logic;
+      cmd_startE                     : in std_logic;
+      fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);
+      addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);            -- generated address used to determine data pattern.
+      user_burst_cnt                 : in std_logic_vector(6 downto 0);         -- generated burst length for control the burst data
+      
+      fifo_rdy_i                     : in std_logic;            -- connect from mcb_wr_full when used as wr_data_gen
+      -- connect from mcb_rd_empty when used as rd_data_gen
+      -- When both data_rdy and data_valid is asserted, the ouput data is valid.
+      data_o                         : out std_logic_vector(DWIDTH - 1 downto 0)                -- generated data pattern   
+   );
+end entity sp6_data_gen;
+
+architecture trans of sp6_data_gen is
+
+COMPONENT data_prbs_gen IS
+   GENERIC (
+      EYE_TEST        : STRING := "FALSE";
+      PRBS_WIDTH      : INTEGER := 32;
+      SEED_WIDTH      : INTEGER := 32
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      clk_en          : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      prbs_seed_init  : IN STD_LOGIC;
+      prbs_seed_i     : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
+      
+      prbs_o          : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
+   );
+END COMPONENT;
+
+   -- 
+   signal prbs_data                : std_logic_vector(31 downto 0);
+   
+   signal adata                    : std_logic_vector(31 downto 0);
+   signal hdata                    : std_logic_vector(DWIDTH - 1 downto 0);
+   signal ndata                    : std_logic_vector(DWIDTH - 1 downto 0);
+   signal w1data                   : std_logic_vector(DWIDTH - 1 downto 0);
+   signal data                     : std_logic_vector(DWIDTH - 1 downto 0);
+   signal burst_count_reached2     : std_logic;
+   
+   signal data_valid               : std_logic;
+   signal walk_cnt                 : std_logic_vector(2 downto 0);
+   signal user_address             : std_logic_vector(ADDR_WIDTH - 1 downto 0);
+   
+   signal i                        : integer;
+   signal j                        : integer;
+   signal user_bl                  : std_logic_vector(BL_WIDTH - 1 downto 0);
+   signal BLANK                    : std_logic_vector(7 downto 0);
+   
+   signal SHIFT_0                  : std_logic_vector(7 downto 0);
+   signal SHIFT_1                  : std_logic_vector(7 downto 0);
+   signal SHIFT_2                  : std_logic_vector(7 downto 0);
+   signal SHIFT_3                  : std_logic_vector(7 downto 0);
+   signal SHIFT_4                  : std_logic_vector(7 downto 0);
+   signal SHIFT_5                  : std_logic_vector(7 downto 0);
+   signal SHIFT_6                  : std_logic_vector(7 downto 0);
+   signal SHIFT_7                  : std_logic_vector(7 downto 0);
+   signal SHIFTB_0                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_1                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_2                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_3                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_4                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_5                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_6                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_7                 : std_logic_vector(31 downto 0);
+   signal TSTB                     : std_logic_vector(3 downto 0);
+   --*********************************************************************************************
+   
+   --  4'b0000: data = 32'b0;       //bram
+   --   4'b0001: data = 32'b0;       // fixed
+   -- address as data
+   -- DGEN_HAMMER
+   -- DGEN_NEIGHBOUR
+   -- DGEN_WALKING1
+   -- DGEN_WALKING0
+   
+   --bram
+   -- fixed
+   -- address as data
+   -- DGEN_HAMMER
+   -- DGEN_NEIGHBOUR
+   -- DGEN_WALKING1
+   -- DGEN_WALKING0
+   
+   --bram
+   -- fixed
+   -- address as data
+   -- DGEN_HAMMER
+   -- DGEN_NEIGHBOUR
+   -- DGEN_WALKING1
+   -- DGEN_WALKING0
+   
+   -- WALKING ONES:
+   
+   -- WALKING ONE
+   
+   -- NEIGHBOR ONE
+   
+   -- WALKING ZERO
+   
+   -- WALKING ONE
+   
+   -- NEIGHBOR ONE
+   
+   -- WALKING ZERO
+   
+   signal tmpdata                  : std_logic_vector(DWIDTH - 1 downto 0);
+   signal ndata_rising             : std_logic;
+   signal shift_en                 : std_logic;
+   signal data_clk_en              : std_logic;
+   SIGNAL ZEROS  : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
+   
+begin
+   ZEROS <= (others => '0');
+   data_o <= data;
+   xhdl0 : if (DWIDTH = 32) generate
+      process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
+      begin
+         case data_mode_i is
+            when "0001" =>
+               data <= fixed_data_i;
+            when "0010" =>
+               data <= adata;
+            when "0011" =>
+               data <= hdata;
+            when "0100" =>
+               data <= ndata;
+            when "0101" =>
+               data <= w1data;
+            when "0110" =>
+               data <= w1data;
+            when "0111" =>
+               data <= prbs_data;
+            WHEN OTHERS =>
+               data <= (others => '0');
+         END CASE;
+      END PROCESS;
+      
+   end generate;
+   xhdl1 : if (DWIDTH = 64) generate
+      process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
+      begin
+         case data_mode_i is
+            when "0000" =>
+               data <= (others => '0');
+            when "0001" =>
+               data <= fixed_data_i;
+            when "0010" =>
+--               data <= (adata & adata)(31 downto 0);
+               data <= (adata & adata);
+            when "0011" =>
+               data <= hdata;
+            when "0100" =>
+               data <= ndata;
+            when "0101" =>
+               data <= w1data;
+            when "0110" =>
+               data <= w1data;
+            when "0111" =>
+--               data <= (prbs_data & prbs_data)(31 downto 0);
+               data <= (prbs_data & prbs_data);
+            when others =>
+               data <= (others => '0');
+         end case;
+      end process;
+      
+   end generate;
+   xhdl2 : if (DWIDTH = 128) generate
+      process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
+      begin
+         case data_mode_i is
+            when "0000" =>
+               data <= (others => '0');
+            when "0001" =>
+               data <= fixed_data_i;
+            when "0010" =>
+--               data <= (adata & adata & adata & adata)(31 downto 0);
+               data <= (adata & adata & adata & adata);
+            when "0011" =>
+               data <= hdata;
+            when "0100" =>
+               data <= ndata;
+            when "0101" =>
+               data <= w1data;
+            when "0110" =>
+               data <= w1data;
+            when "0111" =>
+--               data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
+               data <= (prbs_data & prbs_data & prbs_data & prbs_data);
+            when others =>
+               data <= (others => '0');--"00000000000000000000000000000000";
+         end case;
+      end process;
+      
+   end generate;
+   xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
+      process (data_mode_i)
+      begin
+         if (data_mode_i = "0101" or data_mode_i = "0100") then
+            BLANK <= "00000000";
+            SHIFT_0 <= "00000001";
+            SHIFT_1 <= "00000010";
+            SHIFT_2 <= "00000100";
+            SHIFT_3 <= "00001000";
+            SHIFT_4 <= "00010000";
+            SHIFT_5 <= "00100000";
+            SHIFT_6 <= "01000000";
+            SHIFT_7 <= "10000000";
+         elsif (data_mode_i = "0100") then
+            BLANK <= "00000000";
+            SHIFT_0 <= "00000001";
+            SHIFT_1 <= "00000010";
+            SHIFT_2 <= "00000100";
+            SHIFT_3 <= "00001000";
+            SHIFT_4 <= "00010000";
+            SHIFT_5 <= "00100000";
+            SHIFT_6 <= "01000000";
+            SHIFT_7 <= "10000000";
+         elsif (data_mode_i = "0110") then
+            BLANK <= "11111111";
+            SHIFT_0 <= "11111110";
+            SHIFT_1 <= "11111101";
+            SHIFT_2 <= "11111011";
+            SHIFT_3 <= "11110111";
+            SHIFT_4 <= "11101111";
+            SHIFT_5 <= "11011111";
+            SHIFT_6 <= "10111111";
+            SHIFT_7 <= "01111111";
+         else
+            BLANK <= "11111111";
+            SHIFT_0 <= "11111110";
+            SHIFT_1 <= "11111101";
+            SHIFT_2 <= "11111011";
+            SHIFT_3 <= "11110111";
+            SHIFT_4 <= "11101111";
+            SHIFT_5 <= "11011111";
+            SHIFT_6 <= "10111111";
+            SHIFT_7 <= "01111111";
+         end if;
+      end process;
+      
+   end generate;
+   process (data_mode_i)
+   begin
+      if (data_mode_i = "0101") then
+         SHIFTB_0 <= "00000000000000100000000000000001";
+         SHIFTB_1 <= "00000000000010000000000000000100";
+         SHIFTB_2 <= "00000000001000000000000000010000";
+         SHIFTB_3 <= "00000000100000000000000001000000";
+         SHIFTB_4 <= "00000010000000000000000100000000";
+         SHIFTB_5 <= "00001000000000000000010000000000";
+         SHIFTB_6 <= "00100000000000000001000000000000";
+         SHIFTB_7 <= "10000000000000000100000000000000";
+      elsif (data_mode_i = "0100") then
+         SHIFTB_0 <= "00000000000000000000000000000001";
+         SHIFTB_1 <= "00000000000000000000000000000010";
+         SHIFTB_2 <= "00000000000000000000000000000100";
+         SHIFTB_3 <= "00000000000000000000000000001000";
+         SHIFTB_4 <= "00000000000000000000000000010000";
+         SHIFTB_5 <= "00000000000000000000000000100000";
+         SHIFTB_6 <= "00000000000000000000000001000000";
+         SHIFTB_7 <= "00000000000000000000000010000000";
+      else
+         SHIFTB_0 <= "11111111111111011111111111111110";
+         SHIFTB_1 <= "11111111111101111111111111111011";
+         SHIFTB_2 <= "11111111110111111111111111101111";
+         SHIFTB_3 <= "11111111011111111111111110111111";
+         SHIFTB_4 <= "11111101111111111111111011111111";
+         SHIFTB_5 <= "11110111111111111111101111111111";
+         SHIFTB_6 <= "11011111111111111110111111111111";
+         SHIFTB_7 <= "01111111111111111011111111111111";
+      end if;
+   end process;
+   
+   xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
+      
+      process (clk_i)
+      begin
+         if (clk_i'event and clk_i = '1') then
+            if (rst_i = '1') then
+               w1data <= (others => '0');
+               ndata_rising <= '1';
+               shift_en <= '0';
+            elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
+               if (NUM_DQ_PINS = 16) then
+                  if (cmd_startC = '1') then
+                     case addr_i(4 downto 2) is
+                        when "000" =>
+                           w1data <= SHIFTB_0;
+                        when "001" =>
+                           w1data <= SHIFTB_1;
+                        when "010" =>
+                           w1data <= SHIFTB_2;
+                        when "011" =>
+                           w1data <= SHIFTB_3;
+                        when "100" =>
+                           w1data <= SHIFTB_4;
+                        when "101" =>
+                           w1data <= SHIFTB_5;
+                        when "110" =>
+                           w1data <= SHIFTB_6;
+                        
+                        when "111" =>
+                           w1data <= SHIFTB_7;
+                        when others =>
+                           w1data <= SHIFTB_0;
+                     end case;
+                     
+                     ndata_rising <= '0';               --(NUM_DQ_PINS == 16) (cmd_startC)  
+                  --shifting
+                  elsif (data_mode_i = "0100") then
+                     w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
+                  else
+                     
+                     w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14));              --(DQ_PINS == 16 
+                  end if;
+               elsif (NUM_DQ_PINS = 8) then
+                  if (cmd_startC = '1') then            -- loading data pattern according the incoming address
+                     case addr_i(2) is
+                        when '0' =>
+                           w1data <= SHIFTB_0;
+                        when '1' =>
+                           w1data <= SHIFTB_1;
+                        when others =>
+                           w1data <= SHIFTB_0;
+                     end case;
+                  else
+                     -- (cmd_startC)   
+                     -- Shifting
+                     -- need neigbour pattern ********************
+                     
+                     w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4));              --(NUM_DQ_PINS == 8)
+                  end if;
+               elsif (NUM_DQ_PINS = 4) then             -- NUM_DQ_PINS == 4   
+                  -- need neigbour pattern ********************      
+                  if (data_mode_i = "0100") then
+                     w1data <= "00001000000001000000001000000001";
+                  else
+                     w1data <= "10000100001000011000010000100001";              -- (NUM_DQ_PINS_4    
+                  end if;
+               end if;
+            end if;
+         end if;
+      end process;
+      
+      
+--      <outdent>               -- DWIDTH == 32
+      end generate;
+      
+      xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
+         
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+                  
+               w1data <= (others => '0');
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
+                  
+                  if (NUM_DQ_PINS = 16) then
+                     if (cmd_startC = '1') then
+                        
+                        
+                        case addr_i(4 downto 3) is
+                           --  7:0
+                           
+                           when "00" =>
+                              w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
+                           
+                           when "01" =>
+                              w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
+                           when "10" =>
+                              w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
+                           
+                           when "11" =>
+                              w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
+                           --15:8 
+                           
+                           when others =>
+                              w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
+                        end case;
+                     else
+                        
+                        --(NUM_DQ_PINS == 16) (cmd_startC)      
+                        --shifting
+                        if (data_mode_i = "0100") then
+                           w1data(63 downto 48) <= "0000000000000000";
+                           w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
+                           w1data(31 downto 16) <= "0000000000000000";
+                           
+                           w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
+                        else
+                           
+--                           w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
+                           w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
+                                                            w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
+                                                           w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
+                                                            w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
+                                                           w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
+                                                            w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
+                                                           w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
+                                                            w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
+                        end if;
+                     end if;
+                  
+                  --(DQ_PINS == 16 
+                  elsif (NUM_DQ_PINS = 8) then
+                     if (cmd_startC = '1') then         -- loading data pattern according the incoming address
+                        
+                        if (data_mode_i = "0100") then
+                           
+                           case addr_i(3) is
+                              
+                              when '0' =>
+                                 w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
+                              
+                              when '1' =>
+                                 w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
+                              --15:8 
+                              
+                              when others =>
+                                 w1data <= (others => '0');--"00000000000000000000000000000000";
+                           end case;
+                        else
+                           
+                           w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001");         --**** checked
+                           w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001");         --**** checked
+                           w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001");         --**** checked
+                        end if;
+                     -- Shifting
+                     elsif (data_mode_i = "0100") then
+                        
+                        w1data(63 downto 56) <= "00000000";
+                        
+                        w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
+                        w1data(47 downto 40) <= "00000000";
+                        
+                        w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
+                        w1data(31 downto 24) <= "00000000";
+                        
+                        w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
+                        w1data(15 downto 8) <= "00000000";
+                        
+                        w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
+                     else
+                        w1data <= w1data;               --(NUM_DQ_PINS == 8)
+                     end if;
+                  elsif (NUM_DQ_PINS = 4) then          -- NUM_DQ_PINS == 4   
+                     if (data_mode_i = "0100") then
+                        w1data <=  "0000100000000100000000100000000100001000000001000000001000000001";
+                     else
+                        
+                        w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
+                     end if;
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      
+      xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
+         
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+                  
+               w1data <= (others => '0');
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
+                  
+                  if (NUM_DQ_PINS = 16) then
+                     if (cmd_startC = '1') then
+                        
+                        case addr_i(4) is
+                           
+                           --  32                                       
+                           
+                           when '0' =>
+                              w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
+                              w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
+                              w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
+                           
+                           --  32                                       
+                           
+                           when '1' =>
+                              w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
+                              w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
+                              w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
+                           --15:8 
+                           
+                           when others =>
+                              w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
+                        end case;
+                     else
+                        
+                        --(NUM_DQ_PINS == 16) (cmd_startC)      
+                        --shifting
+                        if (data_mode_i = "0100") then
+                           w1data(127 downto 112) <= "0000000000000000";
+                           w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
+                           w1data(95 downto 80) <= "0000000000000000";
+                           
+                           w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
+                           w1data(63 downto 48) <= "0000000000000000";
+                           w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
+                           w1data(31 downto 16) <= "0000000000000000";
+                           
+                           w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
+                        else
+                           
+                           w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
+                        end if;
+                     end if;
+                  
+                  --(DQ_PINS == 16 
+                  elsif (NUM_DQ_PINS = 8) then
+                     if (cmd_startC = '1') then         -- loading data pattern according the incoming address
+                        if (data_mode_i = "0100") then
+                           w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
+                        else
+                           
+                           w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0);           -- (cmd_startC) 
+                        end if;
+                     else
+                        -- Shifting
+                        
+                        --{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]}; 
+                        w1data <= w1data;               -- else
+                     end if;
+                  --(NUM_DQ_PINS == 8)
+                  elsif (data_mode_i = "0100") then
+                     w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
+                  else
+                     
+                     w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      -- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins 
+      --                 => the rsing data pattern will be    32'b11111111_11111111_11111111_11111111
+      --                 => the falling data pattern will be  32'b00000000_00000000_00000000_00000000
+      xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+                  hdata <= (others => '0');
+--               elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
+
+                  if (NUM_DQ_PINS = 16) then
+                     hdata <= "00000000000000001111111111111111";
+                  elsif (NUM_DQ_PINS = 8) then
+                     hdata <= "00000000111111110000000011111111";               -- NUM_DQ_PINS == 4    
+                  elsif (NUM_DQ_PINS = 4) then
+                     hdata <= "00001111000011110000111100001111";
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+               hdata <= (others => '0');
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
+                  if (NUM_DQ_PINS = 16) then
+                  hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
+                  elsif (NUM_DQ_PINS = 8) then
+                  hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
+                  elsif (NUM_DQ_PINS = 4) then
+                     
+                  hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+               hdata <= (others => '0');
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
+                  if (NUM_DQ_PINS = 16) then
+                  hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
+                  elsif (NUM_DQ_PINS = 8) then
+                  hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
+                  elsif (NUM_DQ_PINS = 4) then
+                     
+                  hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      process (w1data, hdata)
+      begin
+         for i in 0 to  DWIDTH - 1 loop
+            
+            ndata(i) <= hdata(i) xor w1data(i);
+         end loop;
+      end process;
+      
+      
+      -- HAMMER_PATTERN_MINUS: generate walking HAMMER  data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine 
+      -- the position of the pin driving oppsite polarity
+      --  addr_i[6:2] = 5'h0f ; 32 bit data port
+      --                 => the rsing data pattern will be    32'b11111111_11111111_01111111_11111111
+      --                 => the falling data pattern will be  32'b00000000_00000000_00000000_00000000
+      
+      -- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
+      -- Dataport 32 bit width with starting addr_i  = 30'h12345678, user burst length 4
+      --                 => the 1st data pattern :     32'h12345678
+      --                 => the 2nd data pattern :     32'h12345679
+      --                 => the 3rd data pattern :     32'h1234567a
+      --                 => the 4th data pattern :     32'h1234567b
+      
+      --data_rdy_i
+      
+      xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
+         --data_o logic
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (cmd_startD = '1') then
+                  adata <= addr_i;
+               elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
+                 if (DWIDTH = 128) then
+                    adata <= adata + "00000000000000000000000000010000";
+                 elsif (DWIDTH = 64) then
+                    adata <= adata + "00000000000000000000000000001000";               -- DWIDTH == 32   
+                 else
+                  adata <= adata + "00000000000000000000000000000100";
+                 end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      -- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
+      -- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
+      --                
+      
+      xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
+         
+         --   PRBS DATA GENERATION
+         -- xor all the tap positions before feedback to 1st stage.
+         
+--         data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
+           data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';         
+         
+         
+         data_prbs_gen_inst : data_prbs_gen
+            generic map (
+               prbs_width  => 32,
+               seed_width  => 32
+            )
+            port map (
+               clk_i           => clk_i,
+               clk_en          => data_clk_en,
+               rst_i           => rst_i,
+               prbs_fseed_i    => prbs_fseed_i,
+               prbs_seed_init  => cmd_startE,
+               prbs_seed_i     => addr_i(31 downto 0),
+               prbs_o          => prbs_data
+            );
+         
+      end generate;
+      
+      
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/tg_status.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/tg_status.vhd
new file mode 100755
index 0000000..ec3aa9d
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/tg_status.vhd
@@ -0,0 +1,142 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: tg_status.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:42 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:  This module compare the memory read data agaisnt compare data that generated from data_gen module.
+--          Error signal will be asserted if the comparsion is not equal.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+entity tg_status is
+   generic (
+      TCQ             : TIME   := 100 ps;
+      DWIDTH                         : integer := 32
+   );
+   port (
+      
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic;
+      manual_clear_error             : in std_logic;
+      data_error_i                   : in std_logic;
+      cmp_data_i                     : in std_logic_vector(DWIDTH - 1 downto 0);
+      rd_data_i                      : in std_logic_vector(DWIDTH - 1 downto 0);
+      cmp_addr_i                     : in std_logic_vector(31 downto 0);
+      cmp_bl_i                       : in std_logic_vector(5 downto 0);
+      mcb_cmd_full_i                 : in std_logic;
+      mcb_wr_full_i                  : in std_logic;
+      mcb_rd_empty_i                 : in std_logic;
+      error_status                   : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
+      error                          : out std_logic
+   );
+end entity tg_status;
+
+architecture trans of tg_status is
+   
+   signal data_error_r             : std_logic;
+   signal error_set                : std_logic;
+begin
+   error <= error_set;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         
+         data_error_r <= data_error_i;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         
+         if ((rst_i or manual_clear_error) = '1') then
+--            error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+              error_status <= (others => '0');
+            error_set <= '0';
+         else
+            -- latch the first error only
+            if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
+               error_status(31 downto 0) <= cmp_addr_i;
+               error_status(37 downto 32) <= cmp_bl_i;
+               error_status(40) <= mcb_cmd_full_i;
+               error_status(41) <= mcb_wr_full_i;
+               error_status(42) <= mcb_rd_empty_i;
+               error_set <= '1';
+               error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
+               
+               error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
+            end if;
+            
+            error_status(39 downto 38) <= "00";		-- reserved
+            
+            error_status(63 downto 43) <= "000000000000000000000";		-- reserved
+         end if;
+      end if;
+   end process;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/v6_data_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/v6_data_gen.vhd
new file mode 100755
index 0000000..34b1766
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/v6_data_gen.vhd
@@ -0,0 +1,3276 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : %version
+--  \   \         Application        : MIG
+--  /   /         Filename           : v6_data_gen.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:43 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+-- Device       : Virtex6
+-- Design Name  : DDR2/DDR3
+-- Purpose      : This module generates different data pattern as described in
+--                parameter DATA_PATTERN and is set up for Virtex 6 family.
+-- Reference    :
+-- Revision History:
+--*****************************************************************************
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity v6_data_gen is
+   generic (
+      EYE_TEST        : string := "FALSE";
+      ADDR_WIDTH      : integer := 32;
+      MEM_BURST_LEN   : integer := 8;
+      BL_WIDTH        : integer := 6;
+      DWIDTH          : integer := 288;
+      DATA_PATTERN    : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
+      NUM_DQ_PINS     : integer := 72;
+      COLUMN_WIDTH    : integer := 10;
+      SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+   );
+   port (
+      clk_i           : in std_logic;
+      rst_i           : in std_logic;
+      prbs_fseed_i    : in std_logic_vector(31 downto 0);
+      data_mode_i     : in std_logic_vector(3 downto 0);
+      data_rdy_i      : in std_logic;
+      cmd_startA      : in std_logic;
+      cmd_startB      : in std_logic;
+      cmd_startC      : in std_logic;
+      cmd_startD      : in std_logic;
+      cmd_startE      : in std_logic;
+      m_addr_i        : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      fixed_data_i    : in std_logic_vector(DWIDTH-1 downto 0);
+      addr_i          : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      user_burst_cnt  : in std_logic_vector(6 downto 0);
+      fifo_rdy_i      : in std_logic;
+      data_o          : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
+   );
+end entity v6_data_gen;
+
+architecture trans of v6_data_gen is
+
+component data_prbs_gen is
+   generic (
+      EYE_TEST        : string := "FALSE";
+      PRBS_WIDTH      : integer := 32;
+      SEED_WIDTH      : integer := 32
+     );
+   port (
+      clk_i           : in std_logic;
+      clk_en          : in std_logic;
+      rst_i           : in std_logic;
+      prbs_fseed_i    : in std_logic_vector(31 downto 0);
+      prbs_seed_init  : in std_logic;
+      prbs_seed_i     : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
+
+      prbs_o          : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
+   );
+end component;
+
+   constant ALL_0               : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
+   signal prbs_data             : std_logic_vector(31 downto 0);
+   signal acounts               : std_logic_vector(35 downto 0);
+   signal adata                 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal hdata                 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal ndata                 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal w1data                : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal w0data                : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal data                  : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal tstpts                : std_logic_vector(7 downto 0);
+   signal burst_count_reached2  : std_logic;
+   signal data_valid            : std_logic;
+   signal walk_cnt              : std_logic_vector(2 downto 0);
+   signal user_address          : std_logic_vector(ADDR_WIDTH - 1 downto 0);
+   signal sel_w1gen_logic       : std_logic;
+   --signal BLANK                 : std_logic_vector(7 downto 0);
+   --signal SHIFT_0               : std_logic_vector(7 downto 0);
+   --signal SHIFT_1               : std_logic_vector(7 downto 0);
+   --signal SHIFT_2               : std_logic_vector(7 downto 0);
+   --signal SHIFT_3               : std_logic_vector(7 downto 0);
+   --signal SHIFT_4               : std_logic_vector(7 downto 0);
+   --signal SHIFT_5               : std_logic_vector(7 downto 0);
+   --signal SHIFT_6               : std_logic_vector(7 downto 0);
+   --signal SHIFT_7               : std_logic_vector(7 downto 0);
+   signal sel_victimline_r      : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
+   signal data_clk_en           : std_logic;
+   signal full_prbs_data        : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal h_prbsdata            : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal i                     : integer;
+   signal j                     : integer;
+
+   signal data_mode_rr_a        : std_logic_vector(3 downto 0);
+   signal data_mode_rr_b        : std_logic_vector(3 downto 0);
+   signal data_mode_rr_c        : std_logic_vector(3 downto 0);
+   signal prbs_seed_i           : std_logic_vector(31 downto 0);
+
+  function concat ( in1 : integer;
+                    in2 : std_logic_vector) return std_logic_vector is
+  variable rang : integer := in2'length;
+  variable temp : std_logic_vector(in1*rang-1 downto 0);
+  begin
+    for i in 0 to in1-1 loop
+      temp(rang*(i+1)-1 downto rang*i) := in2;
+    end loop;
+
+  return temp;
+  end function;
+
+
+  function Data_Gen ( int       : integer
+                     ) return std_logic_vector is
+
+    variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
+    variable j : integer;
+  begin
+    j := int/2;
+      if((int mod 2) = 1) then
+
+       data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
+       data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
+       data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
+       data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
+     else
+       data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
+       data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
+       data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
+       data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
+     end if;
+
+
+
+    return data_bus;
+  end function;
+
+  function Data_GenW0 ( int       : integer) return std_logic_vector is
+
+    variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
+    variable j : integer;
+  begin
+    j := int/2;
+      if((int mod 2) = 1) then
+        data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
+        data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
+        data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
+        data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
+      else
+        data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
+        data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
+        data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
+        data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
+      end if;
+
+    return data_bus;
+  end function;
+
+  
+
+begin
+   data_o         <= data;
+   full_prbs_data <= concat(DWIDTH/32,prbs_data);
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         data_mode_rr_a <= data_mode_i;
+         data_mode_rr_b <= data_mode_i;
+         data_mode_rr_c <= data_mode_i;
+      end if;
+   end process;
+
+
+   process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
+   begin
+      case data_mode_rr_a is
+         when "0000" =>
+            data <= h_prbsdata;
+         when "0001" =>     --  "0001" = fixed data
+            data <= fixed_data_i;
+         when "0010" =>     --  "0010" = address as data
+            data <= adata;
+         when "0011" =>     --  "0011" = hammer
+            data <= hdata;
+         when "0100" =>     --  "0100" = neighbour
+            data <= ndata;
+         when "0101" =>     --  "0101" = walking 1's
+            data <= w1data;
+            
+         when "0110" =>     --  "0110" = walking 0's
+            data <= w1data;
+         when "0111" =>     --  "0111" = prbs
+            data <= full_prbs_data;
+         when others =>
+            data <= (others => '0');
+      end case;
+   end process;
+
+--   process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
+--   begin
+--      case data_mode_rr_a is
+--         when "0000" =>
+--            data <= h_prbsdata;
+--         when "0001" =>     --  "0001" = fixed data
+--             data <= fixed_data_i;
+--         when "0010" =>     --  "0010" = address as data
+--            data <= adata;
+--         when "0011" =>     --  "0011" = hammer
+--            data <= hdata;
+--         when "0100" =>     --  "0100" = neighbour
+--            data <= ndata;
+--         when "0111" =>     --  "0111" = prbs
+--            data <= full_prbs_data;
+--         when others =>
+--            data <= w1data;
+--      end case;
+--   end process;
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
+            sel_w1gen_logic <= '1';
+         else
+            sel_w1gen_logic <= '0';
+         end if;
+      end if;
+   end process;
+
+   WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if (fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(3) is
+
+                 when '0' =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                   else
+                       w1data <= Data_GenW0(0);
+                   end if;
+                 when '1' =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                   else
+                       w1data <= Data_GenW0(1);
+                   end if;
+                 when others =>
+                   w1data <= (others => '0');
+
+                 end case;
+               end if;
+             elsif (MEM_BURST_LEN = 8) then
+               w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+               w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+               w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+               w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+             end if;
+           end if;
+         end if;
+       end process;
+     end generate;
+
+   WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(4 downto 3) is
+
+                 when "00" =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                   else
+                       w1data <= Data_GenW0(0);
+                   end if;
+
+                 when "01" =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                   else
+                       w1data <= Data_GenW0(1);
+                   end if;
+
+                 when "10" =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                   else
+                       w1data <= Data_GenW0(2);
+                   end if;
+
+                 when "11" =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                   else
+                       w1data <= Data_GenW0(3);
+                   end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(7 downto 3) is
+
+                 when "00000" | "00110" | "01100" |
+                      "10010" | "11000" | "11110" =>
+            --       when  "10010" | "11000"=> 
+   
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                   else
+                       w1data <= Data_GenW0(0);
+                   end if;
+
+                when "00001" | "00111" | "01101" |
+                     "10011" | "11001" | "11111" =>
+                  if (data_mode_i = "0101") then
+                      w1data <= Data_Gen(1);
+                  else
+                      w1data <= Data_GenW0(1);
+                  end if;
+
+                 when "00010" | "01000" | "01110" |  --2,8,14,20,26  
+                      "10100" | "11010"           =>
+ 
+                   if (data_mode_i = "0101") then
+                         w1data <= Data_Gen(2);
+                   else
+                       w1data <= Data_GenW0(2);
+                   end if;
+
+                 when "00011" | "01001" | "01111" |  --3,9,15,21,27
+                    "10101" | "11011"           =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+
+               when "00100" | "01010" | "10000" |
+                    "10110" | "11100"           =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+               when "00101" | "01011" | "10001" |
+                    "10111" | "11101"           =>
+                  
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(5);
+                 end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;  -- cmd_startC
+         end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
+       end if;  -- clk
+     end process;
+   end generate;
+
+   WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(6 downto 4) is
+
+                 when "000" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                 else
+                     w1data <= Data_GenW0(0);
+                 end if;
+
+                 when "001" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                 else
+                     w1data <= Data_GenW0(1);
+                 end if;
+
+                 when "010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                 else
+                     w1data <= Data_GenW0(2);
+                 end if;
+
+                 when "011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+
+                 when "100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+                 when "101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(5);
+                 end if;
+
+                 when "110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(6);
+                 else
+                     w1data <= Data_GenW0(6);
+                 end if;
+
+                 when "111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(7);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+--
+   WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(7 downto 4) is
+
+                 when "0000" | "1010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                 else
+                     w1data <= Data_GenW0(0);
+                 end if;
+
+                 when "0001" | "1011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                 else
+                     w1data <= Data_GenW0(1);
+                 end if;
+
+                 when "0010" | "1100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                 else
+                     w1data <= Data_GenW0(2);
+                 end if;
+
+                 when "0011" | "1101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+
+                 when "0100" | "1110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+                 when "0101" | "1111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when "0110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(6);
+                 else
+                     w1data <= Data_GenW0(6);
+                 end if;
+
+                 when "0111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(7);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when "1000" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(8);
+                 else
+                     w1data <= Data_GenW0(8);
+                 end if;
+
+                 when "1001" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(9);
+                 else
+                     w1data <= Data_GenW0(9);
+                 end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_48_PATTERN : 
+   if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(7 downto 4) is
+
+                 when "0000" | "1100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                 else
+                     w1data <= Data_GenW0(0);
+                 end if;
+
+                 when "0001" | "1101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                 else
+                     w1data <= Data_GenW0(1);
+                 end if;
+
+                 when "0010" | "1110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                 else
+                     w1data <= Data_GenW0(2);
+                 end if;
+
+                 when "0011" | "1111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+
+                 when "0100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+                 when "0101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(5);
+                 end if;
+
+                 when "0110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(6);
+                 else
+                     w1data <= Data_GenW0(6);
+                 end if;
+
+                 when "0111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(7);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when "1000" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(8);
+                 else
+                     w1data <= Data_GenW0(8);
+                 end if;
+
+                 when "1001" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(9);
+                 else
+                     w1data <= Data_GenW0(9);
+                 end if;
+
+                 when "1010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(10);
+                 else
+                     w1data <= Data_GenW0(10);
+                 end if;
+
+                 when "1011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(11);
+                 else
+                     w1data <= Data_GenW0(11);
+                 end if;
+--
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+
+WALKING_ONE_56_PATTERN:
+    if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(8 downto 5) is
+
+                 when "0000" | "1110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                 else
+                     w1data <= Data_GenW0(0);
+                 end if;
+
+
+                 when "0001" | "1111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                 else
+                     w1data <= Data_GenW0(1);
+                 end if;
+
+
+                 when "0010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                 else
+                     w1data <= Data_GenW0(2);
+                 end if;
+
+
+                 when "0011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+                 when "0100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else 
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+                 when "0101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(5);
+                 end if;
+
+                 when "0110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(6);
+                 else 
+                     w1data <= Data_GenW0(6);
+                 end if;
+
+                 when "0111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(7);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when "1000" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(8);
+                 else
+                     w1data <= Data_GenW0(8);
+                 end if;
+
+                 when "1001" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(9);
+                 else
+                     w1data <= Data_GenW0(9);
+                 end if;
+
+                 when "1010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(10);
+                 else
+                     w1data <= Data_GenW0(10);
+                 end if;
+                 when "1011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(11);
+                 else
+                     w1data <= Data_GenW0(11);
+                 end if;
+
+                 when "1100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(12);
+                 else
+                     w1data <= Data_GenW0(12);
+                 end if;
+
+                 when "1101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(13);
+                 else
+                     w1data <= Data_GenW0(13);
+                 end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+--
+WALKING_ONE_64_PATTERN :
+if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(8 downto 5) is
+
+                 when "0000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(0);
+                     else
+                         w1data <= Data_GenW0(0);
+                     end if;
+
+                 when "0001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(1);
+                     else
+                         w1data <= Data_GenW0(1);
+                     end if;
+
+                 when "0010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(2);
+                     else
+                         w1data <= Data_GenW0(2);
+                     end if;
+
+                 when "0011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(3);
+                     else
+                         w1data <= Data_GenW0(3);
+                     end if;
+
+                 when "0100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(4);
+                     else
+                         w1data <= Data_GenW0(4);
+                     end if;
+
+                 when "0101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(5);
+                     else
+                         w1data <= Data_GenW0(5);
+                     end if;
+
+                 when "0110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(6);
+                     else
+                         w1data <= Data_GenW0(6);
+                     end if;
+
+                 when "0111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(7);
+                     else
+                         w1data <= Data_GenW0(7);
+                     end if;
+
+                 when "1000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(8);
+                     else
+                         w1data <= Data_GenW0(8);
+                     end if;
+
+                 when "1001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(9);
+                     else
+                         w1data <= Data_GenW0(9);
+                     end if;
+
+                 when "1010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(10);
+                     else
+                         w1data <= Data_GenW0(10);
+                     end if;
+
+                 when "1011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(11);
+                     else
+                         w1data <= Data_GenW0(11);
+                     end if;
+
+                 when "1100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(12);
+                     else
+                         w1data <= Data_GenW0(12);
+                     end if;
+
+                 when "1101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(13);
+                     else
+                         w1data <= Data_GenW0(13);
+                     end if;
+
+                 when "1110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(14);
+                     else
+                         w1data <= Data_GenW0(14);
+                     end if;
+
+                 when "1111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(15);
+                     else
+                         w1data <= Data_GenW0(15);
+                     end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+WALKING_ONE_72_PATTERN :
+   if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "10010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(0);
+                     else
+                         w1data <= Data_GenW0(0);
+                     end if;
+
+                 when "00001" | "10011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(1);
+                     else
+                         w1data <= Data_GenW0(1);
+                     end if;
+
+                 when "00010" | "10100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(2);
+                     else
+                         w1data <= Data_GenW0(2);
+                     end if;
+
+                 when "00011" | "10101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(3);
+                     else
+                         w1data <= Data_GenW0(3);
+                     end if;
+
+                 when "00100" | "10110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(4);
+                     else
+                         w1data <= Data_GenW0(4);
+                     end if;
+
+                 when "00101" | "10111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(5);
+                     else
+                         w1data <= Data_GenW0(5);
+                     end if;
+
+                 when "00110" | "11000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(6);
+                     else
+                         w1data <= Data_GenW0(6);
+                     end if;
+
+                 when "00111" | "11001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(7);
+                     else
+                         w1data <= Data_GenW0(7);
+                     end if;
+
+                 when "01000" | "11010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(8);
+                     else
+                         w1data <= Data_GenW0(8);
+                     end if;
+
+                 when "01001" | "11011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(9);
+                     else
+                         w1data <= Data_GenW0(9);
+                     end if;
+
+                 when "01010" |  "11100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(10);
+                     else
+                         w1data <= Data_GenW0(10);
+                     end if;
+
+                 when "01011" | "11101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(11);
+                     else
+                         w1data <= Data_GenW0(11);
+                     end if;
+
+                 when "01100" | "11110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(12);
+                     else
+                         w1data <= Data_GenW0(12);
+                     end if;
+
+                 when "01101" | "11111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(13);
+                     else
+                         w1data <= Data_GenW0(13);
+                     end if;
+
+                 when "01110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(14);
+                     else
+                         w1data <= Data_GenW0(14);
+                     end if;
+
+                 when "01111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(15);
+                     else
+                         w1data <= Data_GenW0(15);
+                     end if;
+
+                 when "10000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(16);
+                     else
+                         w1data <= Data_GenW0(16);
+                     end if;
+
+                 when "10001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(17);
+                     else
+                         w1data <= Data_GenW0(17);
+                     end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+WALKING_ONE_80_PATTERN :
+
+   if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "10100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(0);
+                     else
+                         w1data <= Data_GenW0(0);
+                     end if;
+
+                 when "00001" | "10101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(1);
+                     else
+                         w1data <= Data_GenW0(1);
+                     end if;
+
+                 when "00010" | "10110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(2);
+                     else
+                         w1data <= Data_GenW0(2);
+                     end if;
+
+                 when "00011" | "10111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(3);
+                     else
+                         w1data <= Data_GenW0(3);
+                     end if;
+
+                 when "00100" | "11000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(4);
+                     else
+                         w1data <= Data_GenW0(4);
+                     end if;
+
+                 when "00101" | "11001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(5);
+                     else
+                         w1data <= Data_GenW0(5);
+                     end if;
+
+                 when "00110" | "11010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(6);
+                     else
+                         w1data <= Data_GenW0(6);
+                     end if;
+
+                 when "00111" | "11011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(7);
+                     else
+                         w1data <= Data_GenW0(7);
+                     end if;
+
+                 when "01000" | "11100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(8);
+                     else
+                         w1data <= Data_GenW0(8);
+                     end if;
+
+                 when "01001" | "11101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(9);
+                     else
+                         w1data <= Data_GenW0(9);
+                     end if;
+
+                 when "01010" |  "11110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(10);
+                     else
+                         w1data <= Data_GenW0(10);
+                     end if;
+
+                 when "01011" | "11111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(11);
+                     else
+                         w1data <= Data_GenW0(11);
+                     end if;
+
+                 when "01100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(12);
+                     else
+                         w1data <= Data_GenW0(12);
+                     end if;
+
+                 when "01101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(13);
+                     else
+                         w1data <= Data_GenW0(13);
+                     end if;
+
+                 when "01110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(14);
+                     else
+                         w1data <= Data_GenW0(14);
+                     end if;
+
+                 when "01111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(15);
+                     else
+                         w1data <= Data_GenW0(15);
+                     end if;
+
+                 when "10000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(16);
+                     else
+                         w1data <= Data_GenW0(16);
+                     end if;
+
+                 when "10001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(17);
+                     else
+                         w1data <= Data_GenW0(17);
+                     end if;
+
+                 when "10010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(18);
+                     else
+                         w1data <= Data_GenW0(18);
+                     end if;
+
+                 when "10011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(19);
+                     else
+                         w1data <= Data_GenW0(19);
+                     end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+WALKING_ONE_88_PATTERN:
+     if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" | "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" | "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" | "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" | "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" | "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" | "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+
+WALKING_ONE_96_PATTERN:
+     if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" | "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" | "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" | "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" | "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else 
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_104_PATTERN:
+     if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" | "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" | "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+
+                 when "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_112_PATTERN:
+      if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+
+                 when "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+
+                 when "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+
+                 when "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_120_PATTERN:
+      if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if; 
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+
+                 when "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+
+                 when "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+
+                 when "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+
+                 when "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(28);
+                       else
+                           w1data <= Data_GenW0(28);
+                       end if;
+
+                 when "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(29);
+                       else
+                           w1data <= Data_GenW0(29);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_128_PATTERN:
+     if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(10 downto 6) is
+
+                 when "00000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+
+                 when "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+
+                 when "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+
+                 when "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+
+                 when "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(28);
+                       else
+                           w1data <= Data_GenW0(28);
+                       end if;
+
+                 when "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(29);
+                       else
+                           w1data <= Data_GenW0(29);
+                       end if;
+
+                 when "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(30);
+                       else
+                           w1data <= Data_GenW0(30);
+                       end if;
+
+                 when "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(31);
+                       else
+                           w1data <= Data_GenW0(31);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_136_PATTERN:
+     if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(11 downto 6) is
+
+                 when "000000"  =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+               when "000001" | "100011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(1);
+                     else
+                         w1data <= Data_GenW0(1);
+                     end if;
+
+               when "000010" | "100100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(2);
+                     else
+                         w1data <= Data_GenW0(2);
+                     end if;
+           
+               when "000011" | "100101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(3);
+                     else
+                         w1data <= Data_GenW0(3);
+                     end if;
+           
+               when "000100" | "100110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(4);
+                     else 
+                         w1data <= Data_GenW0(4);
+                     end if;
+           
+               when "000101" | "100111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(5);
+                     else
+                         w1data <= Data_GenW0(5);
+                     end if;
+           
+               when "000110" | "101000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(6);
+                     else
+                         w1data <= Data_GenW0(6);
+                     end if;
+           
+               when "000111" | "101001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(7);
+                     else
+                         w1data <= Data_GenW0(7);
+                     end if;
+           
+               when "001000" | "101010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(8);
+                     else
+                         w1data <= Data_GenW0(8);
+                     end if;
+           
+                 when "001001" | "101011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+           
+                 when "001010" | "101100" =>
+                       if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(10);
+                     else
+                         w1data <= Data_GenW0(10);
+                     end if;
+           
+               when "001011" | "101101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(11);
+                     else
+                         w1data <= Data_GenW0(11);
+                     end if;
+           
+               when "001100" | "101110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(12);
+                     else
+                         w1data <= Data_GenW0(12);
+                     end if;
+           
+               when "001101" | "101111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(13);
+                     else
+                         w1data <= Data_GenW0(13);
+                     end if;
+           
+               when "001110" | "110000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(14);
+                     else
+                         w1data <= Data_GenW0(14);
+                     end if;
+           
+               when "001111" | "110001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(15);
+                     else
+                         w1data <= Data_GenW0(15);
+                     end if;
+           
+               when "010000" | "110010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(16);
+                     else
+                         w1data <= Data_GenW0(16);
+                     end if;
+           
+               when "010001" | "110011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(17);
+                     else
+                         w1data <= Data_GenW0(17);
+                     end if;
+           
+               when "010010" | "110100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(18);
+                     else
+                         w1data <= Data_GenW0(18);
+                     end if;
+           
+               when "010011" | "110101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(19);
+                     else
+                         w1data <= Data_GenW0(19);
+                     end if;
+           
+               when "010100" | "110110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(20);
+                     else
+                         w1data <= Data_GenW0(20);
+                     end if;
+           
+               when "010101" | "110111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(21);
+                     else
+                         w1data <= Data_GenW0(21);
+                     end if;
+           
+               when "010110" | "111000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(22);
+                     else
+                         w1data <= Data_GenW0(22);
+                     end if;
+           
+               when "010111" | "111001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+        
+                 when "011000" | "111010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+        
+                 when "011001" | "111011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+        
+                 when "011010" | "111100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+        
+                 when "011011" | "111101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+        
+                 when "011100" | "111110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(28);
+                       else
+                           w1data <= Data_GenW0(28);
+                       end if;
+        
+                 when "011101" | "111111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(29);
+                       else
+                           w1data <= Data_GenW0(29);
+                       end if;
+        
+                 when "011110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(30);
+                       else
+                           w1data <= Data_GenW0(30);
+                       end if;
+        
+                 when "011111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(31);
+                       else
+                           w1data <= Data_GenW0(31);
+                       end if;
+        
+                 when "100000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(32);
+                       else
+                           w1data <= Data_GenW0(32);
+                       end if;
+        
+                 when "100001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(33);
+                       else
+                           w1data <= Data_GenW0(33);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_144_PATTERN:
+      if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(11 downto 6) is
+
+                 when "000000" | "100100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "000001" | "100101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else 
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "000010" | "100110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "000011" | "100111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "000100" | "101000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "000101" | "101001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "000110" | "101010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+                 when "000111" | "101011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+         
+                 when "001000" | "101100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+         
+                 when "001001" | "101101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+         
+                 when "001010" | "101110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+         
+                 when "001011" | "101111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+         
+                 when "001100" | "110000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+         
+                 when "001101" | "110001" =>
+                     if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+         
+                 when "001110" | "110010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+         
+                 when "001111" | "110011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+         
+                when "010000" | "110100" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(16);
+                      else
+                          w1data <= Data_GenW0(16);
+                      end if;
+         
+                when "010001" | "110101" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(17);
+                      else
+                          w1data <= Data_GenW0(17);
+                      end if;
+         
+                when "010010" | "110110" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(18);
+                      else
+                          w1data <= Data_GenW0(18);
+                      end if;
+         
+                when "010011" | "110111" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(19);
+                      else
+                          w1data <= Data_GenW0(19);
+                      end if;
+         
+                when "010100" | "111000" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(20);
+                      else
+                          w1data <= Data_GenW0(20);
+                      end if;
+         
+                when "010101" | "111001" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(21);
+                      else
+                          w1data <= Data_GenW0(21);
+                      end if;
+         
+                when "010110" | "111010" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(22);
+                      else
+                          w1data <= Data_GenW0(22);
+                      end if;
+         
+                when "010111" | "111011" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(23);
+                      else
+                          w1data <= Data_GenW0(23);
+                      end if;
+         
+                when "011000" | "111100" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(24);
+                      else
+                          w1data <= Data_GenW0(24);
+                      end if;
+         
+                 when "011001" | "111101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+         
+                 when "011010" | "111110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+         
+                 when "011011" | "111111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+         
+                 when "011100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(28);
+                       else
+                           w1data <= Data_GenW0(28);
+                       end if;
+         
+                 when "011101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(29);
+                       else
+                           w1data <= Data_GenW0(29);
+                       end if;
+         
+                 when "011110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(30);
+                       else
+                           w1data <= Data_GenW0(30);
+                       end if;
+         
+                 when "011111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(31);
+                       else
+                           w1data <= Data_GenW0(31);
+                       end if;
+         
+                 when "100000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(32);
+                       else
+                           w1data <= Data_GenW0(32);
+                       end if;
+         
+                 when "100001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(33);
+                       else
+                           w1data <= Data_GenW0(33);
+                       end if;
+         
+                 when "100010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(34);
+                       else
+                           w1data <= Data_GenW0(34);
+                       end if;
+         
+                 when "100011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(35);
+                       else
+                           w1data <= Data_GenW0(35);
+                       end if;
+         
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+
+   process (clk_i)
+   begin
+     if (clk_i'event and clk_i = '1') then
+       for i in 0 to  4 * NUM_DQ_PINS - 1 loop
+         if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
+           hdata(i) <= '1';
+         elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
+           hdata(i) <= '1';
+         elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
+           hdata(i) <= '0';
+         elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
+           hdata(i) <= '1';
+         elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
+           hdata(i) <= '0';
+         else
+           hdata(i) <= '1';
+         end if;
+       end loop;
+     end if;
+   end process;
+
+   process (w1data, hdata)
+   begin
+      for i in 0 to 4 * NUM_DQ_PINS - 1 loop
+         ndata(i) <= hdata(i) xor w1data(i);
+      end loop;
+   end process;
+
+   process (full_prbs_data, hdata)
+   begin
+     for i in 0 to  4 * NUM_DQ_PINS - 1 loop
+       if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
+         h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
+       else
+         h_prbsdata(i) <= hdata(i);
+       end if;
+     end loop;
+   end process;
+
+   addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if (cmd_startD = '1') then
+           acounts <= ("0000" & addr_i);
+         elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
+           if (NUM_DQ_PINS = 8 ) then
+             acounts <= acounts + X"000000004";
+           elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
+             acounts <= acounts + X"000000008";
+           elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
+             acounts <= acounts +  X"000000010";
+           elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
+             acounts <= acounts + X"000000020";
+           elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
+             acounts <= acounts + X"000000040";
+           end if;
+         end if;
+       end if;
+     end process;
+
+     adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
+
+     end generate;
+
+     -- When doing eye_test, traffic gen only does write and want to
+     -- keep the prbs random and address is fixed at a location.
+     d_clk_en1 : if (EYE_TEST = "TRUE") generate
+        data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
+     end generate;
+
+     d_clk_en2 : if (EYE_TEST = "FALSE") generate
+        data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
+     end generate;
+
+     prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
+
+        -- PRBS DATA GENERATION
+        -- xor all the tap positions before feedback to 1st stage.
+        prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
+
+        data_prbs_gen_inst : data_prbs_gen
+           generic map (
+              PRBS_WIDTH  => 32,
+              SEED_WIDTH  => 32,
+              EYE_TEST    => EYE_TEST
+           )
+           port map (
+              clk_i           => clk_i,
+              rst_i           => rst_i,
+              clk_en          => data_clk_en,
+              prbs_fseed_i    => prbs_fseed_i,
+              prbs_seed_init  => cmd_startE,
+              prbs_seed_i     => prbs_seed_i,
+              prbs_o          => prbs_data
+           );
+
+     end generate;
+
+end architecture trans;
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/wr_data_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/wr_data_gen.vhd
new file mode 100755
index 0000000..e2c40d2
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/wr_data_gen.vhd
@@ -0,0 +1,511 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: wr_data_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+   use ieee.numeric_std.all;
+
+entity wr_data_gen is
+   generic (
+      
+      TCQ                            : TIME   := 100 ps;
+      FAMILY                         : string := "SPARTAN6";            -- "SPARTAN6", "VIRTEX6"
+      MEM_BURST_LEN                  : integer := 8;
+      
+      MODE                           : string := "WR";          --"WR", "RD"
+      ADDR_WIDTH                     : integer := 32;
+      BL_WIDTH                       : integer := 6;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_PRBS";           --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      SEL_VICTIM_LINE                : integer := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+      
+      COLUMN_WIDTH                   : integer := 10;
+      EYE_TEST                       : string := "FALSE"
+   );
+   port (
+      
+      clk_i                          : in std_logic;            --
+      rst_i                          : in std_logic_vector(4 downto 0);
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      
+      data_mode_i                    : in std_logic_vector(3 downto 0);         -- "00" = bram; 
+      
+      cmd_rdy_o                      : out std_logic;           -- ready to receive command. It should assert when data_port is ready at the                                        // beginning and will be deasserted once see the cmd_valid_i is asserted. 
+      -- And then it should reasserted when 
+      -- it is generating the last_word.
+      cmd_valid_i                    : in std_logic;            -- when both cmd_valid_i and cmd_rdy_o is high, the command  is valid.
+      cmd_validB_i                   : in std_logic;
+      cmd_validC_i                   : in std_logic;
+      
+      last_word_o                    : out std_logic;
+      
+      --  input [5:0] port_data_counts_i,// connect to data port fifo counts
+--      m_addr_i                       : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);  
+      addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);            -- generated address used to determine data pattern.
+      bl_i                           : in std_logic_vector(BL_WIDTH - 1 downto 0);              -- generated burst length for control the burst data
+      
+      data_rdy_i                     : in std_logic;            -- connect from mcb_wr_full when used as wr_data_gen
+      -- connect from mcb_rd_empty when used as rd_data_gen
+      -- When both data_rdy and data_valid is asserted, the ouput data is valid.
+      data_valid_o                   : out std_logic;           -- connect to wr_en or rd_en and is asserted whenever the 
+      -- pattern is available.
+      data_o                         : out std_logic_vector(DWIDTH - 1 downto 0);               -- generated data pattern   
+      data_wr_end_o                  : out std_logic
+   );
+end entity wr_data_gen;
+
+architecture trans of wr_data_gen is
+
+COMPONENT sp6_data_gen IS
+   GENERIC (
+      
+      ADDR_WIDTH      : INTEGER := 32;
+      BL_WIDTH        : INTEGER := 6;
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_PRBS";
+      NUM_DQ_PINS     : INTEGER := 8;
+      COLUMN_WIDTH    : INTEGER := 10
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      cmd_startA      : IN STD_LOGIC;
+      cmd_startB      : IN STD_LOGIC;
+      cmd_startC      : IN STD_LOGIC;
+      cmd_startD      : IN STD_LOGIC;
+      cmd_startE      : IN STD_LOGIC;
+      fixed_data_i    : IN std_logic_vector(DWIDTH - 1 downto 0);  
+      
+      addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      user_burst_cnt  : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
+      
+      fifo_rdy_i      : IN STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
+   );
+END COMPONENT;   
+
+COMPONENT v6_data_gen IS
+   GENERIC (
+      
+      ADDR_WIDTH      : INTEGER := 32;
+      BL_WIDTH        : INTEGER := 6;
+      MEM_BURST_LEN                  : integer := 8;
+
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_PRBS";
+      NUM_DQ_PINS     : INTEGER := 8;
+      SEL_VICTIM_LINE : INTEGER := 3;
+      COLUMN_WIDTH    : INTEGER := 10;
+      EYE_TEST        : STRING  := "FALSE"
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      cmd_startA      : IN STD_LOGIC;
+      cmd_startB      : IN STD_LOGIC;
+      cmd_startC      : IN STD_LOGIC;
+      cmd_startD      : IN STD_LOGIC;
+      fixed_data_i    : IN std_logic_vector(DWIDTH - 1 downto 0);  
+      cmd_startE      : IN STD_LOGIC;
+      m_addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      user_burst_cnt  : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
+      
+      fifo_rdy_i      : IN STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
+   );
+END COMPONENT;      
+
+   signal data                          : std_logic_vector(DWIDTH - 1 downto 0);
+   
+   signal cmd_rdy                       : std_logic;
+   signal cmd_rdyB                      : std_logic;
+   signal cmd_rdyC                      : std_logic;
+   signal cmd_rdyD                      : std_logic;
+   signal cmd_rdyE                      : std_logic;
+   signal cmd_rdyF                      : std_logic;
+   signal cmd_start                     : std_logic;
+   signal cmd_startB                    : std_logic;
+   signal cmd_startC                    : std_logic;
+   signal cmd_startD                    : std_logic;
+   signal cmd_startE                    : std_logic;
+   signal cmd_startF                    : std_logic;
+   
+   signal burst_count_reached2          : std_logic;
+   
+   signal data_valid                    : std_logic;
+   signal user_burst_cnt                : std_logic_vector(6 downto 0);
+   signal walk_cnt                      : std_logic_vector(2 downto 0);
+   
+   signal fifo_not_full                 : std_logic;
+   signal i                             : integer;
+   signal j                             : integer;
+   signal w3data                        : std_logic_vector(31 downto 0);
+   
+   -- counter to count user burst length
+   
+   -- bl_i;
+   
+   signal u_bcount_2                    : std_logic;
+   signal last_word_t                   : std_logic;
+   
+   -- Declare intermediate signals for referenced outputs
+   signal last_word_o_xhdl1             : std_logic;
+   signal data_o_xhdl0                  : std_logic_vector(DWIDTH - 1 downto 0);
+   signal tpt_hdata_xhdl2               : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+begin
+   -- Drive referenced outputs
+   last_word_o <= last_word_o_xhdl1;
+   data_o <= data_o_xhdl0;
+   fifo_not_full <= data_rdy_i;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
+            data_wr_end_o <= '1';
+         else
+            data_wr_end_o <= '0';
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         cmd_start <= cmd_validC_i and cmd_rdyC;
+         cmd_startB <= cmd_valid_i and cmd_rdyB;
+         cmd_startC <= cmd_validB_i and cmd_rdyC;
+         cmd_startD <= cmd_validB_i and cmd_rdyD;
+         cmd_startE <= cmd_validB_i and cmd_rdyE;
+         cmd_startF <= cmd_validB_i and cmd_rdyF;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            user_burst_cnt <= "0000000" ;
+         elsif (cmd_start = '1') then
+            if (FAMILY = "SPARTAN6") then
+               if (bl_i = "000000") then
+                  user_burst_cnt <= "1000000" ;
+               else
+                  user_burst_cnt <= ('0' & bl_i) ;
+               end if;
+            else
+               user_burst_cnt <= ('0' & bl_i)  ;
+            end if;
+         elsif (fifo_not_full = '1') then
+            if (user_burst_cnt /= "0000000") then
+               user_burst_cnt <= user_burst_cnt - "0000001"  ;
+            else
+               user_burst_cnt <= "0000000"  ;
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
+            u_bcount_2 <= '1' ;
+         elsif (last_word_o_xhdl1 = '1') then
+            u_bcount_2 <= '0' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
+   
+   -- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
+   -- is assert and reassert during the last data
+   
+   cmd_rdy_o <= cmd_rdy and fifo_not_full;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdy <= '1' ;
+         elsif (cmd_start = '1') then
+            if (bl_i = "000001") then
+               cmd_rdy <= '1' ;
+            else
+               cmd_rdy <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdy <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyB <= '1' ;
+         elsif (cmd_startB = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyB <= '1' ;
+            else
+               cmd_rdyB <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyB <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyC <= '1' ;
+         elsif (cmd_startC = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyC <= '1' ;
+            else
+               cmd_rdyC <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyC <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyD <= '1' ;
+         elsif (cmd_startD = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyD <= '1' ;
+            else
+               cmd_rdyD <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyD <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyE <= '1' ;
+         elsif (cmd_startE = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyE <= '1' ;
+            else
+               cmd_rdyE <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyE <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyF <= '1' ;
+         elsif (cmd_startF = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyF <= '1' ;
+            else
+               cmd_rdyF <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyF <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(1)) = '1') then
+            data_valid <= '0' ;
+         elsif (cmd_start = '1') then
+            data_valid <= '1' ;
+         elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
+            data_valid <= '0' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   data_valid_o <= data_valid and fifo_not_full;
+   
+   s6_wdgen : if (FAMILY = "SPARTAN6") generate
+      
+      
+      
+      
+      sp6_data_gen_inst : sp6_data_gen
+         generic map (
+            ADDR_WIDTH    => 32,
+            BL_WIDTH      => BL_WIDTH,
+            DWIDTH        => DWIDTH,
+            DATA_PATTERN  => DATA_PATTERN,
+            NUM_DQ_PINS   => NUM_DQ_PINS,
+            COLUMN_WIDTH  => COLUMN_WIDTH
+         )
+         port map (
+            clk_i           => clk_i,
+            rst_i           => rst_i(1),
+            data_rdy_i      => data_rdy_i,
+            prbs_fseed_i    => prbs_fseed_i,
+            
+            data_mode_i     => data_mode_i,
+            cmd_startA      => cmd_start,
+            cmd_startB      => cmd_startB,
+            cmd_startC      => cmd_startC,
+            cmd_startD      => cmd_startD,
+            cmd_startE      => cmd_startE,
+            fixed_data_i    => fixed_data_i,
+            addr_i          => addr_i,
+            user_burst_cnt  => user_burst_cnt,
+            fifo_rdy_i      => fifo_not_full,
+            data_o          => data_o_xhdl0
+         );
+      
+   end generate;                                    
+                                                    
+   v6_wdgen : if (FAMILY = "VIRTEX6") generate         
+                                                    
+                                                    
+                                                    
+                                                    
+      v6_data_gen_inst : v6_data_gen                
+         generic map (                              
+            ADDR_WIDTH       => 32,
+            BL_WIDTH         => BL_WIDTH,
+            DWIDTH           => DWIDTH,
+            MEM_BURST_LEN    => MEM_BURST_LEN,
+            
+            DATA_PATTERN     => DATA_PATTERN,
+            NUM_DQ_PINS      => NUM_DQ_PINS,        
+            SEL_VICTIM_LINE  => SEL_VICTIM_LINE,    
+            COLUMN_WIDTH     => COLUMN_WIDTH,       
+            EYE_TEST         => EYE_TEST
+         )                                          
+         port map (                                 
+            clk_i           => clk_i,               
+            rst_i           => rst_i(1),               
+            data_rdy_i      => data_rdy_i,          
+            prbs_fseed_i    => prbs_fseed_i,        
+                                                    
+            data_mode_i     => data_mode_i,         
+            cmd_starta      => cmd_start,           
+            cmd_startb      => cmd_startB,          
+            cmd_startc      => cmd_startC,          
+            cmd_startd      => cmd_startD,          
+            cmd_starte      => cmd_startE,          
+            fixed_data_i    => fixed_data_i,        
+            m_addr_i        => addr_i,      --m_addr_i,            
+            addr_i          => addr_i,              
+            user_burst_cnt  => user_burst_cnt,      
+            fifo_rdy_i      => fifo_not_full,       
+            data_o          => data_o_xhdl0         
+         );                                         
+   end generate;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/write_data_path.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/write_data_path.vhd
new file mode 100755
index 0000000..37d0cf4
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/write_data_path.vhd
@@ -0,0 +1,210 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: write_data_path.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This is top level of write path.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+entity write_data_path is
+   generic (
+      TCQ                            : TIME   := 100 ps;
+      MEM_BURST_LEN                  : integer := 8;
+      FAMILY                         : string := "SPARTAN6";
+      ADDR_WIDTH                     : integer := 32;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_ALL";            --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      SEL_VICTIM_LINE                : integer := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+      
+      MEM_COL_WIDTH                  : integer := 10;
+      EYE_TEST                       : string := "FALSE"
+   );
+   port (
+      
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic_vector(9 downto 0);
+      cmd_rdy_o                      : out std_logic;
+      cmd_valid_i                    : in std_logic;
+      cmd_validB_i                   : in std_logic;
+      cmd_validC_i                   : in std_logic;
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      data_mode_i                    : in std_logic_vector(3 downto 0);
+--      m_addr_i                       : in std_logic_vector(31 downto 0);
+      fixed_data_i                   : in std_logic_vector(DWIDTH-1 downto 0);
+      addr_i                         : in std_logic_vector(31 downto 0);
+      
+      bl_i                           : in std_logic_vector(5 downto 0);
+      
+      --   input [5:0]            port_data_counts_i,// connect to data port fifo counts
+      
+      data_rdy_i                     : in std_logic;
+      data_valid_o                   : out std_logic;
+      last_word_wr_o                 : out std_logic;
+      data_o                         : out std_logic_vector(DWIDTH - 1 downto 0);
+      data_mask_o                    : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
+      data_wr_end_o                  : out std_logic   );
+end entity write_data_path;
+
+architecture trans of write_data_path is
+
+   COMPONENT wr_data_gen IS
+      GENERIC (
+      TCQ                            : TIME   := 100 ps;
+      FAMILY                         : STRING  := "SPARTAN6";           -- "SPARTAN6", "VIRTEX6"      
+      MODE                           : STRING  := "WR";         --"WR", "RD"
+      MEM_BURST_LEN                  : integer := 8;      
+      ADDR_WIDTH                     : INTEGER := 32;
+      BL_WIDTH                       : INTEGER := 6;
+      DWIDTH                         : INTEGER := 32;
+      DATA_PATTERN                   : STRING  := "DGEN_PRBS";          --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : INTEGER := 8;
+      SEL_VICTIM_LINE                : INTEGER := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern      
+      COLUMN_WIDTH                   : INTEGER := 10;
+      EYE_TEST                       : STRING  := "FALSE"
+      );
+      PORT (
+         clk_i           : IN STD_LOGIC;
+         rst_i           : in STD_LOGIC_VECTOR(4 downto 0);
+         prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+         cmd_rdy_o       : OUT STD_LOGIC;
+         cmd_valid_i     : IN STD_LOGIC;
+         cmd_validB_i    : IN STD_LOGIC;
+         cmd_validC_i    : IN STD_LOGIC;
+         last_word_o     : OUT STD_LOGIC;
+         fixed_data_i    : IN std_logic_vector(DWIDTH-1 downto 0);
+         
+--         m_addr_i        : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+         addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+         bl_i            : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
+         data_rdy_i      : IN STD_LOGIC;
+         data_valid_o    : OUT STD_LOGIC;
+         data_o          : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+         data_wr_end_o   : OUT STD_LOGIC
+      );
+   END COMPONENT;
+
+   signal data_valid                    : std_logic;
+   signal cmd_rdy                       : std_logic;
+   
+   -- Declare intermediate signals for referenced outputs
+   signal cmd_rdy_o_xhdl0               : std_logic;
+   signal last_word_wr_o_xhdl3          : std_logic;
+   signal data_o_xhdl1                  : std_logic_vector(DWIDTH - 1 downto 0);
+   signal data_wr_end_o_xhdl2           : std_logic;
+begin
+   -- Drive referenced outputs
+   cmd_rdy_o <= cmd_rdy_o_xhdl0;
+   last_word_wr_o <= last_word_wr_o_xhdl3;
+   data_o <= data_o_xhdl1;
+   data_wr_end_o <= data_wr_end_o_xhdl2;
+   
+   data_valid_o <= data_valid and data_rdy_i;
+--   data_mask_o <= "0000";             -- for now 
+   data_mask_o <= (others => '0');   
+   
+   
+   wr_data_gen_inst : wr_data_gen
+      generic map (
+         TCQ              => TCQ,
+         family           => FAMILY,
+         num_dq_pins      => NUM_DQ_PINS,
+         sel_victim_line  => SEL_VICTIM_LINE,
+         MEM_BURST_LEN    => MEM_BURST_LEN,
+         
+         data_pattern     => DATA_PATTERN,
+         dwidth           => DWIDTH,
+         column_width     => MEM_COL_WIDTH,
+         eye_test         => EYE_TEST
+      )
+      port map (
+         clk_i          => clk_i,
+         rst_i          => rst_i(9 downto 5),
+         prbs_fseed_i   => prbs_fseed_i,
+         
+         data_mode_i    => data_mode_i,
+         cmd_rdy_o      => cmd_rdy_o_xhdl0,
+         cmd_valid_i    => cmd_valid_i,
+         cmd_validb_i   => cmd_validB_i,
+         cmd_validc_i   => cmd_validC_i,
+         
+         last_word_o    => last_word_wr_o_xhdl3,
+         --     .port_data_counts_i (port_data_counts_i),
+--         m_addr_i       => m_addr_i,
+         fixed_data_i   => fixed_data_i,
+         addr_i         => addr_i,
+         bl_i           => bl_i,
+         data_rdy_i     => data_rdy_i,
+         data_valid_o   => data_valid,
+         data_o         => data_o_xhdl1,
+         data_wr_end_o  => data_wr_end_o_xhdl2
+      );
+   
+end architecture trans;
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/ddr2_model_c3.v b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/ddr2_model_c3.v
new file mode 100755
index 0000000..cba3e7f
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/ddr2_model_c3.v
@@ -0,0 +1,2031 @@
+/****************************************************************************************
+*
+*    File Name:  ddr2_model.v
+*      Version:  5.82
+*        Model:  BUS Functional
+*
+* Dependencies:  ddr2_model_parameters.vh
+*
+*  Description:  Micron SDRAM DDR2 (Double Data Rate 2)
+*
+*   Limitation:  - doesn't check for average refresh timings
+*                - positive ck and ck_n edges are used to form internal clock
+*                - positive dqs and dqs_n edges are used to latch data
+*                - test mode is not modeled
+*
+*         Note:  - Set simulator resolution to "ps" accuracy
+*                - Set Debug = 0 to disable $display messages
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+* Rev   Author   Date        Changes
+* ---------------------------------------------------------------------------------------
+* 1.00  JMK      07/29/03    Initial Release
+* 1.10  JMK      08/09/03    Timing Parameter updates to tIS, tIH, tDS, tDH
+* 2.20  JMK      08/07/03    General cleanup
+* 2.30  JMK      11/26/03    Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
+*                            Added AL_MIN and AL_MAX parameters.
+*                            Removed support for OCD.
+* 2.40  JMK      01/15/04    Removed verilog 2001 constructs.
+* 2.50  JMK      01/29/04    Removed tRP checks during Precharge command.
+* 2.60  JMK      04/20/04    Fixed tWTR check.
+* 2.70  JMK      04/30/04    Added tRFC maximum check.
+*                            Combined Self Refresh and Power Down always blocks.
+*                            Added Reset Function (CKE LOW Anytime).
+* 2.80  JMK      08/19/04    Precharge is treated as NOP when bank is not active.  
+*                            Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
+*                            tRFC maximum violation will only display one time.
+* 2.90  JMK      11/05/04    Fixed DQS checking during write.
+*                            Fixed false tRFC max assertion during power up and self ref.
+*                            Added warning for 200us CKE low time during initialization.
+*                            Added -3, -3E, and -37V speed grades to ddr2_parameters.v
+* 3.00  JMK      04/22/05    Removed ODT off requirement during power down.
+*                            Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
+*                            Added ODT status messages.
+*                            Updated the initialization sequence.
+*                            Disable ODT and CLK pins during self refresh.
+*                            Disable cmd and addr pins during power down and self refresh.
+* 3.10  JMK      06/07/05    Disable trpa checking if the part does not have 8 banks.
+*                            Changed tAXPD message from error to a warning.
+*                            Added tDSS checking.
+*                            Removed tDQSL checking during tWPRE and tWPST.
+*                            Fixed a burst order error during writes.
+*                            Renamed parameters file with .vh extension.
+* 3.20  JMK      07/18/05    Removed 14 tCK requirement from LMR to READ.
+* 3.30  JMK      08/03/05    Added check for interrupting a burst with auto precharge.
+* 4.00  JMK      11/21/05    Parameter names all UPPERCASE, signal names all lowercase.
+*                            Clock jitter can be tolerated within specification range.
+*                            Clock frequency is sampled from the CK pin.
+*                            Scaleable up to 64 DQ and 16 DQS bits.
+*                            Read data can be randomly skewed using RANDOM_OUT_DELAY.
+*                            Parameterized read and write DQS, and read DQ.
+*                            Initialization can be bypassed using initialize task.
+* 4.10  JMK      11/30/05    Fixed compile errors when `MAX_MEM was defined.
+* 4.20  JMK      12/09/05    Fixed memory addressing error when `MAX_MEM was defined.
+* 4.30  JMK      02/15/06    Added dummy write to initialization sequence.
+*                            Removed tWPST maximum checking.
+*                            Rising dqs_n edge latches data when enabled in EMR.
+*                            Fixed a sign error in the tJIT(cc) calculation.
+* 4.40  JMK      02/16/06    Fixed dummy write when`MAX_MEM was defined.
+* 4.50  JMK      02/27/06    Fixed extra tDQSS assertions.
+*                            Fixed tRCD and tWTR checking.
+*                            Errors entering Power Down or Self Refresh will cause reset.
+*                            Ignore dqs_n when disabled in EMR.
+* 5.00  JMK      04/24/06    Test stimulus now included from external file (subtest.vh)
+*                            Fixed tRFC max assertion during self refresh.
+*                            Fixed tANPD checking during Power Down.
+*                            Removed dummy write from initialization sequence.
+* 5.01  JMK      04/28/06    Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
+*                            Removed Auto Precharge error message during Power Down Enter.
+* 5.10  JMK      07/26/06    Created internal clock using ck and ck_n.
+*                            RDQS can only be enabled in EMR for x8 configurations.
+*                            CAS latency is checked vs frequency when DLL locks.
+*                            tMOD changed from tCK units to ns units.
+*                            Added 50 Ohm setting for Rtt in EMR.
+*                            Improved checking of DQS during writes.
+* 5.20  JMK      10/02/06    Fixed DQS checking for interrupting write to write and x16.
+* 5.30  JMK      05/25/07    Fixed checking for 0-Z transition on write postamble.
+* 5.50  JMK      05/30/08    Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.
+*                            Added a register delay to ddr2_module.v when RDIMM is defined.
+*                            Added multi-chip package model support in ddr2_mcp.v
+*                            Added High Temp Self Refresh rate setting in EMRS2[7]
+* 5.70  JMK      04/23/09    Updated tRPA definition
+*                            Increased internal width to 72 bit DQ bus
+* 5.80  SPH      08/12/09    Fixed tRAS maximum violation (only check if bank still open)
+* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW
+* 5.82  SPH      04/08/10    Correct debug message for SRT in EMR2         
+* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW
+* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW
+****************************************************************************************/
+
+// DO NOT CHANGE THE TIMESCALE
+// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
+`timescale 1ps / 1ps
+
+module ddr2_model_c3 (
+    ck,
+    ck_n,
+    cke,
+    cs_n,
+    ras_n,
+    cas_n,
+    we_n,
+    dm_rdqs,
+    ba,
+    addr,
+    dq,
+    dqs,
+    dqs_n,
+    rdqs_n,
+    odt
+);
+
+    `include "ddr2_model_parameters_c3.vh"
+
+    // text macros
+    `define DQ_PER_DQS DQ_BITS/DQS_BITS
+    `define BANKS      (1<<BA_BITS)
+    `define MAX_BITS   (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
+    `define MAX_SIZE   (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
+    `define MEM_SIZE   (1<<MEM_BITS)
+    `define MAX_PIPE   2*(AL_MAX + CL_MAX)
+
+    // Declare Ports
+    input   ck;
+    input   ck_n;
+    input   cke;
+    input   cs_n;
+    input   ras_n;
+    input   cas_n;
+    input   we_n;
+    inout   [DM_BITS-1:0]   dm_rdqs;
+    input   [BA_BITS-1:0]   ba;
+    input   [ADDR_BITS-1:0] addr;
+    inout   [DQ_BITS-1:0]   dq;
+    inout   [DQS_BITS-1:0]  dqs;
+    inout   [DQS_BITS-1:0]  dqs_n;
+    output  [DQS_BITS-1:0]  rdqs_n;
+    input   odt;
+                            
+    // clock jitter
+    real    tck_avg;
+    time    tck_sample [TDLLK-1:0];
+    time    tch_sample [TDLLK-1:0];
+    time    tcl_sample [TDLLK-1:0];
+    time    tck_i;
+    time    tch_i;
+    time    tcl_i;
+    real    tch_avg;
+    real    tcl_avg;
+    time    tm_ck_pos;
+    time    tm_ck_neg;
+    real    tjit_per_rtime;
+    integer tjit_cc_time;
+    real    terr_nper_rtime;
+
+    // clock skew
+    real    out_delay;
+    integer dqsck [DQS_BITS-1:0];
+    integer dqsck_min;
+    integer dqsck_max;
+    integer dqsq_min;
+    integer dqsq_max;
+    integer seed;
+
+    // Mode Registers
+    reg     burst_order;
+    reg     [BL_BITS:0] burst_length;
+    integer cas_latency;
+    integer additive_latency;
+    reg     dll_reset;
+    reg     dll_locked;
+    reg     dll_en;
+    integer write_recovery;
+    reg     low_power;
+    reg     [1:0] odt_rtt;
+    reg     odt_en;
+    reg     [2:0] ocd;
+    reg     dqs_n_en;
+    reg     rdqs_en;
+    reg     out_en;
+    integer read_latency;
+    integer write_latency;
+
+    // cmd encoding
+    parameter
+        LOAD_MODE = 4'b0000,
+        REFRESH   = 4'b0001,
+        PRECHARGE = 4'b0010,
+        ACTIVATE  = 4'b0011,
+        WRITE     = 4'b0100,
+        READ      = 4'b0101,
+        NOP       = 4'b0111,
+        PWR_DOWN  = 4'b1000,
+        SELF_REF  = 4'b1001
+    ;
+
+    reg [8*9-1:0] cmd_string [9:0];
+    initial begin
+        cmd_string[LOAD_MODE] = "Load Mode";
+        cmd_string[REFRESH  ] = "Refresh  ";
+        cmd_string[PRECHARGE] = "Precharge";
+        cmd_string[ACTIVATE ] = "Activate ";
+        cmd_string[WRITE    ] = "Write    ";
+        cmd_string[READ     ] = "Read     ";
+        cmd_string[NOP      ] = "No Op    ";
+        cmd_string[PWR_DOWN ] = "Pwr Down ";
+        cmd_string[SELF_REF ] = "Self Ref ";
+    end
+
+    // command state
+    reg     [`BANKS-1:0] active_bank;
+    reg     [`BANKS-1:0] auto_precharge_bank;
+    reg     [`BANKS-1:0] write_precharge_bank;
+    reg     [`BANKS-1:0] read_precharge_bank;
+    reg     [ROW_BITS-1:0] active_row [`BANKS-1:0];
+    reg     in_power_down;
+    reg     in_self_refresh;
+    reg     [3:0] init_mode_reg;
+    reg     init_done;
+    integer init_step;
+    reg     er_trfc_max;
+    reg     odt_state;
+    reg     prev_odt;
+
+    // cmd timers/counters
+    integer ref_cntr;
+    integer ck_cntr;
+    integer ck_load_mode;
+    integer ck_write;
+    integer ck_read;
+    integer ck_write_ap;
+    integer ck_power_down;
+    integer ck_slow_exit_pd;
+    integer ck_self_refresh;
+    integer ck_cke;
+    integer ck_odt;
+    integer ck_dll_reset;
+    integer ck_bank_write     [`BANKS-1:0];
+    integer ck_bank_read      [`BANKS-1:0];
+    time    tm_refresh;
+    time    tm_precharge;
+    time    tm_precharge_all;
+    time    tm_activate;
+    time    tm_write_end;
+    time    tm_self_refresh;
+    time    tm_odt_en;
+    time    tm_bank_precharge [`BANKS-1:0];
+    time    tm_bank_activate  [`BANKS-1:0];
+    time    tm_bank_write_end [`BANKS-1:0];
+    time    tm_bank_read_end  [`BANKS-1:0];
+
+    // pipelines
+    reg     [`MAX_PIPE:0]   al_pipeline;
+    reg     [`MAX_PIPE:0]   wr_pipeline;
+    reg     [`MAX_PIPE:0]   rd_pipeline;
+    reg     [`MAX_PIPE:0]   odt_pipeline;
+    reg     [BA_BITS-1:0]   ba_pipeline  [`MAX_PIPE:0];
+    reg     [ROW_BITS-1:0]  row_pipeline [`MAX_PIPE:0];
+    reg     [COL_BITS-1:0]  col_pipeline [`MAX_PIPE:0];
+    reg     prev_cke;
+    
+    // data state
+    reg     [BL_MAX*DQ_BITS-1:0] memory_data;
+    reg     [BL_MAX*DQ_BITS-1:0] bit_mask;
+    reg     [BL_BITS-1:0]        burst_position;
+    reg     [BL_BITS:0]          burst_cntr;
+    reg     [DQ_BITS-1:0]        dq_temp;
+    reg     [35:0] check_write_postamble;
+    reg     [35:0] check_write_preamble;
+    reg     [35:0] check_write_dqs_high;
+    reg     [35:0] check_write_dqs_low;
+    reg     [17:0] check_dm_tdipw;
+    reg     [71:0] check_dq_tdipw;
+
+    // data timers/counters
+    time    tm_cke;
+    time    tm_odt;
+    time    tm_tdqss;
+    time    tm_dm        [17:0];
+    time    tm_dqs       [17:0];
+    time    tm_dqs_pos   [35:0];
+    time    tm_dqss_pos  [35:0];
+    time    tm_dqs_neg   [35:0];
+    time    tm_dq        [71:0];
+    time    tm_cmd_addr  [22:0];
+    reg [8*7-1:0] cmd_addr_string [22:0];
+    initial begin
+        cmd_addr_string[ 0] = "CS_N   ";
+        cmd_addr_string[ 1] = "RAS_N  ";
+        cmd_addr_string[ 2] = "CAS_N  ";
+        cmd_addr_string[ 3] = "WE_N   ";
+        cmd_addr_string[ 4] = "BA 0   ";
+        cmd_addr_string[ 5] = "BA 1   ";
+        cmd_addr_string[ 6] = "BA 2   ";
+        cmd_addr_string[ 7] = "ADDR  0";
+        cmd_addr_string[ 8] = "ADDR  1";
+        cmd_addr_string[ 9] = "ADDR  2";
+        cmd_addr_string[10] = "ADDR  3";
+        cmd_addr_string[11] = "ADDR  4";
+        cmd_addr_string[12] = "ADDR  5";
+        cmd_addr_string[13] = "ADDR  6";
+        cmd_addr_string[14] = "ADDR  7";
+        cmd_addr_string[15] = "ADDR  8";
+        cmd_addr_string[16] = "ADDR  9";
+        cmd_addr_string[17] = "ADDR 10";
+        cmd_addr_string[18] = "ADDR 11";
+        cmd_addr_string[19] = "ADDR 12";
+        cmd_addr_string[20] = "ADDR 13";
+        cmd_addr_string[21] = "ADDR 14";
+        cmd_addr_string[22] = "ADDR 15";
+    end
+
+    reg [8*5-1:0] dqs_string [1:0];
+    initial begin
+        dqs_string[0] = "DQS  ";
+        dqs_string[1] = "DQS_N";
+    end
+
+    // Memory Storage
+`ifdef MAX_MEM
+    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MAX_SIZE-1];
+`else
+    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MEM_SIZE-1];
+    reg     [`MAX_BITS-1:0]      address [0:`MEM_SIZE-1];
+    reg     [MEM_BITS:0]         memory_index;
+    reg     [MEM_BITS:0]         memory_used;
+`endif
+
+    // receive
+    reg            ck_in;
+    reg            ck_n_in;
+    reg            cke_in;
+    reg            cs_n_in;
+    reg            ras_n_in;
+    reg            cas_n_in;
+    reg            we_n_in;
+    reg     [17:0] dm_in;
+    reg     [2:0]  ba_in;
+    reg     [15:0] addr_in;
+    reg     [71:0] dq_in;
+    reg     [35:0] dqs_in;
+    reg            odt_in;
+
+    reg     [17:0] dm_in_pos;
+    reg     [17:0] dm_in_neg;
+    reg     [71:0] dq_in_pos;
+    reg     [71:0] dq_in_neg;
+    reg            dq_in_valid;
+    reg            dqs_in_valid;
+    integer        wdqs_cntr;
+    integer        wdq_cntr;
+    integer        wdqs_pos_cntr [35:0];
+    reg            b2b_write;
+    reg     [35:0] prev_dqs_in;
+    reg            diff_ck;
+
+    always @(ck     ) ck_in     <= #BUS_DELAY ck;
+    always @(ck_n   ) ck_n_in   <= #BUS_DELAY ck_n;
+    always @(cke    ) cke_in    <= #BUS_DELAY cke;
+    always @(cs_n   ) cs_n_in   <= #BUS_DELAY cs_n;
+    always @(ras_n  ) ras_n_in  <= #BUS_DELAY ras_n;
+    always @(cas_n  ) cas_n_in  <= #BUS_DELAY cas_n;
+    always @(we_n   ) we_n_in   <= #BUS_DELAY we_n;
+    always @(dm_rdqs) dm_in     <= #BUS_DELAY dm_rdqs;
+    always @(ba     ) ba_in     <= #BUS_DELAY ba;
+    always @(addr   ) addr_in   <= #BUS_DELAY addr;
+    always @(dq     ) dq_in     <= #BUS_DELAY dq;
+    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;
+    always @(odt    ) odt_in    <= #BUS_DELAY odt;
+    // create internal clock
+    always @(posedge ck_in)   diff_ck <= ck_in;
+    always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
+
+    wire    [17:0] dqs_even = dqs_in[17:0];
+    wire    [17:0] dqs_odd  = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];
+    wire    [3:0]  cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP;  //deselect = nop 
+
+    // transmit
+    reg                    dqs_out_en;
+    reg     [DQS_BITS-1:0] dqs_out_en_dly;
+    reg                    dqs_out;
+    reg     [DQS_BITS-1:0] dqs_out_dly;
+    reg                    dq_out_en;
+    reg     [DQ_BITS-1:0]  dq_out_en_dly;
+    reg     [DQ_BITS-1:0]  dq_out;
+    reg     [DQ_BITS-1:0]  dq_out_dly;
+    integer                rdqsen_cntr;
+    integer                rdqs_cntr;
+    integer                rdqen_cntr;
+    integer                rdq_cntr;
+
+    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}});
+    bufif1 buf_dm     [DM_BITS-1:0]  (dm_rdqs, dqs_out_dly,  dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
+    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
+    bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n,  ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
+    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}});
+
+    initial begin
+        if (BL_MAX < 2) 
+            $display("%m ERROR: BL_MAX parameter must be >= 2.  \nBL_MAX = %d", BL_MAX);
+        if ((1<<BO_BITS) > BL_MAX) 
+            $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
+        $timeformat (-12, 1, " ps", 1);
+        reset_task;
+        seed = RANDOM_SEED;
+        ck_cntr = 0;
+    end
+
+    // calculate the absolute value of a real number
+    function real abs_value;
+    input arg;
+    real arg;
+    begin
+        if (arg < 0.0)
+            abs_value = -1.0 * arg;
+        else
+            abs_value = arg;
+    end
+    endfunction
+
+`ifdef MAX_MEM
+`else
+    function get_index;
+        input [`MAX_BITS-1:0] addr;
+        begin : index
+            get_index = 0;
+            for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
+                if (address[memory_index] == addr) begin
+                    get_index = 1;
+                    disable index;
+                end
+            end
+        end
+    endfunction
+`endif
+
+    task memory_write;
+        input  [BA_BITS-1:0]  bank;
+        input  [ROW_BITS-1:0] row;
+        input  [COL_BITS-1:0] col;
+        input  [BL_MAX*DQ_BITS-1:0] data;
+        reg    [`MAX_BITS-1:0] addr;
+        begin
+            // chop off the lowest address bits
+            addr = {bank, row, col}/BL_MAX;
+`ifdef MAX_MEM
+            memory[addr] = data;
+`else
+            if (get_index(addr)) begin
+                address[memory_index] = addr;
+                memory[memory_index] = data;
+            end else if (memory_used == `MEM_SIZE) begin
+                $display ("%m: at time %t ERROR: Memory overflow.  Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
+                if (STOP_ON_ERROR) $stop(0);
+            end else begin
+                address[memory_used] = addr;
+                memory[memory_used] = data;
+                memory_used = memory_used + 1;
+            end
+`endif
+        end
+    endtask
+
+    task memory_read;
+        input  [BA_BITS-1:0]  bank;
+        input  [ROW_BITS-1:0] row;
+        input  [COL_BITS-1:0] col;
+        output [BL_MAX*DQ_BITS-1:0] data;
+        reg    [`MAX_BITS-1:0] addr;
+        begin
+            // chop off the lowest address bits
+            addr = {bank, row, col}/BL_MAX;
+`ifdef MAX_MEM
+            data = memory[addr];
+`else
+            if (get_index(addr)) begin
+                data = memory[memory_index];
+            end else begin
+                data = {BL_MAX*DQ_BITS{1'bx}};
+            end
+`endif
+        end
+    endtask
+
+    // Before this task runs, the model must be in a valid state for precharge power down.
+    // After this task runs, NOP commands must be issued until tRFC has been met
+    task initialize;
+        input [ADDR_BITS-1:0] mode_reg0;
+        input [ADDR_BITS-1:0] mode_reg1;
+        input [ADDR_BITS-1:0] mode_reg2;
+        input [ADDR_BITS-1:0] mode_reg3;
+        begin
+            if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
+            cmd_task(1,       NOP, 'bx, 'bx);
+            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL
+            cmd_task(1, LOAD_MODE, 3, mode_reg3);
+            cmd_task(1, LOAD_MODE, 2, mode_reg2);
+            cmd_task(1, LOAD_MODE, 1, mode_reg1);
+            cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
+            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL
+            cmd_task(1,   REFRESH, 'bx, 'bx);
+            cmd_task(1,   REFRESH, 'bx, 'bx);
+            cmd_task(1, LOAD_MODE, 0, mode_reg0);
+            cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
+            cmd_task(1, LOAD_MODE, 1, mode_reg1);
+            cmd_task(0,       NOP, 'bx, 'bx);
+        end
+    endtask
+    
+    task reset_task;
+        integer i;
+        begin
+            // disable inputs
+            dq_in_valid          = 0;
+            dqs_in_valid        <= 0;
+            wdqs_cntr            = 0;
+            wdq_cntr             = 0;
+            for (i=0; i<36; i=i+1) begin
+                wdqs_pos_cntr[i]    <= 0;
+            end
+            b2b_write           <= 0;
+            // disable outputs
+            out_en               = 0;
+            dqs_n_en             = 0;
+            rdqs_en              = 0;
+            dq_out_en            = 0;
+            rdq_cntr             = 0;
+            dqs_out_en           = 0;
+            rdqs_cntr            = 0;
+            // disable ODT
+            odt_en               = 0;
+            odt_state            = 0;
+            // reset bank state
+            active_bank          = {`BANKS{1'b1}};
+            auto_precharge_bank  = 0;
+	        read_precharge_bank  = 0;
+	        write_precharge_bank = 0;
+            // require initialization sequence
+            init_done            = 0;
+            init_step            = 0;
+            init_mode_reg        = 0;
+            // reset DLL
+            dll_en               = 0;
+            dll_reset            = 0;
+            dll_locked           = 0;
+            ocd                  = 0;
+            // exit power down and self refresh
+            in_power_down        = 0;
+            in_self_refresh      = 0;
+            // clear pipelines
+            al_pipeline          = 0;
+            wr_pipeline          = 0;
+            rd_pipeline          = 0;
+            odt_pipeline         = 0;
+            // clear memory
+`ifdef MAX_MEM
+            for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
+                memory[i] <= 'bx;
+            end
+`else
+            memory_used <= 0; //erase memory
+`endif
+            // clear maximum timing checks
+            tm_refresh <= 'bx;
+            for (i=0; i<`BANKS; i=i+1) begin
+                tm_bank_activate[i] <= 'bx;
+            end
+        end
+    endtask
+
+    task chk_err;
+        input samebank;
+        input [BA_BITS-1:0] bank;
+        input [3:0] fromcmd;
+        input [3:0] cmd;
+        reg err;
+    begin
+        // all matching case expressions will be evaluated
+        casex ({samebank, fromcmd, cmd})
+            {1'b0, LOAD_MODE, 4'b0xxx  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                       $display ("%m: at time %t ERROR:  tMRD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, LOAD_MODE, 4'b100x  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                 begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time);                    init_done = 0; end end
+            {1'b0, REFRESH  , 4'b0xxx  } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                       $display ("%m: at time %t ERROR:  tRFC violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, REFRESH  , PWR_DOWN } : ; // 1 tCK
+            {1'b0, REFRESH  , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                 begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time);                       init_done = 0; end end
+            {1'b0, PRECHARGE, 4'b000x  } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);
+                                                 if ($time - tm_precharge < TRP)                                                                                          $display ("%m: at time %t ERROR:   tRP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA))                                                                          $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);
+                                                 if (DEBUG && ($time - tm_bank_precharge[bank] < TRP))                                                                    $display ("%m: at time %t INFO: Precharge bank %d interruption during %s", $time, cmd_string[cmd], bank);  end
+            {1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);
+                                                 if ($time - tm_bank_precharge[bank] < TRP)                                                                               $display ("%m: at time %t ERROR:   tRP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
+            {1'b0, PRECHARGE, SELF_REF } : begin if (($time - tm_precharge_all < TRPA) || ($time - tm_precharge < TRP))                                             begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time);                     init_done = 0; end end
+            {1'b0, ACTIVATE , REFRESH  } : begin if ($time - tm_activate < TRC)                                                                                           $display ("%m: at time %t ERROR:   tRC violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b1, ACTIVATE , PRECHARGE} : begin if (($time - tm_bank_activate[bank] > TRAS_MAX) && (active_bank[bank] === 1'b1))                                         $display ("%m: at time %t ERROR:  tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
+                                                 if ($time - tm_bank_activate[bank] < TRAS_MIN)                                                                           $display ("%m: at time %t ERROR:  tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
+            {1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD)                                                                                          $display ("%m: at time %t ERROR:  tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC)                                                                                $display ("%m: at time %t ERROR:   tRC violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b1, ACTIVATE , 4'b010x  } : ; // tRCD is checked outside this task
+            {1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
+            {1'b1, WRITE    , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR))        $display ("%m: at time %t ERROR:   tWR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , WRITE    } : begin if (ck_cntr - ck_write < TCCD)                                                                                           $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , READ     } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency))           $display ("%m: at time %t ERROR:  tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && (
+                                                    |write_precharge_bank
+                                                 || (ck_cntr - ck_write_ap < 1)
+                                                 || (ck_cntr - ck_write < write_latency + burst_length/2 + 2) 
+                                                 || ($time - tm_write_end < TWTR)))                                                                                 begin $display ("%m: at time %t INFO: Write to Reset condition", $time);                         init_done = 0; end end
+            {1'b1, READ     , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP))       $display ("%m: at time %t ERROR:  tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , WRITE    } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency))                 $display ("%m: at time %t ERROR:  tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , READ     } : begin if (ck_cntr - ck_read < TCCD)                                                                                            $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1))                           begin $display ("%m: at time %t INFO: Read to Reset condition", $time);                          init_done = 0; end end
+            {1'b0, PWR_DOWN , 4'b00xx  } : begin if (ck_cntr - ck_power_down < TXP)                                                                                       $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, PWR_DOWN , WRITE    } : begin if (ck_cntr - ck_power_down < TXP)                                                                                       $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, PWR_DOWN , READ     } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency)                                                               $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
+                                            else if (ck_cntr - ck_power_down < TXARD)                                                                                     $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , 4'b00xx  } : begin if ($time - tm_self_refresh < TXSNR)                                                                                     $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , WRITE    } : begin if ($time - tm_self_refresh < TXSNR)                                                                                     $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , READ     } : begin if (ck_cntr - ck_self_refresh < TXSRD)                                                                                   $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, 4'b100x  , 4'b100x  } : begin if (ck_cntr - ck_cke < TCKE)                                                                                       begin $display ("%m: at time %t ERROR:  tCKE violation on CKE", $time);                          init_done = 0; end end
+        endcase
+    end
+    endtask
+
+    task cmd_task;
+        input cke;
+        input [2:0] cmd;
+        input [BA_BITS-1:0] bank;
+        input [ADDR_BITS-1:0] addr;
+        reg [`BANKS:0] i;
+        integer j;
+        reg [`BANKS:0] tfaw_cntr;
+        reg [COL_BITS-1:0] col;
+        begin
+
+            // tRFC max check
+            if (!er_trfc_max && !in_self_refresh) begin
+                if ($time - tm_refresh > TRFC_MAX) begin
+                    $display ("%m: at time %t ERROR:  tRFC maximum violation during %s", $time, cmd_string[cmd]);
+                    er_trfc_max = 1;
+                end
+            end
+            if (cke) begin
+                if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin
+                    for (j=0; j<NOP; j=j+1) begin
+                        chk_err(1'b0, bank, j, cmd);
+                        chk_err(1'b1, bank, j, cmd);
+                    end
+                    chk_err(1'b0, bank, PWR_DOWN, cmd);
+                    chk_err(1'b0, bank, SELF_REF, cmd);
+                end
+
+                case (cmd)
+                    LOAD_MODE : begin
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
+                            case (bank)
+                                0 : begin
+                                    // Burst Length
+                                    burst_length = 1<<addr[2:0];
+                                    if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
+                                    end
+                                    // Burst Order
+                                    burst_order = addr[3];
+                                    if (!burst_order) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
+                                    end else if (burst_order) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
+                                    end
+                                    // CAS Latency
+                                    cas_latency = addr[6:4];
+                                    read_latency = cas_latency + additive_latency;
+                                    write_latency = read_latency - 1;
+                                    if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
+                                    end
+                                    // Test Mode
+                                    if (!addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
+                                    end
+                                    // DLL Reset
+                                    dll_reset = addr[8];
+                                    if (!dll_reset) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
+                                    end else if (dll_reset) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
+                                        dll_locked = 0;
+                                        ck_dll_reset <= ck_cntr;
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
+                                    end
+                                    // Write Recovery
+                                    write_recovery  = addr[11:9] + 1;
+                                    if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
+                                    end
+                                    // Power Down Mode
+                                    low_power = addr[12];
+                                    if (!low_power) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
+                                    end else if (low_power) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
+                                    end
+                                end
+                                1 : begin
+                                    // DLL Enable
+                                    dll_en = !addr[0];
+                                    if (!dll_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (dll_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
+                                    end
+                                    // Output Drive Strength
+                                    if (!addr[1]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
+                                    end else if (addr[1]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
+                                    end
+                                    // ODT Rtt
+                                    odt_rtt = {addr[6], addr[2]};
+                                    if (odt_rtt == 2'b00) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
+                                        odt_en = 0;
+                                    end else if (odt_rtt == 2'b01) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else if (odt_rtt == 2'b10) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else if (odt_rtt == 2'b11) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
+                                        odt_en = 0;
+                                    end
+                                    // Additive Latency
+                                    additive_latency = addr[5:3];
+                                    read_latency = cas_latency + additive_latency;
+                                    write_latency = read_latency - 1;
+                                    if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
+                                    end
+                                    // OCD Program
+                                    ocd = addr[9:7];
+                                    if (ocd == 3'b000) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
+                                    end else if (ocd == 3'b111) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
+                                    end
+
+                                    // DQS_N Enable
+                                    dqs_n_en = !addr[10];
+                                    if (!dqs_n_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (dqs_n_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
+                                    end 
+                                    // RDQS Enable
+                                    rdqs_en = addr[11];
+                                    if (!rdqs_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (rdqs_en) begin
+`ifdef x8
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
+`else
+                                        $display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable.  RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
+                                        rdqs_en = 0;
+`endif
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
+                                    end 
+                                    // Output Enable
+                                    out_en = !addr[12];
+                                    if (!out_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (out_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
+                                    end 
+                                end
+                                2 : begin
+                                    // High Temperature Self Refresh rate
+                                    if (!addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 1X (0C-85C)", $time, cmd_string[cmd], bank);
+                                    end else if (addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 2X (>85C)", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]);
+                                    end
+                                    if ((addr & ~(1<<7)) !== 0) begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
+                                    end
+                                end
+                                3 : begin
+                                    if (addr !== 0) begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
+                                    end
+                                end
+                            endcase
+                            init_mode_reg[bank] = 1;
+                            ck_load_mode <= ck_cntr;
+                        end
+                    end
+                    REFRESH : begin
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
+                            er_trfc_max = 0;
+                            ref_cntr = ref_cntr + 1;
+                            tm_refresh <= $time;
+                        end
+                    end
+                    PRECHARGE : begin
+                        if (addr[AP]) begin
+                            // tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
+                            // the number of banks already open or closed.
+                            for (i=0; i<`BANKS; i=i+1) begin
+                                for (j=0; j<NOP; j=j+1) begin
+                                    chk_err(1'b0, i, j, cmd);
+                                    chk_err(1'b1, i, j, cmd);
+                                end
+                                chk_err(1'b0, i, PWR_DOWN, cmd);
+                                chk_err(1'b0, i, SELF_REF, cmd);
+                            end
+                            if (|auto_precharge_bank) begin
+                                $display ("%m: at time %t ERROR: %s All Failure.  Auto Precharge is scheduled.", $time, cmd_string[cmd]);
+                                if (STOP_ON_ERROR) $stop(0);
+                            end else begin
+                                if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
+                                active_bank = 0;
+                                tm_precharge_all <= $time;
+                            end
+                        end else begin
+                            // A PRECHARGE command is allowed if there is no open row in that bank (idle state) 
+                            // or if the previously open row is already in the process of precharging. 
+                            // However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
+                            if (auto_precharge_bank[bank]) begin
+                                $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                                if (STOP_ON_ERROR) $stop(0);
+                            end else begin
+                                if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], bank);
+                                active_bank[bank] = 1'b0;
+                                tm_bank_precharge[bank] <= $time;
+                                tm_precharge <= $time;
+                            end
+                        end
+                    end
+                    ACTIVATE : begin
+                        if (`BANKS == 8) begin
+                            tfaw_cntr = 0;
+                            for (i=0; i<`BANKS; i=i+1) begin
+                                if ($time - tm_bank_activate[i] < TFAW) begin
+                                    tfaw_cntr = tfaw_cntr + 1;
+                                end
+                            end
+                            if (tfaw_cntr > 3) begin
+                                $display ("%m: at time %t ERROR:  tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
+                            end
+                        end
+
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr >= 1<<ROW_BITS) begin
+                                $display ("%m: at time %t WARNING: row = %h does not exist.  Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
+                            active_bank[bank] = 1'b1;
+                            active_row[bank] = addr;
+                            tm_bank_activate[bank] <= $time;
+                            tm_activate <= $time;
+                        end
+                        
+                    end
+                    WRITE : begin
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (!active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (auto_precharge_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr[AP]) begin
+                                auto_precharge_bank[bank] = 1'b1;
+                                write_precharge_bank[bank] = 1'b1;
+                            end
+                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
+                            if (col >= 1<<COL_BITS) begin
+                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
+                            wr_pipeline[2*write_latency + 1]  = 1;
+                            ba_pipeline[2*write_latency + 1]  = bank;
+                            row_pipeline[2*write_latency + 1] = active_row[bank];
+                            col_pipeline[2*write_latency + 1] = col;
+                            ck_bank_write[bank] <= ck_cntr;
+                            ck_write <= ck_cntr;
+                        end
+                    end
+                    READ : begin
+                        if (!dll_locked)
+                            $display ("%m: at time %t WARNING: %s prior to DLL locked.  Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (!active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (auto_precharge_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr[AP]) begin
+                                auto_precharge_bank[bank] = 1'b1;
+                                read_precharge_bank[bank] = 1'b1;
+                            end
+                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
+                            if (col >= 1<<COL_BITS) begin
+                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
+                            rd_pipeline[2*read_latency - 1]  = 1;
+                            ba_pipeline[2*read_latency - 1]  = bank;
+                            row_pipeline[2*read_latency - 1] = active_row[bank];
+                            col_pipeline[2*read_latency - 1] = col;
+                            ck_bank_read[bank] <= ck_cntr;
+                            ck_read <= ck_cntr;
+                        end
+                    end
+                    NOP: begin
+                        if (in_power_down) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
+                            in_power_down = 0;
+                            if (|active_bank & low_power) begin // slow exit active power down
+                                ck_slow_exit_pd <= ck_cntr;
+                            end
+                            ck_power_down <= ck_cntr;
+                        end
+                        if (in_self_refresh) begin
+                            if ($time - tm_cke < TISXR)
+                                $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
+                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
+                            in_self_refresh = 0;
+                            ck_dll_reset <= ck_cntr;
+                            ck_self_refresh <= ck_cntr;
+                            tm_self_refresh <= $time;
+                            tm_refresh <= $time;
+                        end
+                    end
+                endcase
+                if ((prev_cke !== 1) && (cmd !== NOP)) begin
+                    $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
+                end
+                if (!init_done) begin
+                    case (init_step)
+                        0 : begin
+                            if ($time < 200000000) 
+                                $display ("%m: at time %t WARNING: 200 us is required before CKE goes active.", $time);
+//                          if (cmd_chk + 200000000 > $time)
+//                              $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
+                            init_step = init_step + 1;
+                        end
+                        1 : if (dll_en)        init_step = init_step + 1;
+                        2 : begin
+                            if (&init_mode_reg && dll_reset) begin
+                                active_bank = {`BANKS{1'b1}};   // require Precharge All or bank Precharges
+                                ref_cntr = 0;                   // require refresh
+                                init_step = init_step + 1;
+                            end
+                        end
+                        3 : if (ref_cntr == 2) begin
+                            init_step = init_step + 1;
+                        end
+                        4 : if (!dll_reset)    init_step = init_step + 1;
+                        5 : if (ocd == 3'b111) init_step = init_step + 1;
+                        6 : begin
+                            if (ocd == 3'b000) begin
+                                if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
+                                init_done = 1;
+                            end
+                        end
+                    endcase
+                end
+            end else if (prev_cke) begin
+                if ((!init_done) && (init_step > 1)) begin
+                    $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
+                    if (STOP_ON_ERROR) $stop(0);
+                end
+                case (cmd)
+                    REFRESH : begin
+                        for (j=0; j<NOP; j=j+1) begin
+                            chk_err(1'b0, bank, j, SELF_REF);
+                        end
+                        chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
+                        chk_err(1'b0, bank, SELF_REF, SELF_REF);
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: Self Refresh Failure.  All banks must be Precharged.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                            init_done = 0;
+                        end else if (odt_en && odt_state) begin
+                            $display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                            init_done = 0;
+                        end else if (!init_done) begin
+                            $display ("%m: at time %t ERROR: Self Refresh Failure.  Initialization sequence is not complete.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
+                            in_self_refresh = 1;
+                            dll_locked = 0;
+                        end
+                    end
+                    NOP : begin
+                        // entering slow_exit or precharge power down and tANPD has not been satisfied
+                        if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
+                            $display ("%m: at time %t WARNING: tANPD violation during %s.  Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
+                        for (j=0; j<NOP; j=j+1) begin
+                            chk_err(1'b0, bank, j, PWR_DOWN);
+                        end
+                        chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
+                        chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
+
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: Power Down Failure.  Initialization sequence is not complete.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) begin
+                                if (|active_bank) begin
+                                    $display ("%m: at time %t INFO: Active Power Down Enter", $time);
+                                end else begin
+                                    $display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
+                                end
+                            end
+                            in_power_down = 1;
+                        end
+                    end
+                    default : begin
+                        $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
+                        init_done = 0;
+                    end
+                endcase
+                if (!init_done) begin
+                    if (DEBUG) $display ("%m: at time %t WARNING: Reset has occurred.  Device must be re-initialized.", $time);
+                    reset_task;
+                end
+            end
+            prev_cke  = cke;
+        end
+    endtask
+
+    task data_task;
+        reg [BA_BITS-1:0] bank;
+        reg [ROW_BITS-1:0] row;
+        reg [COL_BITS-1:0] col;
+        integer i;
+        integer j;
+        begin
+
+            if (diff_ck) begin
+                for (i=0; i<36; i=i+1) begin
+                    if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
+                        $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    if (check_write_dqs_high[i])
+                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/18], i%18);
+                end
+                check_write_dqs_high <= 0;
+            end else begin
+                for (i=0; i<36; i=i+1) begin
+                    if (dll_locked && dq_in_valid) begin
+                        tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
+                        if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
+                            $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18); 
+                    end
+                    if (check_write_dqs_low[i])
+                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18);
+                end
+                check_write_preamble <= 0;
+                check_write_postamble <= 0;
+                check_write_dqs_low <= 0;
+            end
+
+            if (wr_pipeline[0] || rd_pipeline[0]) begin
+                bank = ba_pipeline[0];
+                row = row_pipeline[0];
+                col = col_pipeline[0];
+                burst_cntr = 0;
+                memory_read(bank, row, col, memory_data);
+            end
+
+            // burst counter
+            if (burst_cntr < burst_length) begin
+                burst_position = col ^ burst_cntr;
+                if (!burst_order) begin
+                    burst_position[BO_BITS-1:0] = col + burst_cntr;
+                end
+                burst_cntr = burst_cntr + 1;
+            end
+
+            // write dqs counter
+            if (wr_pipeline[WDQS_PRE + 1]) begin
+                wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
+            end
+            // write dqs
+            if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
+                check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+            end
+            if (wdqs_cntr > 1) begin  // write data
+                if ((wdqs_cntr - WDQS_PST)%2) begin
+                    check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+                end else begin
+                    check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+                end
+            end
+            if (wdqs_cntr == WDQS_PST) begin // write postamble
+                check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+            end 
+            if (wdqs_cntr > 0) begin
+                wdqs_cntr = wdqs_cntr - 1;
+            end
+
+            // write dq
+            if (dq_in_valid) begin // write data
+                bit_mask = 0;
+                if (diff_ck) begin
+                    for (i=0; i<DM_BITS; i=i+1) begin
+                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
+                    end
+                    memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
+                end else begin
+                    for (i=0; i<DM_BITS; i=i+1) begin
+                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
+                    end
+                    memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
+                end
+                dq_temp = memory_data>>(burst_position*DQ_BITS);
+                if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
+                if (burst_cntr%BL_MIN == 0) begin
+                    memory_write(bank, row, col, memory_data);
+                end
+            end
+            if (wr_pipeline[1]) begin
+                wdq_cntr = burst_length;
+            end
+            if (wdq_cntr > 0) begin
+                wdq_cntr = wdq_cntr - 1;
+                dq_in_valid = 1'b1;
+            end else begin
+                dq_in_valid = 1'b0;
+                dqs_in_valid <= 1'b0;
+                for (i=0; i<36; i=i+1) begin
+                    wdqs_pos_cntr[i] <= 0;
+                end
+            end
+            if (wr_pipeline[0]) begin
+                b2b_write <= 1'b0;
+            end
+            if (wr_pipeline[2]) begin
+                if (dqs_in_valid) begin
+                    b2b_write <= 1'b1;
+                end
+                dqs_in_valid <= 1'b1;
+            end
+            // read dqs enable counter
+            if (rd_pipeline[RDQSEN_PRE]) begin
+                rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
+            end
+            if (rdqsen_cntr > 0) begin
+                rdqsen_cntr = rdqsen_cntr - 1;
+                dqs_out_en = 1'b1;
+            end else begin
+                dqs_out_en = 1'b0;
+            end
+            
+            // read dqs counter
+            if (rd_pipeline[RDQS_PRE]) begin
+                rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
+            end
+            // read dqs
+            if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
+                dqs_out = 1'b0;
+            end else if (rdqs_cntr > RDQS_PST) begin // read data
+                dqs_out = rdqs_cntr - RDQS_PST;
+            end else if (rdqs_cntr > 0) begin // read postamble
+                dqs_out = 1'b0;
+            end else begin
+                dqs_out = 1'b1;
+            end
+            if (rdqs_cntr > 0) begin
+                rdqs_cntr = rdqs_cntr - 1;
+            end
+
+            // read dq enable counter
+            if (rd_pipeline[RDQEN_PRE]) begin
+                rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
+            end
+            if (rdqen_cntr > 0) begin
+                rdqen_cntr = rdqen_cntr - 1;
+                dq_out_en = 1'b1;
+            end else begin
+                dq_out_en = 1'b0;
+            end
+            // read dq
+            if (rd_pipeline[0]) begin
+                rdq_cntr = burst_length;
+            end
+            if (rdq_cntr > 0) begin // read data
+                dq_temp = memory_data>>(burst_position*DQ_BITS);
+                dq_out = dq_temp;
+                if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
+                rdq_cntr = rdq_cntr - 1;
+            end else begin
+                dq_out = {DQ_BITS{1'b1}};
+            end
+
+            // delay signals prior to output
+            if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
+                for (i=0; i<DQS_BITS; i=i+1) begin
+                    // DQSCK requirements
+                    // 1.) less than tDQSCK
+                    // 2.) greater than -tDQSCK
+                    // 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
+                    dqsck_max = TDQSCK;
+                    if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
+                        dqsck_max = dqsck[i] + TQHS + TDQSQ;
+                    end
+                    dqsck_min = -1*TDQSCK;
+                    if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
+                        dqsck_min = dqsck[i] - TQHS - TDQSQ;
+                    end
+
+                    // DQSQ requirements
+                    // 1.) less than tAC - DQSCK
+                    // 2.) less than tDQSQ
+                    // 3.) greater than -tAC
+                    // 4.) greater than tQH from previous DQS edge
+                    dqsq_min = -1*TAC;
+                    if (dqsq_min < dqsck[i] - TQHS) begin
+                        dqsq_min = dqsck[i] - TQHS;
+                    end
+                    if (dqsck_min == dqsck_max) begin
+                        dqsck[i] = dqsck_min;
+                    end else begin
+                        dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
+                    end
+                    dqsq_max = TAC;
+                    if (dqsq_max > TDQSQ + dqsck[i]) begin
+                        dqsq_max = TDQSQ + dqsck[i];
+                    end
+
+                    dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en;
+                    dqs_out_dly[i]    <= #(tck_avg/2.0 + dqsck[i]) dqs_out;
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if (dq_out_en) begin // tLZ2
+                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en;
+                        end else begin // tHZ
+                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en;
+                        end
+                        if (dqsq_min == dqsq_max) begin
+                            dq_out_dly   [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
+                        end else begin
+                            dq_out_dly   [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
+                        end
+                    end
+                end
+            end else begin
+                out_delay = tck_avg/2.0;
+                dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
+                dqs_out_dly    <= #(out_delay) {DQS_BITS{dqs_out   }};
+                dq_out_en_dly  <= #(out_delay) {DQ_BITS {dq_out_en }};
+                dq_out_dly     <= #(out_delay) {DQ_BITS {dq_out    }};
+            end
+        end
+    endtask
+
+    always @(diff_ck) begin : main
+        integer i;
+
+        if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
+            $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
+        data_task;
+        if (diff_ck) begin
+            // check setup of command signals
+            if ($time > TIS) begin
+                if ($time - tm_cke < TIS) 
+                    $display ("%m: at time %t ERROR:   tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
+                if (cke_in) begin
+                    for (i=0; i<22; i=i+1) begin
+                        if ($time - tm_cmd_addr[i] < TIS) 
+                            $display ("%m: at time %t ERROR:   tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
+                    end
+                end
+            end
+
+            // update current state
+            if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
+                // check CL value against the clock frequency
+                if (cas_latency*tck_avg < CL_TIME)
+                    $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
+                // check WR value against the clock frequency
+                if (write_recovery*tck_avg < TWR)
+                    $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
+                dll_locked = 1;
+            end
+            if (|auto_precharge_bank) begin
+                for (i=0; i<`BANKS; i=i+1) begin
+                    // Write with Auto Precharge Calculation
+                    // 1.  Meet minimum tRAS requirement
+                    // 2.  Write Latency PLUS BL/2 cycles PLUS WR after Write command
+                    if (write_precharge_bank[i]
+                        && ($time - tm_bank_activate[i] >= TRAS_MIN)
+                        && (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin
+
+                        if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
+                        write_precharge_bank[i] = 0;
+                        active_bank[i] = 0;
+                        auto_precharge_bank[i] = 0;
+                        ck_write_ap = ck_cntr;
+                        tm_bank_precharge[i] = $time;
+                        tm_precharge = $time;
+                    end
+                    // Read with Auto Precharge Calculation
+                    // 1.  Meet minimum tRAS requirement
+                    // 2.  Additive Latency plus BL/2 cycles after Read command
+                    // 3.  tRTP after the last 4-bit prefetch
+                    if (read_precharge_bank[i]
+                        && ($time - tm_bank_activate[i] >= TRAS_MIN) 
+                        && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
+
+                        read_precharge_bank[i] = 0;
+                        // In case the internal precharge is pushed out by tRTP, tRP starts at the point where
+                        // the internal precharge happens (not at the next rising clock edge after this event).
+                        if ($time - tm_bank_read_end[i] < TRTP) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
+                            active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
+                            auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
+                            tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
+                            tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
+                            active_bank[i] = 0;
+                            auto_precharge_bank[i] = 0;
+                            tm_bank_precharge[i] = $time;
+                            tm_precharge = $time;
+                        end
+                    end
+                end
+            end
+
+            // respond to incoming command
+            if (cke_in ^ prev_cke) begin
+                ck_cke <= ck_cntr;
+            end
+
+            cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
+            if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
+                al_pipeline[2*additive_latency] = 1'b1;
+            end
+            if (al_pipeline[0]) begin
+                // check tRCD after additive latency
+                if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
+                    if (rd_pipeline[2*cas_latency - 1]) begin
+                        $display ("%m: at time %t ERROR:  tRCD violation during %s", $time, cmd_string[READ]);
+                    end else begin
+                        $display ("%m: at time %t ERROR:  tRCD violation during %s", $time, cmd_string[WRITE]);
+                    end
+                end
+                // check tWTR after additive latency
+                if (rd_pipeline[2*cas_latency - 1]) begin
+                    if ($time - tm_write_end < TWTR)
+                        $display ("%m: at time %t ERROR:  tWTR violation during %s", $time, cmd_string[READ]);
+                end
+            end
+            if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
+                tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
+            end
+            for (i=0; i<`BANKS; i=i+1) begin
+                if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
+                    tm_bank_write_end[i] <= $time;
+                    tm_write_end <= $time;
+                end
+            end
+
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh) begin
+                tjit_cc_time = $time - tm_ck_pos - tck_i;
+                tck_i   = $time - tm_ck_pos;
+                tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tck_avg = tck_avg + tck_i/$itor(TDLLK);
+                tck_sample[ck_cntr%TDLLK] = tck_i;
+                tjit_per_rtime = tck_i - tck_avg;
+
+                if (dll_locked) begin
+                    // check accumulated error
+                    terr_nper_rtime = 0;
+                    for (i=0; i<50; i=i+1) begin
+                        terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
+                        terr_nper_rtime = abs_value(terr_nper_rtime);
+                        case (i)
+                                  0 :;
+                                  1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
+                                  2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
+                                  3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
+                                  4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
+                          5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
+                            default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
+                        endcase
+                    end
+
+                    // check tCK min/max/jitter
+                    if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) 
+                        $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
+                    if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) 
+                        $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
+                    if (TCK_MIN - tck_avg >= 1.0)
+                        $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
+                    if (tck_avg - TCK_MAX >= 1.0) 
+                        $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
+                    if (tm_ck_pos + TCK_MIN - TJIT_PER > $time) 
+                        $display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
+                    if (tm_ck_pos + TCK_MAX + TJIT_PER < $time) 
+                        $display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
+
+                    // check tCL
+                    if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time) 
+                        $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
+                    if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time) 
+                        $display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
+                    if (tcl_avg < TCL_MIN*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
+                    if (tcl_avg > TCL_MAX*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
+                end
+
+                // calculate the tch avg jitter
+                tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tch_avg = tch_avg + tch_i/$itor(TDLLK);
+                tch_sample[ck_cntr%TDLLK] = tch_i;
+
+                // update timers/counters
+                tcl_i <= $time - tm_ck_neg;
+            end
+
+            prev_odt <= odt_in;
+            // update timers/counters
+            ck_cntr <= ck_cntr + 1;
+            tm_ck_pos <= $time;
+        end else begin
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh) begin
+                if (dll_locked) begin
+                    if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time) 
+                        $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
+                    if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time) 
+                        $display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
+                    if (tch_avg < TCH_MIN*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
+                    if (tch_avg > TCH_MAX*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
+                end
+
+                // calculate the tcl avg jitter
+                tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
+                tcl_sample[ck_cntr%TDLLK] = tcl_i;
+
+                // update timers/counters
+                tch_i <= $time - tm_ck_pos;
+            end
+            tm_ck_neg <= $time;
+        end
+
+        // on die termination
+        if (odt_en) begin
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh && diff_ck) begin
+                if ($time - tm_odt < TIS) begin
+                    $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
+                end
+                if (prev_odt ^ odt_in) begin
+                    if (!dll_locked)
+                        $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
+                    if (odt_in && ($time - tm_odt_en  < TMOD))
+                        $display ("%m: at time %t ERROR:  tMOD violation during ODT transition", $time);
+                    if ($time - tm_self_refresh < TXSNR)
+                        $display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
+                    if (in_self_refresh)
+                        $display ("%m: at time %t ERROR:  Illegal ODT transition during Self Refresh.", $time);
+
+                    // async ODT mode applies:
+                    // 1.) during active power down with slow exit
+                    // 2.) during precharge power down
+                    // 3.) if tANPD has not been satisfied
+                    // 4.) until tAXPD has been satisfied
+                    if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
+                        if (ck_cntr - ck_slow_exit_pd < TAXPD)
+                            $display ("%m: at time %t WARNING: tAXPD violation during ODT transition.  Synchronous or asynchronous change in termination resistance is possible.", $time);
+                        if (odt_in) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
+                            odt_state <= #(TAONPD) 1'b1;
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
+                            odt_state <= #(TAOFPD) 1'b0;
+                        end
+                    // sync ODT mode applies:
+                    // 1.) during normal operation
+                    // 2.) during active power down with fast exit
+                    end else begin
+                        if (odt_in) begin
+                            i = TAOND*2;
+                            odt_pipeline[i] = 1'b1;
+                        end else begin
+                            i = TAOFD*2;
+                            odt_pipeline[i] = 1'b1;
+                        end
+                    end
+                    ck_odt <= ck_cntr;
+                end
+            end
+            if (odt_pipeline[0]) begin
+                odt_state = ~odt_state;
+                if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
+            end
+        end
+
+        // shift pipelines
+        if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
+            al_pipeline = al_pipeline>>1;
+            wr_pipeline = wr_pipeline>>1;
+            rd_pipeline = rd_pipeline>>1;
+            for (i=0; i<`MAX_PIPE; i=i+1) begin
+                ba_pipeline[i] = ba_pipeline[i+1];
+                row_pipeline[i] = row_pipeline[i+1];
+                col_pipeline[i] = col_pipeline[i+1];
+            end
+        end
+        if (|odt_pipeline) begin
+            odt_pipeline = odt_pipeline>>1;
+        end
+    end
+
+    // receiver(s)
+    task dqs_even_receiver;
+        input [4:0] i;
+        reg [71:0] bit_mask;
+        begin
+            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
+            if (dqs_even[i]) begin
+                if (rdqs_en) begin // rdqs disables dm
+                    dm_in_pos[i] = 1'b0;
+                end else begin
+                    dm_in_pos[i] = dm_in[i];
+                end
+                dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
+            end
+        end
+    endtask
+
+    always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
+    always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
+    always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
+    always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
+    always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
+    always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
+    always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
+    always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
+    always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
+    always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
+    always @(posedge dqs_even[10]) dqs_even_receiver(10);
+    always @(posedge dqs_even[11]) dqs_even_receiver(11);
+    always @(posedge dqs_even[12]) dqs_even_receiver(12);
+    always @(posedge dqs_even[13]) dqs_even_receiver(13);
+    always @(posedge dqs_even[14]) dqs_even_receiver(14);
+    always @(posedge dqs_even[15]) dqs_even_receiver(15);
+    always @(posedge dqs_even[16]) dqs_even_receiver(16);
+    always @(posedge dqs_even[17]) dqs_even_receiver(17);
+
+    task dqs_odd_receiver;
+        input [4:0] i;
+        reg [71:0] bit_mask;
+        begin
+            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
+            if (dqs_odd[i]) begin
+                if (rdqs_en) begin // rdqs disables dm
+                    dm_in_neg[i] = 1'b0;
+                end else begin
+                    dm_in_neg[i] = dm_in[i];
+                end
+                dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
+            end
+        end
+    endtask
+
+    always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
+    always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
+    always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
+    always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
+    always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
+    always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
+    always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
+    always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
+    always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
+    always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
+    always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
+    always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
+    always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
+    always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
+    always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
+    always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
+    always @(posedge dqs_odd[16]) dqs_odd_receiver(16);
+    always @(posedge dqs_odd[17]) dqs_odd_receiver(17);
+ 
+    // Processes to check hold and pulse width of control signals
+    always @(cke_in) begin
+        if ($time > TIH) begin
+            if ($time - tm_ck_pos < TIH) 
+                $display ("%m: at time %t ERROR:  tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
+        end
+        if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
+            $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
+        tm_cke = $time;
+    end
+    always @(odt_in) begin
+        if (odt_en && !in_self_refresh) begin
+            if ($time - tm_ck_pos < TIH) 
+                $display ("%m: at time %t ERROR:  tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
+            if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
+                $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
+        end
+        tm_odt = $time;
+    end
+
+    task cmd_addr_timing_check;
+    input i;
+    reg [4:0] i;
+    begin
+        if (prev_cke) begin
+            if ((i == 0) && ($time - tm_ck_pos < TIH))                      // Always check tIH for CS#
+                $display ("%m: at time %t ERROR:  tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
+            if ((i > 0) && (cs_n_in == 1'b0) && ($time - tm_ck_pos < TIH))  // Only check tIH for cmd_addr if CS# low
+                $display ("%m: at time %t ERROR:  tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
+            if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
+                $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
+        end
+        tm_cmd_addr[i] = $time;
+    end
+    endtask
+
+    always @(cs_n_in    ) cmd_addr_timing_check( 0);
+    always @(ras_n_in   ) cmd_addr_timing_check( 1);
+    always @(cas_n_in   ) cmd_addr_timing_check( 2);
+    always @(we_n_in    ) cmd_addr_timing_check( 3);
+    always @(ba_in  [ 0]) cmd_addr_timing_check( 4);
+    always @(ba_in  [ 1]) cmd_addr_timing_check( 5);
+    always @(ba_in  [ 2]) cmd_addr_timing_check( 6);
+    always @(addr_in[ 0]) cmd_addr_timing_check( 7);
+    always @(addr_in[ 1]) cmd_addr_timing_check( 8);
+    always @(addr_in[ 2]) cmd_addr_timing_check( 9);
+    always @(addr_in[ 3]) cmd_addr_timing_check(10);
+    always @(addr_in[ 4]) cmd_addr_timing_check(11);
+    always @(addr_in[ 5]) cmd_addr_timing_check(12);
+    always @(addr_in[ 6]) cmd_addr_timing_check(13);
+    always @(addr_in[ 7]) cmd_addr_timing_check(14);
+    always @(addr_in[ 8]) cmd_addr_timing_check(15);
+    always @(addr_in[ 9]) cmd_addr_timing_check(16);
+    always @(addr_in[10]) cmd_addr_timing_check(17);
+    always @(addr_in[11]) cmd_addr_timing_check(18);
+    always @(addr_in[12]) cmd_addr_timing_check(19);
+    always @(addr_in[13]) cmd_addr_timing_check(20);
+    always @(addr_in[14]) cmd_addr_timing_check(21);
+    always @(addr_in[15]) cmd_addr_timing_check(22);
+
+    // Processes to check setup and hold of data signals
+    task dm_timing_check;
+    input i;
+    reg [4:0] i;
+    begin
+        if (dqs_in_valid) begin
+            if ($time - tm_dqs[i] < TDH) 
+                $display ("%m: at time %t ERROR:   tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
+            if (check_dm_tdipw[i]) begin
+                if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
+                    $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
+            end
+        end
+        check_dm_tdipw[i] <= 1'b0;
+        tm_dm[i] = $time;
+    end
+    endtask
+
+    always @(dm_in[ 0]) dm_timing_check( 0);
+    always @(dm_in[ 1]) dm_timing_check( 1);
+    always @(dm_in[ 2]) dm_timing_check( 2);
+    always @(dm_in[ 3]) dm_timing_check( 3);
+    always @(dm_in[ 4]) dm_timing_check( 4);
+    always @(dm_in[ 5]) dm_timing_check( 5);
+    always @(dm_in[ 6]) dm_timing_check( 6);
+    always @(dm_in[ 7]) dm_timing_check( 7);
+    always @(dm_in[ 8]) dm_timing_check( 8);
+    always @(dm_in[ 9]) dm_timing_check( 9);
+    always @(dm_in[10]) dm_timing_check(10);
+    always @(dm_in[11]) dm_timing_check(11);
+    always @(dm_in[12]) dm_timing_check(12);
+    always @(dm_in[13]) dm_timing_check(13);
+    always @(dm_in[14]) dm_timing_check(14);
+    always @(dm_in[15]) dm_timing_check(15);
+    always @(dm_in[16]) dm_timing_check(16);
+    always @(dm_in[17]) dm_timing_check(17);
+
+    task dq_timing_check;
+    input i;
+    reg [6:0] i;
+    begin
+        if (dqs_in_valid) begin
+            if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) 
+                $display ("%m: at time %t ERROR:   tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
+            if (check_dq_tdipw[i]) begin
+                if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
+                    $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
+            end
+        end
+        check_dq_tdipw[i] <= 1'b0;
+        tm_dq[i] = $time;
+    end 
+    endtask
+
+    always @(dq_in[ 0]) dq_timing_check( 0);
+    always @(dq_in[ 1]) dq_timing_check( 1);
+    always @(dq_in[ 2]) dq_timing_check( 2);
+    always @(dq_in[ 3]) dq_timing_check( 3);
+    always @(dq_in[ 4]) dq_timing_check( 4);
+    always @(dq_in[ 5]) dq_timing_check( 5);
+    always @(dq_in[ 6]) dq_timing_check( 6);
+    always @(dq_in[ 7]) dq_timing_check( 7);
+    always @(dq_in[ 8]) dq_timing_check( 8);
+    always @(dq_in[ 9]) dq_timing_check( 9);
+    always @(dq_in[10]) dq_timing_check(10);
+    always @(dq_in[11]) dq_timing_check(11);
+    always @(dq_in[12]) dq_timing_check(12);
+    always @(dq_in[13]) dq_timing_check(13);
+    always @(dq_in[14]) dq_timing_check(14);
+    always @(dq_in[15]) dq_timing_check(15);
+    always @(dq_in[16]) dq_timing_check(16);
+    always @(dq_in[17]) dq_timing_check(17);
+    always @(dq_in[18]) dq_timing_check(18);
+    always @(dq_in[19]) dq_timing_check(19);
+    always @(dq_in[20]) dq_timing_check(20);
+    always @(dq_in[21]) dq_timing_check(21);
+    always @(dq_in[22]) dq_timing_check(22);
+    always @(dq_in[23]) dq_timing_check(23);
+    always @(dq_in[24]) dq_timing_check(24);
+    always @(dq_in[25]) dq_timing_check(25);
+    always @(dq_in[26]) dq_timing_check(26);
+    always @(dq_in[27]) dq_timing_check(27);
+    always @(dq_in[28]) dq_timing_check(28);
+    always @(dq_in[29]) dq_timing_check(29);
+    always @(dq_in[30]) dq_timing_check(30);
+    always @(dq_in[31]) dq_timing_check(31);
+    always @(dq_in[32]) dq_timing_check(32);
+    always @(dq_in[33]) dq_timing_check(33);
+    always @(dq_in[34]) dq_timing_check(34);
+    always @(dq_in[35]) dq_timing_check(35);
+    always @(dq_in[36]) dq_timing_check(36);
+    always @(dq_in[37]) dq_timing_check(37);
+    always @(dq_in[38]) dq_timing_check(38);
+    always @(dq_in[39]) dq_timing_check(39);
+    always @(dq_in[40]) dq_timing_check(40);
+    always @(dq_in[41]) dq_timing_check(41);
+    always @(dq_in[42]) dq_timing_check(42);
+    always @(dq_in[43]) dq_timing_check(43);
+    always @(dq_in[44]) dq_timing_check(44);
+    always @(dq_in[45]) dq_timing_check(45);
+    always @(dq_in[46]) dq_timing_check(46);
+    always @(dq_in[47]) dq_timing_check(47);
+    always @(dq_in[48]) dq_timing_check(48);
+    always @(dq_in[49]) dq_timing_check(49);
+    always @(dq_in[50]) dq_timing_check(50);
+    always @(dq_in[51]) dq_timing_check(51);
+    always @(dq_in[52]) dq_timing_check(52);
+    always @(dq_in[53]) dq_timing_check(53);
+    always @(dq_in[54]) dq_timing_check(54);
+    always @(dq_in[55]) dq_timing_check(55);
+    always @(dq_in[56]) dq_timing_check(56);
+    always @(dq_in[57]) dq_timing_check(57);
+    always @(dq_in[58]) dq_timing_check(58);
+    always @(dq_in[59]) dq_timing_check(59);
+    always @(dq_in[60]) dq_timing_check(60);
+    always @(dq_in[61]) dq_timing_check(61);
+    always @(dq_in[62]) dq_timing_check(62);
+    always @(dq_in[63]) dq_timing_check(63);
+    always @(dq_in[64]) dq_timing_check(64);
+    always @(dq_in[65]) dq_timing_check(65);
+    always @(dq_in[66]) dq_timing_check(66);
+    always @(dq_in[67]) dq_timing_check(67);
+    always @(dq_in[68]) dq_timing_check(68);
+    always @(dq_in[69]) dq_timing_check(69);
+    always @(dq_in[70]) dq_timing_check(70);
+    always @(dq_in[71]) dq_timing_check(71);
+
+    task dqs_pos_timing_check;
+    input i;
+    reg [5:0] i;
+    reg [3:0] j;
+    begin
+        if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin
+            if (dqs_in[i] ^ prev_dqs_in[i]) begin
+                if (dll_locked) begin
+                    if (check_write_preamble[i]) begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
+                            $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18);
+                    end else if (check_write_postamble[i]) begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
+                            $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    end else begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
+                            $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    end
+                end
+                if ($time - tm_dm[i%18] < TDS) 
+                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i,  tm_dm[i%18] + TDS - $time);
+                if (!dq_out_en) begin
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) 
+                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
+                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
+                    end
+                end
+                if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
+                    wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
+                end else begin
+                    wdqs_pos_cntr[i] <= 1;
+                end
+                check_dm_tdipw[i%18] <= 1'b1;
+                check_write_preamble[i] <= 1'b0;
+                check_write_postamble[i] <= 1'b0;
+                check_write_dqs_low[i] <= 1'b0;
+                tm_dqs[i%18] <= $time;
+            end else begin
+                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
+            end
+        end
+        tm_dqss_pos[i] <= $time;
+        tm_dqs_pos[i] = $time;
+        prev_dqs_in[i] <= dqs_in[i];
+    end
+    endtask
+
+    always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
+    always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
+    always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
+    always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
+    always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
+    always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
+    always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
+    always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
+    always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
+    always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
+    always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
+    always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
+    always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
+    always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
+    always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
+    always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
+    always @(posedge dqs_in[16]) dqs_pos_timing_check(16);
+    always @(posedge dqs_in[17]) dqs_pos_timing_check(17);
+    always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
+    always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
+    always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
+    always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
+    always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
+    always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
+    always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
+    always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
+    always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
+    always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
+    always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
+    always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
+    always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
+    always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
+    always @(negedge dqs_in[32]) dqs_neg_timing_check(32);
+    always @(negedge dqs_in[33]) dqs_neg_timing_check(33);
+    always @(negedge dqs_in[34]) dqs_neg_timing_check(34);
+    always @(negedge dqs_in[35]) dqs_neg_timing_check(35);
+
+    task dqs_neg_timing_check;
+    input i;
+    reg [5:0] i;
+    reg [3:0] j;
+    begin
+        if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin
+            if (dqs_in[i] ^ prev_dqs_in[i]) begin
+                if (dll_locked) begin
+                    if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
+                        $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
+                        $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18); 
+                end
+                if ($time - tm_dm[i%18] < TDS) 
+                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i,  tm_dm[i%18] + TDS - $time);
+                if (!dq_out_en) begin
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) 
+                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
+                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
+                    end
+                end
+                check_dm_tdipw[i%18] <= 1'b1;
+                check_write_dqs_high[i] <= 1'b0;
+                tm_dqs[i%18] <= $time;
+            end else begin
+                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
+            end
+        end
+        tm_dqs_neg[i] = $time;
+        prev_dqs_in[i] <= dqs_in[i];
+    end
+    endtask
+
+    always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
+    always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
+    always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
+    always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
+    always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
+    always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
+    always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
+    always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
+    always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
+    always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
+    always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
+    always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
+    always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
+    always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
+    always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
+    always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
+    always @(negedge dqs_in[16]) dqs_neg_timing_check(16);
+    always @(negedge dqs_in[17]) dqs_neg_timing_check(17);
+    always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
+    always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
+    always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
+    always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
+    always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
+    always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
+    always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
+    always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
+    always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
+    always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
+    always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
+    always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
+    always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
+    always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
+    always @(posedge dqs_in[32]) dqs_neg_timing_check(32);
+    always @(posedge dqs_in[33]) dqs_neg_timing_check(33);
+    always @(posedge dqs_in[34]) dqs_neg_timing_check(34);
+    always @(posedge dqs_in[35]) dqs_neg_timing_check(35);
+
+endmodule
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/ddr2_model_parameters_c3.vh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/ddr2_model_parameters_c3.vh
new file mode 100755
index 0000000..1c8e277
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/ddr2_model_parameters_c3.vh
@@ -0,0 +1,1394 @@
+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or
+*                limitation of liability for consequential or incidental damages, the
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+
+    // Timing parameters based on Speed Grade
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef x256Mb
+
+    `ifdef sg187E
+        parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     125; // tIS    ps    Input Setup Time
+        parameter TIH              =     200; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   13125; // tRP    ps    Precharge command period
+        parameter TRPA             =   13125; // tRPA   ps    Precharge All period
+        parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25E
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12500; // tRP    ps    Precharge command period
+        parameter TRPA             =   12500; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3E
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12000; // tRP    ps    Precharge command period
+        parameter TRPA             =   12000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg37E
+        parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     250; // tIS    ps    Input Setup Time
+        parameter TIH              =     375; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `define sg5E
+        parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     350; // tIS    ps    Input Setup Time
+        parameter TIH              =     475; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `endif `endif `endif `endif `endif `endif
+
+    `ifdef x16
+      `ifdef sg187E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `else // x4, x8
+      `ifdef sg187E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `endif
+
+        // Timing Parameters
+
+        // Mode Register
+        parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+        parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+        parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+        parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+        parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+        parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+        parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+        parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+        // Clock
+        parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+        parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+        parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+        parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+        parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+        // Data
+        parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+        parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+        parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+        // Data Strobe
+        parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+        parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+        parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+        parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+        parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+        parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+        parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+        // Command and Address
+        parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
+        parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+        parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+        parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+        parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+        parameter TWR              =   15000; // tWR    ps    Write recovery time
+        parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+        parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+        // Refresh
+        parameter TRFC_MIN         =   75000; // tRFC   ps    Refresh to Refresh Command interval minimum value
+        parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+        // Self Refresh
+        parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+        parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+        parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+        // ODT
+        parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+        parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+        parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+        parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+        parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+        // Power Down
+        parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+        // Size Parameters based on Part Width
+
+    `ifdef x4
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =      11; // Number of Column bits
+        parameter DQ_BITS          =       4; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `ifdef x8
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DQ_BITS          =       8; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `define x16
+        parameter DM_BITS          =       2; // Number of Data Mask bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =       9; // Number of Column bits
+        parameter DQ_BITS          =      16; // Number of Data bits
+        parameter DQS_BITS         =       2; // Number of Dqs bits
+        parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+    `endif `endif
+
+    `ifdef QUAD_RANK
+        `define DUAL_RANK // also define DUAL_RANK
+        parameter CS_BITS          =       4; // Number of Chip Select Bits
+        parameter RANKS            =       4; // Number of Chip Select Bits
+    `else `ifdef DUAL_RANK
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       2; // Number of Chip Select Bits
+    `else
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       1; // Number of Chip Select Bits
+    `endif `endif
+
+        // Size Parameters
+        parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits
+        parameter ADDR_BITS        =      13; // Address Bits
+        parameter MEM_BITS         =      15; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+        parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+        parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+        parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+`else `ifdef x512Mb
+
+    `ifdef sg187E
+        parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     125; // tIS    ps    Input Setup Time
+        parameter TIH              =     200; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   13125; // tRP    ps    Precharge command period
+        parameter TRPA             =   13125; // tRPA   ps    Precharge All period
+        parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25E
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12500; // tRP    ps    Precharge command period
+        parameter TRPA             =   12500; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3E
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12000; // tRP    ps    Precharge command period
+        parameter TRPA             =   12000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg37E
+        parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     250; // tIS    ps    Input Setup Time
+        parameter TIH              =     375; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `define sg5E
+        parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     350; // tIS    ps    Input Setup Time
+        parameter TIH              =     475; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `endif `endif `endif `endif `endif `endif
+
+    `ifdef x16
+      `ifdef sg187E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `else // x4, x8
+      `ifdef sg187E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `endif
+
+        // Timing Parameters
+
+        // Mode Register
+        parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+        parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+        parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+        parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+        parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+        parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+        parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+        parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+        // Clock
+        parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+        parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+        parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+        parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+        parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+        // Data
+        parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+        parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+        parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+        // Data Strobe
+        parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+        parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+        parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+        parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+        parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+        parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+        parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+        // Command and Address
+        parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
+        parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+        parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+        parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+        parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+        parameter TWR              =   15000; // tWR    ps    Write recovery time
+        parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+        parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+        // Refresh
+        parameter TRFC_MIN         =  105000; // tRFC   ps    Refresh to Refresh Command interval minimum value
+        parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+        // Self Refresh
+        parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+        parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+        parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+        // ODT
+        parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+        parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+        parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+        parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+        parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+        // Power Down
+        parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+        // Size Parameters based on Part Width
+
+    `ifdef x4
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      11; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       4; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `ifdef x8
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       8; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `define x16
+        parameter ADDR_BITS        =      13; // Address Bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       2; // Number of Data Mask bits
+        parameter DQ_BITS          =      16; // Number of Data bits
+        parameter DQS_BITS         =       2; // Number of Dqs bits
+        parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+    `endif `endif
+
+    `ifdef QUAD_RANK
+        `define DUAL_RANK // also define DUAL_RANK
+        parameter CS_BITS          =       4; // Number of Chip Select Bits
+        parameter RANKS            =       4; // Number of Chip Select Bits
+    `else `ifdef DUAL_RANK
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       2; // Number of Chip Select Bits
+    `else
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       1; // Number of Chip Select Bits
+    `endif `endif
+
+        // Size Parameters
+        parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits
+        parameter MEM_BITS         =      15; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+        parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+        parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+        parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+`else `ifdef x1Gb
+
+    `ifdef sg187E
+        parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     125; // tIS    ps    Input Setup Time
+        parameter TIH              =     200; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   13125; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25E
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12500; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   17500; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3E
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   18000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg37E
+        parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     250; // tIS    ps    Input Setup Time
+        parameter TIH              =     375; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   18750; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `define sg5E
+        parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     350; // tIS    ps    Input Setup Time
+        parameter TIH              =     475; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   20000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `endif `endif `endif `endif `endif `endif
+
+    `ifdef x16
+      `ifdef sg187E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `else // x4, x8
+      `ifdef sg187E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `endif
+
+        // Timing Parameters
+
+        // Mode Register
+        parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+        parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+        parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+        parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+        parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+        parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+        parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+        parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+        // Clock
+        parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+        parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+        parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+        parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+        parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+        // Data
+        parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+        parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+        parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+        // Data Strobe
+        parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+        parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+        parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+        parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+        parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+        parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+        parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+        // Command and Address
+        parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
+        parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+        parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+        parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+        parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+        parameter TWR              =   15000; // tWR    ps    Write recovery time
+        parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+        parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+        // Refresh
+        parameter TRFC_MIN         =  127500; // tRFC   ps    Refresh to Refresh Command interval minimum value
+        parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+        // Self Refresh
+        parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+        parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+        parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+        // ODT
+        parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+        parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+        parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+        parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+        parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+        // Power Down
+        parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+        // Size Parameters based on Part Width
+
+    `ifdef x4
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      11; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       4; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `ifdef x8
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       8; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `define x16
+        parameter ADDR_BITS        =      13; // Address Bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       2; // Number of Data Mask bits
+        parameter DQ_BITS          =      16; // Number of Data bits
+        parameter DQS_BITS         =       2; // Number of Dqs bits
+        parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+    `endif `endif
+
+    `ifdef QUAD_RANK
+        `define DUAL_RANK // also define DUAL_RANK
+        parameter CS_BITS          =       4; // Number of Chip Select Bits
+        parameter RANKS            =       4; // Number of Chip Select Bits
+    `else `ifdef DUAL_RANK
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       2; // Number of Chip Select Bits
+    `else
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       1; // Number of Chip Select Bits
+    `endif `endif
+
+        // Size Parameters
+        parameter BA_BITS          =       3; // Set this parmaeter to control how many Bank Address bits
+        parameter MEM_BITS         =      15; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+        parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+        parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+        parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+`else `define x2Gb
+
+    `ifdef sg187E
+        parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     125; // tIS    ps    Input Setup Time
+        parameter TIH              =     200; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   13125; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25E
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12500; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   17500; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3E
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   18000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg37E
+        parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     250; // tIS    ps    Input Setup Time
+        parameter TIH              =     375; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   18750; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `define sg5E
+        parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     350; // tIS    ps    Input Setup Time
+        parameter TIH              =     475; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   20000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `endif `endif `endif `endif `endif `endif
+
+    `ifdef x16
+      `ifdef sg187E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `else // x4, x8
+      `ifdef sg187E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `endif
+
+        // Timing Parameters
+
+        // Mode Register
+        parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+        parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+        parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+        parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+        parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+        parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+        parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+        parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+        // Clock
+        parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+        parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+        parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+        parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+        parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+        // Data
+        parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+        parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+        parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+        // Data Strobe
+        parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+        parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+        parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+        parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+        parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+        parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+        parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+        // Command and Address
+        parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
+        parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+        parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+        parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+        parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+        parameter TWR              =   15000; // tWR    ps    Write recovery time
+        parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+        parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+        // Refresh
+        parameter TRFC_MIN         =  197500; // tRFC   ps    Refresh to Refresh Command interval minimum value
+        parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+        // Self Refresh
+        parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+        parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+        parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+        // ODT
+        parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+        parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+        parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+        parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+        parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+        // Power Down
+        parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+        // Size Parameters based on Part Width
+
+    `ifdef x4
+        parameter ADDR_BITS        =      15; // Address Bits
+        parameter ROW_BITS         =      15; // Number of Address bits
+        parameter COL_BITS         =      11; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       4; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `ifdef x8
+        parameter ADDR_BITS        =      15; // Address Bits
+        parameter ROW_BITS         =      15; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       8; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `define x16
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       2; // Number of Data Mask bits
+        parameter DQ_BITS          =      16; // Number of Data bits
+        parameter DQS_BITS         =       2; // Number of Dqs bits
+        parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+    `endif `endif
+
+    `ifdef QUAD_RANK
+        `define DUAL_RANK // also define DUAL_RANK
+        parameter CS_BITS          =       4; // Number of Chip Select Bits
+        parameter RANKS            =       4; // Number of Chip Select Bits
+    `else `ifdef DUAL_RANK
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       2; // Number of Chip Select Bits
+    `else
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       1; // Number of Chip Select Bits
+    `endif `endif
+
+        // Size Parameters
+        parameter BA_BITS          =       3; // Set this parmaeter to control how many Bank Address bits
+        parameter MEM_BITS         =      15; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+        parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+        parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+        parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+`endif `endif `endif
+
+    // Simulation parameters
+    parameter STOP_ON_ERROR    =       1; // If set to 1, the model will halt on command sequence/major errors
+    parameter DEBUG            =       1; // Turn on Debug messages
+    parameter BUS_DELAY        =       0; // delay in nanoseconds
+    parameter RANDOM_OUT_DELAY =       0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
+    parameter RANDOM_SEED      = 711689044; //seed value for random generator.
+
+    parameter RDQSEN_PRE       =       2; // DQS driving time prior to first read strobe
+    parameter RDQSEN_PST       =       1; // DQS driving time after last read strobe
+    parameter RDQS_PRE         =       2; // DQS low time prior to first read strobe
+    parameter RDQS_PST         =       1; // DQS low time after last valid read strobe
+    parameter RDQEN_PRE        =       0; // DQ/DM driving time prior to first read data
+    parameter RDQEN_PST        =       0; // DQ/DM driving time after last read data
+    parameter WDQS_PRE         =       1; // DQS half clock periods prior to first write strobe
+    parameter WDQS_PST         =       1; // DQS half clock periods after last valid write strobe
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.sh
new file mode 100755
index 0000000..4c23a30
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.sh
@@ -0,0 +1,70 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+#   ____  ____
+#  /   /\/   /
+# /___/  \  /    Vendor                : Xilinx
+# \   \   \/     Version               : 3.92
+#  \   \         Application           : MIG
+#  /   /         Filename              : isim.bat
+# /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+# \   \  /  \    Date Created          : Fri Feb 06 2009
+#  \___\/\___\
+#
+# Device            : Spartan-6
+# Design Name       : DDR/DDR2/DDR3/LPDDR
+# Purpose           : Batch file to run Simulation through ISIM
+# Reference         :
+# Revision History  :
+# ****************************************************************************
+
+echo Simulation Tool: ISIM
+fuse work.sim_tb_top work.glbl -prj ddr2.prj -L unisim -L secureip -timeprecision_vhdl fs -o ddr2
+./ddr2 -gui -tclbatch isim.tcl -wdb ddr2.wdb
+echo done
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.tcl
new file mode 100755
index 0000000..dc37142
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.tcl
@@ -0,0 +1,72 @@
+###############################################################################
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+###############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor             : Xilinx
+## \   \   \/     Version            : 3.92
+##  \   \         Application	     : MIG
+##  /   /         Filename           : isim.tcl
+## /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:55 $
+## \   \  /  \    Date Created       : Mon Mar 2 2009
+##  \___\/\___\
+##
+## Device          : Spartan-6
+## Design Name     : DDR/DDR2/DDR3/LPDDR
+## Purpose         : To give commands to ISIM Simulator through batch mode
+## Assumptions:
+##      - Simulation takes place in \sim folder of MIG output directory
+## Reference       :
+## Revision History:
+###############################################################################
+
+onerror {resume}
+isim set radix hex
+wave add /sim_tb_top
+run 200 us
+quit
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/readme.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/readme.txt
new file mode 100755
index 0000000..139937a
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/readme.txt
@@ -0,0 +1,131 @@
+###############################################################################
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+###############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor             : Xilinx
+## \   \   \/     Version            : 3.92
+##  \   \         Application	     : MIG
+##  /   /         Filename           : readme.txt
+## /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:55 $
+## \   \  /  \    Date Created       : Mon Oct 19 2009
+##  \___\/\___\
+##
+## Device          : Spartan-6
+## Design Name     : DDR/DDR2/DDR3/LPDDR
+## Purpose         : Steps to run simulation using ISIM/Modelsim simualtor in this folder
+## Assumptions:
+##      - Simulation takes place in \sim\<functional/timing> folder of MIG output directory
+## Reference       :
+## Revision History:
+###############################################################################
+
+The sim/functional folder has files to perform functional simulation of the design.
+
+1. Simulation using Modelsim simulator
+
+A) sim.do File :
+   
+   1) The 'sim.do' file has commands to compile and simulate memory interface
+      design and run the simulation for specified period of time. 
+    
+   2) It has the syntax to Map the required libraries.
+      Also, $XILINX environment variable must be set in order to compile glbl.v file
+
+   3) Displays the waveforms that are listed with "add wave" command.
+     
+B) Steps to run the Modelsim simulation:
+
+   1) The user should invoke the Modelsim simulator GUI.
+   2) Change the present working directory path to the sim/functional folder.
+      In Transcript window, at Modelsim prompt, type the following command to 
+      change directory path.
+           cd <sim/functional directory path>
+
+   2) Run the simulation using sim.do file.
+      At Modelsim prompt, type the following command:
+           do sim.do      
+
+   3) To exit simulation, type the following command at Modelsim prompt:
+           quit -f
+
+   4) Verify the transcript file for the memory transactions.
+
+C) For simulation with Elpida parts perform the following steps and then
+   the above mentioned steps in 'B'
+
+   1) Download the Elpida memory model from Elpida webpage.
+
+   2) Update the memorymodel name in the vlog command given in sim.do file.
+
+
+2. Simulation using ISIM simulator
+  
+A) Following files are provided :
+   
+   1) The '.prj' file contains the list of all the files associated with the design.
+      It also contains the hdl, library and the source file name.       
+    
+   2) The '.tcl' file contains the Tcl commands for simulation and 
+      resume on error. 
+
+   3) The 'isim.bat' has commands which use '.prj' and '.tcl' files. 
+
+     
+B) Steps to run the ISIM simulation:
+
+   The user should execute the file isim.bat, which does the following steps:
+   1) Compiles, elaborates the design and generates the simulation executable using
+      the fuse command in 'isim.bat' file.
+
+   2) Invokes the ISIM GUI.
+
+   3) User can add required signals from objects window to the waveform viewer and run 
+      simulation for specified time using the command "run <time>" in ISIM GUI.
+
+C) Simulations using ISIM simulator is not supported for Elpida parts. 
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim.do b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim.do
new file mode 100755
index 0000000..2806625
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim.do
@@ -0,0 +1,144 @@
+###############################################################################
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+###############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor             : Xilinx
+## \   \   \/     Version            : 3.92
+##  \   \         Application	     : MIG
+##  /   /         Filename           : sim.do
+## /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:56 $
+## \   \  /  \    Date Created       : Mon Mar 2 2009
+##  \___\/\___\
+##
+## Device: Spartan-6
+## Design Name : DDR/DDR2/DDR3/LPDDR
+## Purpose:
+##    Sample sim .do file to compile and simulate memory interface
+##    design and run the simulation for specified period of time. Display the
+##    waveforms that are listed with "add wave" command.
+##    Assumptions:
+##      - Simulation takes place in \sim folder of MIG output directory
+## Reference:
+## Revision History:
+###############################################################################
+
+vlib work
+
+#Map the required libraries here.#
+#vmap unisim <unisim lib path>
+#vmap secureip <secureip lib path> 
+
+#Compile all rtl modules#
+vcom ../../rtl/*.vhd
+
+
+
+#Compile all traffic_gen modules#
+vcom  ../../rtl/traffic_gen/*.vhd
+
+
+
+#Compile files in sim folder (excluding model parameter file)#
+#$XILINX variable must be set
+vlog  $env(XILINX)/verilog/src/glbl.v
+vcom  ../functional/*.vhd
+
+#Pass the parameters for memory model parameter file#
+vlog  +incdir+. +define+x1Gb +define+sg25E +define+x16 ddr2_model_c3.v
+
+#Load the design. Use required libraries.#
+vsim -t ps -novopt +notimingchecks -L unisim -L secureip work.sim_tb_top glbl
+
+onerror {resume}
+
+#Log all the objects in design. These will appear in .wlf file#
+log -r /*
+
+#View sim_tb_top signals in waveform#
+add wave sim:/sim_tb_top/*
+
+#Change radix to Hexadecimal#
+radix hex
+#Supress Numeric Std package and Arith package warnings.#
+#For VHDL designs we get some warnings due to unknown values on some signals at startup#
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
+#We may also get some Arithmetic packeage warnings because of unknown values on#
+#some of the signals that are used in an Arithmetic operation.#
+#In order to suppress these warnings, we use following two commands#
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+#Choose simulation run time by inserting a breakpoint and then run for specified #
+#period. Refer simulation_help file.#
+when {/sim_tb_top/design_top/calib_done = 1} {
+echo "Calibration Done"
+  if {[when -label a_100] == ""} {
+    when -label a_100 { $now = 50 us } {
+      nowhen a_100
+      report simulator control
+      report simulator state
+      if {[examine /sim_tb_top/design_top/error] == 0} {
+        echo "TEST PASSED"
+        stop
+        }
+      if {[examine /sim_tb_top/design_top/error] != 0} {
+        echo "TEST FAILED: DATA ERROR"
+        stop
+        }
+      }
+    }
+  }
+
+#In case calibration fails to complete, choose the run time and then quit#
+when {$now = @500 us and /sim_tb_top/design_top/calib_done != 1} {
+echo "TEST FAILED: INITIALIZATION DID NOT COMPLETE"
+stop
+}
+run -all
+stop
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim_tb_top.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim_tb_top.vhd
new file mode 100644
index 0000000..fc7fcd3
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim_tb_top.vhd
@@ -0,0 +1,445 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /   Vendor             : Xilinx
+-- \   \   \/    Version            : 3.92
+--  \   \        Application        : MIG
+--  /   /        Filename           : sim_tb_top.vhd
+-- /___/   /\    Date Last Modified : $Date: 2011/06/02 07:16:56 $
+-- \   \  /  \   Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+-- Device      : Spartan-6
+-- Design Name : DDR/DDR2/DDR3/LPDDR
+-- Purpose     : This is the simulation testbench which is used to verify the
+--               design. The basic clocks and resets to the interface are
+--               generated here. This also connects the memory interface to the
+--               memory model.
+--*****************************************************************************
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity sim_tb_top is
+
+end entity sim_tb_top;
+
+architecture arch of sim_tb_top is
+
+
+
+-- ========================================================================== --
+-- Parameters                                                                 --
+-- ========================================================================== --
+   constant DEBUG_EN              : integer :=0;   
+   
+   constant C3_HW_TESTING      : string := "FALSE";
+ 
+function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) )  return  std_logic_vector is
+   begin
+   if (C3_HW_TESTING = "FALSE") then
+     return val1;
+   else
+     return val2;
+   end if;
+   end function;		
+
+   constant  C3_MEMCLK_PERIOD : integer    := 3000;
+   constant C3_RST_ACT_LOW : integer := 0;
+   constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
+   constant C3_CLK_PERIOD_NS   : real := 3000.0 / 1000.0;
+   constant C3_TCYC_SYS        : real := C3_CLK_PERIOD_NS/2.0;
+   constant C3_TCYC_SYS_DIV2   : time := C3_TCYC_SYS * 1 ns;
+   constant C3_NUM_DQ_PINS        : integer := 16;
+   constant C3_MEM_ADDR_WIDTH     : integer := 13;
+   constant C3_MEM_BANKADDR_WIDTH : integer := 3;
+   constant C3_MEM_ADDR_ORDER     : string := "BANK_ROW_COLUMN"; 
+      constant C3_P0_MASK_SIZE : integer      := 4;
+   constant C3_P0_DATA_PORT_SIZE : integer := 32;  
+   constant C3_P1_MASK_SIZE   : integer    := 4;
+   constant C3_P1_DATA_PORT_SIZE  : integer := 32;
+   constant C3_CALIB_SOFT_IP      : string := "TRUE";
+   constant C3_SIMULATION      : string := "TRUE";
+   
+
+-- ========================================================================== --
+-- Component Declarations
+-- ========================================================================== --
+
+
+component example_top is
+generic 
+(
+            C3_P0_MASK_SIZE         : integer;
+    C3_P0_DATA_PORT_SIZE    : integer;
+    C3_P1_MASK_SIZE         : integer;
+    C3_P1_DATA_PORT_SIZE    : integer;
+    
+    C3_MEMCLK_PERIOD        : integer; 
+    C3_RST_ACT_LOW          : integer;
+    C3_INPUT_CLK_TYPE       : string;
+    DEBUG_EN                : integer;
+
+    C3_CALIB_SOFT_IP        : string;
+    C3_SIMULATION           : string;
+    C3_HW_TESTING           : string;
+    C3_MEM_ADDR_ORDER       : string;
+    C3_NUM_DQ_PINS          : integer; 
+    C3_MEM_ADDR_WIDTH       : integer; 
+    C3_MEM_BANKADDR_WIDTH   : integer
+);  
+  port
+  (
+           calib_done                    : out std_logic;
+   error                                 : out std_logic;
+
+   mcb3_dram_dq                            : inout  std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
+   mcb3_dram_a                             : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+   mcb3_dram_ba                            : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
+   mcb3_dram_ras_n                         : out std_logic;
+   mcb3_dram_cas_n                         : out std_logic;
+   mcb3_dram_we_n                          : out std_logic;
+   mcb3_dram_odt                           : out std_logic;
+   mcb3_dram_cke                           : out std_logic;
+   mcb3_dram_dm                            : out std_logic;
+      mcb3_rzq    				   : inout  std_logic;
+
+      mcb3_zio    				   : inout  std_logic;
+
+        c3_sys_clk                            : in  std_logic;
+   c3_sys_rst_i                            : in  std_logic;
+	
+   mcb3_dram_dqs                           : inout  std_logic;
+   mcb3_dram_dqs_n : inout std_logic;
+   
+		mcb3_dram_udqs                           : inout  std_logic;
+		mcb3_dram_udqs_n : inout std_logic;
+		   
+   mcb3_dram_udm                            : out std_logic;
+		
+   mcb3_dram_ck                            : out std_logic;
+   mcb3_dram_ck_n                          : out std_logic
+   
+  );
+end component;
+
+
+        component ddr2_model_c3 is
+    port (
+      ck      : in    std_logic;
+      ck_n    : in    std_logic;
+      cke     : in    std_logic;
+      cs_n    : in    std_logic;
+      ras_n   : in    std_logic;
+      cas_n   : in    std_logic;
+      we_n    : in    std_logic;
+      dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
+      ba      : in    std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
+      addr    : in    std_logic_vector((C3_MEM_ADDR_WIDTH  - 1) downto 0);
+      dq      : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
+      dqs     : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
+      dqs_n   : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
+      rdqs_n  : out   std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
+      odt     : in    std_logic
+      );
+  end component;
+
+-- ========================================================================== --
+-- Signal Declarations                                                        --
+-- ========================================================================== --
+
+ 			-- Clocks
+   signal  c3_sys_clk     : std_logic := '0';
+   signal  c3_sys_clk_p   : std_logic;
+   signal  c3_sys_clk_n   : std_logic;
+-- System Reset
+   signal  c3_sys_rst   : std_logic := '0';
+   signal  c3_sys_rst_i     : std_logic;
+
+
+
+-- Design-Top Port Map   
+   signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+   signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);  
+
+   signal  mcb3_dram_ck : std_logic;  
+   signal  mcb3_dram_ck_n : std_logic;  
+   signal  mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);   
+   signal  mcb3_dram_dqs   : std_logic;
+   signal  mcb3_dram_dqs_n : std_logic;
+   signal  mcb3_dram_dm    : std_logic;   
+   signal  mcb3_dram_ras_n : std_logic;   
+   signal  mcb3_dram_cas_n : std_logic;   
+   signal  mcb3_dram_we_n  : std_logic;    
+   signal  mcb3_dram_cke   : std_logic;   
+   signal  mcb3_dram_odt   : std_logic;  
+       signal  calib_done                        : std_logic;  
+   signal  error                             : std_logic;  
+
+
+      signal  mcb3_dram_udqs   : std_logic;
+   signal  mcb3_dram_udqs_n : std_logic;
+   signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
+   signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
+      signal   mcb3_dram_udm :std_logic;     -- for X16 parts
+   signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
+   
+   
+
+
+   signal mcb3_command               : std_logic_vector(2 downto 0);
+   signal mcb3_enable1                : std_logic;
+   signal mcb3_enable2              : std_logic;
+
+   signal  rzq3     : std_logic;
+      
+   signal  zio3     : std_logic;
+      
+
+
+function vector (asi:std_logic) return std_logic_vector is
+  variable v : std_logic_vector(0 downto 0) ; 
+begin
+  v(0) := asi;
+  return(v); 
+end function vector; 
+
+begin
+-- ========================================================================== --
+-- Clocks Generation                                                          --
+-- ========================================================================== --
+
+
+  process
+  begin
+    c3_sys_clk <= not c3_sys_clk;
+    wait for (C3_TCYC_SYS_DIV2);
+  end process;
+
+  c3_sys_clk_p <= c3_sys_clk;
+  c3_sys_clk_n <= not c3_sys_clk;
+
+-- ========================================================================== --
+-- Reset Generation                                                           --
+-- ========================================================================== --
+ 
+ process
+  begin
+    c3_sys_rst <= '0';
+    wait for 200 ns;
+    c3_sys_rst <= '1';
+    wait;
+  end process;
+
+    c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
+
+
+
+
+
+   
+
+   
+   -- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
+-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
+   zio_pulldown3 : PULLDOWN port map(O => zio3);
+   rzq_pulldown3 : PULLDOWN port map(O => rzq3);
+   
+
+-- ========================================================================== --
+-- DESIGN TOP INSTANTIATION                                                    --
+-- ========================================================================== --
+
+design_top : example_top generic map
+(
+  
+C3_P0_MASK_SIZE  =>     C3_P0_MASK_SIZE,
+C3_P0_DATA_PORT_SIZE  => C3_P0_DATA_PORT_SIZE,
+C3_P1_MASK_SIZE       => C3_P1_MASK_SIZE,
+C3_P1_DATA_PORT_SIZE  => C3_P1_DATA_PORT_SIZE, 
+	C3_MEMCLK_PERIOD  =>       C3_MEMCLK_PERIOD,
+C3_RST_ACT_LOW    =>     C3_RST_ACT_LOW,
+C3_INPUT_CLK_TYPE =>     C3_INPUT_CLK_TYPE, 
+DEBUG_EN              => DEBUG_EN,
+
+C3_MEM_ADDR_ORDER     => C3_MEM_ADDR_ORDER,
+C3_NUM_DQ_PINS        => C3_NUM_DQ_PINS,
+C3_MEM_ADDR_WIDTH     => C3_MEM_ADDR_WIDTH,
+C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
+
+
+C3_HW_TESTING   =>      C3_HW_TESTING,
+C3_SIMULATION   =>      C3_SIMULATION,
+
+C3_CALIB_SOFT_IP      => C3_CALIB_SOFT_IP
+) 
+port map ( 
+
+  calib_done         =>                      calib_done,
+  error                          =>           error,
+  c3_sys_clk  =>         c3_sys_clk,
+  c3_sys_rst_i    =>       c3_sys_rst_i,                        
+
+  mcb3_dram_dq     =>      mcb3_dram_dq,  
+  mcb3_dram_a      =>      mcb3_dram_a,  
+  mcb3_dram_ba     =>      mcb3_dram_ba,
+  mcb3_dram_ras_n  =>      mcb3_dram_ras_n,                        
+  mcb3_dram_cas_n  =>      mcb3_dram_cas_n,                        
+  mcb3_dram_we_n   =>      mcb3_dram_we_n,                          
+  mcb3_dram_odt    =>      mcb3_dram_odt,
+  mcb3_dram_cke    =>      mcb3_dram_cke,                          
+  mcb3_dram_ck     =>      mcb3_dram_ck,                          
+  mcb3_dram_ck_n   =>      mcb3_dram_ck_n,       
+  mcb3_dram_dqs_n  =>      mcb3_dram_dqs_n,
+  mcb3_dram_udqs  =>       mcb3_dram_udqs,    -- for X16 parts           
+  mcb3_dram_udqs_n    =>   mcb3_dram_udqs_n,  -- for X16 parts
+  mcb3_dram_udm  =>        mcb3_dram_udm,     -- for X16 parts
+  mcb3_dram_dm  =>       mcb3_dram_dm,
+     mcb3_rzq        =>            rzq3,
+	
+     mcb3_zio        =>            zio3,
+	
+  mcb3_dram_dqs    =>      mcb3_dram_dqs
+);      
+
+
+
+-- ========================================================================== --
+-- Memory model instances                                                     -- 
+-- ========================================================================== --
+
+    mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
+
+    process(mcb3_dram_ck)
+    begin
+      if (rising_edge(mcb3_dram_ck)) then
+        if (c3_sys_rst = '0') then
+          mcb3_enable1   <= '0';
+          mcb3_enable2 <= '0';
+        elsif (mcb3_command = "100") then
+          mcb3_enable2 <= '0';
+        elsif (mcb3_command = "101") then
+          mcb3_enable2 <= '1';
+        else
+          mcb3_enable2 <= mcb3_enable2;
+        end if;
+        mcb3_enable1     <= mcb3_enable2;
+      end if;
+    end process;
+
+-----------------------------------------------------------------------------
+--read
+-----------------------------------------------------------------------------
+    mcb3_dram_dqs_vector(1 downto 0)               <= (mcb3_dram_udqs & mcb3_dram_dqs)
+                                                           when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
+							   else "ZZ";
+    mcb3_dram_dqs_n_vector(1 downto 0)             <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
+                                                           when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
+							   else "ZZ";
+    
+-----------------------------------------------------------------------------
+--write
+-----------------------------------------------------------------------------
+    mcb3_dram_dqs          <= mcb3_dram_dqs_vector(0)
+                              when ( mcb3_enable1 = '1') else 'Z';
+
+    mcb3_dram_udqs          <= mcb3_dram_dqs_vector(1)
+                              when (mcb3_enable1 = '1') else 'Z';
+
+
+     mcb3_dram_dqs_n        <= mcb3_dram_dqs_n_vector(0)
+                              when (mcb3_enable1 = '1') else 'Z';
+    mcb3_dram_udqs_n         <= mcb3_dram_dqs_n_vector(1)
+                              when (mcb3_enable1 = '1') else 'Z';
+
+   
+   
+mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
+
+     u_mem_c3 : ddr2_model_c3 port map(
+        ck        => mcb3_dram_ck,
+        ck_n      => mcb3_dram_ck_n,
+        cke       => mcb3_dram_cke,
+        cs_n      => '0',
+        ras_n     => mcb3_dram_ras_n,
+        cas_n     => mcb3_dram_cas_n,
+        we_n      => mcb3_dram_we_n,
+        dm_rdqs   => mcb3_dram_dm_vector ,
+        ba        => mcb3_dram_ba,
+        addr      => mcb3_dram_a,
+        dq        => mcb3_dram_dq,
+        dqs       => mcb3_dram_dqs_vector,
+        dqs_n     => mcb3_dram_dqs_n_vector,
+        rdqs_n    => open,
+        odt       => mcb3_dram_odt
+      );
+
+-----------------------------------------------------------------------------     
+-- Reporting the test case status 
+-----------------------------------------------------------------------------
+   Logging: process 
+   begin
+      wait for 200 us;
+      if (calib_done = '1') then
+         if (error = '0') then
+   	    report ("****TEST PASSED****");
+         else
+            report ("****TEST FAILED: DATA ERROR****");
+         end if;
+      else
+         report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
+      end if;
+   end process;   
+
+end architecture;
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/timing_sim.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/timing_sim.sh
new file mode 100755
index 0000000..fcd79a0
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/timing_sim.sh
@@ -0,0 +1,72 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+#   ____  ____
+#  /   /\/   /
+# /___/  \  /    Vendor                : Xilinx
+# \   \   \/     Version               : 3.92
+#  \   \         Application           : MIG
+#  /   /         Filename              : timing_sim.bat
+# /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:56 $
+# \   \  /  \    Date Created          : Fri Feb 06 2009
+#  \___\/\___\
+#
+# Device            : Spartan-6
+# Design Name       : DDR/DDR2/DDR3/LPDDR
+# Purpose           : Batch file to generate simulation netlist file.
+# Reference         :
+# Revision History  :
+# ****************************************************************************
+
+echo Simulation Tool: TIMING SIMULATION
+cd ../../par
+./ise_flow.bat
+echo Netlist Generated
+cd ../sim/timing
+echo done
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/mem_interface_top_synp.sdc b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/mem_interface_top_synp.sdc
new file mode 100644
index 0000000..7fff765
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/mem_interface_top_synp.sdc
@@ -0,0 +1,36 @@
+# Synplicity, Inc. constraint file
+# Written on Mon Jun 27 15:50:39 2005
+
+define_attribute          {v:work.example_top} syn_hier {hard}
+define_attribute          {v:work.iodrp_controller} syn_hier {hard}
+define_attribute          {v:work.iodrp_mcb_controller} syn_hier {hard}
+define_attribute          {v:work.mcb_raw_wrapper} syn_hier {hard}
+define_attribute          {v:work.mcb_soft_calibration} syn_hier {hard}
+define_attribute          {v:work.mcb_soft_calibration_top} syn_hier {hard}
+define_attribute          {v:work.memc3_infrastructure} syn_hier {hard}
+define_attribute          {v:work.memc3_tb_top} syn_hier {hard}
+define_attribute          {v:work.memc3_wrapper} syn_hier {hard}
+define_attribute          {v:work.afifo} syn_hier {hard}
+define_attribute          {v:work.cmd_gen} syn_hier {hard}
+define_attribute          {v:work.cmd_prbs_gen} syn_hier {hard}
+define_attribute          {v:work.data_prbs_gen} syn_hier {hard}
+define_attribute          {v:work.init_mem_pattern_ctr} syn_hier {hard}
+define_attribute          {v:work.mcb_flow_control} syn_hier {hard}
+define_attribute          {v:work.mcb_traffic_gen} syn_hier {hard}
+define_attribute          {v:work.rd_data_gen} syn_hier {hard}
+define_attribute          {v:work.read_data_path} syn_hier {hard}
+define_attribute          {v:work.read_posted_fifo} syn_hier {hard}
+define_attribute          {v:work.sp6_data_gen} syn_hier {hard}
+define_attribute          {v:work.tg_status} syn_hier {hard}
+define_attribute          {v:work.v6_data_gen} syn_hier {hard}
+define_attribute          {v:work.wr_data_gen} syn_hier {hard}
+define_attribute          {v:work.write_data_path} syn_hier {hard}
+
+# clock Constraints
+define_clock -disable -name {memc3_infrastructure_inst} -period 3000 -clockgroup default_clkgroup_1
+define_clock          -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 3000 -clockgroup default_clkgroup_2
+define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 3000 -clockgroup default_clkgroup_3
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/script_synp.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/script_synp.tcl
new file mode 100644
index 0000000..6cb9704
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/script_synp.tcl
@@ -0,0 +1,56 @@
+project -new 
+add_file -vhdl "../rtl/example_top.vhd"
+add_file -vhdl "../rtl/iodrp_controller.vhd"
+add_file -vhdl "../rtl/iodrp_mcb_controller.vhd"
+add_file -vhdl "../rtl/mcb_raw_wrapper.vhd"
+add_file -vhdl "../rtl/mcb_soft_calibration.vhd"
+add_file -vhdl "../rtl/mcb_soft_calibration_top.vhd"
+add_file -vhdl "../rtl/memc3_infrastructure.vhd"
+add_file -vhdl "../rtl/memc3_tb_top.vhd"
+add_file -vhdl "../rtl/memc3_wrapper.vhd"
+add_file -vhdl "../rtl/traffic_gen/afifo.vhd"
+add_file -vhdl "../rtl/traffic_gen/cmd_gen.vhd"
+add_file -vhdl "../rtl/traffic_gen/cmd_prbs_gen.vhd"
+add_file -vhdl "../rtl/traffic_gen/data_prbs_gen.vhd"
+add_file -vhdl "../rtl/traffic_gen/init_mem_pattern_ctr.vhd"
+add_file -vhdl "../rtl/traffic_gen/mcb_flow_control.vhd"
+add_file -vhdl "../rtl/traffic_gen/mcb_traffic_gen.vhd"
+add_file -vhdl "../rtl/traffic_gen/rd_data_gen.vhd"
+add_file -vhdl "../rtl/traffic_gen/read_data_path.vhd"
+add_file -vhdl "../rtl/traffic_gen/read_posted_fifo.vhd"
+add_file -vhdl "../rtl/traffic_gen/sp6_data_gen.vhd"
+add_file -vhdl "../rtl/traffic_gen/tg_status.vhd"
+add_file -vhdl "../rtl/traffic_gen/v6_data_gen.vhd"
+add_file -vhdl "../rtl/traffic_gen/wr_data_gen.vhd"
+add_file -vhdl "../rtl/traffic_gen/write_data_path.vhd"
+add_file -constraint "../synth/mem_interface_top_synp.sdc"
+impl -add rev_1
+set_option -technology spartan6
+set_option -part xc6slx45
+set_option -package csg324
+set_option -speed_grade -3
+set_option -default_enum_encoding default
+#AXI_ENABLE synp definition is not required for user_design
+set_option -symbolic_fsm_compiler 1
+set_option -resource_sharing 0
+set_option -use_fsm_explorer 0
+set_option -top_module "example_top"
+set_option -frequency 333.333
+set_option -fanout_limit 1000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -fixgatedclocks 0
+set_option -retiming 0
+set_option -modular 0
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -write_apr_constraint 0
+project -result_file "../synth/rev_1/example_top.edf"
+set_option -vlog_std v2001
+set_option -auto_constrain_io 0
+impl -active "../synth/rev_1"
+project -run
+project -save
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/datasheet.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/datasheet.txt
new file mode 100644
index 0000000..e659cf3
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/datasheet.txt
@@ -0,0 +1,72 @@
+
+
+CORE Generator Options:
+   Target Device              : xc6slx45-csg324
+   Speed Grade                : -3
+   HDL                        : vhdl
+   Synthesis Tool             : Foundation_ISE
+
+MIG Output Options:
+   Component Name             : ddr2
+   No of Controllers          : 1
+   Hardware Test Bench           : disabled
+
+    
+/*******************************************************/
+/*                  Controller 3                       */
+/*******************************************************/
+Controller Options : 
+   Memory                  : DDR2_SDRAM
+   Interface               : NATIVE
+   Design Clock Frequency  : 3000 ps (333.33 MHz)
+   Memory Type             : Components
+   Memory Part             : MT47H64M16XX-25E
+   Equivalent Part(s)      : MT47H64M16HR-25E
+   Row Address             : 13
+   Column Address          : 10
+   Bank Address            : 3
+   Data Mask               : enabled
+
+Memory Options :
+   Burst Length                       : 4(010)
+   CAS Latency                        : 5
+   DQS# Enable                        : Enable
+   DLL Enable                         : Enable-Normal
+   OCD Operation                      : OCD Exit
+   Output Drive Strength              : Fullstrength
+   Outputs                            : Enable
+   Additive Latency (AL)              : 0
+   RDQS Enable                        : Disable
+   RTT (nominal) - ODT                : 50ohms       
+   High Temparature Self Refresh Rate : Disable
+
+User Interface Parameters :
+   Configuration Type     : Four 32-bit bi-directional ports
+   Ports Selected         : Port0, Port1, Port2, Port3
+   Memory Address Mapping : BANK_ROW_COLUMN
+
+   Arbitration Algorithm  : Round Robin
+
+   Arbitration            : 
+      Time Slot0 : 0123
+      Time Slot1 : 1230
+      Time Slot2 : 2301
+      Time Slot3 : 3012
+      Time Slot4 : 0123
+      Time Slot5 : 1230
+      Time Slot6 : 2301
+      Time Slot7 : 3012
+      Time Slot8 : 0123
+      Time Slot9 : 1230
+      Time Slot10: 2301
+      Time Slot11: 3012
+
+FPGA Options :
+   Class for Address and Control       : II
+   Class for Data                      : II
+   Memory Interface Pin Termination    : CALIB_TERM
+   DQ/DQS                              : 25 Ohms
+   Bypass Calibration                  : enabled
+   Debug Signals for Memory Controller : Disable
+   Input Clock Type                    : Single-Ended 
+    
\ No newline at end of file
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/create_ise.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/create_ise.sh
new file mode 100755
index 0000000..d71e95f
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/create_ise.sh
@@ -0,0 +1,72 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+#   ____  ____
+#  /   /\/   /
+# /___/  \  /    Vendor                : Xilinx
+# \   \   \/     Version               : 3.92
+#  \   \         Application           : MIG
+#  /   /         Filename              : create_ise.bat
+# /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+# \   \  /  \    Date Created          : Fri Feb 06 2009
+#  \___\/\___\
+#
+# Device            : Spartan-6
+# Design Name       : DDR/DDR2/DDR3/LPDDR
+# Purpose           : Batch file to run PAR through ISE
+# Reference         :
+# Revision History  :
+# ****************************************************************************
+
+./rem_files.sh
+
+
+
+
+xtclsh set_ise_prop.tcl
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ddr2.ucf b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ddr2.ucf
new file mode 100644
index 0000000..1b35b90
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ddr2.ucf
@@ -0,0 +1,163 @@
+############################################################################
+## 
+##  Xilinx, Inc. 2006            www.xilinx.com 
+##  Sun Jul 28 12:10:25 2013
+##  Generated by MIG Version 3.92
+##  
+############################################################################
+##  File name :       ddr2.ucf
+## 
+##  Details :     Constraints file
+##                    FPGA family:       spartan6
+##                    FPGA:              xc6slx45-csg324
+##                    Speedgrade:        -3
+##                    Design Entry:      VHDL
+##                    Design:            without Test bench
+##                    DCM Used:          Enable
+##                    No.Of Memory Controllers: 1
+##
+############################################################################ 
+############################################################################
+# VCC AUX VOLTAGE 
+############################################################################
+CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
+
+############################################################################
+# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
+# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
+# follows the corresponding GUI option setting. However, DDR3 can operate at higher 
+# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
+# remove/edit the below constraint to avoid false errors.
+############################################################################
+CONFIG MCB_PERFORMANCE= STANDARD;
+
+
+##################################################################################
+# Timing Ignore constraints for paths crossing the clock domain 
+##################################################################################
+NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
+NET "c?_pll_lock" TIG;
+INST "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
+
+#Please uncomment the below TIG if used in a design which enables self-refresh mode
+#NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
+     
+NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
+     
+
+############################################################################
+## Memory Controller 3                               
+## Memory Device: DDR2_SDRAM->MT47H64M16XX-25E 
+## Frequency: 333.333 MHz
+## Time Period: 3000 ps
+## Supported Part Numbers: MT47H64M16HR-25E
+############################################################################
+
+############################################################################
+## Clock constraints                                                        
+############################################################################
+NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
+TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3"  3  ns HIGH 50 %;
+############################################################################
+
+############################################################################
+## I/O TERMINATION                                                          
+############################################################################
+NET "mcb3_dram_dq[*]"                                 IN_TERM = NONE;
+NET "mcb3_dram_dqs"                                   IN_TERM = NONE;
+NET "mcb3_dram_dqs_n"                                 IN_TERM = NONE;
+NET "mcb3_dram_udqs"                                  IN_TERM = NONE;
+NET "mcb3_dram_udqs_n"                                IN_TERM = NONE;
+
+############################################################################
+# I/O STANDARDS 
+############################################################################
+
+NET  "mcb3_dram_dq[*]"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_a[*]"                                IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_ba[*]"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_dqs"                                 IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_udqs"                                IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_dqs_n"                               IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_udqs_n"                              IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_ck"                                  IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_ck_n"                                IOSTANDARD = DIFF_SSTL18_II ;
+NET  "mcb3_dram_cke"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_ras_n"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_cas_n"                               IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_we_n"                                IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_odt"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_dm"                                  IOSTANDARD = SSTL18_II ;
+NET  "mcb3_dram_udm"                                 IOSTANDARD = SSTL18_II ;
+NET  "mcb3_rzq"                                      IOSTANDARD = SSTL18_II ;
+NET  "mcb3_zio"                                      IOSTANDARD = SSTL18_II ;
+NET  "c3_sys_clk"                                  IOSTANDARD = LVCMOS25 ;
+NET  "c3_sys_rst_i"                                IOSTANDARD = LVCMOS18 ;
+############################################################################
+# MCB 3
+# Pin Location Constraints for Clock, Masks, Address, and Controls
+############################################################################
+
+NET  "mcb3_dram_a[0]"                            LOC = "J7" ;
+NET  "mcb3_dram_a[10]"                           LOC = "F4" ;
+NET  "mcb3_dram_a[11]"                           LOC = "D3" ;
+NET  "mcb3_dram_a[12]"                           LOC = "G6" ;
+NET  "mcb3_dram_a[1]"                            LOC = "J6" ;
+NET  "mcb3_dram_a[2]"                            LOC = "H5" ;
+NET  "mcb3_dram_a[3]"                            LOC = "L7" ;
+NET  "mcb3_dram_a[4]"                            LOC = "F3" ;
+NET  "mcb3_dram_a[5]"                            LOC = "H4" ;
+NET  "mcb3_dram_a[6]"                            LOC = "H3" ;
+NET  "mcb3_dram_a[7]"                            LOC = "H6" ;
+NET  "mcb3_dram_a[8]"                            LOC = "D2" ;
+NET  "mcb3_dram_a[9]"                            LOC = "D1" ;
+NET  "mcb3_dram_ba[0]"                           LOC = "F2" ;
+NET  "mcb3_dram_ba[1]"                           LOC = "F1" ;
+NET  "mcb3_dram_ba[2]"                           LOC = "E1" ;
+NET  "mcb3_dram_cas_n"                           LOC = "K5" ;
+NET  "mcb3_dram_ck"                              LOC = "G3" ;
+NET  "mcb3_dram_ck_n"                            LOC = "G1" ;
+NET  "mcb3_dram_cke"                             LOC = "H7" ;
+NET  "mcb3_dram_dm"                              LOC = "K3" ;
+NET  "mcb3_dram_dq[0]"                           LOC = "L2" ;
+NET  "mcb3_dram_dq[10]"                          LOC = "N2" ;
+NET  "mcb3_dram_dq[11]"                          LOC = "N1" ;
+NET  "mcb3_dram_dq[12]"                          LOC = "T2" ;
+NET  "mcb3_dram_dq[13]"                          LOC = "T1" ;
+NET  "mcb3_dram_dq[14]"                          LOC = "U2" ;
+NET  "mcb3_dram_dq[15]"                          LOC = "U1" ;
+NET  "mcb3_dram_dq[1]"                           LOC = "L1" ;
+NET  "mcb3_dram_dq[2]"                           LOC = "K2" ;
+NET  "mcb3_dram_dq[3]"                           LOC = "K1" ;
+NET  "mcb3_dram_dq[4]"                           LOC = "H2" ;
+NET  "mcb3_dram_dq[5]"                           LOC = "H1" ;
+NET  "mcb3_dram_dq[6]"                           LOC = "J3" ;
+NET  "mcb3_dram_dq[7]"                           LOC = "J1" ;
+NET  "mcb3_dram_dq[8]"                           LOC = "M3" ;
+NET  "mcb3_dram_dq[9]"                           LOC = "M1" ;
+NET  "mcb3_dram_dqs"                             LOC = "L4" ;
+NET  "mcb3_dram_dqs_n"                           LOC = "L3" ;
+NET  "mcb3_dram_odt"                             LOC = "K6" ;
+NET  "mcb3_dram_ras_n"                           LOC = "L5" ;
+NET  "c3_sys_clk"                                LOC = "R10" ;
+NET  "c3_sys_rst_i"                              LOC = "M8" ;
+NET  "mcb3_dram_udm"                             LOC = "K4" ;
+NET  "mcb3_dram_udqs"                            LOC = "P2" ;
+NET  "mcb3_dram_udqs_n"                          LOC = "P1" ;
+NET  "mcb3_dram_we_n"                            LOC = "E3" ;
+
+##################################################################################
+#RZQ is required for all MCB designs.   Do not move the location #
+#of this pin for ES devices.For production devices, RZQ can be moved to any #
+#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
+#a 2R resistor should be connected between RZQand ground, where R is the desired#
+#input termination value.  Otherwise, RZQ should be left as a no-connect (NC) pin.#
+##################################################################################
+NET  "mcb3_rzq"                                  LOC = "N4" ;
+##################################################################################
+#ZIO is only required for MCB designs using Calibrated Input Termination.#
+#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
+#MCB bank but must be left as a no-connect (NC) pin.#
+##################################################################################
+NET  "mcb3_zio"                                  LOC = "P4" ;
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/icon_coregen.xco b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/icon_coregen.xco
new file mode 100644
index 0000000..ac21f7c
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/icon_coregen.xco
@@ -0,0 +1,48 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.1
+# Date: Wed Mar 11 07:09:11 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -3
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
+# END Select
+# BEGIN Parameters
+CSET component_name=icon
+CSET enable_jtag_bufg=true
+CSET number_control_ports=2
+CSET use_ext_bscan=false
+CSET use_softbscan=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+GENERATE
+# CRC: 7da1f376
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ila_coregen.xco b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ila_coregen.xco
new file mode 100644
index 0000000..888c551
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ila_coregen.xco
@@ -0,0 +1,131 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.1
+# Date: Wed Mar 11 06:55:40 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -3
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
+# END Select
+# BEGIN Parameters
+CSET component_name=ila
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=256
+CSET data_same_as_trigger=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET exclude_from_data_storage_1=true
+CSET exclude_from_data_storage_10=true
+CSET exclude_from_data_storage_11=true
+CSET exclude_from_data_storage_12=true
+CSET exclude_from_data_storage_13=true
+CSET exclude_from_data_storage_14=true
+CSET exclude_from_data_storage_15=true
+CSET exclude_from_data_storage_16=true
+CSET exclude_from_data_storage_2=true
+CSET exclude_from_data_storage_3=true
+CSET exclude_from_data_storage_4=true
+CSET exclude_from_data_storage_5=true
+CSET exclude_from_data_storage_6=true
+CSET exclude_from_data_storage_7=true
+CSET exclude_from_data_storage_8=true
+CSET exclude_from_data_storage_9=true
+CSET match_type_1=basic_with_edges
+CSET match_type_10=basic
+CSET match_type_11=basic
+CSET match_type_12=basic
+CSET match_type_13=basic
+CSET match_type_14=basic
+CSET match_type_15=basic
+CSET match_type_16=basic
+CSET match_type_2=basic
+CSET match_type_3=basic
+CSET match_type_4=basic
+CSET match_type_5=basic
+CSET match_type_6=basic
+CSET match_type_7=basic
+CSET match_type_8=basic
+CSET match_type_9=basic
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=1024
+CSET sample_on=Rising
+CSET trigger_port_width_1=2
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=true
+# END Parameters
+GENERATE
+# CRC: eff89f81
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_flow.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_flow.sh
new file mode 100755
index 0000000..bb7157e
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_flow.sh
@@ -0,0 +1,86 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+#   ____  ____
+#  /   /\/   /
+# /___/  \  /    Vendor                : Xilinx
+# \   \   \/     Version               : 3.92
+#  \   \         Application           : MIG
+#  /   /         Filename              : ise_flow.bat
+# /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+# \   \  /  \    Date Created          : Fri Feb 06 2009
+#  \___\/\___\
+#
+# Device            : Spartan-6
+# Design Name       : DDR/DDR2/DDR3/LPDDR
+# Purpose           : Batch file to run PAR through ISE batch mode
+# Reference         :
+# Revision History  :
+# ****************************************************************************
+
+./rem_files.sh
+
+
+
+
+echo Synthesis Tool: XST
+
+mkdir "../synth/__projnav" > ise_flow_results.txt
+mkdir "../synth/xst" >> ise_flow_results.txt
+mkdir "../synth/xst/work" >> ise_flow_results.txt
+
+xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt
+ngdbuild -intstyle ise -dd ../synth/_ngo -uc ddr2.ucf -p xc6slx45csg324-3 ddr2.ngc ddr2.ngd >> ise_flow_results.txt
+
+map -intstyle ise -detail -w -pr off -c 100 -o ddr2_map.ncd ddr2.ngd ddr2.pcf >> ise_flow_results.txt
+par -w -intstyle ise -ol std ddr2_map.ncd ddr2.ncd ddr2.pcf >> ise_flow_results.txt
+trce -e 100 ddr2.ncd ddr2.pcf >> ise_flow_results.txt
+bitgen -intstyle ise -f mem_interface_top.ut ddr2.ncd >> ise_flow_results.txt
+
+echo done!
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_run.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_run.txt
new file mode 100644
index 0000000..b22e978
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_run.txt
@@ -0,0 +1,58 @@
+set -tmpdir ../synth/__projnav 
+set -xsthdpdir ../synth/xst
+run 
+#Source Parameters
+-ifn ../synth/ddr2.prj
+-ifmt mixed
+-iuc No
+#Target Parameters
+-ofn ddr2
+-ofmt NGC
+-p xc6slx45-3csg324
+#AXI_ENABLE definition is not required for NATIVE interface
+#Source Options
+-top ddr2
+-fsm_extract Yes 
+-fsm_encoding one-hot
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-rom_style Auto
+-shreg_extract Yes
+-resource_sharing Yes
+-async_to_sync no
+-mult_style auto
+-register_balancing No
+#Target Options
+-iobuf Yes
+#Max fanout value shouldn't be set below 64 for MCB design
+-max_fanout 500
+-bufg 16 
+-register_duplication yes
+-optimize_primitives No
+-use_clock_enable Auto 
+-use_sync_set Auto   
+-use_sync_reset Auto 
+-iob auto
+-equivalent_register_removal yes
+#General Options
+-opt_mode Speed
+-opt_level 1
+-lso ../synth/ddr2.lso
+-keep_hierarchy NO
+-netlist_hierarchy as_optimized
+-rtlview Yes
+-glob_opt allclocknets
+-read_cores Yes
+-write_timing_constraints No
+-cross_clock_analysis No
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-auto_bram_packing No
+-slice_utilization_ratio_maxmargin 5
+quit
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/makeproj.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/makeproj.sh
new file mode 100755
index 0000000..2f5c9f7
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/makeproj.sh
@@ -0,0 +1,2 @@
+NEWPROJECT .
+SETPROJECT .
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/mem_interface_top.ut b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/mem_interface_top.ut
new file mode 100644
index 0000000..bc59a01
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/mem_interface_top.ut
@@ -0,0 +1,22 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullNone
+-g UserID:0xFFFFFFFF
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
+-g ConfigRate:6
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/readme.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/readme.txt
new file mode 100644
index 0000000..aaa9848
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/readme.txt
@@ -0,0 +1,146 @@
+::****************************************************************************
+:: (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+::
+:: This file contains confidential and proprietary information
+:: of Xilinx, Inc. and is protected under U.S. and
+:: international copyright and other intellectual property
+:: laws.
+::
+:: DISCLAIMER
+:: This disclaimer is not a license and does not grant any
+:: rights to the materials distributed herewith. Except as
+:: otherwise provided in a valid license issued to you by
+:: Xilinx, and to the maximum extent permitted by applicable
+:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+:: (2) Xilinx shall not be liable (whether in contract or tort,
+:: including negligence, or under any other theory of
+:: liability) for any loss or damage of any kind or nature
+:: related to, arising under or in connection with these
+:: materials, including for any direct, or any indirect,
+:: special, incidental, or consequential loss or damage
+:: (including loss of data, profits, goodwill, or any type of
+:: loss or damage suffered as a result of any action brought
+:: by a third party) even if such damage or loss was
+:: reasonably foreseeable or Xilinx had been advised of the
+:: possibility of the same.
+::
+:: CRITICAL APPLICATIONS
+:: Xilinx products are not designed or intended to be fail-
+:: safe, or for use in any application requiring fail-safe
+:: performance, such as life-support or safety devices or
+:: systems, Class III medical devices, nuclear facilities,
+:: applications related to the deployment of airbags, or any
+:: other applications that could lead to death, personal
+:: injury, or severe property or environmental damage
+:: (individually and collectively, "Critical
+:: Applications"). Customer assumes the sole risk and
+:: liability of any use of Xilinx products in Critical
+:: Applications, subject only to applicable laws and
+:: regulations governing limitations on product liability.
+::
+:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+:: PART OF THIS FILE AT ALL TIMES.
+::
+::****************************************************************************
+::   ____  ____
+::  /   /\/   /
+:: /___/  \  /    Vendor                : Xilinx
+:: \   \   \/     Version               : 3.92
+::  \   \         Application           : MIG
+::  /   /         Filename              : readme.txt
+:: /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+:: \   \  /  \    Date Created          : Fri Feb 06 2009
+::  \___\/\___\
+::
+:: Device            : Spartan-6
+:: Design Name       : DDR/DDR2/DDR3/LPDDR
+:: Purpose           : Information about par folder
+:: Reference         :
+:: Revision History  :
+::****************************************************************************
+
+This folder has the batch files to synthesize using XST or Synplify Pro and
+implement the design either in "Command Line Mode" or in "GUI Mode".
+
+Steps to run the design using the ise_flow (batch mode):
+
+1. Executing the "ise_flow.bat" file synthesizes the design using XST or
+   Synplify Pro and does implement the design.
+     a. First it removes the XST/Synplify Pro report files, implementation
+        files, supporting scripts, the generated chipscope designs (if 
+        enabled) and the ISE project files (if exist any on previous runs)
+     b. Synthesizes the design either with XST or Synplicity
+     c. Implements the design with ISE.   
+
+2. After the design is run, it creates ise_flow_results.txt file that will have
+   the ISE log information.
+
+Steps to run the design using the create_ise (GUI mode - for XST cases only):
+
+1. This file will appear for XST cases only.
+
+2. On executing the "create_ise.bat" file creates "test.xise" project file
+   and set all the properties of the design selected.
+
+3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
+
+4. In Linux operating systems, test.xise project can be invoked by executing the command
+   'ise test.xise' from the terminal.
+
+Other files in PAR folder :
+
+* "ddr2.ucf" file is the constraint file for the design.
+  It has clock constraints, location constraints and IO standards.
+
+* "mem_interface_top.ut" file has the options for the Configuration file
+  generation i.e. the "ddr2.bit" file to run in batch mode.
+
+* "rem_files.bat" file has all the ISE/Synplify Pro generated report files, 
+  implementation files, supporting scripts, the generated chipscope designs
+  (if enabled) and the ISE project files.
+
+* "set_ise_prop.tcl" file has all the properties that are to be
+  set in GUI mode.
+
+* "ise_run.txt" file has synthesis options for the XST tool.
+  This file is used for batch mode.
+
+* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to 
+   generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the 
+   EDIF/NGC files, you must execute the following commands before starting 
+   synthesis and PAR.
+
+           coregen -b ila_coregen.xco
+           coregen -b icon_coregen.xco
+           coregen -b vio_coregen.xco
+
+Note : When you generate the design using "Debug Signals for Memory Controller"
+       option Enable, the above mentioned ChipScope coregen commands are printed
+       into ise_flow.bat and create_ise.bat files. The ddr2 rtl file
+       will have the design debug signals portmapped to vio and icon
+       ChipScope modules.
+
+* At the start of a Chip Scope Analyzer project, all of the signals in
+  every core have generic names. "ddr2.cdc" is a file that contains
+  all the signal names of all cores. Upon importing this file, signal names are
+  renamed to the specified names in "ddr2.cdc" file. This file will work
+  for the generated designs from MIG. If any of the design parameter values
+  are changed after generating the design, this file will not work.
+  For Multiple Controller designs, signal names provided in CDC file are of 
+  the controller that is enabled for Debug in the GUI.
+
+synth folder:
+
+1. mem_interface_top_synp.sdc
+2. script_synp.tcl
+3. ddr2.prj
+4. ddr2.lso
+
+   mem_interface_top_synp.sdc and script_synp.tcl files are being used by
+   Synplify Pro and ddr2.prj and ddr2.lso are being used by XST.
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/rem_files.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/rem_files.sh
new file mode 100755
index 0000000..824ad8c
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/rem_files.sh
@@ -0,0 +1,169 @@
+##!/bin/csh -f
+##****************************************************************************
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+##****************************************************************************
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor                : Xilinx
+## \   \   \/     Version               : 3.92
+##  \   \         Application           : MIG
+##  /   /         Filename              : rem_files.bat
+## /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+## \   \  /  \    Date Created          : Fri Feb 06 2009
+##  \___\/\___\
+##
+## Device            : Spartan-6
+## Design Name       : DDR/DDR2/DDR3/LPDDR
+## Purpose           : Batch file to remove files generated from ISE
+## Reference         :
+## Revision History  :
+##****************************************************************************
+
+rm -rf "../synth/__projnav" 
+rm -rf "../synth/xst" 
+rm -rf "../synth/_ngo" 
+
+rm -rf tmp 
+rm -rf _xmsgs
+rm -rf ila_xdb 
+rm -rf icon_xdb
+rm -rf vio_xdb
+
+rm -rf xlnx_auto_0_xdb 
+
+rm -rf vio_xmdf.tcl
+rm -rf vio_readme.txt
+rm -rf vio_flist.txt
+rm -rf vio.xise del
+rm -rf vio.xco del
+rm -rf vio.ngc del
+rm -rf vio.ise del
+rm -rf vio.gise del
+rm -rf vio.cdc del
+
+rm -rf coregen.cgp
+rm -rf coregen.cgc
+rm -rf coregen.log 
+rm -rf ila.cdc 
+rm -rf ila.gise 
+rm -rf ila.ise 
+rm -rf ila.ngc 
+rm -rf ila.xco 
+rm -rf ila.xise 
+rm -rf ila_flist.txt 
+rm -rf ila_readme.txt 
+rm -rf ila_xmdf.tcl 
+
+rm -rf icon.asy
+rm -rf icon.gise
+rm -rf icon.ise
+rm -rf icon.ncf
+rm -rf icon.ngc
+rm -rf icon.xco
+rm -rf icon.xise
+rm -rf icon_flist.txt
+rm -rf icon_readme.txt
+rm -rf icon_xmdf.tcl
+
+rm -rf ise_flow_results.txt 
+rm -rf ddr2_vhdl.prj 
+rm -rf mem_interface_top.syr 
+rm -rf ddr2.ngc 
+rm -rf ddr2.ngr 
+rm -rf ddr2_xst.xrpt 
+rm -rf ddr2.bld 
+rm -rf ddr2.ngd 
+rm -rf ddr2_ngdbuild.xrpt 
+rm -rf ddr2_map.map 
+rm -rf ddr2_map.mrp 
+rm -rf ddr2_map.ngm 
+rm -rf ddr2.pcf 
+rm -rf ddr2_map.ncd 
+rm -rf ddr2_map.xrpt 
+rm -rf ddr2_summary.xml 
+rm -rf ddr2_usage.xml 
+rm -rf ddr2.ncd 
+rm -rf ddr2.par 
+rm -rf ddr2.xpi 
+rm -rf ddr2.ptwx 
+rm -rf ddr2.pad 
+rm -rf ddr2.unroutes 
+rm -rf ddr2_pad.csv 
+rm -rf ddr2_pad.txt 
+rm -rf ddr2_par.xrpt 
+rm -rf ddr2.twx 
+rm -rf ddr2.bgn 
+rm -rf ddr2.twr 
+rm -rf ddr2.drc 
+rm -rf ddr2_bitgen.xwbt
+rm -rf ddr2.bit 
+
+# Files and folders generated by create ise
+rm -rf test_xdb
+rm -rf _xmsgs
+rm -rf test.gise
+rm -rf test.xise
+rm -rf test.xise
+
+# Files and folders generated by ISE through GUI mode
+rm -rf _ngo
+rm -rf xst
+rm -rf ddr2.lso 
+rm -rf ddr2.prj 
+rm -rf ddr2.xst 
+rm -rf ddr2.stx 
+rm -rf ddr2_prev_built.ngd 
+rm -rf test.ntrc_log 
+rm -rf ddr2_guide.ncd 
+rm -rf ddr2.cmd_log 
+rm -rf ddr2_summary.html 
+rm -rf ddr2.ut 
+rm -rf par_usage_statistics.html
+rm -rf usage_statistics_webtalk.html
+rm -rf webtalk.log
+rm -rf device_usage_statistics.html 
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/set_ise_prop.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/set_ise_prop.tcl
new file mode 100644
index 0000000..adcfe11
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/set_ise_prop.tcl
@@ -0,0 +1,90 @@
+project new test.xise
+
+project set "Device Family" "spartan6"
+
+project set "Device" "xc6slx45"
+
+project set "Package" "csg324"
+
+project set "Speed Grade" "-3"
+
+project set "Synthesis Tool" "XST (VHDL/Verilog)"
+
+project set "Simulator" "ISim (VHDL/Verilog)"
+
+xfile add "../rtl/ddr2.vhd"
+xfile add "../rtl/iodrp_controller.vhd"
+xfile add "../rtl/iodrp_mcb_controller.vhd"
+xfile add "../rtl/mcb_raw_wrapper.vhd"
+xfile add "../rtl/mcb_soft_calibration.vhd"
+xfile add "../rtl/mcb_soft_calibration_top.vhd"
+xfile add "../rtl/memc3_infrastructure.vhd"
+xfile add "../rtl/memc3_wrapper.vhd"
+
+xfile add "ddr2.ucf"
+
+
+project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
+project set "Safe Implementation" "No" -process "Synthesize - XST"
+project set "FSM Style" "LUT" -process "Synthesize - XST"
+project set "RAM Extraction" "True" -process "Synthesize - XST"
+project set "RAM Style" "Auto" -process "Synthesize - XST"
+project set "ROM Extraction" "True" -process "Synthesize - XST"
+project set "ROM Style" "Auto" -process "Synthesize - XST"
+project set "Resource Sharing" "True" -process "Synthesize - XST"
+project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST"
+project set "Register Balancing" "No" -process "Synthesize - XST"
+project set "Add I/O Buffers" "True" -process "Synthesize - XST"
+project set "Max Fanout" "500" -process "Synthesize - XST"
+project set "Number of Clock Buffers" "8" -process "Synthesize - XST"
+project set "Register Duplication" "True" -process "Synthesize - XST"
+project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST"
+project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
+project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
+project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
+project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
+project set "Equivalent Register Removal" "True" -process "Synthesize - XST"
+project set "Optimization Goal" "Speed" -process "Synthesize - XST"
+project set "Optimization Effort" "Normal" -process "Synthesize - XST"
+project set "Library Search Order" "../synth/ddr2.lso" -process "Synthesize - XST"
+project set "Keep Hierarchy" "Soft" -process "Synthesize - XST"
+project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
+project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
+project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
+project set "Read Cores" "True" -process "Synthesize - XST"
+project set "Write Timing Constraints" "False" -process "Synthesize - XST"
+project set "Cross Clock Analysis" "False" -process "Synthesize - XST"
+project set "Hierarchy Separator" "/" -process "Synthesize - XST"
+project set "Bus Delimiter" "<>" -process "Synthesize - XST"
+project set "Case" "Maintain" -process "Synthesize - XST"
+project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
+project set "Automatic BRAM Packing" "False" -process "Synthesize - XST"
+project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map
+
+project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
+
+project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing"
+
+project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File"
+project set "Create Binary Configuration File" "False" -process "Generate Programming File"
+project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File"
+project set "Configuration Rate" "6" -process "Generate Programming File"
+project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
+project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
+project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
+project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
+project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
+project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
+project set "Unused IOB Pins" "Float" -process "Generate Programming File"
+project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
+project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
+project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
+project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
+project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
+project set "Enable Internal Done Pipe" "False" -process "Generate Programming File"
+project set "Drive Done Pin High" "False" -process "Generate Programming File"
+project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
+
+project close
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/vio_coregen.xco b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/vio_coregen.xco
new file mode 100644
index 0000000..ec8adfb
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/vio_coregen.xco
@@ -0,0 +1,51 @@
+##############################################################
+#
+# Xilinx Core Generator version 11.2
+# Date: Fri Jun 12 05:42:56 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped  
+SET createndf = False
+SET designentry = vhdl
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Foundation_ISE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -3
+SET verilogsim = False
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
+# END Select
+# BEGIN Parameters
+CSET asynchronous_input_port_width=8
+CSET asynchronous_output_port_width=7
+CSET component_name=vio
+CSET enable_asynchronous_input_port=false
+CSET enable_asynchronous_output_port=true
+CSET enable_synchronous_input_port=false
+CSET enable_synchronous_output_port=false
+CSET invert_clock_input=false
+CSET synchronous_input_port_width=8
+CSET synchronous_output_port_width=8
+# END Parameters
+GENERATE
+# CRC: 66fe39ed
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd
new file mode 100644
index 0000000..6ffced2
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd
@@ -0,0 +1,822 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : 3.92
+--  \   \         Application        : MIG
+--  /   /         Filename           : ddr2.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:56 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+--Device           : Spartan-6
+--Design Name      : DDR/DDR2/DDR3/LPDDR 
+--Purpose          : This is the design top level. which instantiates top wrapper,
+--                   test bench top and infrastructure modules.
+--Reference        :
+--Revision History :
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+entity ddr2 is
+generic
+  (
+            C3_P0_MASK_SIZE           : integer := 4;
+          C3_P0_DATA_PORT_SIZE      : integer := 32;
+          C3_P1_MASK_SIZE           : integer := 4;
+          C3_P1_DATA_PORT_SIZE      : integer := 32;
+    C3_MEMCLK_PERIOD        : integer := 3000; 
+                                       -- Memory data transfer clock period.
+    C3_RST_ACT_LOW          : integer := 0; 
+                                       -- # = 1 for active low reset,
+                                       -- # = 0 for active high reset.
+    C3_INPUT_CLK_TYPE       : string := "SINGLE_ENDED"; 
+                                       -- input clock type DIFFERENTIAL or SINGLE_ENDED.
+    C3_CALIB_SOFT_IP        : string := "TRUE"; 
+                                       -- # = TRUE, Enables the soft calibration logic,
+                                       -- # = FALSE, Disables the soft calibration logic.
+    C3_SIMULATION           : string := "FALSE"; 
+                                       -- # = TRUE, Simulating the design. Useful to reduce the simulation time,
+                                       -- # = FALSE, Implementing the design.
+    DEBUG_EN                : integer := 0; 
+                                       -- # = 1, Enable debug signals/controls,
+                                       --   = 0, Disable debug signals/controls.
+    C3_MEM_ADDR_ORDER       : string := "BANK_ROW_COLUMN"; 
+                                       -- The order in which user address is provided to the memory controller,
+                                       -- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
+    C3_NUM_DQ_PINS          : integer := 16; 
+                                       -- External memory data width.
+    C3_MEM_ADDR_WIDTH       : integer := 13; 
+                                       -- External memory address width.
+    C3_MEM_BANKADDR_WIDTH   : integer := 3 
+                                       -- External memory bank address width.
+  );
+   
+  port
+  (
+
+   mcb3_dram_dq                            : inout  std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
+   mcb3_dram_a                             : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+   mcb3_dram_ba                            : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
+   mcb3_dram_ras_n                         : out std_logic;
+   mcb3_dram_cas_n                         : out std_logic;
+   mcb3_dram_we_n                          : out std_logic;
+   mcb3_dram_odt                           : out std_logic;
+   mcb3_dram_cke                           : out std_logic;
+   mcb3_dram_dm                            : out std_logic;
+   mcb3_dram_udqs                          : inout  std_logic;
+   mcb3_dram_udqs_n                        : inout  std_logic;
+   mcb3_rzq                                : inout  std_logic;
+   mcb3_zio                                : inout  std_logic;
+   mcb3_dram_udm                           : out std_logic;
+   c3_sys_clk                              : in  std_logic;
+   c3_sys_rst_i                            : in  std_logic;
+   c3_calib_done                           : out std_logic;
+   c3_clk0                                 : out std_logic;
+   c3_rst0                                 : out std_logic;
+   mcb3_dram_dqs                           : inout  std_logic;
+   mcb3_dram_dqs_n                         : inout  std_logic;
+   mcb3_dram_ck                            : out std_logic;
+   mcb3_dram_ck_n                          : out std_logic;
+   c3_p0_cmd_clk                           : in std_logic;
+   c3_p0_cmd_en                            : in std_logic;
+   c3_p0_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p0_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p0_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p0_cmd_empty                         : out std_logic;
+   c3_p0_cmd_full                          : out std_logic;
+   c3_p0_wr_clk                            : in std_logic;
+   c3_p0_wr_en                             : in std_logic;
+   c3_p0_wr_mask                           : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
+   c3_p0_wr_data                           : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+   c3_p0_wr_full                           : out std_logic;
+   c3_p0_wr_empty                          : out std_logic;
+   c3_p0_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p0_wr_underrun                       : out std_logic;
+   c3_p0_wr_error                          : out std_logic;
+   c3_p0_rd_clk                            : in std_logic;
+   c3_p0_rd_en                             : in std_logic;
+   c3_p0_rd_data                           : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+   c3_p0_rd_full                           : out std_logic;
+   c3_p0_rd_empty                          : out std_logic;
+   c3_p0_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p0_rd_overflow                       : out std_logic;
+   c3_p0_rd_error                          : out std_logic;
+   c3_p1_cmd_clk                           : in std_logic;
+   c3_p1_cmd_en                            : in std_logic;
+   c3_p1_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p1_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p1_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p1_cmd_empty                         : out std_logic;
+   c3_p1_cmd_full                          : out std_logic;
+   c3_p1_wr_clk                            : in std_logic;
+   c3_p1_wr_en                             : in std_logic;
+   c3_p1_wr_mask                           : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
+   c3_p1_wr_data                           : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+   c3_p1_wr_full                           : out std_logic;
+   c3_p1_wr_empty                          : out std_logic;
+   c3_p1_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p1_wr_underrun                       : out std_logic;
+   c3_p1_wr_error                          : out std_logic;
+   c3_p1_rd_clk                            : in std_logic;
+   c3_p1_rd_en                             : in std_logic;
+   c3_p1_rd_data                           : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+   c3_p1_rd_full                           : out std_logic;
+   c3_p1_rd_empty                          : out std_logic;
+   c3_p1_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p1_rd_overflow                       : out std_logic;
+   c3_p1_rd_error                          : out std_logic;
+   c3_p2_cmd_clk                           : in std_logic;
+   c3_p2_cmd_en                            : in std_logic;
+   c3_p2_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p2_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p2_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p2_cmd_empty                         : out std_logic;
+   c3_p2_cmd_full                          : out std_logic;
+   c3_p2_wr_clk                            : in std_logic;
+   c3_p2_wr_en                             : in std_logic;
+   c3_p2_wr_mask                           : in std_logic_vector(3 downto 0);
+   c3_p2_wr_data                           : in std_logic_vector(31 downto 0);
+   c3_p2_wr_full                           : out std_logic;
+   c3_p2_wr_empty                          : out std_logic;
+   c3_p2_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p2_wr_underrun                       : out std_logic;
+   c3_p2_wr_error                          : out std_logic;
+   c3_p2_rd_clk                            : in std_logic;
+   c3_p2_rd_en                             : in std_logic;
+   c3_p2_rd_data                           : out std_logic_vector(31 downto 0);
+   c3_p2_rd_full                           : out std_logic;
+   c3_p2_rd_empty                          : out std_logic;
+   c3_p2_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p2_rd_overflow                       : out std_logic;
+   c3_p2_rd_error                          : out std_logic;
+   c3_p3_cmd_clk                           : in std_logic;
+   c3_p3_cmd_en                            : in std_logic;
+   c3_p3_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p3_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p3_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p3_cmd_empty                         : out std_logic;
+   c3_p3_cmd_full                          : out std_logic;
+   c3_p3_wr_clk                            : in std_logic;
+   c3_p3_wr_en                             : in std_logic;
+   c3_p3_wr_mask                           : in std_logic_vector(3 downto 0);
+   c3_p3_wr_data                           : in std_logic_vector(31 downto 0);
+   c3_p3_wr_full                           : out std_logic;
+   c3_p3_wr_empty                          : out std_logic;
+   c3_p3_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p3_wr_underrun                       : out std_logic;
+   c3_p3_wr_error                          : out std_logic;
+   c3_p3_rd_clk                            : in std_logic;
+   c3_p3_rd_en                             : in std_logic;
+   c3_p3_rd_data                           : out std_logic_vector(31 downto 0);
+   c3_p3_rd_full                           : out std_logic;
+   c3_p3_rd_empty                          : out std_logic;
+   c3_p3_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p3_rd_overflow                       : out std_logic;
+   c3_p3_rd_error                          : out std_logic
+  );
+end ddr2;
+
+architecture arc of ddr2 is
+
+ 
+
+component memc3_infrastructure is
+    generic (
+      C_RST_ACT_LOW        : integer;
+      C_INPUT_CLK_TYPE     : string;
+      C_CLKOUT0_DIVIDE     : integer;
+      C_CLKOUT1_DIVIDE     : integer;
+      C_CLKOUT2_DIVIDE     : integer;
+      C_CLKOUT3_DIVIDE     : integer;
+      C_CLKFBOUT_MULT      : integer;
+      C_DIVCLK_DIVIDE      : integer;
+      C_INCLK_PERIOD       : integer
+
+      );
+    port (
+      sys_clk_p                              : in    std_logic;
+      sys_clk_n                              : in    std_logic;
+      sys_clk                                : in    std_logic;
+      sys_rst_i                              : in    std_logic;
+      clk0                                   : out   std_logic;
+      rst0                                   : out   std_logic;
+      async_rst                              : out   std_logic;
+      sysclk_2x                              : out   std_logic;
+      sysclk_2x_180                          : out   std_logic;
+      pll_ce_0                               : out   std_logic;
+      pll_ce_90                              : out   std_logic;
+      pll_lock                               : out   std_logic;
+      mcb_drp_clk                            : out   std_logic
+
+      );
+  end component;
+
+
+component memc3_wrapper is
+    generic (
+      C_MEMCLK_PERIOD      : integer;
+      C_CALIB_SOFT_IP      : string;
+      C_SIMULATION         : string;
+      C_P0_MASK_SIZE       : integer;
+      C_P0_DATA_PORT_SIZE   : integer;
+      C_P1_MASK_SIZE       : integer;
+      C_P1_DATA_PORT_SIZE   : integer;
+      C_ARB_NUM_TIME_SLOTS   : integer;
+      C_ARB_TIME_SLOT_0    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_1    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_2    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_3    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_4    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_5    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_6    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_7    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_8    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_9    : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_10   : bit_vector(11 downto 0);
+      C_ARB_TIME_SLOT_11   : bit_vector(11 downto 0);
+      C_MEM_TRAS           : integer;
+      C_MEM_TRCD           : integer;
+      C_MEM_TREFI          : integer;
+      C_MEM_TRFC           : integer;
+      C_MEM_TRP            : integer;
+      C_MEM_TWR            : integer;
+      C_MEM_TRTP           : integer;
+      C_MEM_TWTR           : integer;
+      C_MEM_ADDR_ORDER     : string;
+      C_NUM_DQ_PINS        : integer;
+      C_MEM_TYPE           : string;
+      C_MEM_DENSITY        : string;
+      C_MEM_BURST_LEN      : integer;
+      C_MEM_CAS_LATENCY    : integer;
+      C_MEM_ADDR_WIDTH     : integer;
+      C_MEM_BANKADDR_WIDTH   : integer;
+      C_MEM_NUM_COL_BITS   : integer;
+      C_MEM_DDR1_2_ODS     : string;
+      C_MEM_DDR2_RTT       : string;
+      C_MEM_DDR2_DIFF_DQS_EN   : string;
+      C_MEM_DDR2_3_PA_SR   : string;
+      C_MEM_DDR2_3_HIGH_TEMP_SR   : string;
+      C_MEM_DDR3_CAS_LATENCY   : integer;
+      C_MEM_DDR3_ODS       : string;
+      C_MEM_DDR3_RTT       : string;
+      C_MEM_DDR3_CAS_WR_LATENCY   : integer;
+      C_MEM_DDR3_AUTO_SR   : string;
+      C_MEM_DDR3_DYN_WRT_ODT   : string;
+      C_MEM_MOBILE_PA_SR   : string;
+      C_MEM_MDDR_ODS       : string;
+      C_MC_CALIB_BYPASS    : string;
+      C_MC_CALIBRATION_MODE   : string;
+      C_MC_CALIBRATION_DELAY   : string;
+      C_SKIP_IN_TERM_CAL   : integer;
+      C_SKIP_DYNAMIC_CAL   : integer;
+      C_LDQSP_TAP_DELAY_VAL   : integer;
+      C_LDQSN_TAP_DELAY_VAL   : integer;
+      C_UDQSP_TAP_DELAY_VAL   : integer;
+      C_UDQSN_TAP_DELAY_VAL   : integer;
+      C_DQ0_TAP_DELAY_VAL   : integer;
+      C_DQ1_TAP_DELAY_VAL   : integer;
+      C_DQ2_TAP_DELAY_VAL   : integer;
+      C_DQ3_TAP_DELAY_VAL   : integer;
+      C_DQ4_TAP_DELAY_VAL   : integer;
+      C_DQ5_TAP_DELAY_VAL   : integer;
+      C_DQ6_TAP_DELAY_VAL   : integer;
+      C_DQ7_TAP_DELAY_VAL   : integer;
+      C_DQ8_TAP_DELAY_VAL   : integer;
+      C_DQ9_TAP_DELAY_VAL   : integer;
+      C_DQ10_TAP_DELAY_VAL   : integer;
+      C_DQ11_TAP_DELAY_VAL   : integer;
+      C_DQ12_TAP_DELAY_VAL   : integer;
+      C_DQ13_TAP_DELAY_VAL   : integer;
+      C_DQ14_TAP_DELAY_VAL   : integer;
+      C_DQ15_TAP_DELAY_VAL   : integer
+      );
+    port (
+      mcb3_dram_dq                           : inout  std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
+      mcb3_dram_a                            : out  std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
+      mcb3_dram_ba                           : out  std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
+      mcb3_dram_ras_n                        : out  std_logic;
+      mcb3_dram_cas_n                        : out  std_logic;
+      mcb3_dram_we_n                         : out  std_logic;
+      mcb3_dram_odt                          : out  std_logic;
+      mcb3_dram_cke                          : out  std_logic;
+      mcb3_dram_dm                           : out  std_logic;
+      mcb3_dram_udqs                         : inout  std_logic;
+      mcb3_dram_udqs_n                       : inout  std_logic;
+      mcb3_rzq                               : inout  std_logic;
+      mcb3_zio                               : inout  std_logic;
+      mcb3_dram_udm                          : out  std_logic;
+      calib_done                             : out  std_logic;
+      async_rst                              : in  std_logic;
+      sysclk_2x                              : in  std_logic;
+      sysclk_2x_180                          : in  std_logic;
+      pll_ce_0                               : in  std_logic;
+      pll_ce_90                              : in  std_logic;
+      pll_lock                               : in  std_logic;
+      mcb_drp_clk                            : in  std_logic;
+      mcb3_dram_dqs                          : inout  std_logic;
+      mcb3_dram_dqs_n                        : inout  std_logic;
+      mcb3_dram_ck                           : out  std_logic;
+      mcb3_dram_ck_n                         : out  std_logic;
+      p0_cmd_clk                            : in std_logic;
+      p0_cmd_en                             : in std_logic;
+      p0_cmd_instr                          : in std_logic_vector(2 downto 0);
+      p0_cmd_bl                             : in std_logic_vector(5 downto 0);
+      p0_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
+      p0_cmd_empty                          : out std_logic;
+      p0_cmd_full                           : out std_logic;
+      p0_wr_clk                             : in std_logic;
+      p0_wr_en                              : in std_logic;
+      p0_wr_mask                            : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+      p0_wr_data                            : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_wr_full                            : out std_logic;
+      p0_wr_empty                           : out std_logic;
+      p0_wr_count                           : out std_logic_vector(6 downto 0);
+      p0_wr_underrun                        : out std_logic;
+      p0_wr_error                           : out std_logic;
+      p0_rd_clk                             : in std_logic;
+      p0_rd_en                              : in std_logic;
+      p0_rd_data                            : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_rd_full                            : out std_logic;
+      p0_rd_empty                           : out std_logic;
+      p0_rd_count                           : out std_logic_vector(6 downto 0);
+      p0_rd_overflow                        : out std_logic;
+      p0_rd_error                           : out std_logic;
+      p1_cmd_clk                            : in std_logic;
+      p1_cmd_en                             : in std_logic;
+      p1_cmd_instr                          : in std_logic_vector(2 downto 0);
+      p1_cmd_bl                             : in std_logic_vector(5 downto 0);
+      p1_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
+      p1_cmd_empty                          : out std_logic;
+      p1_cmd_full                           : out std_logic;
+      p1_wr_clk                             : in std_logic;
+      p1_wr_en                              : in std_logic;
+      p1_wr_mask                            : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+      p1_wr_data                            : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_wr_full                            : out std_logic;
+      p1_wr_empty                           : out std_logic;
+      p1_wr_count                           : out std_logic_vector(6 downto 0);
+      p1_wr_underrun                        : out std_logic;
+      p1_wr_error                           : out std_logic;
+      p1_rd_clk                             : in std_logic;
+      p1_rd_en                              : in std_logic;
+      p1_rd_data                            : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_rd_full                            : out std_logic;
+      p1_rd_empty                           : out std_logic;
+      p1_rd_count                           : out std_logic_vector(6 downto 0);
+      p1_rd_overflow                        : out std_logic;
+      p1_rd_error                           : out std_logic;
+      p2_cmd_clk                            : in std_logic;
+      p2_cmd_en                             : in std_logic;
+      p2_cmd_instr                          : in std_logic_vector(2 downto 0);
+      p2_cmd_bl                             : in std_logic_vector(5 downto 0);
+      p2_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
+      p2_cmd_empty                          : out std_logic;
+      p2_cmd_full                           : out std_logic;
+      p2_wr_clk                             : in std_logic;
+      p2_wr_en                              : in std_logic;
+      p2_wr_mask                            : in std_logic_vector(3 downto 0);
+      p2_wr_data                            : in std_logic_vector(31 downto 0);
+      p2_wr_full                            : out std_logic;
+      p2_wr_empty                           : out std_logic;
+      p2_wr_count                           : out std_logic_vector(6 downto 0);
+      p2_wr_underrun                        : out std_logic;
+      p2_wr_error                           : out std_logic;
+      p2_rd_clk                             : in std_logic;
+      p2_rd_en                              : in std_logic;
+      p2_rd_data                            : out std_logic_vector(31 downto 0);
+      p2_rd_full                            : out std_logic;
+      p2_rd_empty                           : out std_logic;
+      p2_rd_count                           : out std_logic_vector(6 downto 0);
+      p2_rd_overflow                        : out std_logic;
+      p2_rd_error                           : out std_logic;
+      p3_cmd_clk                            : in std_logic;
+      p3_cmd_en                             : in std_logic;
+      p3_cmd_instr                          : in std_logic_vector(2 downto 0);
+      p3_cmd_bl                             : in std_logic_vector(5 downto 0);
+      p3_cmd_byte_addr                      : in std_logic_vector(29 downto 0);
+      p3_cmd_empty                          : out std_logic;
+      p3_cmd_full                           : out std_logic;
+      p3_wr_clk                             : in std_logic;
+      p3_wr_en                              : in std_logic;
+      p3_wr_mask                            : in std_logic_vector(3 downto 0);
+      p3_wr_data                            : in std_logic_vector(31 downto 0);
+      p3_wr_full                            : out std_logic;
+      p3_wr_empty                           : out std_logic;
+      p3_wr_count                           : out std_logic_vector(6 downto 0);
+      p3_wr_underrun                        : out std_logic;
+      p3_wr_error                           : out std_logic;
+      p3_rd_clk                             : in std_logic;
+      p3_rd_en                              : in std_logic;
+      p3_rd_data                            : out std_logic_vector(31 downto 0);
+      p3_rd_full                            : out std_logic;
+      p3_rd_empty                           : out std_logic;
+      p3_rd_count                           : out std_logic_vector(6 downto 0);
+      p3_rd_overflow                        : out std_logic;
+      p3_rd_error                           : out std_logic;
+      selfrefresh_enter                     : in std_logic;
+      selfrefresh_mode                      : out std_logic
+
+      );
+  end component;
+
+
+
+
+
+
+   constant C3_CLKOUT0_DIVIDE       : integer := 1; 
+   constant C3_CLKOUT1_DIVIDE       : integer := 1; 
+   constant C3_CLKOUT2_DIVIDE       : integer := 6; 
+   constant C3_CLKOUT3_DIVIDE       : integer := 7; 
+   constant C3_CLKFBOUT_MULT        : integer := 20; 
+   constant C3_DIVCLK_DIVIDE        : integer := 3; 
+   constant C3_INCLK_PERIOD         : integer := 10000; --((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); 
+   constant C3_ARB_NUM_TIME_SLOTS   : integer := 12; 
+   constant C3_ARB_TIME_SLOT_0      : bit_vector(11 downto 0) := o"0124"; 
+   constant C3_ARB_TIME_SLOT_1      : bit_vector(11 downto 0) := o"1240"; 
+   constant C3_ARB_TIME_SLOT_2      : bit_vector(11 downto 0) := o"2401"; 
+   constant C3_ARB_TIME_SLOT_3      : bit_vector(11 downto 0) := o"4012"; 
+   constant C3_ARB_TIME_SLOT_4      : bit_vector(11 downto 0) := o"0124"; 
+   constant C3_ARB_TIME_SLOT_5      : bit_vector(11 downto 0) := o"1240"; 
+   constant C3_ARB_TIME_SLOT_6      : bit_vector(11 downto 0) := o"2401"; 
+   constant C3_ARB_TIME_SLOT_7      : bit_vector(11 downto 0) := o"4012"; 
+   constant C3_ARB_TIME_SLOT_8      : bit_vector(11 downto 0) := o"0124"; 
+   constant C3_ARB_TIME_SLOT_9      : bit_vector(11 downto 0) := o"1240"; 
+   constant C3_ARB_TIME_SLOT_10     : bit_vector(11 downto 0) := o"2401"; 
+   constant C3_ARB_TIME_SLOT_11     : bit_vector(11 downto 0) := o"4012"; 
+   constant C3_MEM_TRAS             : integer := 42500; 
+   constant C3_MEM_TRCD             : integer := 12500; 
+   constant C3_MEM_TREFI            : integer := 7800000; 
+   constant C3_MEM_TRFC             : integer := 127500; 
+   constant C3_MEM_TRP              : integer := 12500; 
+   constant C3_MEM_TWR              : integer := 15000; 
+   constant C3_MEM_TRTP             : integer := 7500; 
+   constant C3_MEM_TWTR             : integer := 7500; 
+   constant C3_MEM_TYPE             : string := "DDR2"; 
+   constant C3_MEM_DENSITY          : string := "1Gb"; 
+   constant C3_MEM_BURST_LEN        : integer := 4; 
+   constant C3_MEM_CAS_LATENCY      : integer := 5; 
+   constant C3_MEM_NUM_COL_BITS     : integer := 10; 
+   constant C3_MEM_DDR1_2_ODS       : string := "FULL"; 
+   constant C3_MEM_DDR2_RTT         : string := "50OHMS"; 
+   constant C3_MEM_DDR2_DIFF_DQS_EN  : string := "YES"; 
+   constant C3_MEM_DDR2_3_PA_SR     : string := "FULL"; 
+   constant C3_MEM_DDR2_3_HIGH_TEMP_SR  : string := "NORMAL"; 
+   constant C3_MEM_DDR3_CAS_LATENCY  : integer := 6; 
+   constant C3_MEM_DDR3_ODS         : string := "DIV6"; 
+   constant C3_MEM_DDR3_RTT         : string := "DIV2"; 
+   constant C3_MEM_DDR3_CAS_WR_LATENCY  : integer := 5; 
+   constant C3_MEM_DDR3_AUTO_SR     : string := "ENABLED"; 
+   constant C3_MEM_DDR3_DYN_WRT_ODT  : string := "OFF"; 
+   constant C3_MEM_MOBILE_PA_SR     : string := "FULL"; 
+   constant C3_MEM_MDDR_ODS         : string := "FULL"; 
+   constant C3_MC_CALIB_BYPASS      : string := "NO"; 
+   constant C3_MC_CALIBRATION_MODE  : string := "CALIBRATION"; 
+   constant C3_MC_CALIBRATION_DELAY  : string := "HALF"; 
+   constant C3_SKIP_IN_TERM_CAL     : integer := 0; 
+   constant C3_SKIP_DYNAMIC_CAL     : integer := 0; 
+   constant C3_LDQSP_TAP_DELAY_VAL  : integer := 0; 
+   constant C3_LDQSN_TAP_DELAY_VAL  : integer := 0; 
+   constant C3_UDQSP_TAP_DELAY_VAL  : integer := 0; 
+   constant C3_UDQSN_TAP_DELAY_VAL  : integer := 0; 
+   constant C3_DQ0_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ1_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ2_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ3_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ4_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ5_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ6_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ7_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ8_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ9_TAP_DELAY_VAL    : integer := 0; 
+   constant C3_DQ10_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ11_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ12_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ13_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ14_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_DQ15_TAP_DELAY_VAL   : integer := 0; 
+   constant C3_SMALL_DEVICE         : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
+                                                         -- as most of them cannot fit the complete example design when the
+                                                         -- Chip scope modules are enabled
+
+  signal  c3_sys_clk_p                             : std_logic;
+  signal  c3_sys_clk_n                             : std_logic;
+  signal  c3_async_rst                             : std_logic;
+  signal  c3_sysclk_2x                             : std_logic;
+  signal  c3_sysclk_2x_180                         : std_logic;
+  signal  c3_pll_ce_0                              : std_logic;
+  signal  c3_pll_ce_90                             : std_logic;
+  signal  c3_pll_lock                              : std_logic;
+  signal  c3_mcb_drp_clk                           : std_logic;
+  signal  c3_cmp_error                             : std_logic;
+  signal  c3_cmp_data_valid                        : std_logic;
+  signal  c3_vio_modify_enable                     : std_logic;
+  signal  c3_error_status                          : std_logic_vector(127 downto 0);
+  signal  c3_vio_data_mode_value                   : std_logic_vector(2 downto 0);
+  signal  c3_vio_addr_mode_value                   : std_logic_vector(2 downto 0);
+  signal  c3_cmp_data                              : std_logic_vector(31 downto 0);
+  signal  c3_selfrefresh_enter                     : std_logic;
+  signal  c3_selfrefresh_mode                      : std_logic;
+
+
+
+begin
+ 
+
+c3_sys_clk_p <= '0';
+c3_sys_clk_n <= '0';
+c3_selfrefresh_enter <= '0';
+memc3_infrastructure_inst : memc3_infrastructure
+
+generic map
+ (
+   C_RST_ACT_LOW                     => C3_RST_ACT_LOW,
+   C_INPUT_CLK_TYPE                  => C3_INPUT_CLK_TYPE,
+   C_CLKOUT0_DIVIDE                  => C3_CLKOUT0_DIVIDE,
+   C_CLKOUT1_DIVIDE                  => C3_CLKOUT1_DIVIDE,
+   C_CLKOUT2_DIVIDE                  => C3_CLKOUT2_DIVIDE,
+   C_CLKOUT3_DIVIDE                  => C3_CLKOUT3_DIVIDE,
+   C_CLKFBOUT_MULT                   => C3_CLKFBOUT_MULT,
+   C_DIVCLK_DIVIDE                   => C3_DIVCLK_DIVIDE,
+   C_INCLK_PERIOD                    => C3_INCLK_PERIOD
+   )
+port map
+ (
+   sys_clk_p                       => c3_sys_clk_p,
+   sys_clk_n                       => c3_sys_clk_n,
+   sys_clk                         => c3_sys_clk,
+   sys_rst_i                       => c3_sys_rst_i,
+   clk0                            => c3_clk0,
+   rst0                            => c3_rst0,
+   async_rst                       => c3_async_rst,
+   sysclk_2x                       => c3_sysclk_2x,
+   sysclk_2x_180                   => c3_sysclk_2x_180,
+   pll_ce_0                        => c3_pll_ce_0,
+   pll_ce_90                       => c3_pll_ce_90,
+   pll_lock                        => c3_pll_lock,
+   mcb_drp_clk                     => c3_mcb_drp_clk
+   );
+
+
+-- wrapper instantiation
+ memc3_wrapper_inst : memc3_wrapper
+
+generic map
+ (
+   C_MEMCLK_PERIOD                   => C3_MEMCLK_PERIOD,
+   C_CALIB_SOFT_IP                   => C3_CALIB_SOFT_IP,
+   C_SIMULATION                      => C3_SIMULATION,
+   C_P0_MASK_SIZE                    => C3_P0_MASK_SIZE,
+   C_P0_DATA_PORT_SIZE               => C3_P0_DATA_PORT_SIZE,
+   C_P1_MASK_SIZE                    => C3_P1_MASK_SIZE,
+   C_P1_DATA_PORT_SIZE               => C3_P1_DATA_PORT_SIZE,
+   C_ARB_NUM_TIME_SLOTS              => C3_ARB_NUM_TIME_SLOTS,
+   C_ARB_TIME_SLOT_0                 => C3_ARB_TIME_SLOT_0,
+   C_ARB_TIME_SLOT_1                 => C3_ARB_TIME_SLOT_1,
+   C_ARB_TIME_SLOT_2                 => C3_ARB_TIME_SLOT_2,
+   C_ARB_TIME_SLOT_3                 => C3_ARB_TIME_SLOT_3,
+   C_ARB_TIME_SLOT_4                 => C3_ARB_TIME_SLOT_4,
+   C_ARB_TIME_SLOT_5                 => C3_ARB_TIME_SLOT_5,
+   C_ARB_TIME_SLOT_6                 => C3_ARB_TIME_SLOT_6,
+   C_ARB_TIME_SLOT_7                 => C3_ARB_TIME_SLOT_7,
+   C_ARB_TIME_SLOT_8                 => C3_ARB_TIME_SLOT_8,
+   C_ARB_TIME_SLOT_9                 => C3_ARB_TIME_SLOT_9,
+   C_ARB_TIME_SLOT_10                => C3_ARB_TIME_SLOT_10,
+   C_ARB_TIME_SLOT_11                => C3_ARB_TIME_SLOT_11,
+   C_MEM_TRAS                        => C3_MEM_TRAS,
+   C_MEM_TRCD                        => C3_MEM_TRCD,
+   C_MEM_TREFI                       => C3_MEM_TREFI,
+   C_MEM_TRFC                        => C3_MEM_TRFC,
+   C_MEM_TRP                         => C3_MEM_TRP,
+   C_MEM_TWR                         => C3_MEM_TWR,
+   C_MEM_TRTP                        => C3_MEM_TRTP,
+   C_MEM_TWTR                        => C3_MEM_TWTR,
+   C_MEM_ADDR_ORDER                  => C3_MEM_ADDR_ORDER,
+   C_NUM_DQ_PINS                     => C3_NUM_DQ_PINS,
+   C_MEM_TYPE                        => C3_MEM_TYPE,
+   C_MEM_DENSITY                     => C3_MEM_DENSITY,
+   C_MEM_BURST_LEN                   => C3_MEM_BURST_LEN,
+   C_MEM_CAS_LATENCY                 => C3_MEM_CAS_LATENCY,
+   C_MEM_ADDR_WIDTH                  => C3_MEM_ADDR_WIDTH,
+   C_MEM_BANKADDR_WIDTH              => C3_MEM_BANKADDR_WIDTH,
+   C_MEM_NUM_COL_BITS                => C3_MEM_NUM_COL_BITS,
+   C_MEM_DDR1_2_ODS                  => C3_MEM_DDR1_2_ODS,
+   C_MEM_DDR2_RTT                    => C3_MEM_DDR2_RTT,
+   C_MEM_DDR2_DIFF_DQS_EN            => C3_MEM_DDR2_DIFF_DQS_EN,
+   C_MEM_DDR2_3_PA_SR                => C3_MEM_DDR2_3_PA_SR,
+   C_MEM_DDR2_3_HIGH_TEMP_SR         => C3_MEM_DDR2_3_HIGH_TEMP_SR,
+   C_MEM_DDR3_CAS_LATENCY            => C3_MEM_DDR3_CAS_LATENCY,
+   C_MEM_DDR3_ODS                    => C3_MEM_DDR3_ODS,
+   C_MEM_DDR3_RTT                    => C3_MEM_DDR3_RTT,
+   C_MEM_DDR3_CAS_WR_LATENCY         => C3_MEM_DDR3_CAS_WR_LATENCY,
+   C_MEM_DDR3_AUTO_SR                => C3_MEM_DDR3_AUTO_SR,
+   C_MEM_DDR3_DYN_WRT_ODT            => C3_MEM_DDR3_DYN_WRT_ODT,
+   C_MEM_MOBILE_PA_SR                => C3_MEM_MOBILE_PA_SR,
+   C_MEM_MDDR_ODS                    => C3_MEM_MDDR_ODS,
+   C_MC_CALIB_BYPASS                 => C3_MC_CALIB_BYPASS,
+   C_MC_CALIBRATION_MODE             => C3_MC_CALIBRATION_MODE,
+   C_MC_CALIBRATION_DELAY            => C3_MC_CALIBRATION_DELAY,
+   C_SKIP_IN_TERM_CAL                => C3_SKIP_IN_TERM_CAL,
+   C_SKIP_DYNAMIC_CAL                => C3_SKIP_DYNAMIC_CAL,
+   C_LDQSP_TAP_DELAY_VAL             => C3_LDQSP_TAP_DELAY_VAL,
+   C_LDQSN_TAP_DELAY_VAL             => C3_LDQSN_TAP_DELAY_VAL,
+   C_UDQSP_TAP_DELAY_VAL             => C3_UDQSP_TAP_DELAY_VAL,
+   C_UDQSN_TAP_DELAY_VAL             => C3_UDQSN_TAP_DELAY_VAL,
+   C_DQ0_TAP_DELAY_VAL               => C3_DQ0_TAP_DELAY_VAL,
+   C_DQ1_TAP_DELAY_VAL               => C3_DQ1_TAP_DELAY_VAL,
+   C_DQ2_TAP_DELAY_VAL               => C3_DQ2_TAP_DELAY_VAL,
+   C_DQ3_TAP_DELAY_VAL               => C3_DQ3_TAP_DELAY_VAL,
+   C_DQ4_TAP_DELAY_VAL               => C3_DQ4_TAP_DELAY_VAL,
+   C_DQ5_TAP_DELAY_VAL               => C3_DQ5_TAP_DELAY_VAL,
+   C_DQ6_TAP_DELAY_VAL               => C3_DQ6_TAP_DELAY_VAL,
+   C_DQ7_TAP_DELAY_VAL               => C3_DQ7_TAP_DELAY_VAL,
+   C_DQ8_TAP_DELAY_VAL               => C3_DQ8_TAP_DELAY_VAL,
+   C_DQ9_TAP_DELAY_VAL               => C3_DQ9_TAP_DELAY_VAL,
+   C_DQ10_TAP_DELAY_VAL              => C3_DQ10_TAP_DELAY_VAL,
+   C_DQ11_TAP_DELAY_VAL              => C3_DQ11_TAP_DELAY_VAL,
+   C_DQ12_TAP_DELAY_VAL              => C3_DQ12_TAP_DELAY_VAL,
+   C_DQ13_TAP_DELAY_VAL              => C3_DQ13_TAP_DELAY_VAL,
+   C_DQ14_TAP_DELAY_VAL              => C3_DQ14_TAP_DELAY_VAL,
+   C_DQ15_TAP_DELAY_VAL              => C3_DQ15_TAP_DELAY_VAL
+   )
+port map
+(
+   mcb3_dram_dq                         => mcb3_dram_dq,
+   mcb3_dram_a                          => mcb3_dram_a,
+   mcb3_dram_ba                         => mcb3_dram_ba,
+   mcb3_dram_ras_n                      => mcb3_dram_ras_n,
+   mcb3_dram_cas_n                      => mcb3_dram_cas_n,
+   mcb3_dram_we_n                       => mcb3_dram_we_n,
+   mcb3_dram_odt                        => mcb3_dram_odt,
+   mcb3_dram_cke                        => mcb3_dram_cke,
+   mcb3_dram_dm                         => mcb3_dram_dm,
+   mcb3_dram_udqs                       => mcb3_dram_udqs,
+   mcb3_dram_udqs_n                     => mcb3_dram_udqs_n,
+   mcb3_rzq                             => mcb3_rzq,
+   mcb3_zio                             => mcb3_zio,
+   mcb3_dram_udm                        => mcb3_dram_udm,
+   calib_done                      => c3_calib_done,
+   async_rst                       => c3_async_rst,
+   sysclk_2x                       => c3_sysclk_2x,
+   sysclk_2x_180                   => c3_sysclk_2x_180,
+   pll_ce_0                        => c3_pll_ce_0,
+   pll_ce_90                       => c3_pll_ce_90,
+   pll_lock                        => c3_pll_lock,
+   mcb_drp_clk                     => c3_mcb_drp_clk,
+   mcb3_dram_dqs                        => mcb3_dram_dqs,
+   mcb3_dram_dqs_n                      => mcb3_dram_dqs_n,
+   mcb3_dram_ck                         => mcb3_dram_ck,
+   mcb3_dram_ck_n                       => mcb3_dram_ck_n,
+   p0_cmd_clk                           =>  c3_p0_cmd_clk,
+   p0_cmd_en                            =>  c3_p0_cmd_en,
+   p0_cmd_instr                         =>  c3_p0_cmd_instr,
+   p0_cmd_bl                            =>  c3_p0_cmd_bl,
+   p0_cmd_byte_addr                     =>  c3_p0_cmd_byte_addr,
+   p0_cmd_empty                         =>  c3_p0_cmd_empty,
+   p0_cmd_full                          =>  c3_p0_cmd_full,
+   p0_wr_clk                            =>  c3_p0_wr_clk,
+   p0_wr_en                             =>  c3_p0_wr_en,
+   p0_wr_mask                           =>  c3_p0_wr_mask,
+   p0_wr_data                           =>  c3_p0_wr_data,
+   p0_wr_full                           =>  c3_p0_wr_full,
+   p0_wr_empty                          =>  c3_p0_wr_empty,
+   p0_wr_count                          =>  c3_p0_wr_count,
+   p0_wr_underrun                       =>  c3_p0_wr_underrun,
+   p0_wr_error                          =>  c3_p0_wr_error,
+   p0_rd_clk                            =>  c3_p0_rd_clk,
+   p0_rd_en                             =>  c3_p0_rd_en,
+   p0_rd_data                           =>  c3_p0_rd_data,
+   p0_rd_full                           =>  c3_p0_rd_full,
+   p0_rd_empty                          =>  c3_p0_rd_empty,
+   p0_rd_count                          =>  c3_p0_rd_count,
+   p0_rd_overflow                       =>  c3_p0_rd_overflow,
+   p0_rd_error                          =>  c3_p0_rd_error,
+   p1_cmd_clk                           =>  c3_p1_cmd_clk,
+   p1_cmd_en                            =>  c3_p1_cmd_en,
+   p1_cmd_instr                         =>  c3_p1_cmd_instr,
+   p1_cmd_bl                            =>  c3_p1_cmd_bl,
+   p1_cmd_byte_addr                     =>  c3_p1_cmd_byte_addr,
+   p1_cmd_empty                         =>  c3_p1_cmd_empty,
+   p1_cmd_full                          =>  c3_p1_cmd_full,
+   p1_wr_clk                            =>  c3_p1_wr_clk,
+   p1_wr_en                             =>  c3_p1_wr_en,
+   p1_wr_mask                           =>  c3_p1_wr_mask,
+   p1_wr_data                           =>  c3_p1_wr_data,
+   p1_wr_full                           =>  c3_p1_wr_full,
+   p1_wr_empty                          =>  c3_p1_wr_empty,
+   p1_wr_count                          =>  c3_p1_wr_count,
+   p1_wr_underrun                       =>  c3_p1_wr_underrun,
+   p1_wr_error                          =>  c3_p1_wr_error,
+   p1_rd_clk                            =>  c3_p1_rd_clk,
+   p1_rd_en                             =>  c3_p1_rd_en,
+   p1_rd_data                           =>  c3_p1_rd_data,
+   p1_rd_full                           =>  c3_p1_rd_full,
+   p1_rd_empty                          =>  c3_p1_rd_empty,
+   p1_rd_count                          =>  c3_p1_rd_count,
+   p1_rd_overflow                       =>  c3_p1_rd_overflow,
+   p1_rd_error                          =>  c3_p1_rd_error,
+   p2_cmd_clk                           =>  c3_p2_cmd_clk,
+   p2_cmd_en                            =>  c3_p2_cmd_en,
+   p2_cmd_instr                         =>  c3_p2_cmd_instr,
+   p2_cmd_bl                            =>  c3_p2_cmd_bl,
+   p2_cmd_byte_addr                     =>  c3_p2_cmd_byte_addr,
+   p2_cmd_empty                         =>  c3_p2_cmd_empty,
+   p2_cmd_full                          =>  c3_p2_cmd_full,
+   p2_wr_clk                            =>  c3_p2_wr_clk,
+   p2_wr_en                             =>  c3_p2_wr_en,
+   p2_wr_mask                           =>  c3_p2_wr_mask,
+   p2_wr_data                           =>  c3_p2_wr_data,
+   p2_wr_full                           =>  c3_p2_wr_full,
+   p2_wr_empty                          =>  c3_p2_wr_empty,
+   p2_wr_count                          =>  c3_p2_wr_count,
+   p2_wr_underrun                       =>  c3_p2_wr_underrun,
+   p2_wr_error                          =>  c3_p2_wr_error,
+   p2_rd_clk                            =>  c3_p2_rd_clk,
+   p2_rd_en                             =>  c3_p2_rd_en,
+   p2_rd_data                           =>  c3_p2_rd_data,
+   p2_rd_full                           =>  c3_p2_rd_full,
+   p2_rd_empty                          =>  c3_p2_rd_empty,
+   p2_rd_count                          =>  c3_p2_rd_count,
+   p2_rd_overflow                       =>  c3_p2_rd_overflow,
+   p2_rd_error                          =>  c3_p2_rd_error,
+   p3_cmd_clk                           =>  c3_p3_cmd_clk,
+   p3_cmd_en                            =>  c3_p3_cmd_en,
+   p3_cmd_instr                         =>  c3_p3_cmd_instr,
+   p3_cmd_bl                            =>  c3_p3_cmd_bl,
+   p3_cmd_byte_addr                     =>  c3_p3_cmd_byte_addr,
+   p3_cmd_empty                         =>  c3_p3_cmd_empty,
+   p3_cmd_full                          =>  c3_p3_cmd_full,
+   p3_wr_clk                            =>  c3_p3_wr_clk,
+   p3_wr_en                             =>  c3_p3_wr_en,
+   p3_wr_mask                           =>  c3_p3_wr_mask,
+   p3_wr_data                           =>  c3_p3_wr_data,
+   p3_wr_full                           =>  c3_p3_wr_full,
+   p3_wr_empty                          =>  c3_p3_wr_empty,
+   p3_wr_count                          =>  c3_p3_wr_count,
+   p3_wr_underrun                       =>  c3_p3_wr_underrun,
+   p3_wr_error                          =>  c3_p3_wr_error,
+   p3_rd_clk                            =>  c3_p3_rd_clk,
+   p3_rd_en                             =>  c3_p3_rd_en,
+   p3_rd_data                           =>  c3_p3_rd_data,
+   p3_rd_full                           =>  c3_p3_rd_full,
+   p3_rd_empty                          =>  c3_p3_rd_empty,
+   p3_rd_count                          =>  c3_p3_rd_count,
+   p3_rd_overflow                       =>  c3_p3_rd_overflow,
+   p3_rd_error                          =>  c3_p3_rd_error,
+   selfrefresh_enter                    =>  c3_selfrefresh_enter,
+   selfrefresh_mode                     =>  c3_selfrefresh_mode
+);
+
+ 
+ 
+  
+
+ end  arc;
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_controller.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_controller.vhd
new file mode 100755
index 0000000..f0a4b52
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_controller.vhd
@@ -0,0 +1,372 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: iodrp_controller.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:25 $
+-- \   \  /  \    Date Created: Mon Feb 9 2009
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR
+--Purpose:  Xilinx reference design for IODRP controller for v0.9 device
+--
+--Reference:
+--
+--    Revision: Date:       Comment
+--    1.0:      02/06/09:   Initial version for MIG wrapper.
+--    1.1:      02/01/09:   updates to indentations.
+--    1.2:      02/12/09:   changed non-blocking assignments to blocking ones
+--                          for state machine always block.  Also, assigned
+--                          intial value to load_shift_n to avoid latch
+-- End Revision
+--*******************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+
+entity iodrp_controller is
+      --output to IODRP SDI pin
+      --input from IODRP SDO pin
+      
+      -- Register where memcell_address is captured during the READY state
+      -- Register which stores the write data until it is ready to be shifted out
+      -- The shift register which shifts out SDO and shifts in SDI.
+      -- This register is loaded before the address or data phase, but continues
+      -- to shift for a writeback of read data
+      -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
+      -- The signal which indicates where the shift_through_reg should load from.  0 -> data_reg  1 -> memcell_addr_reg
+      -- The counter for which bit is being shifted during address or data phase
+      -- This is set after the first address phase has executed
+      
+      --  (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate;
+      
+      -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
+      -- added so that DRP_SDI output is only active when DRP_CS is active
+      
+   port (
+      memcell_address    : in std_logic_vector(7 downto 0);
+      write_data         : in std_logic_vector(7 downto 0);
+      read_data          : out std_logic_vector(7 downto 0);
+      rd_not_write       : in std_logic;
+      cmd_valid          : in std_logic;
+      rdy_busy_n         : out std_logic;
+      use_broadcast      : in std_logic;
+      sync_rst           : in std_logic;
+      DRP_CLK            : in std_logic;
+      DRP_CS             : out std_logic;
+      DRP_SDI            : out std_logic;
+      DRP_ADD            : out std_logic;
+      DRP_BKST           : out std_logic;
+      DRP_SDO            : in std_logic
+   );
+end entity iodrp_controller;
+
+architecture trans of iodrp_controller is
+
+
+     constant READY              : std_logic_vector(2 downto 0) := "000";
+     constant DECIDE             : std_logic_vector(2 downto 0) := "001";
+     constant ADDR_PHASE         : std_logic_vector(2 downto 0) := "010";
+     constant ADDR_TO_DATA_GAP   : std_logic_vector(2 downto 0) := "011";
+     constant ADDR_TO_DATA_GAP2  : std_logic_vector(2 downto 0) := "100";
+     constant ADDR_TO_DATA_GAP3  : std_logic_vector(2 downto 0) := "101";
+     constant DATA_PHASE         : std_logic_vector(2 downto 0) := "110";
+     constant ALMOST_READY       : std_logic_vector(2 downto 0) := "111";
+      
+     constant IOI_DQ0            : std_logic_vector(4 downto 0) := "00001"; 
+     constant IOI_DQ1            : std_logic_vector(4 downto 0) := "00000"; 
+     constant IOI_DQ2            : std_logic_vector(4 downto 0) := "00011"; 
+     constant IOI_DQ3            : std_logic_vector(4 downto 0) := "00010"; 
+     constant IOI_DQ4            : std_logic_vector(4 downto 0) := "00101"; 
+     constant IOI_DQ5            : std_logic_vector(4 downto 0) := "00100"; 
+     constant IOI_DQ6            : std_logic_vector(4 downto 0) := "00111"; 
+     constant IOI_DQ7            : std_logic_vector(4 downto 0) := "00110"; 
+     constant IOI_DQ8            : std_logic_vector(4 downto 0) := "01001"; 
+     constant IOI_DQ9            : std_logic_vector(4 downto 0) := "01000"; 
+     constant IOI_DQ10           : std_logic_vector(4 downto 0) := "01011"; 
+     constant IOI_DQ11           : std_logic_vector(4 downto 0) := "01010"; 
+     constant IOI_DQ12           : std_logic_vector(4 downto 0) := "01101"; 
+     constant IOI_DQ13           : std_logic_vector(4 downto 0) := "01100"; 
+     constant IOI_DQ14           : std_logic_vector(4 downto 0) := "01111"; 
+     constant IOI_DQ15           : std_logic_vector(4 downto 0) := "01110"; 
+     constant IOI_UDQS_CLK       : std_logic_vector(4 downto 0) := "11101"; 
+     constant IOI_UDQS_PIN       : std_logic_vector(4 downto 0) := "11100"; 
+     constant IOI_LDQS_CLK       : std_logic_vector(4 downto 0) := "11111"; 
+     constant IOI_LDQS_PIN       : std_logic_vector(4 downto 0) := "11110"; 
+
+
+
+
+   signal memcell_addr_reg  : std_logic_vector(7 downto 0);
+   signal data_reg          : std_logic_vector(7 downto 0);
+   signal shift_through_reg : std_logic_vector(7 downto 0);
+   signal load_shift_n      : std_logic;
+   signal addr_data_sel_n   : std_logic;
+   signal bit_cnt           : std_logic_vector(2 downto 0);
+   signal rd_not_write_reg  : std_logic;
+   signal AddressPhase      : std_logic;
+   signal capture_read_data : std_logic;
+   signal state             : std_logic_vector(2 downto 0);
+   signal nextstate         : std_logic_vector(2 downto 0);
+   signal data_out_mux      : std_logic_vector(7 downto 0);
+   signal DRP_SDI_pre       : std_logic;
+
+   signal ALMOST_READY_ST   : std_logic;
+   signal ADDR_PHASE_ST     : std_logic;
+   signal BIT_CNT7          : std_logic;
+   signal ADDR_PHASE_ST1     : std_logic;
+   signal DATA_PHASE_ST     : std_logic;
+
+   signal state_ascii       : std_logic_vector(32 * 8 - 1 downto 0);
+begin
+   --synthesis translate_off
+   
+--   process (state)
+--   begin
+--      case state is
+--         when READY =>
+--            state_ascii <= "READY";
+--         when DECIDE =>
+--            state_ascii <= "DECIDE";
+--         when ADDR_PHASE =>
+--            state_ascii <= "ADDR_PHASE";
+--         when ADDR_TO_DATA_GAP =>
+--            state_ascii <= "ADDR_TO_DATA_GAP";
+--         when ADDR_TO_DATA_GAP2 =>
+--            state_ascii <= "ADDR_TO_DATA_GAP2";
+--         when ADDR_TO_DATA_GAP3 =>
+--            state_ascii <= "ADDR_TO_DATA_GAP3";
+--         when DATA_PHASE =>
+--            state_ascii <= "DATA_PHASE";
+--         when ALMOST_READY =>		-- case(state)
+--            state_ascii <= "ALMOST_READY";
+--         when others =>
+--            null;
+--      end case;
+--   end process;
+   
+   --synthesis translate_on
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (state = READY) then
+            memcell_addr_reg <= memcell_address;
+            data_reg <= write_data;
+            rd_not_write_reg <= rd_not_write;
+         end if;
+      end if;
+   end process;
+   
+   
+   rdy_busy_n <= '1' when (state = READY) else '0';
+   
+   data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else
+                   data_reg;
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            shift_through_reg <= "00000000";
+         else
+            if (load_shift_n = '1') then		--Assume the shifter is either loading or shifting, bit 0 is shifted out first
+               shift_through_reg <= data_out_mux;
+            else
+               shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1));
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
+            bit_cnt <= bit_cnt + "001";
+         else
+            bit_cnt <= "000";
+         end if;
+      end if;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            --     capture_read_data <= 1'b0;
+            read_data <= "00000000";
+         else
+            --       capture_read_data <= (state == DATA_PHASE);
+            --       if(capture_read_data)
+            if (state = ALMOST_READY) then
+               --      else
+               --        read_data <= read_data;
+               read_data <= shift_through_reg;
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0';
+   ADDR_PHASE_ST   <= '1' when state = ADDR_PHASE else '0';
+   BIT_CNT7         <= '1' when bit_cnt = "111" else '0';
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            AddressPhase <= '0';
+         else
+            if (AddressPhase = '1') then
+               -- Keep it set until we finish the cycle
+               AddressPhase <= AddressPhase and (not ALMOST_READY_ST);
+            else
+               -- set the address phase when ever we finish the address phase
+               AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
+            end if;
+         end if;
+      end if;
+   end process;
+   
+ADDR_PHASE_ST1 <= '1' when  nextstate = ADDR_PHASE else '0';
+DATA_PHASE_ST <= '1' when  nextstate = DATA_PHASE else '0';
+
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         DRP_ADD <= ADDR_PHASE_ST1;
+         DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
+         if (state = READY) then
+            DRP_BKST <= use_broadcast;
+         end if;
+      end if;
+   end process;
+   
+   
+   --  assign DRP_SDI_pre  = (DRP_CS)? shift_through_reg[0] : 1'b0;  //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
+   --  assign DRP_SDI      = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
+   DRP_SDI <= shift_through_reg(0);		-- The new read method only requires that we shift out the address and the write data
+   
+   process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
+   begin
+      addr_data_sel_n <= '0';
+      load_shift_n <= '0';
+      case state is
+         when READY =>
+            if (cmd_valid = '1') then
+               nextstate <= DECIDE;
+            else
+               nextstate <= READY;
+            end if;
+         when DECIDE =>
+            load_shift_n <= '1';
+            addr_data_sel_n <= '1';
+            nextstate <= ADDR_PHASE;
+         -- After the second pass go to end of statemachine
+         -- execute a second address phase for the read access.
+         when ADDR_PHASE =>
+            if (BIT_CNT7 = '1') then
+               if (rd_not_write_reg = '1') then
+                  if (AddressPhase = '1') then
+                     nextstate <= ALMOST_READY;
+                  else
+                     nextstate <= DECIDE;
+                  end if;
+               else
+                  nextstate <= ADDR_TO_DATA_GAP;
+               end if;
+            else
+               nextstate <= ADDR_PHASE;
+            end if;
+         when ADDR_TO_DATA_GAP =>
+            load_shift_n <= '1';
+            nextstate <= ADDR_TO_DATA_GAP2;
+         when ADDR_TO_DATA_GAP2 =>
+            load_shift_n <= '1';
+            nextstate <= ADDR_TO_DATA_GAP3;
+         when ADDR_TO_DATA_GAP3 =>
+            load_shift_n <= '1';
+            nextstate <= DATA_PHASE;
+         when DATA_PHASE =>
+            if (BIT_CNT7 = '1') then
+               nextstate <= ALMOST_READY;
+            else
+               nextstate <= DATA_PHASE;
+            end if;
+         when ALMOST_READY =>
+            nextstate <= READY;
+         when others =>
+            nextstate <= READY;
+      end case;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            state <= READY;
+         else
+            state <= nextstate;
+         end if;
+      end if;
+   end process;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_mcb_controller.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_mcb_controller.vhd
new file mode 100755
index 0000000..22451be
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_mcb_controller.vhd
@@ -0,0 +1,517 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: iodrp_mcb_controller.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:25 $
+-- \   \  /  \    Date Created: Mon Feb 9 2009
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR
+--Purpose:  Xilinx reference design for IODRP controller for v0.9 device
+--
+--Reference:
+--
+--    Revision: Date:       Comment
+--    1.0:      03/19/09:   Initial version for IODRP_MCB read operations.
+--    1.1:      04/03/09:   SLH - Added left shift for certain IOI's   
+--    1.2:      02/14/11:   Change FSM encoding from one-hot to gray to match Verilog version.
+-- End Revision
+--*******************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+
+entity iodrp_mcb_controller is
+      --output to IODRP SDI pin
+      --input from IODRP SDO pin
+      
+      -- Register where memcell_address is captured during the READY state
+      -- Register which stores the write data until it is ready to be shifted out
+      -- The shift register which shifts out SDO and shifts in SDI.
+      --    This register is loaded before the address or data phase, but continues to shift for a writeback of read data
+      -- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
+      -- The signal which indicates where the shift_through_reg should load from.  0 -> data_reg  1 -> memcell_addr_reg
+      -- The counter for which bit is being shifted during address or data phase
+      -- This is set after the first address phase has executed
+      
+      -- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
+      --added so that DRP_SDI output is only active when DRP_CS is active
+   port (
+      memcell_address    : in std_logic_vector(7 downto 0);
+      write_data         : in std_logic_vector(7 downto 0);
+      read_data          : out std_logic_vector(7 downto 0);
+      rd_not_write       : in std_logic;
+      cmd_valid          : in std_logic;
+      rdy_busy_n         : out std_logic;
+      use_broadcast      : in std_logic;
+      drp_ioi_addr       : in std_logic_vector(4 downto 0);
+      sync_rst           : in std_logic;
+      DRP_CLK            : in std_logic;
+      DRP_CS             : out std_logic;
+      DRP_SDI            : out std_logic;
+      DRP_ADD            : out std_logic;
+      DRP_BKST           : out std_logic;
+      DRP_SDO            : in std_logic;
+      MCB_UIREAD         : out std_logic
+   );
+end entity iodrp_mcb_controller;
+
+architecture trans of iodrp_mcb_controller is
+
+
+    type StType is (
+    
+    READY,
+    DECIDE  ,         
+    ADDR_PHASE ,      
+    ADDR_TO_DATA_GAP ,
+    ADDR_TO_DATA_GAP2,
+    ADDR_TO_DATA_GAP3,
+    DATA_PHASE ,      
+    
+    ALMOST_READY  ,   
+    ALMOST_READY2 ,   
+    ALMOST_READY3    
+        
+    );
+
+
+      
+     constant IOI_DQ0            : std_logic_vector(4 downto 0) := "00001"; 
+     constant IOI_DQ1            : std_logic_vector(4 downto 0) := "00000"; 
+     constant IOI_DQ2            : std_logic_vector(4 downto 0) := "00011"; 
+     constant IOI_DQ3            : std_logic_vector(4 downto 0) := "00010"; 
+     constant IOI_DQ4            : std_logic_vector(4 downto 0) := "00101"; 
+     constant IOI_DQ5            : std_logic_vector(4 downto 0) := "00100"; 
+     constant IOI_DQ6            : std_logic_vector(4 downto 0) := "00111"; 
+     constant IOI_DQ7            : std_logic_vector(4 downto 0) := "00110"; 
+     constant IOI_DQ8            : std_logic_vector(4 downto 0) := "01001"; 
+     constant IOI_DQ9            : std_logic_vector(4 downto 0) := "01000"; 
+     constant IOI_DQ10           : std_logic_vector(4 downto 0) := "01011"; 
+     constant IOI_DQ11           : std_logic_vector(4 downto 0) := "01010"; 
+     constant IOI_DQ12           : std_logic_vector(4 downto 0) := "01101"; 
+     constant IOI_DQ13           : std_logic_vector(4 downto 0) := "01100"; 
+     constant IOI_DQ14           : std_logic_vector(4 downto 0) := "01111"; 
+     constant IOI_DQ15           : std_logic_vector(4 downto 0) := "01110"; 
+     constant IOI_UDQS_CLK       : std_logic_vector(4 downto 0) := "11101"; 
+     constant IOI_UDQS_PIN       : std_logic_vector(4 downto 0) := "11100"; 
+     constant IOI_LDQS_CLK       : std_logic_vector(4 downto 0) := "11111"; 
+     constant IOI_LDQS_PIN       : std_logic_vector(4 downto 0) := "11110"; 
+
+
+   signal memcell_addr_reg  : std_logic_vector(7 downto 0);
+   signal data_reg          : std_logic_vector(7 downto 0);
+   signal shift_through_reg : std_logic_vector(8 downto 0);
+   signal load_shift_n      : std_logic;
+   signal addr_data_sel_n   : std_logic;
+   signal bit_cnt           : std_logic_vector(2 downto 0);
+   signal rd_not_write_reg  : std_logic;
+   signal AddressPhase      : std_logic;
+   signal DRP_CS_pre        : std_logic;
+   signal extra_cs          : std_logic;
+   
+   
+   signal state,nextstate : StType;
+   
+   attribute fsm_encoding : string;
+   attribute fsm_encoding of state : signal is "gray";
+   attribute fsm_encoding of nextstate : signal is "gray";
+   
+   signal data_out          : std_logic_vector(8 downto 0);
+   signal data_out_mux      : std_logic_vector(8 downto 0);
+   signal DRP_SDI_pre       : std_logic;
+   
+   --synthesis translate_off
+   signal state_ascii       : std_logic_vector(32 * 8 - 1 downto 0);
+   -- case(state)
+   --synthesis translate_on
+   
+   -- The changes below are to compensate for an issue with 1.0 silicon.
+   -- It may still be necessary to add a clock cycle to the ADD and CS signals
+   
+   --`define DRP_v1_0_FIX    // Uncomment out this line for synthesis
+   
+   procedure shift_n_expand(
+      data_in            : in std_logic_vector(7 downto 0);
+      data_out           : out std_logic_vector(8 downto 0)) is
+   
+      variable data_out_xilinx2 : std_logic_vector(8 downto 0);
+      begin
+      if ((data_in(0)) = '1') then
+         data_out_xilinx2(1 downto 0) := "11";
+      else
+         
+         data_out_xilinx2(1 downto 0) := "00";
+      end if;
+      if (data_in(1 downto 0) = "10") then
+         data_out_xilinx2(2 downto 1) := "11";
+      else
+         
+         data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
+      end if;
+      if (data_in(2 downto 1) = "10") then
+         data_out_xilinx2(3 downto 2) := "11";
+      else
+         
+         data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
+      end if;
+      if (data_in(3 downto 2) = "10") then
+         data_out_xilinx2(4 downto 3) := "11";
+      else
+         
+         data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
+      end if;
+      if (data_in(4 downto 3) = "10") then
+         data_out_xilinx2(5 downto 4) := "11";
+      else
+         
+         data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
+      end if;
+      if (data_in(5 downto 4) = "10") then
+         data_out_xilinx2(6 downto 5) := "11";
+      else
+         
+         data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
+      end if;
+      if (data_in(6 downto 5) = "10") then
+         data_out_xilinx2(7 downto 6) := "11";
+      else
+         
+         data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
+      end if;
+      if (data_in(7 downto 6) = "10") then
+         data_out_xilinx2(8 downto 7) := "11";
+      else
+         data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
+      end if;
+   end shift_n_expand;
+   
+   
+   -- Declare intermediate signals for referenced outputs
+   signal DRP_CS_xilinx1    : std_logic;
+   signal DRP_ADD_xilinx0   : std_logic;
+
+   signal ALMOST_READY2_ST : std_logic;
+   signal ADDR_PHASE_ST     : std_logic;
+   signal BIT_CNT7          : std_logic;
+   signal ADDR_PHASE_ST1     : std_logic;
+   signal DATA_PHASE_ST     : std_logic;
+
+begin
+   -- Drive referenced outputs
+   DRP_CS <= DRP_CS_xilinx1;
+   DRP_ADD <= DRP_ADD_xilinx0;
+
+
+--   process (state)
+--   begin
+--      case state is
+--         when READY =>
+--            state_ascii <= "READY";
+--         when DECIDE =>
+--            state_ascii <= "DECIDE";
+--         when ADDR_PHASE =>
+--            state_ascii <= "ADDR_PHASE";
+--         when ADDR_TO_DATA_GAP =>
+--            state_ascii <= "ADDR_TO_DATA_GAP";
+--         when ADDR_TO_DATA_GAP2 =>
+--            state_ascii <= "ADDR_TO_DATA_GAP2";
+--         when ADDR_TO_DATA_GAP3 =>
+--            state_ascii <= "ADDR_TO_DATA_GAP3";
+--         when DATA_PHASE =>
+--            state_ascii <= "DATA_PHASE";
+--         when ALMOST_READY =>
+--            state_ascii <= "ALMOST_READY";
+--         when ALMOST_READY2 =>
+--            state_ascii <= "ALMOST_READY2";
+--         when ALMOST_READY3 =>
+--            state_ascii <= "ALMOST_READY3";
+--         when others =>
+--            null;
+--      end case;
+--   end process;
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (state = READY) then
+            memcell_addr_reg <= memcell_address;
+            data_reg <= write_data;
+            rd_not_write_reg <= rd_not_write;
+         end if;
+      end if;
+   end process;
+   
+   rdy_busy_n <= '1'  when state = READY else '0';
+   
+   process (drp_ioi_addr, data_out)
+   begin
+      
+      case drp_ioi_addr is
+         when IOI_DQ0 =>
+            data_out_mux <= data_out;
+         when IOI_DQ1 =>
+            data_out_mux <= data_out;
+         when IOI_DQ2 =>
+            data_out_mux <= data_out;
+         when IOI_DQ3 =>
+            data_out_mux <= data_out;
+         when IOI_DQ4 =>
+            data_out_mux <= data_out;
+         when IOI_DQ5 =>
+            data_out_mux <= data_out;
+         when IOI_DQ6 =>
+            data_out_mux <= data_out;
+         when IOI_DQ7 =>
+            data_out_mux <= data_out;
+         when IOI_DQ8 =>
+            data_out_mux <= data_out;
+         when IOI_DQ9 =>
+            data_out_mux <= data_out;
+         when IOI_DQ10 =>
+            data_out_mux <= data_out;
+         when IOI_DQ11 =>
+            data_out_mux <= data_out;
+         when IOI_DQ12 =>
+            data_out_mux <= data_out;
+         when IOI_DQ13 =>
+            data_out_mux <= data_out;
+         when IOI_DQ14 =>
+            data_out_mux <= data_out;
+         when IOI_DQ15 =>
+            data_out_mux <= data_out;
+         when IOI_UDQS_CLK =>
+            data_out_mux <= data_out;
+         when IOI_UDQS_PIN =>
+            data_out_mux <= data_out;
+         when IOI_LDQS_CLK =>
+            data_out_mux <= data_out;
+         when IOI_LDQS_PIN =>
+            data_out_mux <= data_out;
+         when others =>
+            data_out_mux <= data_out;
+      end case;
+   end process;
+   
+   
+   data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
+               ('0' & data_reg);
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            shift_through_reg <= "000000000";
+         else
+            if (load_shift_n = '1') then                --Assume the shifter is either loading or shifting, bit 0 is shifted out first
+               shift_through_reg <= data_out_mux;
+            else
+               shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then
+            bit_cnt <= bit_cnt + "001";
+         else
+            bit_cnt <= "000";
+         end if;
+      end if;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            read_data <= "00000000";
+         else
+            if (state = ALMOST_READY3) then
+               read_data <= shift_through_reg(7 downto 0);
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
+   ADDR_PHASE_ST   <= '1' when state = ADDR_PHASE else '0';
+   BIT_CNT7         <= '1' when bit_cnt = "111" else '0';
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            AddressPhase <= '0';
+         else
+            if (AddressPhase = '1') then
+               -- Keep it set until we finish the cycle
+               AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
+            else
+               -- set the address phase when ever we finish the address phase
+               AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
+            end if;
+         end if;
+      end if;
+   end process;
+   
+ADDR_PHASE_ST1 <= '1' when  nextstate = ADDR_PHASE else '0';
+DATA_PHASE_ST <= '1' when  nextstate = DATA_PHASE else '0';
+
+
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
+         --      DRP_CS      <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
+         DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
+         MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
+         if (state = READY) then
+            DRP_BKST <= use_broadcast;
+         end if;
+      end if;
+   end process;
+   
+   
+   DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else         --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
+                  '0';
+   DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else          --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
+              DRP_SDI_pre;
+   
+   process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
+   begin
+      addr_data_sel_n <= '0';
+      load_shift_n <= '0';
+      case state is
+         when READY =>
+            load_shift_n <= '0';
+            if (cmd_valid = '1') then
+               nextstate <= DECIDE;
+            else
+               nextstate <= READY;
+            end if;
+         when DECIDE =>
+            load_shift_n <= '1';
+            addr_data_sel_n <= '1';
+            nextstate <= ADDR_PHASE;
+         -- After the second pass go to end of statemachine
+         -- execute a second address phase for the alternative access method.
+         when ADDR_PHASE =>
+            load_shift_n <= '0';
+            if (BIT_CNT7 = '1') then
+               if (('1' and rd_not_write_reg) = '1') then
+                  if (AddressPhase = '1') then
+                     nextstate <= ALMOST_READY;
+                  else
+                     nextstate <= DECIDE;
+                  end if;
+               else
+                  nextstate <= ADDR_TO_DATA_GAP;
+               end if;
+            else
+               nextstate <= ADDR_PHASE;
+            end if;
+         when ADDR_TO_DATA_GAP =>
+            load_shift_n <= '1';
+            nextstate <= ADDR_TO_DATA_GAP2;
+         when ADDR_TO_DATA_GAP2 =>
+            load_shift_n <= '1';
+            nextstate <= ADDR_TO_DATA_GAP3;
+         when ADDR_TO_DATA_GAP3 =>
+            load_shift_n <= '1';
+            nextstate <= DATA_PHASE;
+         when DATA_PHASE =>
+            load_shift_n <= '0';
+            if (BIT_CNT7 = '1') then
+               nextstate <= ALMOST_READY;
+            else
+               nextstate <= DATA_PHASE;
+            end if;
+         when ALMOST_READY =>
+            load_shift_n <= '0';
+            nextstate <= ALMOST_READY2;
+         when ALMOST_READY2 =>
+            load_shift_n <= '0';
+            nextstate <= ALMOST_READY3;
+         when ALMOST_READY3 =>
+            load_shift_n <= '0';
+            nextstate <= READY;
+         when others =>
+            load_shift_n <= '0';
+            nextstate <= READY;
+      end case;
+   end process;
+   
+   
+   process (DRP_CLK)
+   begin
+      if (DRP_CLK'event and DRP_CLK = '1') then
+         if (sync_rst = '1') then
+            state <= READY;
+         else
+            state <= nextstate;
+         end if;
+      end if;
+   end process;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_raw_wrapper.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_raw_wrapper.vhd
new file mode 100755
index 0000000..51dc7cc
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_raw_wrapper.vhd
@@ -0,0 +1,7117 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_raw_wrapper.v
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:04 $
+-- \   \  /  \    Date Created: Thu June 24 2008
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR 
+--Purpose:
+--Reference:
+--   This module is the intialization control logic of the memory interface.
+--   All commands are issued from here acoording to the burst, CAS Latency and
+--   the user commands.
+--   
+-- Revised History:  
+--    Rev 1.1 - added port_enable assignment for all configurations  and rearrange 
+--              assignment siganls according to port number
+--            - added timescale directive  -SN 7-28-08
+--            - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through 
+--              15 -SN 7-28-08
+--            - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
+--            - removed ghighb, gpwrdnb, gsr, gwe in port declaration. 
+--              For now tb need to force the signals inside the MCB and Wrapper
+--              until a glbl.v is ready.  Not sure how to do this in NCVerilog 
+--              flow. -SN 7-28-08
+--
+--    Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
+--    Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5   - SN 8-8-08
+--    Rev 1.4 -- update changes that required by MCB core.  - SN 9-11-09
+--    Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
+--               delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90 
+--               delay_we_90 ,delay_address,delay_ba_90 =
+--              --removed :assign #50 delay_dqnum = dqnum;
+--              --removed :assign #50 delay_dqpum = dqpum;
+--              --removed :assign #50 delay_dqnlm = dqnlm;
+--              --removed :assign #50 delay_dqplm = dqplm;
+--              --removed : delay_dqsIO_w_en_90_n
+--              --removed : delay_dqsIO_w_en_90_p              
+--              --removed : delay_dqsIO_w_en_0     
+--              -- corrected spelling error: C_MEM_RTRAS
+--    Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip.  1-12-09              
+--                 -- rename the memc_wrapper.v to mcb_raw_wrapper.v
+--    Rev 1.7  -- --  .READEN    is removed in IODRP2_MCB 1-28-09
+--              -- connection has been updated                            
+--    Rev 1.8   -- update memory parameter equations.    1-30_2009
+--              -- added portion of Soft IP               
+--              -- CAL_CLK_DIV is not used but MCB still has it
+--    Rev  1.9  -- added Error checking for Invalid command to unidirectional port   
+--    Rev  1.10 -- changed the backend connection so that Simulation will work while
+--                 sw tools try to fix the model issues.                  2-3-2009      
+--                 sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
+--                 It is acutally 180 degree difference.
+--    Rev  1.11 -- Added MCB_Soft_Calibration_top. 
+--    Rev  1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009   
+--    Rev  1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
+--    Rev  1.14 -- Added minium condition for tRTP valud/                        
+--    REv  1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top.  6-16-2009
+--    Rev  1.16 -- Fixed the WTR for DDR. 6-23-2009
+--    Rev  1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
+--    Rev  1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
+--    Rev  1.19 -- Added soft fix to support refresh command. 7-15-2009.
+--    Rev  1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
+--                 Dynamic DQS calibration in Soft Calibration module.
+--    Rev  1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
+--                 RTT value is set to "disabled"
+--              -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
+--              -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010                
+--    Rev  1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
+--    Rev  1.23 -- Fixed  CR 558661.  In Config "B64B64" mode, mig_p5_wr_data  <= p1_wr_data(63 downto 32).
+--    Rev  1.24 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE"
+--    Rev  1.25 -- Fixed reset problem when MCB exits from SUSPEND SELFREFRESH mode. 10-20-2010	 
+--    Rev  1.26 -- Synchronize sys_rst before connecting to mcb_soft_calibration module to fix
+--                 CDC static timing issue.	 2-14-2011
+
+
+--*************************************************************************************************************************
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+library unisim;
+use unisim.vcomponents.all;
+
+entity mcb_raw_wrapper is
+generic(
+      C_MEMCLK_PERIOD                  : integer := 2500;
+      C_PORT_ENABLE                    : std_logic_vector(5 downto 0) := (others => '1');
+
+      C_MEM_ADDR_ORDER                 : string := "BANK_ROW_COLUMN";
+      
+      C_ARB_NUM_TIME_SLOTS             : integer := 12;
+      C_ARB_TIME_SLOT_0                : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
+      C_ARB_TIME_SLOT_1                : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
+      C_ARB_TIME_SLOT_2                : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011"; 
+      C_ARB_TIME_SLOT_3                : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
+      C_ARB_TIME_SLOT_4                : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
+      C_ARB_TIME_SLOT_5                : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
+      C_ARB_TIME_SLOT_6                : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
+      C_ARB_TIME_SLOT_7                : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
+      C_ARB_TIME_SLOT_8                : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011"; 
+      C_ARB_TIME_SLOT_9                : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
+      C_ARB_TIME_SLOT_10               : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
+      C_ARB_TIME_SLOT_11               : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
+      C_PORT_CONFIG                    : string :=  "B32_B32_W32_W32_W32_W32";  
+
+      
+      C_MEM_TRAS                       : integer := 45000;
+      C_MEM_TRCD                       : integer := 12500;
+      C_MEM_TREFI                      : integer := 7800;
+      C_MEM_TRFC                       : integer := 127500;
+      C_MEM_TRP                        : integer := 12500;
+      C_MEM_TWR                        : integer := 15000;
+      C_MEM_TRTP                       : integer := 7500;
+      C_MEM_TWTR                       : integer := 7500;
+      
+      C_NUM_DQ_PINS                    : integer := 8;
+      C_MEM_TYPE                       : string := "DDR3";
+      C_MEM_DENSITY                    : string := "512M";
+      C_MEM_BURST_LEN                  : integer := 8;
+      
+      C_MEM_CAS_LATENCY                : integer := 4;
+      C_MEM_ADDR_WIDTH                 : integer := 13;
+      C_MEM_BANKADDR_WIDTH             : integer := 3;
+      C_MEM_NUM_COL_BITS               : integer := 11;
+      
+      C_MEM_DDR3_CAS_LATENCY           : integer := 7;
+      C_MEM_MOBILE_PA_SR               : string := "FULL";
+      C_MEM_DDR1_2_ODS                 : string := "FULL";
+      C_MEM_DDR3_ODS                   : string := "DIV6";
+      C_MEM_DDR2_RTT                   : string := "50OHMS";
+      C_MEM_DDR3_RTT                   : string := "DIV2";
+      C_MEM_MDDR_ODS                   : string := "FULL";
+      
+      C_MEM_DDR2_DIFF_DQS_EN           : string := "YES";
+      C_MEM_DDR2_3_PA_SR               : string := "OFF";
+      C_MEM_DDR3_CAS_WR_LATENCY        : integer := 5;
+      
+      C_MEM_DDR3_AUTO_SR               : string := "ENABLED";
+      C_MEM_DDR2_3_HIGH_TEMP_SR        : string := "NORMAL";
+      C_MEM_DDR3_DYN_WRT_ODT           : string := "OFF";
+      C_MEM_TZQINIT_MAXCNT             : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets 
+      
+      C_MC_CALIB_BYPASS                : string := "NO";
+      C_MC_CALIBRATION_RA              : bit_vector(15 downto 0) := X"0000";
+      C_MC_CALIBRATION_BA              : bit_vector(2 downto 0) := "000";
+
+      C_CALIB_SOFT_IP                  : string := "TRUE";
+      C_SKIP_IN_TERM_CAL               : integer := 0;        --provides option to skip the input termination calibration
+      C_SKIP_DYNAMIC_CAL               : integer := 0;        --provides option to skip the dynamic delay calibration
+      C_SKIP_DYN_IN_TERM               : integer := 1;        -- provides option to skip the input termination calibration
+      C_SIMULATION                     : string  := "FALSE";  -- Tells us whether the design is being simulated or implemented
+
+
+--- ADDED for 1.0 silicon support to bypass Calibration //////
+-- 07-10-09 chipl
+--////////////////////////////////////////////////////////////
+     LDQSP_TAP_DELAY_VAL                : integer := 0;
+     UDQSP_TAP_DELAY_VAL                : integer := 0;
+     LDQSN_TAP_DELAY_VAL                : integer := 0;
+     UDQSN_TAP_DELAY_VAL                : integer := 0;
+     DQ0_TAP_DELAY_VAL                  : integer := 0;  
+     DQ1_TAP_DELAY_VAL                  : integer := 0;  
+     DQ2_TAP_DELAY_VAL                  : integer := 0;  
+     DQ3_TAP_DELAY_VAL                  : integer := 0;  
+     DQ4_TAP_DELAY_VAL                  : integer := 0;  
+     DQ5_TAP_DELAY_VAL                  : integer := 0;  
+     DQ6_TAP_DELAY_VAL                  : integer := 0;  
+     DQ7_TAP_DELAY_VAL                  : integer := 0;  
+     DQ8_TAP_DELAY_VAL                  : integer := 0;  
+     DQ9_TAP_DELAY_VAL                  : integer := 0;  
+     DQ10_TAP_DELAY_VAL                  : integer := 0;  
+     DQ11_TAP_DELAY_VAL                  : integer := 0;  
+     DQ12_TAP_DELAY_VAL                  : integer := 0;  
+     DQ13_TAP_DELAY_VAL                  : integer := 0;  
+     DQ14_TAP_DELAY_VAL                  : integer := 0;  
+     DQ15_TAP_DELAY_VAL                  : integer := 0;  
+
+      C_MC_CALIBRATION_CA              : bit_vector(11 downto 0) := X"000";
+      C_MC_CALIBRATION_CLK_DIV         : integer := 1;
+      C_MC_CALIBRATION_MODE            : string := "CALIBRATION";
+      C_MC_CALIBRATION_DELAY           : string := "HALF";
+      
+      C_P0_MASK_SIZE                   : integer := 4;
+      C_P0_DATA_PORT_SIZE              : integer := 32;
+      C_P1_MASK_SIZE                   : integer := 4;
+      C_P1_DATA_PORT_SIZE              : integer := 32
+      );
+   PORT (
+
+      sysclk_2x                        : in std_logic;
+      sysclk_2x_180                    : in std_logic;
+      pll_ce_0                         : in std_logic;
+      pll_ce_90                        : in std_logic;
+      pll_lock                         : in std_logic;
+      sys_rst                          : in std_logic;
+      
+      p0_arb_en                        : in std_logic;
+      p0_cmd_clk                       : in std_logic;
+      p0_cmd_en                        : in std_logic;
+      p0_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p0_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p0_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p0_cmd_empty                     : out std_logic;
+      p0_cmd_full                      : out std_logic;
+
+      p0_wr_clk                        : in std_logic;
+      p0_wr_en                         : in std_logic;
+      p0_wr_mask                       : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+      p0_wr_data                       : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_wr_full                       : out std_logic;
+      p0_wr_empty                      : out std_logic;
+      p0_wr_count                      : out std_logic_vector(6 downto 0);
+      p0_wr_underrun                   : out std_logic;
+      p0_wr_error                      : out std_logic;
+
+      p0_rd_clk                        : in std_logic;
+      p0_rd_en                         : in std_logic;
+      p0_rd_data                       : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_rd_full                       : out std_logic;
+      p0_rd_empty                      : out std_logic;
+      p0_rd_count                      : out std_logic_vector(6 downto 0);
+      p0_rd_overflow                   : out std_logic;
+      p0_rd_error                      : out std_logic;
+
+      p1_arb_en                        : in std_logic;
+      p1_cmd_clk                       : in std_logic;
+      p1_cmd_en                        : in std_logic;
+      p1_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p1_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p1_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p1_cmd_empty                     : out std_logic;
+      p1_cmd_full                      : out std_logic;
+      p1_wr_clk                        : in std_logic;
+      p1_wr_en                         : in std_logic;
+      p1_wr_mask                       : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+      p1_wr_data                       : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_wr_full                       : out std_logic;
+      p1_wr_empty                      : out std_logic;
+      p1_wr_count                      : out std_logic_vector(6 downto 0);
+      p1_wr_underrun                   : out std_logic;
+      p1_wr_error                      : out std_logic;
+      p1_rd_clk                        : in std_logic;
+      p1_rd_en                         : in std_logic;
+      p1_rd_data                       : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_rd_full                       : out std_logic;
+      p1_rd_empty                      : out std_logic;
+      p1_rd_count                      : out std_logic_vector(6 downto 0);
+      p1_rd_overflow                   : out std_logic;
+      p1_rd_error                      : out std_logic;
+
+      p2_arb_en                        : in std_logic;
+      p2_cmd_clk                       : in std_logic;
+      p2_cmd_en                        : in std_logic;
+      p2_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p2_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p2_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p2_cmd_empty                     : out std_logic;
+      p2_cmd_full                      : out std_logic;
+      p2_wr_clk                        : in std_logic;
+      p2_wr_en                         : in std_logic;
+      p2_wr_mask                       : in std_logic_vector(3 downto 0);
+      p2_wr_data                       : in std_logic_vector(31 downto 0);
+      p2_wr_full                       : out std_logic;
+      p2_wr_empty                      : out std_logic;
+      p2_wr_count                      : out std_logic_vector(6 downto 0);
+      p2_wr_underrun                   : out std_logic;
+      p2_wr_error                      : out std_logic;
+      p2_rd_clk                        : in std_logic;
+      p2_rd_en                         : in std_logic;
+      p2_rd_data                       : out std_logic_vector(31 downto 0);
+      p2_rd_full                       : out std_logic;
+      p2_rd_empty                      : out std_logic;
+      p2_rd_count                      : out std_logic_vector(6 downto 0);
+      p2_rd_overflow                   : out std_logic;
+      p2_rd_error                      : out std_logic;
+
+      p3_arb_en                        : in std_logic;
+      p3_cmd_clk                       : in std_logic;
+      p3_cmd_en                        : in std_logic;
+      p3_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p3_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p3_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p3_cmd_empty                     : out std_logic;
+      p3_cmd_full                      : out std_logic;
+      p3_wr_clk                        : in std_logic;
+      p3_wr_en                         : in std_logic;
+      p3_wr_mask                       : in std_logic_vector(3 downto 0);
+      p3_wr_data                       : in std_logic_vector(31 downto 0);
+      p3_wr_full                       : out std_logic;
+      p3_wr_empty                      : out std_logic;
+      p3_wr_count                      : out std_logic_vector(6 downto 0);
+      p3_wr_underrun                   : out std_logic;
+      p3_wr_error                      : out std_logic;
+      p3_rd_clk                        : in std_logic;
+      p3_rd_en                         : in std_logic;
+      p3_rd_data                       : out std_logic_vector(31 downto 0);
+      p3_rd_full                       : out std_logic;
+      p3_rd_empty                      : out std_logic;
+      p3_rd_count                      : out std_logic_vector(6 downto 0);
+      p3_rd_overflow                   : out std_logic;
+      p3_rd_error                      : out std_logic;
+
+      p4_arb_en                        : in std_logic;
+      p4_cmd_clk                       : in std_logic;
+      p4_cmd_en                        : in std_logic;
+      p4_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p4_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p4_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p4_cmd_empty                     : out std_logic;
+      p4_cmd_full                      : out std_logic;
+      p4_wr_clk                        : in std_logic;
+      p4_wr_en                         : in std_logic;
+      p4_wr_mask                       : in std_logic_vector(3 downto 0);
+      p4_wr_data                       : in std_logic_vector(31 downto 0);
+      p4_wr_full                       : out std_logic;
+      p4_wr_empty                      : out std_logic;
+      p4_wr_count                      : out std_logic_vector(6 downto 0);
+      p4_wr_underrun                   : out std_logic;
+      p4_wr_error                      : out std_logic;
+      p4_rd_clk                        : in std_logic;
+      p4_rd_en                         : in std_logic;
+      p4_rd_data                       : out std_logic_vector(31 downto 0);
+      p4_rd_full                       : out std_logic;
+      p4_rd_empty                      : out std_logic;
+      p4_rd_count                      : out std_logic_vector(6 downto 0);
+      p4_rd_overflow                   : out std_logic;
+      p4_rd_error                      : out std_logic;
+
+      p5_arb_en                        : in std_logic;
+      p5_cmd_clk                       : in std_logic;
+      p5_cmd_en                        : in std_logic;
+      p5_cmd_instr                     : in std_logic_vector(2 downto 0);
+      p5_cmd_bl                        : in std_logic_vector(5 downto 0);
+      p5_cmd_byte_addr                 : in std_logic_vector(29 downto 0);
+      p5_cmd_empty                     : out std_logic;
+      p5_cmd_full                      : out std_logic;
+      p5_wr_clk                        : in std_logic;
+      p5_wr_en                         : in std_logic;
+      p5_wr_mask                       : in std_logic_vector(3 downto 0);
+      p5_wr_data                       : in std_logic_vector(31 downto 0);
+      p5_wr_full                       : out std_logic;
+      p5_wr_empty                      : out std_logic;
+      p5_wr_count                      : out std_logic_vector(6 downto 0);
+      p5_wr_underrun                   : out std_logic;
+      p5_wr_error                      : out std_logic;
+      p5_rd_clk                        : in std_logic;
+      p5_rd_en                         : in std_logic;
+      p5_rd_data                       : out std_logic_vector(31 downto 0);
+      p5_rd_full                       : out std_logic;
+      p5_rd_empty                      : out std_logic;
+      p5_rd_count                      : out std_logic_vector(6 downto 0);
+      p5_rd_overflow                   : out std_logic;
+      p5_rd_error                      : out std_logic;
+
+      mcbx_dram_addr                   : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
+      mcbx_dram_ba                     : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
+      mcbx_dram_ras_n                  : out std_logic;
+      mcbx_dram_cas_n                  : out std_logic;
+      mcbx_dram_we_n                   : out std_logic;
+      mcbx_dram_cke                    : out std_logic;
+      mcbx_dram_clk                    : out std_logic;
+      mcbx_dram_clk_n                  : out std_logic;
+      mcbx_dram_dq                     : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+      mcbx_dram_dqs                    : INOUT std_logic;
+      mcbx_dram_dqs_n                  : INOUT std_logic;
+      mcbx_dram_udqs                   : INOUT std_logic;
+      mcbx_dram_udqs_n                 : INOUT std_logic;
+      mcbx_dram_udm                    : out std_logic;
+      mcbx_dram_ldm                    : out std_logic;
+      mcbx_dram_odt                    : out std_logic;
+      mcbx_dram_ddr3_rst               : out std_logic;
+
+      calib_recal                      : in std_logic;
+      rzq                              : INOUT std_logic;
+      zio                              : INOUT std_logic;
+      ui_read                          : in std_logic;
+      ui_add                           : in std_logic;
+      ui_cs                            : in std_logic;
+      ui_clk                           : in std_logic;
+      ui_sdi                           : in std_logic;
+      ui_addr                          : in std_logic_vector(4 downto 0);
+      ui_broadcast                     : in std_logic;
+      ui_drp_update                    : in std_logic;
+      ui_done_cal                      : in std_logic;
+      ui_cmd                           : in std_logic;
+      ui_cmd_in                        : in std_logic;
+      ui_cmd_en                        : in std_logic;
+      ui_dqcount                       : in std_logic_vector(3 downto 0);
+      ui_dq_lower_dec                  : in std_logic;
+      ui_dq_lower_inc                  : in std_logic;
+      ui_dq_upper_dec                  : in std_logic;
+      ui_dq_upper_inc                  : in std_logic;
+      ui_udqs_inc                      : in std_logic;
+      ui_udqs_dec                      : in std_logic;
+      ui_ldqs_inc                      : in std_logic;
+      ui_ldqs_dec                      : in std_logic;
+      uo_data                          : out std_logic_vector(7 downto 0);
+      uo_data_valid                    : out std_logic;
+      uo_done_cal                      : out std_logic;
+      uo_cmd_ready_in                  : out std_logic;
+      uo_refrsh_flag                   : out std_logic;
+      uo_cal_start                     : out std_logic;
+      uo_sdo                           : out std_logic;
+      status                           : out std_logic_vector(31 downto 0);
+      selfrefresh_enter                : in std_logic;
+      selfrefresh_mode                 : out std_logic
+   );
+end mcb_raw_wrapper;
+
+ architecture aarch of mcb_raw_wrapper is
+   
+component mcb_soft_calibration_top is
+   generic (
+      C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets 
+      C_MC_CALIBRATION_MODE : string :=  "CALIBRATION";  -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
+                                                         --  and does dynamic recal,
+                                                         -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* 
+                                                         --  no dynamic recal will be done 
+      SKIP_IN_TERM_CAL      : integer := 0;             -- provides option to skip the input termination calibration
+      SKIP_DYNAMIC_CAL      : integer := 0;             -- provides option to skip the dynamic delay calibration
+      SKIP_DYN_IN_TERM      : integer := 0;             -- provides option to skip the dynamic delay calibration
+      C_SIMULATION          : string  := "FALSE";       -- Tells us whether the design is being simulated or implemented
+      C_MEM_TYPE            : string  := "DDR3"         -- provides the memory device used for the design
+
+   );
+   port (
+      UI_CLK                : in std_logic;             -- Input - global clock to be used for input_term_tuner and IODRP clock
+      RST                   : in std_logic;             -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for 
+                                                        --  IODRP (sub)controller
+      IOCLK                 : in std_logic;             -- Input - IOCLK input to the IODRP's
+      DONE_SOFTANDHARD_CAL  : out std_logic;            -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
+                                                        --  (MCB hard calib complete)
+      PLL_LOCK              : in std_logic;             -- Lock signal from PLL
+      SELFREFRESH_REQ       : in std_logic;             
+      SELFREFRESH_MCB_MODE  : in std_logic;             
+      SELFREFRESH_MCB_REQ   : out std_logic;            
+      SELFREFRESH_MODE      : out std_logic;            
+      MCB_UIADD             : out std_logic;            -- to MCB's UIADD port
+      MCB_UISDI             : out std_logic;            -- to MCB's UISDI port
+      MCB_UOSDO             : in std_logic;
+      MCB_UODONECAL         : in std_logic;
+      MCB_UOREFRSHFLAG      : in std_logic;
+      MCB_UICS              : out std_logic;
+      MCB_UIDRPUPDATE       : out std_logic;
+      MCB_UIBROADCAST       : out std_logic;
+      MCB_UIADDR            : out std_logic_vector(4 downto 0);
+      MCB_UICMDEN           : out std_logic;
+      MCB_UIDONECAL         : out std_logic;
+      MCB_UIDQLOWERDEC      : out std_logic;
+      MCB_UIDQLOWERINC      : out std_logic;
+      MCB_UIDQUPPERDEC      : out std_logic;
+      MCB_UIDQUPPERINC      : out std_logic;
+      MCB_UILDQSDEC         : out std_logic;
+      MCB_UILDQSINC         : out std_logic;
+      MCB_UIREAD            : out std_logic;
+      MCB_UIUDQSDEC         : out std_logic;
+      MCB_UIUDQSINC         : out std_logic;
+      MCB_RECAL             : out std_logic;
+      MCB_SYSRST            : out std_logic;
+      MCB_UICMD             : out std_logic;
+      MCB_UICMDIN           : out std_logic;
+      MCB_UIDQCOUNT         : out std_logic_vector(3 downto 0);
+      MCB_UODATA            : in std_logic_vector(7 downto 0);
+      MCB_UODATAVALID       : in std_logic;
+      MCB_UOCMDREADY        : in std_logic;
+      MCB_UO_CAL_START      : in std_logic;
+      RZQ_PIN               : inout std_logic;
+      ZIO_PIN               : inout std_logic;
+      CKE_Train             : out std_logic
+   );   
+end component;
+
+constant      C_OSERDES2_DATA_RATE_OQ          : STRING := "SDR";
+constant      C_OSERDES2_DATA_RATE_OT          : STRING := "SDR";
+constant      C_OSERDES2_SERDES_MODE_MASTER    : STRING := "MASTER";
+constant      C_OSERDES2_SERDES_MODE_SLAVE     : STRING := "SLAVE";
+constant      C_OSERDES2_OUTPUT_MODE_SE        : STRING := "SINGLE_ENDED";
+constant      C_OSERDES2_OUTPUT_MODE_DIFF      : STRING := "DIFFERENTIAL";
+      
+constant      C_BUFPLL_0_LOCK_SRC              : STRING := "LOCK_TO_0";
+      
+constant      C_DQ_IODRP2_DATA_RATE            : STRING := "SDR";
+constant      C_DQ_IODRP2_SERDES_MODE_MASTER   : STRING := "MASTER";
+constant      C_DQ_IODRP2_SERDES_MODE_SLAVE    : STRING := "SLAVE";
+      
+constant      C_DQS_IODRP2_DATA_RATE           : STRING := "SDR";
+constant      C_DQS_IODRP2_SERDES_MODE_MASTER  : STRING := "MASTER";
+constant      C_DQS_IODRP2_SERDES_MODE_SLAVE   : STRING := "SLAVE";
+
+-- MIG always set the below ADD_LATENCY to zero
+constant      C_MEM_DDR3_ADD_LATENCY           : STRING := "OFF";
+constant      C_MEM_DDR2_ADD_LATENCY           : INTEGER := 0;
+constant      C_MEM_MOBILE_TC_SR               : INTEGER := 0;
+
+-- convert the memory timing to memory clock units. I
+constant      MEM_RAS_VAL   : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+constant      MEM_RCD_VAL   : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+constant      MEM_REFI_VAL  : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD) - 25;
+constant      MEM_RFC_VAL   : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+constant      MEM_RP_VAL    : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+constant      MEM_WR_VAL    : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+
+ function cdiv return integer is
+  begin
+    if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
+      return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
+    else      
+    return (C_MEM_TRTP/C_MEMCLK_PERIOD);
+    end if;
+  end function cdiv;
+
+constant      MEM_RTP_VAL1                      : INTEGER := cdiv;
+
+
+function MEM_RTP_CYC1 return integer is
+  begin
+    if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
+      return 4;
+    else if(MEM_RTP_VAL1 < 2) then
+      return 2;
+    else
+      return MEM_RTP_VAL1;
+    end if;
+    end if;
+  end function MEM_RTP_CYC1;
+
+constant      MEM_RTP_VAL                      : INTEGER := MEM_RTP_CYC1;
+
+function MEM_WTR_CYC return integer is
+  begin
+    if (C_MEM_TYPE = "DDR") then
+      return 2;
+    elsif (C_MEM_TYPE = "DDR3") then
+      return 4;
+    elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
+      return C_MEM_TWTR;
+    elsif (C_MEM_TYPE = "DDR2"  AND (((C_MEM_TWTR  + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
+      return ((C_MEM_TWTR  + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
+    elsif (C_MEM_TYPE = "DDR2")then
+      return 2;
+    else
+      return 3;
+    end if;
+  end function MEM_WTR_CYC;
+
+constant      MEM_WTR_VAL                      : INTEGER := MEM_WTR_CYC;
+
+function DDR2_WRT_RECOVERY_CYC return integer is
+  begin
+    if (not(C_MEM_TYPE = "DDR2")) then
+      return 5;
+    else
+      return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+    end if;
+  end function DDR2_WRT_RECOVERY_CYC;
+
+
+constant        C_MEM_DDR2_WRT_RECOVERY          : INTEGER := DDR2_WRT_RECOVERY_CYC;
+
+function DDR3_WRT_RECOVERY_CYC return integer is
+  begin
+    if (not(C_MEM_TYPE = "DDR3")) then
+      return 5;
+    else
+      return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
+    end if;
+  end function DDR3_WRT_RECOVERY_CYC;
+
+constant      C_MEM_DDR3_WRT_RECOVERY          : INTEGER := DDR3_WRT_RECOVERY_CYC;
+
+--CR 596422
+constant allzero : std_logic_vector(127 downto 0) := (others => '0');
+--signal allzero : std_logic_vector(127 downto 0) := (others => '0');
+
+----------------------------------------------------------------------------
+-- signal Declarations
+----------------------------------------------------------------------------
+signal addr_in0 : std_logic_vector(31 downto 0);
+signal dqs_out_p : std_logic;              
+signal dqs_out_n : std_logic;              
+signal dqs_sys_p : std_logic;             --from dqs_gen to IOclk network
+signal dqs_sys_n : std_logic;             --from dqs_gen to IOclk network
+signal udqs_sys_p: std_logic;
+signal udqs_sys_n: std_logic;
+signal dqs_p : std_logic;                  -- open net now ?
+signal dqs_n : std_logic;                  -- open net now ?
+
+-- IOI and IOB enable/tristate interface
+signal dqIO_w_en_0      : std_logic;          --enable DQ pads
+signal dqsIO_w_en_90_p  : std_logic;          --enable p side of DQS
+signal dqsIO_w_en_90_n  : std_logic;          --enable n side of DQS
+
+--memory chip control interface
+signal address_90 : std_logic_vector(14 downto 0);
+signal ba_90  : std_logic_vector(2 downto 0);   
+signal ras_90 : std_logic;
+signal cas_90 : std_logic;
+signal we_90  : std_logic;
+signal cke_90 : std_logic;
+signal odt_90 : std_logic;
+signal rst_90 : std_logic;
+
+-- calibration IDELAY control  signals
+signal ioi_drp_clk       : std_logic;   --DRP interface - synchronous clock output
+signal ioi_drp_addr      : std_logic_vector(4 downto 0);   --DRP interface - IOI selection
+signal ioi_drp_sdo       : std_logic;   --DRP interface - serial output for commmands
+signal ioi_drp_sdi       : std_logic;   --DRP interface - serial input for commands
+signal ioi_drp_cs        : std_logic;   --DRP interface - chip select doubles as DONE signal
+signal ioi_drp_add       : std_logic;   --DRP interface - serial address signal
+signal ioi_drp_broadcast : std_logic; 
+signal ioi_drp_train     : std_logic;
+
+-- Calibration datacapture siganls
+signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
+signal dq_in_p : std_logic;         --positive signal sent to calibration logic
+signal dq_in_n : std_logic;         --negative signal sent to calibration logic
+signal cal_done: std_logic;   
+
+--DQS calibration interface
+signal udqs_n : std_logic;
+signal udqs_p : std_logic;
+signal udqs_dqocal_p : std_logic;
+signal udqs_dqocal_n : std_logic;
+
+-- MUI enable interface
+signal df_en_n90 : std_logic;
+
+--INTERNAL signal FOR DRP chain
+-- IOI <-> MUI
+signal ioi_int_tmp : std_logic;
+
+signal dqo_n : std_logic_vector(15 downto 0);  
+signal dqo_p : std_logic_vector(15 downto 0);  
+signal dqnlm : std_logic;      
+signal dqplm : std_logic;      
+signal dqnum : std_logic;      
+signal dqpum : std_logic;      
+
+-- IOI <-> IOB   routes
+signal  ioi_addr  : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
+signal  ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);    
+signal  ioi_cas : std_logic;  
+signal  ioi_ck  : std_logic;  
+signal  ioi_ckn : std_logic;   
+signal  ioi_cke : std_logic;  
+signal  ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0); 
+signal  ioi_dqs  : std_logic; 
+signal  ioi_dqsn : std_logic;
+signal  ioi_udqs : std_logic;
+signal  ioi_udqsn : std_logic;   
+signal  ioi_odt  : std_logic; 
+signal  ioi_ras  : std_logic; 
+signal  ioi_rst  : std_logic; 
+signal  ioi_we   : std_logic;
+signal  ioi_udm  : std_logic;
+signal  ioi_ldm  : std_logic;
+
+signal  in_dq     : std_logic_vector(15 downto 0);
+signal  in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+signal  in_dqs       : std_logic;
+signal  in_pre_dqsp  : std_logic;
+signal  in_pre_dqsn  : std_logic;
+signal  in_pre_udqsp : std_logic;
+signal  in_pre_udqsn : std_logic;
+signal  in_udqs      : std_logic;
+
+-- Memory tri-state control signals
+signal  t_addr  : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
+signal  t_ba    : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);    
+signal  t_cas   : std_logic;
+signal  t_ck    : std_logic;
+signal  t_ckn   : std_logic;
+signal  t_cke   : std_logic;
+signal  t_dq    : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+signal  t_dqs   : std_logic;   
+signal  t_dqsn  : std_logic;
+signal  t_udqs  : std_logic;
+signal  t_udqsn : std_logic;
+signal  t_odt   : std_logic;   
+signal  t_ras   : std_logic;   
+signal  t_rst   : std_logic;   
+signal  t_we    : std_logic;   
+
+signal t_udm             : std_logic;
+signal t_ldm             : std_logic;
+
+signal idelay_dqs_ioi_s  : std_logic;
+signal idelay_dqs_ioi_m  : std_logic;
+signal idelay_udqs_ioi_s : std_logic;
+signal idelay_udqs_ioi_m : std_logic;
+
+signal dqs_pin           : std_logic;
+signal udqs_pin          : std_logic;
+
+-- USER Interface signals
+-- translated memory addresses
+signal p0_cmd_ra : std_logic_vector(14 downto 0);
+signal p0_cmd_ba : std_logic_vector(2 downto 0);
+signal p0_cmd_ca : std_logic_vector(11 downto 0);
+signal p1_cmd_ra : std_logic_vector(14 downto 0);
+signal p1_cmd_ba : std_logic_vector(2 downto 0);
+signal p1_cmd_ca : std_logic_vector(11 downto 0);
+signal p2_cmd_ra : std_logic_vector(14 downto 0);
+signal p2_cmd_ba : std_logic_vector(2 downto 0);
+signal p2_cmd_ca : std_logic_vector(11 downto 0);
+signal p3_cmd_ra : std_logic_vector(14 downto 0);
+signal p3_cmd_ba : std_logic_vector(2 downto 0);
+signal p3_cmd_ca : std_logic_vector(11 downto 0);
+signal p4_cmd_ra : std_logic_vector(14 downto 0);
+signal p4_cmd_ba : std_logic_vector(2 downto 0);
+signal p4_cmd_ca : std_logic_vector(11 downto 0);
+signal p5_cmd_ra : std_logic_vector(14 downto 0);
+signal p5_cmd_ba : std_logic_vector(2 downto 0);
+signal p5_cmd_ca : std_logic_vector(11 downto 0);
+
+   -- user command wires mapped from logical ports to physical ports
+signal mig_p0_arb_en            : std_logic;
+signal mig_p0_cmd_clk           : std_logic;
+signal mig_p0_cmd_en            : std_logic;
+signal mig_p0_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p0_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p0_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p0_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p0_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p0_cmd_empty         : std_logic;
+signal mig_p0_cmd_full          : std_logic;
+
+signal mig_p1_arb_en            : std_logic;
+signal mig_p1_cmd_clk           : std_logic;
+signal mig_p1_cmd_en            : std_logic;
+signal mig_p1_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p1_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p1_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p1_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p1_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p1_cmd_empty         : std_logic;
+signal mig_p1_cmd_full          : std_logic;
+
+signal mig_p2_arb_en            : std_logic;
+signal mig_p2_cmd_clk           : std_logic;
+signal mig_p2_cmd_en            : std_logic;
+signal mig_p2_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p2_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p2_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p2_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p2_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p2_cmd_empty         : std_logic;
+signal mig_p2_cmd_full          : std_logic;
+
+signal mig_p3_arb_en            : std_logic;
+signal mig_p3_cmd_clk           : std_logic;
+signal mig_p3_cmd_en            : std_logic;
+signal mig_p3_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p3_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p3_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p3_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p3_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p3_cmd_empty         : std_logic;
+signal mig_p3_cmd_full          : std_logic;
+
+signal mig_p4_arb_en            : std_logic;
+signal mig_p4_cmd_clk           : std_logic;
+signal mig_p4_cmd_en            : std_logic;
+signal mig_p4_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p4_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p4_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p4_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p4_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p4_cmd_empty         : std_logic;
+signal mig_p4_cmd_full          : std_logic;
+
+signal mig_p5_arb_en            : std_logic;
+signal mig_p5_cmd_clk           : std_logic;
+signal mig_p5_cmd_en            : std_logic;
+signal mig_p5_cmd_ra            : std_logic_vector(14 downto 0);
+signal mig_p5_cmd_ba            : std_logic_vector(2 downto 0);
+signal mig_p5_cmd_ca            : std_logic_vector(11 downto 0);
+
+signal mig_p5_cmd_instr         : std_logic_vector(2 downto 0);
+signal mig_p5_cmd_bl            : std_logic_vector(5 downto 0);
+signal mig_p5_cmd_empty         : std_logic;
+signal mig_p5_cmd_full          : std_logic;
+
+signal mig_p0_wr_clk            : std_logic;
+signal mig_p0_rd_clk            : std_logic;
+signal mig_p1_wr_clk            : std_logic;
+signal mig_p1_rd_clk            : std_logic;
+signal mig_p2_clk               : std_logic;
+signal mig_p3_clk               : std_logic;
+signal mig_p4_clk               : std_logic;
+signal mig_p5_clk               : std_logic;
+
+signal mig_p0_wr_en             : std_logic;
+signal mig_p0_rd_en             : std_logic;
+signal mig_p1_wr_en             : std_logic;
+signal mig_p1_rd_en             : std_logic;
+signal mig_p2_en                : std_logic;
+signal mig_p3_en                : std_logic;
+signal mig_p4_en                : std_logic;
+signal mig_p5_en                : std_logic;
+
+signal mig_p0_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p1_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p2_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p3_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p4_wr_data           : std_logic_vector(31 downto 0);
+signal mig_p5_wr_data           : std_logic_vector(31 downto 0);
+
+signal mig_p0_wr_mask           : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+signal mig_p1_wr_mask           : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+signal mig_p2_wr_mask           : std_logic_vector(3 downto 0);
+signal mig_p3_wr_mask           : std_logic_vector(3 downto 0);
+signal mig_p4_wr_mask           : std_logic_vector(3 downto 0);
+signal mig_p5_wr_mask           : std_logic_vector(3 downto 0);
+
+signal mig_p0_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p1_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p2_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p3_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p4_rd_data           : std_logic_vector(31 downto 0);
+signal mig_p5_rd_data           : std_logic_vector(31 downto 0);
+
+signal mig_p0_rd_overflow       : std_logic;
+signal mig_p1_rd_overflow       : std_logic;
+signal mig_p2_overflow          : std_logic;
+signal mig_p3_overflow          : std_logic;
+
+signal mig_p4_overflow          : std_logic;
+signal mig_p5_overflow          : std_logic;
+
+signal mig_p0_wr_underrun       : std_logic;
+signal mig_p1_wr_underrun       : std_logic;
+signal mig_p2_underrun          : std_logic;
+signal mig_p3_underrun          : std_logic;
+signal mig_p4_underrun          : std_logic;
+signal mig_p5_underrun          : std_logic;
+
+signal mig_p0_rd_error          : std_logic;
+signal mig_p0_wr_error          : std_logic;
+signal mig_p1_rd_error          : std_logic;
+signal mig_p1_wr_error          : std_logic;
+signal mig_p2_error             : std_logic;
+signal mig_p3_error             : std_logic;
+signal mig_p4_error             : std_logic;
+signal mig_p5_error             : std_logic;
+
+signal mig_p0_wr_count          : std_logic_vector(6 downto 0);
+signal mig_p1_wr_count          : std_logic_vector(6 downto 0);
+signal mig_p0_rd_count          : std_logic_vector(6 downto 0);
+signal mig_p1_rd_count          : std_logic_vector(6 downto 0);
+
+signal mig_p2_count             : std_logic_vector(6 downto 0);
+signal mig_p3_count             : std_logic_vector(6 downto 0);
+signal mig_p4_count             : std_logic_vector(6 downto 0);
+signal mig_p5_count             : std_logic_vector(6 downto 0);
+
+signal mig_p0_wr_full           : std_logic;
+signal mig_p1_wr_full           : std_logic;
+
+signal mig_p0_rd_empty          : std_logic;
+signal mig_p1_rd_empty          : std_logic;
+signal mig_p0_wr_empty          : std_logic;
+signal mig_p1_wr_empty          : std_logic;
+signal mig_p0_rd_full           : std_logic;
+signal mig_p1_rd_full           : std_logic;
+signal mig_p2_full              : std_logic;
+signal mig_p3_full              : std_logic;
+signal mig_p4_full              : std_logic;
+signal mig_p5_full              : std_logic;
+signal mig_p2_empty             : std_logic;
+signal mig_p3_empty             : std_logic;
+signal mig_p4_empty             : std_logic;
+signal mig_p5_empty             : std_logic;
+
+-- SELFREESH control signal for suspend feature
+signal selfrefresh_mcb_enter    : std_logic;
+signal selfrefresh_mcb_mode     : std_logic;
+signal selfrefresh_mode_sig     : std_logic;
+
+signal MCB_SYSRST : std_logic;
+signal ioclk0  : std_logic;
+signal ioclk90 : std_logic;
+signal hard_done_cal       : std_logic;
+signal uo_data_int         : std_logic_vector(7 downto 0);
+signal uo_data_valid_int   : std_logic;
+signal uo_cmd_ready_in_int : std_logic;
+signal syn_uiclk_pll_lock  : std_logic;
+signal int_sys_rst         : std_logic;
+
+--testing
+signal ioi_drp_update : std_logic;
+signal aux_sdi_sdo : std_logic_vector(7 downto 0);
+
+
+   signal mcb_recal                : std_logic;
+   signal mcb_ui_read              : std_logic;
+   signal mcb_ui_add               : std_logic;
+   signal mcb_ui_cs                : std_logic;
+   signal mcb_ui_clk               : std_logic;
+   signal mcb_ui_sdi               : std_logic;
+   signal mcb_ui_addr              : STD_LOGIC_vector(4 downto 0);
+   signal mcb_ui_broadcast         : std_logic;
+   signal mcb_ui_drp_update        : std_logic;
+   signal mcb_ui_done_cal          : std_logic;
+   signal mcb_ui_cmd               : std_logic;
+   signal mcb_ui_cmd_in            : std_logic;
+   signal mcb_ui_cmd_en            : std_logic;
+   signal mcb_ui_dqcount           : std_logic_vector(3 downto 0);
+   signal mcb_ui_dq_lower_dec      : std_logic;
+   signal mcb_ui_dq_lower_inc      : std_logic;
+   signal mcb_ui_dq_upper_dec      : std_logic;
+   signal mcb_ui_dq_upper_inc      : std_logic;
+   signal mcb_ui_udqs_inc          : std_logic;
+   signal mcb_ui_udqs_dec          : std_logic;
+   signal mcb_ui_ldqs_inc          : std_logic;
+   signal mcb_ui_ldqs_dec          : std_logic;
+   signal DONE_SOFTANDHARD_CAL     : std_logic;
+
+   signal ck_shiftout0_1           : std_logic;
+   signal ck_shiftout0_2           : std_logic;
+   signal ck_shiftout1_3           : std_logic;
+   signal ck_shiftout1_4           : std_logic;
+
+   signal udm_oq                   : std_logic;
+   signal udm_t                    : std_logic;
+   signal ldm_oq                   : std_logic;
+   signal ldm_t                    : std_logic;
+   signal dqsp_oq                  : std_logic;
+   signal dqsp_tq                  : std_logic;
+   signal dqs_shiftout0_1          : std_logic;
+   signal dqs_shiftout0_2          : std_logic;
+   signal dqs_shiftout1_3          : std_logic;
+   signal dqs_shiftout1_4          : std_logic;
+   signal dqsn_oq                  : std_logic;
+   signal dqsn_tq                  : std_logic;
+   signal udqsp_oq                 : std_logic;
+   signal udqsp_tq                 : std_logic;
+   signal udqs_shiftout0_1         : std_logic;
+   signal udqs_shiftout0_2         : std_logic;
+   signal udqs_shiftout1_3         : std_logic;
+   signal udqs_shiftout1_4         : std_logic;
+   signal udqsn_oq                 : std_logic;
+   signal udqsn_tq                 : std_logic;
+   signal aux_sdi_out_dqsp         : std_logic;
+   signal aux_sdi_out_udqsp        : std_logic;
+   signal aux_sdi_out_udqsn        : std_logic;
+   signal aux_sdi_out_0            : std_logic;
+   signal aux_sdi_out_1            : std_logic;
+   signal aux_sdi_out_2            : std_logic;
+   signal aux_sdi_out_3            : std_logic;
+   signal aux_sdi_out_5            : std_logic;
+   signal aux_sdi_out_6            : std_logic;
+   signal aux_sdi_out_7            : std_logic;
+   signal aux_sdi_out_9            : std_logic;
+   signal aux_sdi_out_10           : std_logic;
+   signal aux_sdi_out_11           : std_logic;
+   signal aux_sdi_out_12           : std_logic;
+   signal aux_sdi_out_13           : std_logic;
+   signal aux_sdi_out_14           : std_logic;
+   signal aux_sdi_out_15           : std_logic;
+   signal aux_sdi_out_8            : std_logic;
+   signal aux_sdi_out_dqsn         : std_logic;
+   signal aux_sdi_out_4            : std_logic;
+   signal aux_sdi_out_udm          : std_logic;
+   signal aux_sdi_out_ldm          : std_logic;
+   signal uo_cal_start_int         : std_logic;
+ 
+   signal cke_train                : std_logic;
+   signal dq_oq                    : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+   signal dq_tq                    : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+
+   signal p0_wr_full_i             : std_logic;
+   signal p0_rd_empty_i            : std_logic;
+   signal p1_wr_full_i             : std_logic;
+   signal p1_rd_empty_i            : std_logic;
+   signal pllclk1                  : std_logic_vector(1 downto 0);
+   signal pllce1                   : std_logic_vector(1 downto 0);
+   signal uo_refrsh_flag_xhdl23    : std_logic;
+   signal uo_sdo_xhdl24            : STD_LOGIC;
+   signal Max_Value_Cal_Error      : std_logic;
+   signal uo_done_cal_sig          : std_logic;
+   signal wait_200us_counter       : std_logic_vector(15 downto 0);
+   signal cke_train_reg            : std_logic;        
+   signal wait_200us_done_r1       : std_logic;
+   signal wait_200us_done_r2       : std_logic;
+   signal syn1_sys_rst             : std_logic;
+   signal syn2_sys_rst             : std_logic;
+   signal selfrefresh_enter_r1     : std_logic;
+   signal selfrefresh_enter_r2     : std_logic;
+   signal selfrefresh_enter_r3     : std_logic;
+   signal gated_pll_lock           : std_logic;
+   signal soft_cal_selfrefresh_req : std_logic;
+   signal normal_operation_window  : std_logic;
+
+   attribute max_fanout            : string;
+   attribute syn_maxfan            : integer;
+   attribute max_fanout of int_sys_rst : signal is "1";
+   attribute syn_maxfan of int_sys_rst : signal is 1;
+
+begin
+   uo_cmd_ready_in   <= uo_cmd_ready_in_int;
+   uo_data_valid     <= uo_data_valid_int;
+   uo_data           <= uo_data_int;
+   uo_refrsh_flag    <= uo_refrsh_flag_xhdl23;
+   uo_sdo            <= uo_sdo_xhdl24;
+
+   p0_wr_full        <= p0_wr_full_i;
+   p0_rd_empty       <= p0_rd_empty_i;
+   p1_wr_full        <= p1_wr_full_i;
+   p1_rd_empty       <= p1_rd_empty_i;
+   ioclk0            <= sysclk_2x;
+   ioclk90           <= sysclk_2x_180;
+   pllclk1           <= (ioclk90 & ioclk0);
+   pllce1            <= (pll_ce_90 & pll_ce_0);
+
+   -- Assign the output signals with corresponding intermediate signals
+   uo_done_cal       <= uo_done_cal_sig;
+
+   -- Added 2/22 - Add flop to pll_lock status signal to improve timing
+   process (ui_clk)
+   begin
+      if (ui_clk'event and ui_clk = '1') then      
+        if ((selfrefresh_enter = '0') and (gated_pll_lock = '0')) then
+         syn_uiclk_pll_lock <= pll_lock;
+        end if;
+      end if;
+   end process;               
+
+   -- logic to determine if Memory  is SELFREFRESH mode operation or NORMAL  mode.
+   process (ui_clk)
+   begin
+      if (ui_clk'event and ui_clk = '1') then      
+        if (sys_rst = '1') then  
+           normal_operation_window <= '1';
+        elsif (selfrefresh_enter_r2 = '1' or selfrefresh_mode_sig = '1') then
+           normal_operation_window <= '0';
+        elsif ((selfrefresh_enter_r2 = '0') and  (selfrefresh_mode_sig = '0')) then
+           normal_operation_window <= '1';
+        else
+           normal_operation_window <= normal_operation_window;
+        end if;
+      end if;
+   end process;   
+   
+   
+   process(normal_operation_window,pll_lock,syn_uiclk_pll_lock)
+   begin
+     if (normal_operation_window = '1') then
+      gated_pll_lock <= pll_lock;
+     else
+      gated_pll_lock <= syn_uiclk_pll_lock;
+     end if;
+   end process;
+
+-- int_sys_rst will be asserted if pll lose lock during normal operation.
+-- It uses the syn_uiclk_pll_lock version when it is entering suspend window , hence
+-- reset will not be generated. 
+
+   int_sys_rst <=  sys_rst or not(gated_pll_lock);
+
+-- synchronize the selfrefresh_enter 
+   process (ui_clk)
+   begin
+      if (ui_clk'event and ui_clk = '1') then      
+        if (sys_rst = '1') then
+          selfrefresh_enter_r1 <= '0';
+          selfrefresh_enter_r2 <= '0';
+          selfrefresh_enter_r3 <= '0';
+        else
+          selfrefresh_enter_r1 <= selfrefresh_enter;
+          selfrefresh_enter_r2 <= selfrefresh_enter_r1;
+          selfrefresh_enter_r3 <= selfrefresh_enter_r2;
+        end if;
+      end if;
+    end process;
+
+
+
+--  The soft_cal_selfrefresh siganl is conditioned before connect to mcb_soft_calibration module.
+--  It will not deassert selfrefresh_mcb_enter to MCB until input pll_lock reestablished in system.
+--  This is to ensure the IOI stables before issued a selfrefresh exit command to dram.
+   process (ui_clk)
+   begin
+      if (ui_clk'event and ui_clk = '1') then      
+        if (sys_rst = '1') then
+          soft_cal_selfrefresh_req <= '0';
+        elsif (selfrefresh_enter_r3 = '1') then
+          soft_cal_selfrefresh_req <= '1';
+        elsif (selfrefresh_enter_r3 = '0' and pll_lock = '1') then 
+          soft_cal_selfrefresh_req <= '0';
+        else
+          soft_cal_selfrefresh_req <= soft_cal_selfrefresh_req;
+        end if;
+      end if;
+    end process;
+  
+
+--Address Remapping
+-- Byte Address remapping
+-- 
+-- Bank Address[x:0] & Row Address[x:0]  & Column Address[x:0]
+-- column address remap for port 0
+
+x16_addr        : if(C_NUM_DQ_PINS = 16) generate  --  port bus remapping sections for CONFIG 2   15,3,12
+x16_addr_rbc    : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row  Column
+
+-- port 0 address remapping
+                
+ x16_p0_a15     : if (C_MEM_ADDR_WIDTH = 15) generate
+                   p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+                end generate;
+
+ x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
+                   p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1)); 
+                   end generate;
+                      
+
+ x16_p0_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p0_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p0_cmd_ba <=  (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  + C_MEM_NUM_COL_BITS + 1));
+                end generate;
+
+                
+ x16_p0_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+                end generate;
+
+ x16_p0_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p0_cmd_ca <=  (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+                end generate;
+
+-- port 1 address remapping
+  
+ x16_p1_a15     : if (C_MEM_ADDR_WIDTH = 15) generate  --Row  
+                        p1_cmd_ra <=  p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+                end generate;
+
+ x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                        p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                            
+                   end generate;
+                      
+
+ x16_p1_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p1_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  + C_MEM_NUM_COL_BITS + 1));
+
+                end generate;
+
+                
+ x16_p1_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+                end generate;
+
+ x16_p1_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+                end generate;
+
+ -- port 2 address remapping
+ x16_p2_a15     : if (C_MEM_ADDR_WIDTH = 15) generate --Row  
+                         p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+                end generate;
+
+ x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                         p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                         
+                   end generate;
+                      
+
+ x16_p2_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p2_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                         p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1));
+                end generate;
+
+                
+ x16_p2_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                         p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+                end generate;
+
+ x16_p2_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                         p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+                end generate;
+                
+
+-- port 3 address remapping
+ x16_p3_a15     : if (C_MEM_ADDR_WIDTH = 15) generate --Row  
+                         p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+
+                end generate;
+
+ x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                        p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                         
+                   end generate;
+                      
+
+ x16_p3_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+
+                end generate;
+
+ x16_p3_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                         p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  + C_MEM_NUM_COL_BITS + 1));
+
+                end generate;
+
+                
+ x16_p3_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+                end generate;
+
+ x16_p3_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+                end generate;
+                
+                
+
+
+ -- port 4 address remapping
+                
+  x16_p4_a15    : if (C_MEM_ADDR_WIDTH = 15) generate --Row  
+                        p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+
+                end generate;
+
+ x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                        p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                         
+                   end generate;
+                      
+
+ x16_p4_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p4_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  C_MEM_NUM_COL_BITS + 1));
+                end generate;
+
+                
+ x16_p4_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+                end generate;
+
+ x16_p4_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+                end generate;
+               
+
+
+-- port 5 address remapping
+  x16_p5_a15    : if (C_MEM_ADDR_WIDTH = 15) generate --Row  
+                          p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);                         
+                end generate;
+
+ x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row  
+                         p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS + 1));                         
+                   end generate;
+                      
+
+ x16_p5_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto   C_MEM_NUM_COL_BITS + 1);
+                end generate;
+
+ x16_p5_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                         p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +   C_MEM_NUM_COL_BITS   downto  + C_MEM_NUM_COL_BITS + 1));
+                end generate;
+
+                
+ x16_p5_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                        p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+                end generate;
+
+ x16_p5_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                        p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+                end generate;
+end generate;   --x16_addr_rbc            
+                
+x16_addr_rbc_n  : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate 
+                
+                
+ -- port 0 address remapping
+
+x16_rbc_n_p0_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+               end generate;
+
+x16_rbc_n_p0_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+               end generate;
+
+x16_rbc_n_p0_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1);                         
+               end generate;
+
+x16_rbc_n_p0_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1));                         
+               end generate;
+
+x16_rbc_n_p0_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+               end generate;
+
+x16_rbc_n_p0_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+               end generate;
+                
+
+                
+
+
+-- port 1 address remapping
+ x16_rbc_n_p1_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+               end generate;
+
+x16_rbc_n_p1_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+               end generate;
+
+x16_rbc_n_p1_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1);                         
+               end generate;
+
+x16_rbc_n_p1_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1));                         
+               end generate;
+
+x16_rbc_n_p1_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+               end generate;
+
+x16_rbc_n_p1_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS  downto 1));
+               end generate;
+
+
+
+ -- port 2 address remapping
+x16_rbc_n_p2_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+               end generate;
+
+x16_rbc_n_p2_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p2_cmd_ba <= (allzero(2  downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+
+               end generate;
+
+x16_rbc_n_p2_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS    downto C_MEM_NUM_COL_BITS + 1);                         
+
+               end generate;
+
+x16_rbc_n_p2_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p2_cmd_ra <= (allzero(14  downto C_MEM_ADDR_WIDTH) &  p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS    downto C_MEM_NUM_COL_BITS + 1));    
+               end generate;
+
+x16_rbc_n_p2_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS  downto 1);
+
+               end generate;
+
+x16_rbc_n_p2_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS  downto 1));
+
+               end generate;
+
+
+ -- port 3 address remapping
+x16_rbc_n_p3_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+
+               end generate;
+
+x16_rbc_n_p3_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p3_cmd_ba <= (allzero(2  downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS   downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+
+               end generate;
+
+x16_rbc_n_p3_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS    downto C_MEM_NUM_COL_BITS + 1);                         
+
+               end generate;
+
+x16_rbc_n_p3_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p3_cmd_ra <= (allzero(14  downto C_MEM_ADDR_WIDTH) &  p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS    downto C_MEM_NUM_COL_BITS + 1));                         
+
+               end generate;
+
+x16_rbc_n_p3_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS  downto 1);
+
+               end generate;
+
+x16_rbc_n_p3_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+               end generate;
+
+
+ -- port 4 address remapping
+x16_rbc_n_p4_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+
+               end generate;
+
+x16_rbc_n_p4_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+
+               end generate;
+
+x16_rbc_n_p4_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1);                         
+
+               end generate;
+
+x16_rbc_n_p4_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1));                         
+               end generate;
+
+x16_rbc_n_p4_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+               end generate;
+
+x16_rbc_n_p4_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+               end generate;
+
+ -- port 5 address remapping
+x16_rbc_n_p5_ba3 :  if (C_MEM_BANKADDR_WIDTH  = 3 ) generate  --Bank
+                        p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
+
+               end generate;
+
+x16_rbc_n_p5_ba3_n :  if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate  --Bank
+                        p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS  downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
+
+               end generate;
+
+x16_rbc_n_p5_a15 :  if (C_MEM_ADDR_WIDTH  = 15 ) generate  --row
+                        p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1);                         
+               end generate;
+
+x16_rbc_n_p5_a15_n :  if (not(C_MEM_ADDR_WIDTH  = 15 )) generate  --row
+                        p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) &  p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS   downto C_MEM_NUM_COL_BITS + 1));                         
+
+               end generate;
+
+x16_rbc_n_p5_c12 :  if (C_MEM_NUM_COL_BITS  = 12 ) generate  --column
+                        p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
+
+               end generate;
+
+x16_rbc_n_p5_c12_n :  if (not(C_MEM_NUM_COL_BITS  = 12 )) generate  --column
+                        p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
+
+               end generate;
+ end generate;--x16_addr_rbc_n
+end generate; --x16_addr
+
+
+
+
+
+
+x8_addr : if(C_NUM_DQ_PINS = 8) generate
+x8_addr_rbc     : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate 
+-- port 0 address remapping
+
+x8_p0_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                           p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p0_cmd_ra <= (allzero(14  downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p0_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                           p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p0_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                           p0_cmd_ba <= (allzero(2  downto C_MEM_BANKADDR_WIDTH)&  
+                                   p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p0_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p0_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p0_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+
+                 
+                 
+-- port 1 address remapping
+ x8_p1_a15      : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p1_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p1_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p1_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p1_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p1_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p1_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                           p1_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                 
+                
+ -- port 2 address remapping
+  x8_p2_a15     : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                             p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p2_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p2_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p2_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p2_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,2,10  ***
+
+                end generate;
+
+                
+ x8_p2_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p2_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p2_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                 
+
+
+--   port 3 address remapping
+ x8_p3_a15      : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p3_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p3_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p3_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p3_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p3_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p3_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p3_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                
+--   port 4 address remapping
+ x8_p4_a15      : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p4_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p4_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p4_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p4_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p4_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p4_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p4_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                  
+
+ --   port 5 address remapping
+  x8_p5_a15     : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                           p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p5_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+                      
+
+ x8_p5_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto   C_MEM_NUM_COL_BITS );  --14,3,10
+
+                end generate;
+
+ x8_p5_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p5_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_NUM_COL_BITS ));  --14,3,10
+
+                end generate;
+
+                
+ x8_p5_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_p5_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p5_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+  end generate; --x8_addr_rbc
+
+
+                 
+x8_addr_rbc_n   : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate 
+ -- port 0 address remapping
+  x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                             p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p0_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p0_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+
+                end generate;
+
+ x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p0_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));                
+
+                   end generate;
+
+                
+ x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p0_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+
+ -- port 1 address remapping
+  x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                             p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p1_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p1_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+
+                end generate;
+
+ x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p1_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p1_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+                
+--port 2 address remapping
+ x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                         p2_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                        p2_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS  ));  
+
+                end generate;
+
+ x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p2_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p2_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+
+ -- port 3 address remapping
+  x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                             p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p3_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p3_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+
+                end generate;
+
+ x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p3_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p3_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+   
+   
+--   port 4 address remapping
+ x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &  
+                                   p4_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+                end generate;
+
+ x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p4_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p4_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+
+
+--   port 5 address remapping
+ x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                            p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS );  
+
+                end generate;
+
+ x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                            p5_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH)&  
+                                   p5_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1  downto  C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS ));  
+
+                end generate;
+
+ x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                            p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH  + C_MEM_NUM_COL_BITS - 1   downto   C_MEM_NUM_COL_BITS );
+
+                end generate;
+
+ x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                            p5_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH  +  C_MEM_NUM_COL_BITS - 1   downto  C_MEM_NUM_COL_BITS ));
+
+                   end generate;
+
+                
+ x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                            p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0);
+
+                end generate;
+
+ x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                            p5_cmd_ca(11 downto 0) <= (allzero(11  downto  C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1  downto  0));
+
+                end generate;
+  end generate; --x8_addr_rbc_n
+ end generate;  --x8_addr
+             
+
+
+
+
+
+
+
+
+x4_addr : if(C_NUM_DQ_PINS = 4) generate
+x4_addr_rbc     : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate 
+
+--   port 0 address remapping
+x4_p0_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p0_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+ x4_p0_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p0_cmd_ba <=  p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p0_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p0_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+ x4_p0_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+ x4_p0_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p0_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+               
+           
+--   port 1 address remapping
+x4_p1_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p1_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+ x4_p1_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p1_cmd_ba <=  p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p1_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p1_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+ x4_p1_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+ x4_p1_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p1_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+
+
+--   port 2 address remapping
+x4_p2_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p2_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+                   end generate;
+                      
+
+ x4_p2_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p2_cmd_ba <=  p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p2_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p2_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+ x4_p2_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+ x4_p2_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p2_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+
+
+--   port 3 address remapping
+x4_p3_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p3_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+ x4_p3_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                        p3_cmd_ba <=  p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+ x4_p3_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p3_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+ x4_p3_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+ x4_p3_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p3_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+
+
+
+
+ 
+
+ x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
+             ) generate
+--   port 4 address remapping
+ 
+x4_p4_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                      p4_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+x4_p4_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                       p4_cmd_ba <=  p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+x4_p4_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                       p4_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+x4_p4_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                      p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+x4_p4_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                      p4_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+--   port 5 address remapping
+               
+
+x4_p5_a15       : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                      p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                      p5_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto  C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
+
+                   end generate;
+                      
+
+x4_p5_ba3 :       if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                       p5_cmd_ba <=  p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1);
+
+                end generate;
+
+x4_p5_ba3_n :   if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                       p5_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2  downto   C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+                
+x4_p5_ca12 :     if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                      p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');                                --14,3,11
+
+                end generate;
+
+x4_p5_ca12_n :     if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                      p5_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+                end generate;
+     end generate; --x4_p4_p5
+ end generate; --x4_addr_rbc
+
+
+
+              
+x4_addr_rbc_n   : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate 
+            
+--   port 0 address remapping
+  x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p0_cmd_ba <=  p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+                end generate;
+
+ x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p0_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+                end generate;
+
+ x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+                end generate;
+
+ x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p0_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+                   end generate;
+
+                
+ x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+                end generate;
+
+ x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p0_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+                end generate;
+               
+           
+--   port 1 address remapping
+  x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p1_cmd_ba <=  p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p1_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p1_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p1_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+            
+--   port 2 address remapping
+  x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p2_cmd_ba <=  p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p2_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p2_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p2_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+            
+--   port 3 address remapping
+  x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p3_cmd_ba <=  p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p3_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p3_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p3_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+            
+
+  x4_p4_p5_n:  if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+             C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
+             ) generate
+--   port 4 address remapping
+
+  x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p4_cmd_ba <=  p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p4_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p4_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p4_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+               end generate;
+            
+ 
+--   port 5 address remapping
+
+  x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH  = 3 ) generate --Bank
+                         p5_cmd_ba <=  p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH  = 3 )) generate --Bank
+                        p5_cmd_ba <= (allzero(2  downto  C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 1));
+
+                end generate;
+
+ x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
+                       p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1);
+
+
+                end generate;
+
+ x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
+                       p5_cmd_ra <= (allzero(14  downto  C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH +  C_MEM_NUM_COL_BITS - 2  downto  C_MEM_NUM_COL_BITS - 1));
+
+
+                   end generate;
+
+                
+ x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12)  generate --Column
+                       p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+
+ x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12))  generate --Column
+                       p5_cmd_ca <= (allzero(11  downto  C_MEM_NUM_COL_BITS ) &  p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2  downto  0) & '0');
+
+
+                end generate;
+            
+end generate;  --x4_p4_p5_n
+
+end generate; --x4_addr_rbc_n
+end generate; --x4_addr
+
+
+
+
+   --  if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
+u_config1_0:   if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
+      ) generate  
+
+  --synthesis translate_off 
+  -- PORT2
+  process (p2_cmd_en,p2_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and 
+      p2_cmd_en = '1' and  p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1')  then
+      report "ERROR - Invalid Command for write only port 2";
+    end if;
+  end process;
+
+  process (p2_cmd_en,p2_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and 
+      p2_cmd_en = '1' and  p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0')  then
+      report "ERROR - Invalid Command for read only port 2";
+    end if;
+  end process;
+
+  -- PORT3
+  process (p3_cmd_en,p3_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and 
+      p3_cmd_en = '1' and  p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1')  then
+      report "ERROR - Invalid Command for write only port 3";
+    end if;
+  end process;
+
+  process (p3_cmd_en,p3_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and 
+      p3_cmd_en = '1' and  p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0')  then
+      report "ERROR - Invalid Command for read only port 3";
+    end if;
+  end process;
+
+  -- PORT4
+  process (p4_cmd_en,p4_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and 
+      p4_cmd_en = '1' and  p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1')  then
+      report "ERROR - Invalid Command for write only port 4";
+    end if;
+  end process;
+
+  process (p4_cmd_en,p4_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and 
+      p4_cmd_en = '1' and  p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0')  then
+      report "ERROR - Invalid Command for read only port 4";
+    end if;
+  end process;
+
+  -- PORT5
+  process (p5_cmd_en,p5_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and 
+      p5_cmd_en = '1' and  p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1')  then
+      report "ERROR - Invalid Command for write only port 5";
+    end if;
+  end process;
+
+  process (p5_cmd_en,p5_cmd_instr)
+  begin
+    if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and 
+      p5_cmd_en = '1' and  p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0')  then
+      report "ERROR - Invalid Command for read only port 5";
+    end if;
+  end process;
+
+
+
+ 
+   --synthesis translate_on 
+ 
+
+ -- the local declaration of input port signals doesn't work.  The mig_p1_xxx through mig_p5_xxx always ends up
+ -- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
+ -- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
+ --
+
+              -- Inputs from Application CMD Port
+
+   p0_cmd_ena:  if (C_PORT_ENABLE(0) = '1') generate
+
+                    mig_p0_arb_en      <=      p0_arb_en ;
+                    mig_p0_cmd_clk     <=      p0_cmd_clk  ;
+                    mig_p0_cmd_en      <=      p0_cmd_en   ;
+                    mig_p0_cmd_ra      <=      p0_cmd_ra  ;
+                    mig_p0_cmd_ba      <=      p0_cmd_ba   ;
+                    mig_p0_cmd_ca      <=      p0_cmd_ca  ;
+                    mig_p0_cmd_instr   <=      p0_cmd_instr;
+                    mig_p0_cmd_bl      <=      ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;
+                    p0_cmd_empty       <=      mig_p0_cmd_empty;
+                    p0_cmd_full        <=      mig_p0_cmd_full ;
+   end generate;   
+   
+      p0_cmd_dis:  if (C_PORT_ENABLE(0) = '0') generate
+                    mig_p0_arb_en      <=     '0';
+                    mig_p0_cmd_clk     <=     '0';
+                    mig_p0_cmd_en      <=     '0';
+                    mig_p0_cmd_ra      <=     (others => '0');
+                    mig_p0_cmd_ba      <=     (others => '0');
+                    mig_p0_cmd_ca      <=     (others => '0');
+                    mig_p0_cmd_instr   <=     (others => '0');
+                    mig_p0_cmd_bl      <=     (others => '0');
+                    p0_cmd_empty       <=     '0';
+                    p0_cmd_full        <=     '0';
+                   
+   end generate;   
+               
+   p1_cmd_ena:  if (C_PORT_ENABLE(1) = '1') generate
+                    mig_p1_arb_en      <=      p1_arb_en ;
+                    mig_p1_cmd_clk     <=      p1_cmd_clk  ;
+                    mig_p1_cmd_en      <=      p1_cmd_en   ;
+                    mig_p1_cmd_ra      <=      p1_cmd_ra  ;
+                    mig_p1_cmd_ba      <=      p1_cmd_ba   ;
+                    mig_p1_cmd_ca      <=      p1_cmd_ca  ;
+                    mig_p1_cmd_instr   <=      p1_cmd_instr;
+                    mig_p1_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           
+                    p1_cmd_empty       <=      mig_p1_cmd_empty;
+                    p1_cmd_full        <=      mig_p1_cmd_full ;
+   end generate;   
+                   
+   p1_cmd_dis:  if (C_PORT_ENABLE(1) = '0') generate
+   
+                   mig_p1_arb_en      <=     '0';
+                    mig_p1_cmd_clk     <=     '0';
+                    mig_p1_cmd_en      <=     '0';
+                    mig_p1_cmd_ra      <=     (others => '0');
+                    mig_p1_cmd_ba      <=     (others => '0');
+                    mig_p1_cmd_ca      <=     (others => '0');
+                    mig_p1_cmd_instr   <=     (others => '0');
+                    mig_p1_cmd_bl      <=     (others => '0');
+                    p1_cmd_empty       <=      '0';
+                    p1_cmd_full        <=      '0';
+   end generate;                      
+
+               
+   p2_cmd_ena:  if (C_PORT_ENABLE(2) = '1') generate
+                    mig_p2_arb_en      <=      p2_arb_en ;
+                    mig_p2_cmd_clk     <=      p2_cmd_clk  ;
+                    mig_p2_cmd_en      <=      p2_cmd_en   ;
+                    mig_p2_cmd_ra      <=      p2_cmd_ra  ;
+                    mig_p2_cmd_ba      <=      p2_cmd_ba   ;
+                    mig_p2_cmd_ca      <=      p2_cmd_ca  ;
+                    mig_p2_cmd_instr   <=      p2_cmd_instr;
+                    mig_p2_cmd_bl      <=      ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0))  ;                           
+
+                    p2_cmd_empty   <=      mig_p2_cmd_empty;
+                    p2_cmd_full    <=      mig_p2_cmd_full ;
+    end generate;   
+                   
+   p2_cmd_dis:  if (C_PORT_ENABLE(2) = '0') generate
+                    mig_p2_arb_en      <=       '0';
+                    mig_p2_cmd_clk      <=       '0';
+                    mig_p2_cmd_en      <=       '0';
+                    mig_p2_cmd_ra      <=      (others => '0');
+                    mig_p2_cmd_ba      <=      (others => '0');
+                    mig_p2_cmd_ca      <=      (others => '0');
+                    mig_p2_cmd_instr   <=      (others => '0');
+                    mig_p2_cmd_bl      <=      (others => '0');
+                    p2_cmd_empty      <=       '0';
+                    p2_cmd_full      <=       '0';
+    end generate;   
+               
+   p3_cmd_ena:  if (C_PORT_ENABLE(3) = '1') generate
+
+                    mig_p3_arb_en    <=        p3_arb_en ;
+                    mig_p3_cmd_clk     <=      p3_cmd_clk  ;
+                    mig_p3_cmd_en      <=      p3_cmd_en   ;
+                    mig_p3_cmd_ra      <=      p3_cmd_ra  ;
+                    mig_p3_cmd_ba      <=      p3_cmd_ba   ;
+                    mig_p3_cmd_ca      <=      p3_cmd_ca  ;
+                    mig_p3_cmd_instr   <=      p3_cmd_instr;
+                    mig_p3_cmd_bl      <=      ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0))  ;                           
+                    p3_cmd_empty   <=      mig_p3_cmd_empty;
+                    p3_cmd_full    <=      mig_p3_cmd_full ;
+     end generate;   
+                   
+   p3_cmd_dis:  if (C_PORT_ENABLE(3) = '0') generate
+                    mig_p3_arb_en    <=       '0';
+                    mig_p3_cmd_clk     <=     '0';
+                    mig_p3_cmd_en      <=     '0';
+                    mig_p3_cmd_ra      <=     (others => '0');
+                    mig_p3_cmd_ba      <=     (others => '0');
+                    mig_p3_cmd_ca      <=     (others => '0');
+                    mig_p3_cmd_instr   <=     (others => '0');
+                    mig_p3_cmd_bl      <=     (others => '0');
+                    p3_cmd_empty      <=       '0';
+                    p3_cmd_full    <=     '0';
+     end generate;   
+
+               
+    p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
+
+                    mig_p4_arb_en    <=        p4_arb_en ;
+                    mig_p4_cmd_clk     <=      p4_cmd_clk  ;
+                    mig_p4_cmd_en      <=      p4_cmd_en   ;
+                    mig_p4_cmd_ra      <=      p4_cmd_ra  ;
+                    mig_p4_cmd_ba      <=      p4_cmd_ba   ;
+                    mig_p4_cmd_ca      <=      p4_cmd_ca  ;
+                    mig_p4_cmd_instr   <=      p4_cmd_instr;
+                    mig_p4_cmd_bl      <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0))  ;                           
+
+                    p4_cmd_empty   <=      mig_p4_cmd_empty;
+                    p4_cmd_full    <=      mig_p4_cmd_full ;
+end generate;
+
+    p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
+
+                    mig_p4_arb_en      <=       '0';
+                    mig_p4_cmd_clk      <=       '0';
+                    mig_p4_cmd_en      <=       '0';
+                    mig_p4_cmd_ra      <=      (others => '0');
+                    mig_p4_cmd_ba      <=      (others => '0');
+                    mig_p4_cmd_ca      <=      (others => '0');
+                    mig_p4_cmd_instr   <=      (others => '0');
+                    mig_p4_cmd_bl      <=      (others => '0');
+                    p4_cmd_empty      <=       '0';
+                    p4_cmd_full    <=      '0';
+end generate;
+                   
+    p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
+                     mig_p5_arb_en    <=     p5_arb_en ;
+                     mig_p5_cmd_clk   <=     p5_cmd_clk  ;
+                     mig_p5_cmd_en    <=     p5_cmd_en   ;
+                     mig_p5_cmd_ra    <=     p5_cmd_ra  ;
+                     mig_p5_cmd_ba    <=     p5_cmd_ba   ;
+                     mig_p5_cmd_ca    <=     p5_cmd_ca  ;
+                     mig_p5_cmd_instr <=     p5_cmd_instr;
+                     mig_p5_cmd_bl    <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0))  ;                           
+
+                    p5_cmd_empty   <=     mig_p5_cmd_empty;
+                    p5_cmd_full    <=     mig_p5_cmd_full ;
+                   
+end generate;
+
+    p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
+
+                     mig_p5_arb_en     <=   '0';
+                     mig_p5_cmd_clk    <=   '0';
+                     mig_p5_cmd_en     <=   '0';
+                     mig_p5_cmd_ra     <=   (others => '0');
+                     mig_p5_cmd_ba     <=   (others => '0');
+                     mig_p5_cmd_ca     <=   (others => '0');
+                    mig_p5_cmd_instr   <=   (others => '0');
+                    mig_p5_cmd_bl      <=   (others => '0');
+                    p5_cmd_empty      <=       '0';
+                    p5_cmd_full    <=     '0';
+end generate;
+
+
+
+p0_wr_rd_ena:  if (C_PORT_ENABLE(0) = '1') generate
+                 mig_p0_wr_clk   <= p0_wr_clk;
+                 mig_p0_rd_clk   <= p0_rd_clk;
+                 mig_p0_wr_en    <= p0_wr_en;
+                 mig_p0_rd_en    <= p0_rd_en;
+                 mig_p0_wr_mask  <= p0_wr_mask(3 downto 0);
+                 mig_p0_wr_data  <= p0_wr_data(31 downto 0);
+                 p0_rd_data        <= mig_p0_rd_data;
+                 p0_rd_full        <= mig_p0_rd_full;
+                 p0_rd_empty_i       <= mig_p0_rd_empty;
+                 p0_rd_error       <= mig_p0_rd_error;
+                 p0_wr_error       <= mig_p0_wr_error;
+                 p0_rd_overflow    <= mig_p0_rd_overflow;
+                 p0_wr_underrun    <= mig_p0_wr_underrun;
+                 p0_wr_empty       <= mig_p0_wr_empty;
+                 p0_wr_full_i        <= mig_p0_wr_full;
+                 p0_wr_count       <= mig_p0_wr_count;
+                 p0_rd_count       <= mig_p0_rd_count  ; 
+end generate;                
+p0_wr_rd_dis:  if (C_PORT_ENABLE(0) = '0') generate
+                 mig_p0_wr_clk     <= '0';
+                 mig_p0_rd_clk     <= '0';
+                 mig_p0_wr_en      <= '0';
+                 mig_p0_rd_en      <= '0';
+                 mig_p0_wr_mask    <= (others => '0');
+                 mig_p0_wr_data    <= (others => '0');
+                 p0_rd_data        <= (others => '0');
+                 p0_rd_full        <= '0';
+                 p0_rd_empty_i       <= '0';
+                 p0_rd_error       <= '0';
+                 p0_wr_error       <= '0';
+                 p0_rd_overflow    <= '0';
+                 p0_wr_underrun    <= '0';
+                 p0_wr_empty       <= '0';
+                 p0_wr_full_i        <= '0';
+                 p0_wr_count       <= (others => '0');
+                 p0_rd_count       <= (others => '0');
+end generate;                  
+              
+p1_wr_rd_ena:  if (C_PORT_ENABLE(1) = '1') generate
+              
+                 mig_p1_wr_clk   <= p1_wr_clk;
+                 mig_p1_rd_clk   <= p1_rd_clk;                
+                 mig_p1_wr_en    <= p1_wr_en;
+                 mig_p1_wr_mask  <= p1_wr_mask(3 downto 0);                
+                 mig_p1_wr_data  <= p1_wr_data(31 downto 0);
+                 mig_p1_rd_en    <= p1_rd_en;
+                 p1_rd_data     <= mig_p1_rd_data;
+                 p1_rd_empty_i    <= mig_p1_rd_empty;
+                 p1_rd_full     <= mig_p1_rd_full;
+                 p1_rd_error    <= mig_p1_rd_error;
+                 p1_wr_error    <= mig_p1_wr_error;
+                 p1_rd_overflow <= mig_p1_rd_overflow;
+                 p1_wr_underrun    <= mig_p1_wr_underrun;
+                 p1_wr_empty    <= mig_p1_wr_empty;
+                 p1_wr_full_i    <= mig_p1_wr_full;
+                 p1_wr_count  <= mig_p1_wr_count;
+                 p1_rd_count  <= mig_p1_rd_count  ; 
+                
+end generate;                
+p1_wr_rd_dis:  if (C_PORT_ENABLE(1) = '0') generate
+              
+                 mig_p1_wr_clk   <= '0';
+                 mig_p1_rd_clk   <= '0';           
+                 mig_p1_wr_en    <= '0';
+                 mig_p1_wr_mask  <= (others => '0');          
+                 mig_p1_wr_data  <= (others => '0');
+                 mig_p1_rd_en    <= '0';
+                 p1_rd_data     <=  (others => '0');
+                 p1_rd_empty_i    <=  '0';
+                 p1_rd_full     <=  '0';
+                 p1_rd_error    <=  '0';
+                 p1_wr_error    <=  '0';
+                 p1_rd_overflow <=  '0';
+                 p1_wr_underrun <=  '0';
+                 p1_wr_empty    <=  '0';
+                 p1_wr_full_i     <=  '0';
+                 p1_wr_count    <=  (others => '0');
+                 p1_rd_count    <=  (others => '0');
+end generate;                  
+end generate;
+                
+                
+
+
+--whenever PORT 2 is in Write mode     
+--      xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
+--u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
+
+u_config1_2W: if(    C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
+  ) generate
+
+p2_wr_ena:    if (C_PORT_ENABLE(2) = '1') generate
+                        mig_p2_clk      <= p2_wr_clk;
+                        mig_p2_wr_data  <= p2_wr_data(31 downto 0);
+                        mig_p2_wr_mask  <= p2_wr_mask(3 downto 0);
+                        mig_p2_en       <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
+                        p2_wr_error     <= mig_p2_error;                       
+                        p2_wr_full      <= mig_p2_full;
+                        p2_wr_empty     <= mig_p2_empty;
+                        p2_wr_underrun  <= mig_p2_underrun;
+                        p2_wr_count     <= mig_p2_count  ;-- wr port
+ end generate;                      
+p2_wr_dis:    if (C_PORT_ENABLE(2) = '0') generate
+                        mig_p2_clk      <= '0';
+                        mig_p2_wr_data  <= (others => '0');
+                        mig_p2_wr_mask  <= (others => '0');
+                        mig_p2_en       <= '0';
+                        p2_wr_error     <= '0';
+                        p2_wr_full      <= '0';
+                        p2_wr_empty     <= '0';
+                        p2_wr_underrun  <= '0';
+                        p2_wr_count     <= (others => '0');
+end generate;                                                
+                    p2_rd_data        <= (others => '0');
+                    p2_rd_overflow    <= '0';
+                    p2_rd_error       <= '0';
+                    p2_rd_full        <= '0';
+                    p2_rd_empty       <= '0';
+                    p2_rd_count       <= (others => '0');
+--                   p2_rd_error       <= '0';
+ end generate;                      
+--u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
+                         
+u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
+
+ p2_rd_ena :  if (C_PORT_ENABLE(2) = '1') generate
+                        mig_p2_clk        <= p2_rd_clk;
+                        p2_rd_data        <= mig_p2_rd_data;
+                        mig_p2_en         <= p2_rd_en;  
+                        p2_rd_overflow    <= mig_p2_overflow;
+                        p2_rd_error       <= mig_p2_error;
+                        p2_rd_full        <= mig_p2_full;
+                        p2_rd_empty       <= mig_p2_empty;
+                        p2_rd_count       <= mig_p2_count  ;-- wr port
+ end generate;                      
+ p2_rd_dis :  if (C_PORT_ENABLE(2) = '0') generate
+                        mig_p2_clk        <= '0';
+                        p2_rd_data        <= (others => '0');
+                        mig_p2_en         <= '0';
+                       
+                        p2_rd_overflow    <= '0';
+                        p2_rd_error       <= '0';
+                        p2_rd_full        <= '0';
+                        p2_rd_empty       <= '0';
+                        p2_rd_count       <= (others => '0');
+ end generate;                      
+                   mig_p2_wr_data  <= (others => '0');
+                   mig_p2_wr_mask  <= (others => '0');
+                   p2_wr_error     <= '0';
+                   p2_wr_full      <= '0';
+                   p2_wr_empty     <= '0';
+                   p2_wr_underrun  <= '0';
+                   p2_wr_count     <= (others => '0');
+          
+ end generate;                      
+--u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64)  = "W32") generate --whenever PORT 3 is in Write mode         
+
+u_config1_3W: if(
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode         
+
+p3_wr_ena:  if (C_PORT_ENABLE(3) = '1')generate
+
+                        mig_p3_clk   <= p3_wr_clk;
+                        mig_p3_wr_data  <= p3_wr_data(31 downto 0);
+                        mig_p3_wr_mask  <= p3_wr_mask(3 downto 0);
+                        mig_p3_en       <= p3_wr_en; 
+                        p3_wr_full      <= mig_p3_full;
+                        p3_wr_empty     <= mig_p3_empty;
+                        p3_wr_underrun  <= mig_p3_underrun;
+                        p3_wr_count     <= mig_p3_count  ;-- wr port
+                        p3_wr_error     <= mig_p3_error;
+ end generate;                      
+                       
+p3_wr_dis:  if (C_PORT_ENABLE(3) = '0')generate
+                        mig_p3_clk      <= '0';
+                        mig_p3_wr_data  <= (others => '0');
+                        mig_p3_wr_mask  <= (others => '0');
+                        mig_p3_en      <= '0';
+                        p3_wr_full      <= '0';
+                        p3_wr_empty     <= '0';
+                        p3_wr_underrun  <=  '0';
+                        p3_wr_count     <= (others => '0');
+                        p3_wr_error     <= '0';
+                                                
+ end generate;                      
+                    p3_rd_overflow <= '0';
+                    p3_rd_error    <= '0';
+                    p3_rd_full     <= '0';
+                    p3_rd_empty    <= '0';
+                    p3_rd_count    <= (others => '0');
+                    p3_rd_data     <= (others => '0');
+ end generate;                      
+                       
+u_config1_3R : if(      
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
+       
+p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
+
+                        mig_p3_clk     <= p3_rd_clk;
+                        p3_rd_data     <= mig_p3_rd_data;                
+                        mig_p3_en      <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
+                        p3_rd_overflow <= mig_p3_overflow;
+                        p3_rd_error    <= mig_p3_error;
+                        p3_rd_full     <= mig_p3_full;
+                        p3_rd_empty    <= mig_p3_empty;
+                        p3_rd_count    <= mig_p3_count  ;-- wr port
+ end generate;                      
+p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
+                        mig_p3_clk     <= '0';
+                        mig_p3_en      <= '0';
+                        p3_rd_overflow <= '0';
+                        p3_rd_full     <= '0';
+                        p3_rd_empty    <= '0';
+                        p3_rd_count    <= (others => '0');
+                        p3_rd_error    <= '0';
+                        p3_rd_data     <= (others => '0');
+ end generate;                      
+                   p3_wr_full      <= '0';
+                   p3_wr_empty     <= '0';
+                   p3_wr_underrun  <=  '0';
+                   p3_wr_count     <= (others => '0');
+                   p3_wr_error     <= '0';
+                   mig_p3_wr_data  <= (others => '0');
+                   mig_p3_wr_mask  <= (others => '0');
+ end generate;   
+ 
+
+u_config1_4W: if(      
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
+      -- whenever PORT 4 is in Write mode       
+
+p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
+                        mig_p4_clk      <= p4_wr_clk;
+                        mig_p4_wr_data  <= p4_wr_data(31 downto 0);
+                        mig_p4_wr_mask  <= p4_wr_mask(3 downto 0);
+                        mig_p4_en       <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
+                        p4_wr_full      <= mig_p4_full;
+                        p4_wr_empty     <= mig_p4_empty;
+                        p4_wr_underrun  <= mig_p4_underrun;
+                        p4_wr_count     <= mig_p4_count  ;-- wr port
+                        p4_wr_error     <= mig_p4_error;
+ end generate;   
+
+p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
+                        mig_p4_clk      <= '0';
+                        mig_p4_wr_data  <= (others => '0');
+                        mig_p4_wr_mask  <= (others => '0');
+                        mig_p4_en      <= '0';
+                        p4_wr_full      <= '0';
+                        p4_wr_empty     <= '0';
+                        p4_wr_underrun  <=  '0';
+                        p4_wr_count     <= (others => '0');
+                        p4_wr_error     <= '0';
+ end generate;   
+
+                    p4_rd_overflow    <= '0';
+                    p4_rd_error       <= '0';
+                    p4_rd_full        <=  '0';
+                    p4_rd_empty       <= '0';
+                    p4_rd_count       <= (others => '0');
+                    p4_rd_data        <= (others => '0');
+ end generate;   
+
+u_config1_4R : if(      
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
+                       
+p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
+                        mig_p4_clk        <= p4_rd_clk;
+                        p4_rd_data        <= mig_p4_rd_data;                
+                        mig_p4_en         <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
+                        p4_rd_overflow    <= mig_p4_overflow;
+                        p4_rd_error       <= mig_p4_error;
+                        p4_rd_full        <= mig_p4_full;
+                        p4_rd_empty       <= mig_p4_empty;
+                        p4_rd_count       <= mig_p4_count  ;-- wr port
+ end generate;   
+p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
+                        mig_p4_clk        <= '0';
+                        p4_rd_data        <= (others => '0');
+                        mig_p4_en         <= '0';
+                        p4_rd_overflow    <= '0';
+                        p4_rd_error       <= '0';
+                        p4_rd_full        <=  '0';
+                        p4_rd_empty       <= '0';
+                        p4_rd_count       <= (others => '0');
+ end generate;   
+                   p4_wr_full      <= '0';
+                   p4_wr_empty     <= '0';
+                   p4_wr_underrun  <=  '0';
+                   p4_wr_count     <= (others => '0');
+                   p4_wr_error     <= '0';
+                   mig_p4_wr_data  <= (others => '0');
+                   mig_p4_wr_mask  <= (others => '0');
+ end generate;   
+         
+u_config1_5W: if(      
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
+      -- whenever PORT 5 is in Write mode           
+
+                       
+p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
+                        mig_p5_clk   <= p5_wr_clk;
+                        mig_p5_wr_data  <= p5_wr_data(31 downto 0);
+                        mig_p5_wr_mask  <= p5_wr_mask(3 downto 0);
+                        mig_p5_en       <= p5_wr_en; 
+                        p5_wr_full      <= mig_p5_full;
+                        p5_wr_empty     <= mig_p5_empty;
+                        p5_wr_underrun  <= mig_p5_underrun;
+                        p5_wr_count     <= mig_p5_count  ; 
+                        p5_wr_error     <= mig_p5_error;
+                       
+end generate;
+p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
+                        mig_p5_clk      <= '0';
+                        mig_p5_wr_data  <= (others => '0');
+                        mig_p5_wr_mask  <= (others => '0');
+                        mig_p5_en      <= '0';
+                        p5_wr_full      <= '0';
+                        p5_wr_empty     <= '0';
+                        p5_wr_underrun  <=  '0';
+                        p5_wr_count     <= (others => '0');
+                        p5_wr_error     <= '0';
+end generate;
+                    p5_rd_data        <= (others => '0');
+                    p5_rd_overflow    <= '0';
+                    p5_rd_error       <= '0';
+                    p5_rd_full        <=  '0';
+                    p5_rd_empty       <= '0';
+                    p5_rd_count       <= (others => '0');
+end generate;                  
+       
+                       
+                         
+u_config1_5R :if(  
+      C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
+      C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
+
+p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
+                        mig_p5_clk        <= p5_rd_clk;
+                        p5_rd_data        <= mig_p5_rd_data;                
+                        mig_p5_en         <= p5_rd_en;  
+                        p5_rd_overflow    <= mig_p5_overflow;
+                        p5_rd_error       <= mig_p5_error;
+                        p5_rd_full        <= mig_p5_full;
+                        p5_rd_empty       <= mig_p5_empty;
+                        p5_rd_count       <= mig_p5_count  ; 
+                       
+end generate;
+
+p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
+
+                        mig_p5_clk        <= '0';
+                        p5_rd_data        <= (others => '0');           
+                        mig_p5_en         <= '0';
+                        p5_rd_overflow    <= '0';
+                        p5_rd_error       <= '0';
+                        p5_rd_full        <= '0';
+                        p5_rd_empty       <= '0';
+                        p5_rd_count       <= (others => '0');
+                 
+end generate;
+                  p5_wr_full      <= '0';
+                  p5_wr_empty     <= '0';
+                  p5_wr_underrun  <=  '0';
+                  p5_wr_count     <= (others => '0');
+                  p5_wr_error     <= '0';
+                  mig_p5_wr_data  <= (others => '0');
+                  mig_p5_wr_mask  <= (others => '0');
+                       
+end generate;
+
+     --//////////////////////////////////////////////////////////////////////////
+     --///////////////////////////////////////////////////////////////////////////
+     ----    
+     ----                        B32_B32_B32_B32
+     ----    
+     --///////////////////////////////////////////////////////////////////////////
+     --//////////////////////////////////////////////////////////////////////////
+                
+u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
+
+           
+              -- Inputs from Application CMD Port
+              -- *************  need to hook up rd /wr error outputs
+               
+p0_c2_ena:  if (C_PORT_ENABLE(0) = '1') generate
+                          -- command port signals
+                            mig_p0_arb_en      <=      p0_arb_en ;
+                            mig_p0_cmd_clk     <=      p0_cmd_clk  ;
+                            mig_p0_cmd_en      <=      p0_cmd_en   ;
+                            mig_p0_cmd_ra      <=      p0_cmd_ra  ;
+                            mig_p0_cmd_ba      <=      p0_cmd_ba   ;
+                            mig_p0_cmd_ca      <=      p0_cmd_ca  ;
+                            mig_p0_cmd_instr   <=      p0_cmd_instr;
+                            mig_p0_cmd_bl      <=      ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;                           
+                          -- Data port signals
+                            mig_p0_rd_en    <= p0_rd_en;                            
+                            mig_p0_wr_clk   <= p0_wr_clk;
+                            mig_p0_rd_clk   <= p0_rd_clk;
+                            mig_p0_wr_en    <= p0_wr_en;
+                            mig_p0_wr_data  <= p0_wr_data(31 downto 0); 
+                            mig_p0_wr_mask  <= p0_wr_mask(3 downto 0);
+                            p0_wr_count     <= mig_p0_wr_count;
+                            p0_rd_count  <= mig_p0_rd_count  ; 
+end generate;
+
+p0_c2_dis:  if (C_PORT_ENABLE(0) = '0') generate
+                           
+                            mig_p0_arb_en      <=       '0';
+                            mig_p0_cmd_clk     <=       '0';
+                            mig_p0_cmd_en      <=       '0';
+                            mig_p0_cmd_ra      <=       (others => '0');
+                            mig_p0_cmd_ba      <=       (others => '0');
+                            mig_p0_cmd_ca      <=       (others => '0');
+                            mig_p0_cmd_instr   <=       (others => '0');
+                            mig_p0_cmd_bl      <=       (others => '0');
+                           
+                            mig_p0_rd_en    <= '0';                    
+                            mig_p0_wr_clk   <= '0';
+                            mig_p0_rd_clk   <= '0';
+                            mig_p0_wr_en    <= '0';
+                            mig_p0_wr_data  <= (others => '0'); 
+                            mig_p0_wr_mask  <= (others => '0');
+                            p0_wr_count     <= (others => '0');
+                            p0_rd_count     <= (others => '0');
+
+                           
+end generate;                           
+             
+                         
+                           
+p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
+                          -- command port signals
+
+                            mig_p1_arb_en      <=      p1_arb_en ;
+                            mig_p1_cmd_clk     <=      p1_cmd_clk  ;
+                            mig_p1_cmd_en      <=      p1_cmd_en   ;
+                            mig_p1_cmd_ra      <=      p1_cmd_ra  ;
+                            mig_p1_cmd_ba      <=      p1_cmd_ba   ;
+                            mig_p1_cmd_ca      <=      p1_cmd_ca  ;
+                            mig_p1_cmd_instr   <=      p1_cmd_instr;
+                            mig_p1_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           
+
+                          -- Data port signals
+                 
+                             mig_p1_wr_en    <= p1_wr_en;
+                             mig_p1_wr_clk   <= p1_wr_clk;
+                             mig_p1_rd_en    <= p1_rd_en;
+                             mig_p1_wr_data  <= p1_wr_data(31 downto 0);
+                             mig_p1_wr_mask  <= p1_wr_mask(3 downto 0);                
+                             mig_p1_rd_clk   <= p1_rd_clk;
+                             p1_wr_count     <= mig_p1_wr_count;
+                             p1_rd_count     <= mig_p1_rd_count;
+                           
+end generate;
+p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
+
+                            mig_p1_arb_en      <=       '0';
+                            mig_p1_cmd_clk     <=       '0';
+                            mig_p1_cmd_en      <=       '0';
+                            mig_p1_cmd_ra      <=       (others => '0');
+                            mig_p1_cmd_ba      <=       (others => '0');
+                            mig_p1_cmd_ca      <=       (others => '0');
+                            mig_p1_cmd_instr   <=       (others => '0');
+                            mig_p1_cmd_bl      <=       (others => '0');
+                          -- Data port signals
+                            mig_p1_wr_en    <= '0'; 
+                            mig_p1_wr_clk   <= '0';
+                            mig_p1_rd_en    <= '0';
+                            mig_p1_wr_data  <= (others => '0');
+                            mig_p1_wr_mask  <= (others => '0');                
+                            mig_p1_rd_clk   <= '0';
+                             p1_wr_count     <= (others => '0');
+                             p1_rd_count     <= (others => '0');
+                  
+end generate;
+                           
+                           
+ 
+p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
+                    --MCB Physical port               Logical Port
+                            mig_p2_arb_en      <=      p2_arb_en ;
+                            mig_p2_cmd_clk     <=      p2_cmd_clk  ;
+                            mig_p2_cmd_en      <=      p2_cmd_en   ;
+                            mig_p2_cmd_ra      <=      p2_cmd_ra  ;
+                            mig_p2_cmd_ba      <=      p2_cmd_ba   ;
+                            mig_p2_cmd_ca      <=      p2_cmd_ca  ;
+                            mig_p2_cmd_instr   <=      p2_cmd_instr;
+                            mig_p2_cmd_bl      <=      ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0))  ;                           
+                            
+                             mig_p2_en       <= p2_rd_en;
+                             mig_p2_clk      <= p2_rd_clk;
+                             mig_p3_en       <= p2_wr_en;
+                             mig_p3_clk      <= p2_wr_clk;
+                             mig_p3_wr_data  <= p2_wr_data(31 downto 0);
+                             mig_p3_wr_mask  <= p2_wr_mask(3 downto 0);
+                             p2_wr_count     <= mig_p3_count;
+                             p2_rd_count     <= mig_p2_count;
+end generate;
+p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
+
+                            mig_p2_arb_en      <=       '0';
+                            mig_p2_cmd_clk      <=       '0';
+                            mig_p2_cmd_en      <=       '0';
+                            mig_p2_cmd_ra      <=      (others => '0');
+                            mig_p2_cmd_ba      <=      (others => '0');
+                            mig_p2_cmd_ca      <=      (others => '0');
+                            mig_p2_cmd_instr   <=      (others => '0');
+                            mig_p2_cmd_bl      <=      (others => '0');
+
+                             mig_p2_en      <= '0'; 
+                             mig_p2_clk      <= '0';
+                             mig_p3_en      <= '0';
+                             mig_p3_clk      <= '0';
+                             mig_p3_wr_data  <= (others => '0'); 
+                             mig_p3_wr_mask  <= (others => '0');
+                             p2_rd_count     <= (others => '0');
+                             p2_wr_count     <= (others => '0');
+                           
+end generate;
+                         
+  
+p3_c2_ena:  if (C_PORT_ENABLE(3) = '1') generate
+                    --MCB Physical port               Logical Port
+                            mig_p4_arb_en      <=      p3_arb_en ;
+                            mig_p4_cmd_clk     <=      p3_cmd_clk  ;
+                            mig_p4_cmd_en      <=      p3_cmd_en   ;
+                            mig_p4_cmd_ra      <=      p3_cmd_ra  ;
+                            mig_p4_cmd_ba      <=      p3_cmd_ba   ;
+                            mig_p4_cmd_ca      <=      p3_cmd_ca  ;
+                            mig_p4_cmd_instr   <=      p3_cmd_instr;
+                            mig_p4_cmd_bl      <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0))  ;                           
+
+                            mig_p4_clk      <= p3_rd_clk;
+                            mig_p4_en       <= p3_rd_en;                            
+                            mig_p5_clk      <= p3_wr_clk;
+                            mig_p5_en       <= p3_wr_en; 
+                            mig_p5_wr_data  <= p3_wr_data(31 downto 0);
+                            mig_p5_wr_mask  <= p3_wr_mask(3 downto 0);
+                            p3_rd_count     <= mig_p4_count;
+                            p3_wr_count     <= mig_p5_count;
+end generate;
+                           
+p3_c2_dis:  if (C_PORT_ENABLE(3) = '0') generate
+                            mig_p4_arb_en      <=     '0';
+                            mig_p4_cmd_clk     <=     '0';
+                            mig_p4_cmd_en      <=     '0';
+                            mig_p4_cmd_ra      <=     (others => '0');
+                            mig_p4_cmd_ba      <=     (others => '0');
+                            mig_p4_cmd_ca      <=     (others => '0');
+                            mig_p4_cmd_instr   <=     (others => '0');
+                            mig_p4_cmd_bl      <=     (others => '0');
+                           
+                             mig_p4_clk      <= '0'; 
+                             mig_p4_en      <= '0';                   
+                             mig_p5_clk      <= '0';
+                             mig_p5_en      <= '0';
+                             mig_p5_wr_data  <= (others => '0'); 
+                             mig_p5_wr_mask  <= (others => '0');
+                             p3_rd_count     <= (others => '0');
+                             p3_wr_count     <= (others => '0');
+end generate;
+                           
+                            p0_cmd_empty       <=      mig_p0_cmd_empty ;
+                            p0_cmd_full        <=      mig_p0_cmd_full  ;
+                            p1_cmd_empty       <=      mig_p1_cmd_empty ;
+                            p1_cmd_full        <=      mig_p1_cmd_full  ;
+                            p2_cmd_empty       <=      mig_p2_cmd_empty ;
+                            p2_cmd_full        <=      mig_p2_cmd_full  ;
+                            p3_cmd_empty       <=      mig_p4_cmd_empty ;
+                            p3_cmd_full        <=      mig_p4_cmd_full  ;
+                           
+                           
+                           -- outputs to Applications User Port
+                             p0_rd_data     <= mig_p0_rd_data;
+                             p1_rd_data     <= mig_p1_rd_data;
+                             p2_rd_data     <= mig_p2_rd_data;
+                             p3_rd_data     <= mig_p4_rd_data;
+
+                             p0_rd_empty_i    <= mig_p0_rd_empty;
+                             p1_rd_empty_i    <= mig_p1_rd_empty;
+                             p2_rd_empty    <= mig_p2_empty;
+                             p3_rd_empty    <= mig_p4_empty;
+
+                             p0_rd_full     <= mig_p0_rd_full;
+                             p1_rd_full     <= mig_p1_rd_full;
+                             p2_rd_full     <= mig_p2_full;
+                             p3_rd_full     <= mig_p4_full;
+
+                             p0_rd_error    <= mig_p0_rd_error;
+                             p1_rd_error    <= mig_p1_rd_error;
+                             p2_rd_error    <= mig_p2_error;
+                             p3_rd_error    <= mig_p4_error;
+                            
+                             p0_rd_overflow <= mig_p0_rd_overflow;
+                             p1_rd_overflow <= mig_p1_rd_overflow;
+                             p2_rd_overflow <= mig_p2_overflow;
+                             p3_rd_overflow <= mig_p4_overflow;
+
+                             p0_wr_underrun <= mig_p0_wr_underrun;
+                             p1_wr_underrun <= mig_p1_wr_underrun;
+                             p2_wr_underrun <= mig_p3_underrun;
+                             p3_wr_underrun <= mig_p5_underrun;
+                            
+                             p0_wr_empty    <= mig_p0_wr_empty;
+                             p1_wr_empty    <= mig_p1_wr_empty;
+                             p2_wr_empty    <= mig_p3_empty; 
+                             p3_wr_empty    <= mig_p5_empty; 
+ 
+                             p0_wr_full_i    <= mig_p0_wr_full;
+                             p1_wr_full_i    <= mig_p1_wr_full;
+                             p2_wr_full    <= mig_p3_full;
+                             p3_wr_full    <= mig_p5_full;
+
+                             p0_wr_error    <= mig_p0_wr_error;
+                             p1_wr_error    <= mig_p1_wr_error;
+                             p2_wr_error    <= mig_p3_error;
+                             p3_wr_error    <= mig_p5_error;
+
+    -- unused ports signals
+                            p4_cmd_empty        <=     '0';
+                            p4_cmd_full         <=     '0';
+                            mig_p2_wr_mask     <=      (others => '0');
+                            mig_p4_wr_mask    <=      (others => '0');
+
+                           mig_p2_wr_data     <=      (others => '0');
+                           mig_p4_wr_data     <=      (others => '0');
+
+
+                            p5_cmd_empty        <=     '0';
+                            p5_cmd_full         <=     '0';
+     
+ 
+                             mig_p3_cmd_clk      <=       '0';
+                             mig_p3_cmd_en      <=       '0';
+                             mig_p3_cmd_ra      <=      (others => '0');
+                             mig_p3_cmd_ba      <=      (others => '0');
+                             mig_p3_cmd_ca      <=      (others => '0');
+                             mig_p3_cmd_instr   <=      (others => '0');
+                             mig_p3_cmd_bl      <=      (others => '0');
+                             mig_p3_arb_en      <=       '0'; -- physical cmd port 3 is not used in this config
+                            
+                            
+                            
+                            
+                             mig_p5_arb_en      <=       '0'; -- physical cmd port 3 is not used in this config
+                             mig_p5_cmd_clk      <=       '0';
+                             mig_p5_cmd_en      <=       '0';
+                             mig_p5_cmd_ra      <=      (others => '0');
+                             mig_p5_cmd_ba      <=      (others => '0');
+                             mig_p5_cmd_ca      <=      (others => '0');
+                             mig_p5_cmd_instr   <=      (others => '0');
+                             mig_p5_cmd_bl      <=      (others => '0');
+
+end generate;
+--
+--
+--     --//////////////////////////////////////////////////////////////////////////
+--     --///////////////////////////////////////////////////////////////////////////
+--     ----    
+--     ----                        B64_B32_B32
+--     ----    
+--     --///////////////////////////////////////////////////////////////////////////
+--     --//////////////////////////////////////////////////////////////////////////
+--
+--     
+--     
+u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
+
+              -- Inputs from Application CMD Port
+ 
+ 
+p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
+                mig_p0_arb_en      <=  p0_arb_en ;
+                mig_p0_cmd_clk     <=  p0_cmd_clk  ;
+                mig_p0_cmd_en      <=  p0_cmd_en   ;
+                mig_p0_cmd_ra      <=  p0_cmd_ra  ;
+                mig_p0_cmd_ba      <=  p0_cmd_ba   ;
+                mig_p0_cmd_ca      <=  p0_cmd_ca  ;
+                mig_p0_cmd_instr   <=  p0_cmd_instr;
+                mig_p0_cmd_bl      <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;
+                p0_cmd_empty       <=  mig_p0_cmd_empty ;
+                p0_cmd_full        <=  mig_p0_cmd_full  ;
+
+                mig_p0_wr_clk   <= p0_wr_clk;
+                mig_p0_rd_clk   <= p0_rd_clk;
+                mig_p1_wr_clk   <= p0_wr_clk;
+                mig_p1_rd_clk   <= p0_rd_clk;
+
+                mig_p0_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                mig_p1_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                mig_p0_wr_data  <= p0_wr_data(31 downto 0);
+                mig_p0_wr_mask(3 downto 0)  <= p0_wr_mask(3 downto 0);
+                mig_p1_wr_data  <= p0_wr_data(63  downto  32);
+                mig_p1_wr_mask(3 downto 0)  <= p0_wr_mask(7  downto  4);     
+
+                p0_rd_empty_i       <= mig_p1_rd_empty;
+                p0_rd_data        <= (mig_p1_rd_data & mig_p0_rd_data); 
+                mig_p0_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+                mig_p1_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+
+
+                 p0_wr_count       <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
+                 p0_rd_count       <= mig_p1_rd_count;
+                 p0_wr_empty       <= mig_p1_wr_empty;
+                 p0_wr_error       <= mig_p1_wr_error or mig_p0_wr_error;  
+                 p0_wr_full_i        <= mig_p1_wr_full;
+                 p0_wr_underrun    <= mig_p1_wr_underrun or mig_p0_wr_underrun; 
+                 p0_rd_overflow    <= mig_p1_rd_overflow or mig_p0_rd_overflow; 
+                 p0_rd_error       <= mig_p1_rd_error or mig_p0_rd_error; 
+                 p0_rd_full        <= mig_p1_rd_full;
+
+end generate; 
+p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
+       
+                mig_p0_arb_en      <= '0';
+                mig_p0_cmd_clk     <= '0';
+                mig_p0_cmd_en      <= '0';
+                mig_p0_cmd_ra      <= (others => '0');
+                mig_p0_cmd_ba      <= (others => '0');
+                mig_p0_cmd_ca      <= (others => '0');
+                mig_p0_cmd_instr   <= (others => '0');
+                mig_p0_cmd_bl      <= (others => '0');
+                p0_cmd_empty       <= '0';
+                p0_cmd_full        <= '0';
+
+
+                mig_p0_wr_clk   <= '0';
+                mig_p0_rd_clk   <= '0';
+                mig_p1_wr_clk   <= '0';
+                mig_p1_rd_clk   <= '0';
+               
+                mig_p0_wr_en    <= '0';
+                mig_p1_wr_en    <= '0';
+                mig_p0_wr_data  <= (others => '0');
+                mig_p0_wr_mask  <= (others => '0');
+                mig_p1_wr_data  <= (others => '0');
+                mig_p1_wr_mask  <= (others => '0'); 
+
+                p0_rd_empty_i       <= '0';
+                p0_rd_data        <= (others => '0');
+                mig_p0_rd_en      <= '0';
+                mig_p1_rd_en      <= '0';
+ 
+ 
+                p0_wr_count       <=  (others => '0');
+                p0_rd_count       <=  (others => '0');
+                p0_wr_empty       <=  '0';
+                p0_wr_error       <=  '0';
+                p0_wr_full_i        <=  '0';
+                p0_wr_underrun    <=  '0';
+                p0_rd_overflow    <=  '0';
+                p0_rd_error       <=  '0';
+                p0_rd_full        <=  '0';
+end generate; 
+
+       
+        
+ 
+p1_c3_ena:  if (C_PORT_ENABLE(1) = '1')generate
+
+                mig_p2_arb_en      <=      p1_arb_en ;
+                mig_p2_cmd_clk     <=      p1_cmd_clk  ;
+                mig_p2_cmd_en      <=      p1_cmd_en   ;
+                mig_p2_cmd_ra      <=      p1_cmd_ra  ;
+                mig_p2_cmd_ba      <=      p1_cmd_ba   ;
+                mig_p2_cmd_ca      <=      p1_cmd_ca  ;
+                mig_p2_cmd_instr   <=      p1_cmd_instr;
+                mig_p2_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           
+
+                p1_cmd_empty       <=      mig_p2_cmd_empty;  
+                p1_cmd_full        <=      mig_p2_cmd_full;   
+
+                mig_p2_clk         <= p1_rd_clk;
+                mig_p3_clk         <= p1_wr_clk;
+
+                mig_p3_en       <= p1_wr_en;
+                mig_p3_wr_data  <= p1_wr_data(31 downto 0);
+                mig_p3_wr_mask  <= p1_wr_mask(3 downto 0);
+                mig_p2_en       <= p1_rd_en;
+
+                p1_rd_data        <= mig_p2_rd_data;
+                p1_wr_count       <= mig_p3_count;
+                p1_rd_count       <= mig_p2_count;
+                p1_wr_empty       <= mig_p3_empty;
+                p1_wr_error       <= mig_p3_error;                 
+                p1_wr_full_i        <= mig_p3_full;
+                p1_wr_underrun    <= mig_p3_underrun;
+                p1_rd_overflow    <= mig_p2_overflow; 
+                p1_rd_error       <= mig_p2_error;
+                p1_rd_full        <= mig_p2_full;
+                p1_rd_empty_i       <= mig_p2_empty;
+ end generate;
+
+p1_c3_dis:  if (C_PORT_ENABLE(1) = '0')generate
+
+                mig_p2_arb_en      <=      '0'; 
+                mig_p2_cmd_clk     <=      '0'; 
+                mig_p2_cmd_en      <=     '0'; 
+                mig_p2_cmd_ra      <=     (others => '0'); 
+                mig_p2_cmd_ba      <=     (others => '0'); 
+                mig_p2_cmd_ca      <=     (others => '0'); 
+                mig_p2_cmd_instr   <=     (others => '0'); 
+                mig_p2_cmd_bl      <=     (others => '0'); 
+                p1_cmd_empty       <=     '0'; 
+                p1_cmd_full        <=     '0'; 
+                mig_p3_en      <= '0'; 
+                mig_p3_wr_data  <= (others => '0'); 
+                mig_p3_wr_mask  <= (others => '0'); 
+                mig_p2_en      <= '0'; 
+
+                mig_p2_clk   <= '0'; 
+                mig_p3_clk   <= '0'; 
+               
+                p1_rd_data        <= (others => '0'); 
+                p1_wr_count       <= (others => '0'); 
+                p1_rd_count       <= (others => '0'); 
+                p1_wr_empty       <= '0'; 
+                p1_wr_error       <= '0';         
+                p1_wr_full_i        <= '0'; 
+                p1_wr_underrun    <= '0'; 
+                p1_rd_overflow    <= '0'; 
+                p1_rd_error       <= '0'; 
+                p1_rd_full        <=  '0'; 
+                p1_rd_empty_i       <= '0'; 
+ 
+end generate;
+       
+p2_c3_ena:  if (C_PORT_ENABLE(2) = '1')generate
+                mig_p4_arb_en      <= p2_arb_en ;
+                mig_p4_cmd_clk     <= p2_cmd_clk  ;
+                mig_p4_cmd_en      <= p2_cmd_en   ;
+                mig_p4_cmd_ra      <= p2_cmd_ra  ;
+                mig_p4_cmd_ba      <= p2_cmd_ba   ;
+                mig_p4_cmd_ca      <= p2_cmd_ca  ;
+                mig_p4_cmd_instr   <= p2_cmd_instr;
+                mig_p4_cmd_bl      <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0))  ;                           
+
+                p2_cmd_empty       <= mig_p4_cmd_empty ; 
+                p2_cmd_full        <= mig_p4_cmd_full  ; 
+                mig_p5_en          <= p2_wr_en;
+                mig_p5_wr_data     <= p2_wr_data(31 downto 0);
+                mig_p5_wr_mask     <= p2_wr_mask(3 downto 0);
+                mig_p4_en          <= p2_rd_en;
+               
+                 mig_p4_clk        <= p2_rd_clk;
+                 mig_p5_clk        <= p2_wr_clk;
+
+                 p2_rd_data        <= mig_p4_rd_data;
+                 p2_wr_count       <= mig_p5_count;
+                 p2_rd_count       <= mig_p4_count;
+                 p2_wr_empty       <= mig_p5_empty;
+                 p2_wr_full        <= mig_p5_full;
+                 p2_wr_error       <= mig_p5_error;  
+                 p2_wr_underrun    <= mig_p5_underrun;
+                 p2_rd_overflow    <= mig_p4_overflow;    
+                 p2_rd_error       <= mig_p4_error;
+                 p2_rd_full        <= mig_p4_full;
+                 p2_rd_empty       <= mig_p4_empty;
+
+end generate; 
+               
+p2_c3_dis:  if (C_PORT_ENABLE(2) = '0')generate
+
+                mig_p4_arb_en      <= '0'; 
+                mig_p4_cmd_clk     <= '0';   
+                mig_p4_cmd_en      <= '0';   
+                mig_p4_cmd_ra      <= (others => '0');   
+                mig_p4_cmd_ba      <= (others => '0');   
+                mig_p4_cmd_ca      <= (others => '0');   
+                mig_p4_cmd_instr   <= (others => '0');   
+                mig_p4_cmd_bl      <= (others => '0');   
+                p2_cmd_empty       <= '0';   
+                p2_cmd_full        <= '0'; 
+                mig_p5_en          <= '0'; 
+                mig_p5_wr_data     <= (others => '0'); 
+                mig_p5_wr_mask     <= (others => '0'); 
+                mig_p4_en          <= '0'; 
+
+                 mig_p4_clk        <= '0'; 
+                 mig_p5_clk        <= '0'; 
+
+                 p2_rd_data        <=   (others => '0');   
+                 p2_wr_count       <=   (others => '0');   
+                 p2_rd_count       <=   (others => '0');   
+                 p2_wr_empty       <=   '0'; 
+                 p2_wr_full        <=   '0';  
+                 p2_wr_error       <=   '0';   
+                 p2_wr_underrun    <=   '0';   
+                 p2_rd_overflow    <=   '0';     
+                 p2_rd_error       <=   '0'; 
+                 p2_rd_full        <=   '0'; 
+                 p2_rd_empty       <=   '0'; 
+
+end generate; 
+
+             -- MCB's port 1,3,5 is not used in this Config mode
+                mig_p1_arb_en      <=       '0';
+                mig_p1_cmd_clk      <=       '0';
+                mig_p1_cmd_en      <=       '0';
+                mig_p1_cmd_ra      <=      (others => '0');
+                mig_p1_cmd_ba      <=      (others => '0');
+                mig_p1_cmd_ca      <=      (others => '0');
+               
+                mig_p1_cmd_instr   <=      (others => '0');
+                mig_p1_cmd_bl      <=      (others => '0');
+                
+                mig_p3_arb_en    <=      '0'; 
+                mig_p3_cmd_clk      <=       '0';
+                mig_p3_cmd_en      <=       '0';
+                mig_p3_cmd_ra      <=      (others => '0');
+                mig_p3_cmd_ba      <=      (others => '0');
+                mig_p3_cmd_ca      <=      (others => '0');
+               
+                mig_p3_cmd_instr   <=      (others => '0');
+                mig_p3_cmd_bl      <=      (others => '0');
+
+                mig_p5_arb_en    <=      '0'; 
+                mig_p5_cmd_clk      <=       '0';
+                mig_p5_cmd_en      <=       '0';
+                mig_p5_cmd_ra      <=      (others => '0');
+                mig_p5_cmd_ba      <=      (others => '0');
+                mig_p5_cmd_ca      <=      (others => '0');
+               
+                mig_p5_cmd_instr   <=      (others => '0');
+                mig_p5_cmd_bl      <=      (others => '0');
+ 
+end generate;
+
+u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
+
+              -- Inputs from Application CMD Port
+
+p0_c4_ena:  if (C_PORT_ENABLE(0) = '1') generate
+               
+                        mig_p0_arb_en      <=      p0_arb_en ;
+                        mig_p1_arb_en      <=      p0_arb_en ;
+                       
+                        mig_p0_cmd_clk     <=      p0_cmd_clk  ;
+                        mig_p0_cmd_en      <=      p0_cmd_en   ;
+                        mig_p0_cmd_ra      <=      p0_cmd_ra  ;
+                        mig_p0_cmd_ba      <=      p0_cmd_ba   ;
+                        mig_p0_cmd_ca      <=      p0_cmd_ca  ;
+                        mig_p0_cmd_instr   <=      p0_cmd_instr;
+                        mig_p0_cmd_bl      <=      ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;
+
+                         mig_p0_wr_clk   <= p0_wr_clk;
+                         mig_p0_rd_clk   <= p0_rd_clk;
+                         mig_p1_wr_clk   <= p0_wr_clk;
+                         mig_p1_rd_clk   <= p0_rd_clk;
+                         mig_p0_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                         mig_p0_wr_data  <= p0_wr_data(31 downto 0);
+                         mig_p0_wr_mask(3 downto 0)  <= p0_wr_mask(3 downto 0);
+                         mig_p1_wr_data  <= p0_wr_data(63  downto  32);
+                         mig_p1_wr_mask(3 downto 0)  <= p0_wr_mask(7  downto  4);                
+                         mig_p1_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                         mig_p0_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+                         mig_p1_rd_en    <= p0_rd_en and not p0_rd_empty_i;  
+                         p0_rd_data     <= (mig_p1_rd_data & mig_p0_rd_data);
+                        
+                         p0_cmd_empty   <=     mig_p0_cmd_empty ;
+                         p0_cmd_full    <=     mig_p0_cmd_full  ;
+                         p0_wr_empty    <= mig_p1_wr_empty;      
+                         p0_wr_full_i    <= mig_p1_wr_full;
+                         p0_wr_error    <= mig_p1_wr_error or mig_p0_wr_error; 
+                         p0_wr_count    <= mig_p1_wr_count;
+                         p0_rd_count    <= mig_p1_rd_count;
+                         p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun; 
+                         p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow; 
+                         p0_rd_error    <= mig_p1_rd_error or mig_p0_rd_error; 
+                         p0_rd_full     <= mig_p1_rd_full;
+                         p0_rd_empty_i    <= mig_p1_rd_empty;
+end generate;                       
+
+p0_c4_dis:  if (C_PORT_ENABLE(0) = '0') generate
+                        mig_p0_arb_en      <=       '0';
+                        mig_p0_cmd_clk      <=       '0';
+                        mig_p0_cmd_en      <=       '0';
+                        mig_p0_cmd_ra      <=      (others => '0');
+                        mig_p0_cmd_ba      <=      (others => '0');
+                        mig_p0_cmd_ca      <=      (others => '0');
+                        mig_p0_cmd_instr   <=      (others => '0');
+                        mig_p0_cmd_bl      <=      (others => '0');
+
+                         mig_p0_wr_clk   <= '0';
+                         mig_p0_rd_clk   <= '0';
+                         mig_p1_wr_clk   <= '0';
+                         mig_p1_rd_clk   <= '0';
+                         mig_p0_wr_en    <= '0';
+                         mig_p1_wr_en    <= '0';
+                         mig_p0_wr_data  <= (others => '0');
+                         mig_p0_wr_mask  <= (others => '0');
+                         mig_p1_wr_data  <= (others => '0');
+                         mig_p1_wr_mask  <= (others => '0');            
+                  --      mig_p1_wr_en    <= (others => '0');
+                         mig_p0_rd_en    <= '0';
+                         mig_p1_rd_en    <= '0';
+                         p0_rd_data     <= (others => '0');
+
+
+                         p0_cmd_empty   <= '0';
+                         p0_cmd_full    <= '0';
+                         p0_wr_empty    <= '0';
+                         p0_wr_full_i     <= '0';
+                         p0_wr_error    <= '0';
+                         p0_wr_count    <= (others => '0');
+                         p0_rd_count    <= (others => '0');
+                         p0_wr_underrun <= '0';  
+                         p0_rd_overflow <= '0';
+                         p0_rd_error    <= '0';
+                         p0_rd_full     <= '0';
+                         p0_rd_empty_i    <= '0';
+                 
+                 
+end generate;
+      
+
+p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
+
+                        mig_p2_arb_en      <=      p1_arb_en ;
+                       
+                        mig_p2_cmd_clk     <=      p1_cmd_clk  ;
+                        mig_p2_cmd_en      <=      p1_cmd_en   ;
+                        mig_p2_cmd_ra      <=      p1_cmd_ra  ;
+                        mig_p2_cmd_ba      <=      p1_cmd_ba   ;
+                        mig_p2_cmd_ca      <=      p1_cmd_ca  ;
+                        mig_p2_cmd_instr   <=      p1_cmd_instr;
+                        mig_p2_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           
+
+
+                         mig_p2_clk     <= p1_rd_clk;
+                         mig_p3_clk     <= p1_wr_clk;
+                         mig_p4_clk     <= p1_rd_clk;
+                         mig_p5_clk     <= p1_wr_clk;
+                         mig_p3_en      <= p1_wr_en and not p1_wr_full_i;
+                         mig_p5_en      <= p1_wr_en and not p1_wr_full_i;
+                         mig_p3_wr_data  <= p1_wr_data(31 downto 0);
+                         mig_p3_wr_mask  <= p1_wr_mask(3 downto 0);
+                         mig_p5_wr_data  <= p1_wr_data(63 downto 32);
+                         mig_p5_wr_mask  <= p1_wr_mask(7 downto 4);
+                         mig_p2_en       <= p1_rd_en and not p1_rd_empty_i;
+                         mig_p4_en       <= p1_rd_en and not p1_rd_empty_i;
+                        
+                         p1_cmd_empty       <=      mig_p2_cmd_empty ;  
+                         p1_cmd_full        <=      mig_p2_cmd_full  ;
+
+                         p1_wr_count    <= mig_p5_count;
+                         p1_rd_count    <= mig_p4_count;
+                         p1_wr_full_i    <= mig_p5_full;
+                         p1_wr_error    <= mig_p5_error or mig_p5_error;
+                         p1_wr_empty    <= mig_p5_empty;
+                         p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
+                         p1_rd_overflow <= mig_p4_overflow;
+                         p1_rd_error    <= mig_p4_error;
+                         p1_rd_full     <= mig_p4_full;
+                         p1_rd_empty_i    <= mig_p4_empty;
+
+                         p1_rd_data     <= (mig_p4_rd_data & mig_p2_rd_data);
+                       
+end generate;                       
+p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
+
+                        mig_p2_arb_en      <= '0';
+                  --     mig_p3_arb_en      <= (others => '0');
+                 --      mig_p4_arb_en      <= (others => '0');
+                 --      mig_p5_arb_en      <= (others => '0');
+                       
+                        mig_p2_cmd_clk     <= '0';
+                        mig_p2_cmd_en      <= '0';
+                        mig_p2_cmd_ra      <= (others => '0');
+                        mig_p2_cmd_ba      <= (others => '0');
+                        mig_p2_cmd_ca      <= (others => '0');
+                        mig_p2_cmd_instr   <= (others => '0');
+                        mig_p2_cmd_bl      <= (others => '0');
+                        mig_p2_clk      <= '0';
+                        mig_p3_clk      <= '0';
+                        mig_p4_clk      <= '0';
+                        mig_p5_clk      <= '0';
+                        mig_p3_en      <= '0';
+                        mig_p5_en      <= '0';
+                        mig_p3_wr_data  <= (others => '0');
+                        mig_p3_wr_mask  <= (others => '0');
+                        mig_p5_wr_data  <= (others => '0');
+                        mig_p5_wr_mask  <= (others => '0'); 
+                        mig_p2_en       <= '0';
+                        mig_p4_en       <= '0';
+                        p1_cmd_empty    <= '0';  
+                        p1_cmd_full     <= '0';  
+
+                        p1_wr_count    <= (others => '0');
+                        p1_rd_count    <= (others => '0');
+                        p1_wr_full_i     <= '0';
+                        p1_wr_error    <= '0';
+                        p1_wr_empty    <= '0';
+                        p1_wr_underrun <= '0';
+                        p1_rd_overflow <= '0';
+                        p1_rd_error    <= '0'; 
+                        p1_rd_full     <= '0'; 
+                        p1_rd_empty_i    <= '0'; 
+                        p1_rd_data     <= (others => '0');
+                       
+end generate;                       
+              
+                 -- unused MCB's signals in this configuration
+                        mig_p3_arb_en      <=       '0';
+                        mig_p4_arb_en      <=       '0';
+                        mig_p5_arb_en      <=       '0';
+                       
+                        mig_p3_cmd_clk      <=       '0';
+                        mig_p3_cmd_en      <=       '0';
+                        mig_p3_cmd_ra      <=      (others => '0');
+                        mig_p3_cmd_ba      <=      (others => '0');
+                        mig_p3_cmd_ca      <=      (others => '0');
+                        mig_p3_cmd_instr   <=      (others => '0');
+
+                        mig_p4_cmd_clk      <=       '0';
+                        mig_p4_cmd_en      <=       '0';
+                        mig_p4_cmd_ra      <=      (others => '0');
+                        mig_p4_cmd_ba      <=      (others => '0');
+                        mig_p4_cmd_ca      <=      (others => '0');
+                        mig_p4_cmd_instr   <=      (others => '0');
+                        mig_p4_cmd_bl      <=      (others => '0');
+
+                        mig_p5_cmd_clk      <=       '0';
+                        mig_p5_cmd_en      <=       '0';
+                        mig_p5_cmd_ra      <=      (others => '0');
+                        mig_p5_cmd_ba      <=      (others => '0');
+                        mig_p5_cmd_ca      <=      (others => '0');                       
+                        mig_p5_cmd_instr   <=      (others => '0');
+                        mig_p5_cmd_bl      <=      (others => '0');
+
+ end generate;                       
+               
+                
+--*******************************BEGIN OF CONFIG 5 SIGNALS ********************************     
+
+u_config_5:   if(C_PORT_CONFIG = "B128" ) generate
+
+
+              -- Inputs from Application CMD Port
+               
+                mig_p0_arb_en      <=  p0_arb_en ;
+                mig_p0_cmd_clk     <=  p0_cmd_clk  ;
+                mig_p0_cmd_en      <=  p0_cmd_en   ;
+                mig_p0_cmd_ra      <=  p0_cmd_ra  ;
+                mig_p0_cmd_ba      <=  p0_cmd_ba   ;
+                mig_p0_cmd_ca      <=  p0_cmd_ca  ;
+                mig_p0_cmd_instr   <=  p0_cmd_instr;
+                mig_p0_cmd_bl      <=      ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0))  ;               
+                p0_cmd_empty       <=      mig_p0_cmd_empty ;
+                p0_cmd_full        <=      mig_p0_cmd_full  ;
+               
+ 
+ 
+               -- Inputs from Application User Port
+                
+                 mig_p0_wr_clk   <= p0_wr_clk;
+                 mig_p0_rd_clk   <= p0_rd_clk;
+                 mig_p1_wr_clk   <= p0_wr_clk;
+                 mig_p1_rd_clk   <= p0_rd_clk;
+                
+                 mig_p2_clk   <= p0_rd_clk;
+                 mig_p3_clk   <= p0_wr_clk;
+                 mig_p4_clk   <= p0_rd_clk;
+                 mig_p5_clk   <= p0_wr_clk;
+                
+                
+                
+                 mig_p0_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                 mig_p1_wr_en    <= p0_wr_en and not p0_wr_full_i;
+                 mig_p3_en       <= p0_wr_en and not p0_wr_full_i;
+                 mig_p5_en       <= p0_wr_en and not p0_wr_full_i;
+                
+                
+                
+                 mig_p0_wr_data <= p0_wr_data(31 downto 0);
+                 mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
+                 mig_p1_wr_data <= p0_wr_data(63  downto  32);
+                 mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7  downto  4);                
+                 mig_p3_wr_data <= p0_wr_data(95  downto  64);
+                 mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11  downto  8);
+                 mig_p5_wr_data <= p0_wr_data(127  downto  96);
+                 mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15  downto  12);
+                
+                 mig_p0_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+                 mig_p1_rd_en    <= p0_rd_en and not p0_rd_empty_i;
+                 mig_p2_en       <= p0_rd_en and not p0_rd_empty_i;
+                 mig_p4_en       <= p0_rd_en and not p0_rd_empty_i;
+                
+               -- outputs to Applications User Port
+                 p0_rd_data     <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
+                 p0_rd_empty_i    <= mig_p4_empty;
+                 p0_rd_full     <= mig_p4_full;
+                 p0_rd_error    <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;  
+                 p0_rd_overflow    <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow; 
+
+                 p0_wr_underrun    <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;      
+                 p0_wr_empty    <= mig_p5_empty;
+                 p0_wr_full_i     <= mig_p5_full;
+                 p0_wr_error    <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error; 
+                
+                 p0_wr_count    <= mig_p5_count;
+                 p0_rd_count    <= mig_p4_count;
+
+
+              -- unused MCB's siganls in this configuration
+               
+                mig_p1_arb_en      <=       '0';
+                mig_p1_cmd_clk      <=       '0';
+                mig_p1_cmd_en      <=       '0';
+                mig_p1_cmd_ra      <=      (others => '0');
+                mig_p1_cmd_ba      <=      (others => '0');
+                mig_p1_cmd_ca      <=      (others => '0');
+               
+                mig_p1_cmd_instr   <=      (others => '0');
+                mig_p1_cmd_bl      <=      (others => '0');
+               
+                mig_p2_arb_en    <=      '0';
+                mig_p2_cmd_clk      <=       '0';
+                mig_p2_cmd_en      <=       '0';
+                mig_p2_cmd_ra      <=      (others => '0');
+                mig_p2_cmd_ba      <=      (others => '0');
+                mig_p2_cmd_ca      <=      (others => '0');
+               
+                mig_p2_cmd_instr   <=      (others => '0');
+                mig_p2_cmd_bl      <=      (others => '0');
+               
+                mig_p3_arb_en    <=      '0';
+                mig_p3_cmd_clk      <=       '0';
+                mig_p3_cmd_en      <=       '0';
+                mig_p3_cmd_ra      <=      (others => '0');
+                mig_p3_cmd_ba      <=      (others => '0');
+                mig_p3_cmd_ca      <=      (others => '0');
+               
+                mig_p3_cmd_instr   <=      (others => '0');
+                mig_p3_cmd_bl      <=      (others => '0');
+               
+                mig_p4_arb_en    <=      '0';
+                mig_p4_cmd_clk      <=       '0';
+                mig_p4_cmd_en      <=       '0';
+                mig_p4_cmd_ra      <=      (others => '0');
+                mig_p4_cmd_ba      <=      (others => '0');
+                mig_p4_cmd_ca      <=      (others => '0');
+               
+                mig_p4_cmd_instr   <=      (others => '0');
+                mig_p4_cmd_bl      <=      (others => '0');
+               
+                mig_p5_arb_en    <=       '0';
+                mig_p5_cmd_clk      <=       '0';
+                mig_p5_cmd_en      <=       '0';
+                mig_p5_cmd_ra      <=      (others => '0');
+                mig_p5_cmd_ba      <=      (others => '0');
+                mig_p5_cmd_ca      <=      (others => '0');
+               
+                mig_p5_cmd_instr   <=      (others => '0');
+                mig_p5_cmd_bl      <=      (others => '0');
+                             
+--*******************************END OF CONFIG 5 SIGNALS ********************************     
+                                
+end generate;
+
+uo_cal_start <= uo_cal_start_int;
+
+
+
+samc_0:   MCB 
+   GENERIC MAP   
+     (          PORT_CONFIG             => C_PORT_CONFIG,                                   
+               MEM_WIDTH              => C_NUM_DQ_PINS    ,       
+               MEM_TYPE                => C_MEM_TYPE       ,
+               MEM_BURST_LEN            => C_MEM_BURST_LEN  , 
+               MEM_ADDR_ORDER           => C_MEM_ADDR_ORDER,              
+               MEM_CAS_LATENCY          => C_MEM_CAS_LATENCY,       
+               MEM_DDR3_CAS_LATENCY      => C_MEM_DDR3_CAS_LATENCY   ,
+               MEM_DDR2_WRT_RECOVERY     => C_MEM_DDR2_WRT_RECOVERY  ,
+               MEM_DDR3_WRT_RECOVERY     => C_MEM_DDR3_WRT_RECOVERY  ,
+               MEM_MOBILE_PA_SR          => C_MEM_MOBILE_PA_SR       ,
+               MEM_DDR1_2_ODS              => C_MEM_DDR1_2_ODS         ,
+               MEM_DDR3_ODS                => C_MEM_DDR3_ODS           ,
+               MEM_DDR2_RTT                => C_MEM_DDR2_RTT           ,
+               MEM_DDR3_RTT                => C_MEM_DDR3_RTT           ,
+               MEM_DDR3_ADD_LATENCY        => C_MEM_DDR3_ADD_LATENCY   ,
+               MEM_DDR2_ADD_LATENCY        => C_MEM_DDR2_ADD_LATENCY   ,
+               MEM_MOBILE_TC_SR            => C_MEM_MOBILE_TC_SR       ,
+               MEM_MDDR_ODS                => C_MEM_MDDR_ODS           ,
+               MEM_DDR2_DIFF_DQS_EN        => C_MEM_DDR2_DIFF_DQS_EN   ,
+               MEM_DDR2_3_PA_SR            => C_MEM_DDR2_3_PA_SR       ,
+               MEM_DDR3_CAS_WR_LATENCY    => C_MEM_DDR3_CAS_WR_LATENCY,
+               MEM_DDR3_AUTO_SR           => C_MEM_DDR3_AUTO_SR       ,
+               MEM_DDR2_3_HIGH_TEMP_SR    => C_MEM_DDR2_3_HIGH_TEMP_SR,
+               MEM_DDR3_DYN_WRT_ODT       => C_MEM_DDR3_DYN_WRT_ODT   ,
+               MEM_RA_SIZE               => C_MEM_ADDR_WIDTH            ,
+               MEM_BA_SIZE               => C_MEM_BANKADDR_WIDTH            ,
+               MEM_CA_SIZE               => C_MEM_NUM_COL_BITS            ,
+               MEM_RAS_VAL               => MEM_RAS_VAL            , 
+               MEM_RCD_VAL               => MEM_RCD_VAL            , 
+               MEM_REFI_VAL               => MEM_REFI_VAL           , 
+               MEM_RFC_VAL               => MEM_RFC_VAL            , 
+               MEM_RP_VAL                => MEM_RP_VAL             , 
+               MEM_WR_VAL                => MEM_WR_VAL             , 
+               MEM_RTP_VAL               => MEM_RTP_VAL            , 
+               MEM_WTR_VAL               => MEM_WTR_VAL            ,
+               CAL_BYPASS        => C_MC_CALIB_BYPASS,     
+               CAL_RA            => C_MC_CALIBRATION_RA,    
+               CAL_BA            => C_MC_CALIBRATION_BA ,   
+               CAL_CA            => C_MC_CALIBRATION_CA, 
+               CAL_CLK_DIV        => C_MC_CALIBRATION_CLK_DIV,      
+               CAL_DELAY         => C_MC_CALIBRATION_DELAY,
+--               CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
+               ARB_NUM_TIME_SLOTS         => C_ARB_NUM_TIME_SLOTS,
+               ARB_TIME_SLOT_0            => C_ARB_TIME_SLOT_0,        
+               ARB_TIME_SLOT_1            => C_ARB_TIME_SLOT_1,        
+               ARB_TIME_SLOT_2            => C_ARB_TIME_SLOT_2,        
+               ARB_TIME_SLOT_3            => C_ARB_TIME_SLOT_3,        
+               ARB_TIME_SLOT_4            => C_ARB_TIME_SLOT_4,        
+               ARB_TIME_SLOT_5            => C_ARB_TIME_SLOT_5,        
+               ARB_TIME_SLOT_6            => C_ARB_TIME_SLOT_6,        
+               ARB_TIME_SLOT_7            => C_ARB_TIME_SLOT_7,        
+               ARB_TIME_SLOT_8            => C_ARB_TIME_SLOT_8,        
+               ARB_TIME_SLOT_9            => C_ARB_TIME_SLOT_9,        
+               ARB_TIME_SLOT_10           => C_ARB_TIME_SLOT_10,            
+               ARB_TIME_SLOT_11           => C_ARB_TIME_SLOT_11            
+             )   PORT MAP                                                
+     (
+                                                                    
+            -- HIGH-SPEED PLL clock interface
+             
+             PLLCLK            => pllclk1,
+             PLLCE              => pllce1,
+
+             PLLLOCK           => '1',
+             
+            -- DQS CLOCK NETWork interface
+             
+             DQSIOIN           => idelay_dqs_ioi_s,
+             DQSIOIP           => idelay_dqs_ioi_m,
+             UDQSIOIN          => idelay_udqs_ioi_s,
+             UDQSIOIP          => idelay_udqs_ioi_m,
+
+
+              --DQSPIN    => in_pre_dqsp,
+               DQI       => in_dq,
+            -- RESETS - GLOBAl and local
+             SYSRST         => MCB_SYSRST ,
+   
+           -- command port 0
+             P0ARBEN            => mig_p0_arb_en,
+             P0CMDCLK           => mig_p0_cmd_clk,
+             P0CMDEN            => mig_p0_cmd_en,
+             P0CMDRA            => mig_p0_cmd_ra,
+             P0CMDBA            => mig_p0_cmd_ba,
+             P0CMDCA            => mig_p0_cmd_ca,
+             
+             P0CMDINSTR         => mig_p0_cmd_instr,
+             P0CMDBL            => mig_p0_cmd_bl,
+             P0CMDEMPTY         => mig_p0_cmd_empty,
+             P0CMDFULL          => mig_p0_cmd_full,
+             
+            -- command port 1 
+            
+             P1ARBEN            => mig_p1_arb_en,
+             P1CMDCLK           => mig_p1_cmd_clk,
+             P1CMDEN            => mig_p1_cmd_en,
+             P1CMDRA            => mig_p1_cmd_ra,
+             P1CMDBA            => mig_p1_cmd_ba,
+             P1CMDCA            => mig_p1_cmd_ca,
+             
+             P1CMDINSTR         => mig_p1_cmd_instr,
+             P1CMDBL            => mig_p1_cmd_bl,
+             P1CMDEMPTY         => mig_p1_cmd_empty,
+             P1CMDFULL          => mig_p1_cmd_full,
+
+            -- command port 2
+             
+             P2ARBEN            => mig_p2_arb_en,
+             P2CMDCLK           => mig_p2_cmd_clk,
+             P2CMDEN            => mig_p2_cmd_en,
+             P2CMDRA            => mig_p2_cmd_ra,
+             P2CMDBA            => mig_p2_cmd_ba,
+             P2CMDCA            => mig_p2_cmd_ca,
+             
+             P2CMDINSTR         => mig_p2_cmd_instr,
+             P2CMDBL            => mig_p2_cmd_bl,
+             P2CMDEMPTY         => mig_p2_cmd_empty,
+             P2CMDFULL          => mig_p2_cmd_full,
+
+            -- command port 3
+             
+             P3ARBEN            => mig_p3_arb_en,
+             P3CMDCLK           => mig_p3_cmd_clk,
+             P3CMDEN            => mig_p3_cmd_en,
+             P3CMDRA            => mig_p3_cmd_ra,
+             P3CMDBA            => mig_p3_cmd_ba,
+             P3CMDCA            => mig_p3_cmd_ca,
+                               
+             P3CMDINSTR         => mig_p3_cmd_instr,
+             P3CMDBL            => mig_p3_cmd_bl,
+             P3CMDEMPTY         => mig_p3_cmd_empty,
+             P3CMDFULL          => mig_p3_cmd_full,
+
+            -- command port 4 -- don't care in config 2
+             
+             P4ARBEN            => mig_p4_arb_en,
+             P4CMDCLK           => mig_p4_cmd_clk,
+             P4CMDEN            => mig_p4_cmd_en,
+             P4CMDRA            => mig_p4_cmd_ra,
+             P4CMDBA            => mig_p4_cmd_ba,
+             P4CMDCA            => mig_p4_cmd_ca,
+                               
+             P4CMDINSTR         => mig_p4_cmd_instr,
+             P4CMDBL            => mig_p4_cmd_bl,
+             P4CMDEMPTY         => mig_p4_cmd_empty,
+             P4CMDFULL          => mig_p4_cmd_full,
+
+            -- command port 5-- don't care in config 2
+             
+             P5ARBEN            => mig_p5_arb_en,
+             P5CMDCLK           => mig_p5_cmd_clk,
+             P5CMDEN            => mig_p5_cmd_en,
+             P5CMDRA            => mig_p5_cmd_ra,
+             P5CMDBA            => mig_p5_cmd_ba,
+             P5CMDCA            => mig_p5_cmd_ca,
+                               
+             P5CMDINSTR         => mig_p5_cmd_instr,
+             P5CMDBL            => mig_p5_cmd_bl,
+             P5CMDEMPTY         => mig_p5_cmd_empty,
+             P5CMDFULL          => mig_p5_cmd_full,
+
+              
+            -- IOI & IOB SIGNals/tristate interface
+             
+             DQIOWEN0        => dqIO_w_en_0,
+             DQSIOWEN90P     => dqsIO_w_en_90_p,
+             DQSIOWEN90N     => dqsIO_w_en_90_n,
+             
+             
+            -- IOB MEMORY INTerface signals
+             ADDR         => address_90, 
+             BA           => ba_90 ,     
+             RAS         => ras_90 ,    
+             CAS         => cas_90 ,    
+             WE          => we_90  ,    
+             CKE          => cke_90 ,    
+             ODT          => odt_90 ,    
+             RST          => rst_90 ,    
+             
+            -- CALIBRATION DRP interface
+             IOIDRPCLK           => ioi_drp_clk    ,
+             IOIDRPADDR          => ioi_drp_addr   ,
+             IOIDRPSDO           => ioi_drp_sdo    ,
+             IOIDRPSDI           => ioi_drp_sdi    ,
+             IOIDRPCS            => ioi_drp_cs     ,
+             IOIDRPADD           => ioi_drp_add    ,
+             IOIDRPBROADCAST     => ioi_drp_broadcast  ,
+             IOIDRPTRAIN         => ioi_drp_train    ,
+             IOIDRPUPDATE         => ioi_drp_update ,
+             
+            -- CALIBRATION DAtacapture interface
+            --SPECIAL COMMANDs
+             RECAL               => mcb_recal    ,
+             UIREAD               => mcb_ui_read,
+             UIADD                => mcb_ui_add    ,
+             UICS                 => mcb_ui_cs     ,
+             UICLK                => mcb_ui_clk    ,
+             UISDI                => mcb_ui_sdi    ,
+             UIADDR               => mcb_ui_addr   ,
+             UIBROADCAST          => mcb_ui_broadcast,
+             UIDRPUPDATE          => mcb_ui_drp_update,
+             UIDONECAL            => mcb_ui_done_cal,
+             UICMD                => mcb_ui_cmd,
+             UICMDIN              => mcb_ui_cmd_in,
+             UICMDEN              => mcb_ui_cmd_en,
+             UIDQCOUNT            => mcb_ui_dqcount,
+             UIDQLOWERDEC          => mcb_ui_dq_lower_dec,
+             UIDQLOWERINC          => mcb_ui_dq_lower_inc,
+             UIDQUPPERDEC          => mcb_ui_dq_upper_dec,
+             UIDQUPPERINC          => mcb_ui_dq_upper_inc,
+             UIUDQSDEC          => mcb_ui_udqs_dec,
+             UIUDQSINC          => mcb_ui_udqs_inc,
+             UILDQSDEC          => mcb_ui_ldqs_dec,
+             UILDQSINC          => mcb_ui_ldqs_inc,
+             UODATA             => uo_data_int,
+             UODATAVALID          => uo_data_valid_int,
+             UODONECAL            => hard_done_cal  ,
+             UOCMDREADYIN         => uo_cmd_ready_in_int,
+             UOREFRSHFLAG         => uo_refrsh_flag_xhdl23,
+             UOCALSTART           => uo_cal_start_int,
+             UOSDO                => uo_sdo_xhdl24,
+
+            --CONTROL SIGNALS
+              STATUS                    => status,
+              SELFREFRESHENTER          => selfrefresh_mcb_enter,
+              SELFREFRESHMODE           => selfrefresh_mcb_mode, 
+------------------------------------------------
+--MUIs
+------------------------------------------------
+            
+              P0RDDATA         =>  mig_p0_rd_data ( 31 downto 0),
+              P1RDDATA         =>  mig_p1_rd_data ( 31 downto 0),
+              P2RDDATA         =>  mig_p2_rd_data ( 31 downto 0),
+              P3RDDATA         =>  mig_p3_rd_data ( 31 downto 0),
+              P4RDDATA         =>  mig_p4_rd_data ( 31 downto 0),
+              P5RDDATA         =>  mig_p5_rd_data ( 31 downto 0),
+              LDMN             =>  dqnlm       ,
+              UDMN             =>  dqnum       ,
+              DQON             =>  dqo_n       ,
+              DQOP             =>  dqo_p       ,
+              LDMP             =>  dqplm       ,
+              UDMP             =>  dqpum       ,
+              
+              P0RDCOUNT          =>  mig_p0_rd_count ,
+              P0WRCOUNT          =>  mig_p0_wr_count ,
+              P1RDCOUNT          =>  mig_p1_rd_count ,
+              P1WRCOUNT          =>  mig_p1_wr_count ,
+              P2COUNT           =>  mig_p2_count  ,
+              P3COUNT           =>  mig_p3_count  ,
+              P4COUNT           =>  mig_p4_count  ,
+              P5COUNT           =>  mig_p5_count  ,
+              
+             -- NEW ADDED FIFo status siganls
+             -- MIG USER PORT 0
+              P0RDEMPTY        =>  mig_p0_rd_empty,
+              P0RDFULL         =>  mig_p0_rd_full,
+              P0RDOVERFLOW     =>  mig_p0_rd_overflow,
+              P0WREMPTY        =>  mig_p0_wr_empty,
+              P0WRFULL         =>  mig_p0_wr_full,
+              P0WRUNDERRUN     =>  mig_p0_wr_underrun,
+             -- MIG USER PORT 1
+              P1RDEMPTY        =>  mig_p1_rd_empty,
+              P1RDFULL         =>  mig_p1_rd_full,
+              P1RDOVERFLOW     =>  mig_p1_rd_overflow, 
+              P1WREMPTY        =>  mig_p1_wr_empty,
+              P1WRFULL         =>  mig_p1_wr_full,
+              P1WRUNDERRUN     =>  mig_p1_wr_underrun, 
+              
+             -- MIG USER PORT 2
+              P2EMPTY          =>  mig_p2_empty,
+              P2FULL           =>  mig_p2_full,
+              P2RDOVERFLOW        =>  mig_p2_overflow,
+              P2WRUNDERRUN       =>  mig_p2_underrun,
+              
+              P3EMPTY          =>  mig_p3_empty ,
+              P3FULL           =>  mig_p3_full ,
+              P3RDOVERFLOW        =>  mig_p3_overflow,
+              P3WRUNDERRUN       =>  mig_p3_underrun ,
+             -- MIG USER PORT 3
+              P4EMPTY          =>  mig_p4_empty,
+              P4FULL           =>  mig_p4_full,
+              P4RDOVERFLOW        =>  mig_p4_overflow,
+              P4WRUNDERRUN       =>  mig_p4_underrun,
+              
+              P5EMPTY          =>  mig_p5_empty ,
+              P5FULL           =>  mig_p5_full ,
+              P5RDOVERFLOW        =>  mig_p5_overflow,
+              P5WRUNDERRUN       =>  mig_p5_underrun,
+              
+             ---------------------------------------------------------
+              P0WREN        =>  mig_p0_wr_en,
+              P0RDEN        =>  mig_p0_rd_en,                        
+              P1WREN        =>  mig_p1_wr_en,
+              P1RDEN        =>  mig_p1_rd_en,
+              P2EN          =>  mig_p2_en,
+              P3EN          =>  mig_p3_en,
+              P4EN          =>  mig_p4_en,
+              P5EN          =>  mig_p5_en,
+             -- WRITE  MASK BIts connection
+              P0RWRMASK        =>  mig_p0_wr_mask(3 downto 0),
+              P1RWRMASK        =>  mig_p1_wr_mask(3 downto 0),
+              P2WRMASK        =>  mig_p2_wr_mask(3 downto 0),
+              P3WRMASK        =>  mig_p3_wr_mask(3 downto 0),
+              P4WRMASK        =>  mig_p4_wr_mask(3 downto 0),
+              P5WRMASK        =>  mig_p5_wr_mask(3 downto 0),
+             -- DATA WRITE COnnection
+              P0WRDATA      =>  mig_p0_wr_data(31 downto 0),
+              P1WRDATA      =>  mig_p1_wr_data(31 downto 0),
+              P2WRDATA      =>  mig_p2_wr_data(31 downto 0),
+              P3WRDATA      =>  mig_p3_wr_data(31 downto 0),
+              P4WRDATA      =>  mig_p4_wr_data(31 downto 0),
+              P5WRDATA      =>  mig_p5_wr_data(31 downto 0),
+              
+              P0WRERROR     => mig_p0_wr_error,
+              P1WRERROR     => mig_p1_wr_error,
+              P0RDERROR     => mig_p0_rd_error,
+              P1RDERROR     => mig_p1_rd_error,
+              
+              P2ERROR       => mig_p2_error,
+              P3ERROR       => mig_p3_error,
+              P4ERROR       => mig_p4_error,
+              P5ERROR       => mig_p5_error,
+              
+             --  USER SIDE DAta ports clock
+             --  128 BITS CONnections
+              P0WRCLK            =>  mig_p0_wr_clk  ,
+              P1WRCLK            =>  mig_p1_wr_clk  ,
+              P0RDCLK            =>  mig_p0_rd_clk  ,
+              P1RDCLK            =>  mig_p1_rd_clk  ,
+              P2CLK              =>  mig_p2_clk  ,
+              P3CLK              =>  mig_p3_clk  ,
+              P4CLK              =>  mig_p4_clk  ,
+              P5CLK              =>  mig_p5_clk 
+              );
+
+--//////////////////////////////////////////////////////
+--// Input Termination Calibration
+--//////////////////////////////////////////////////////
+             
+
+--process(ui_clk)
+--begin
+--if (ui_clk'event and ui_clk = '1') then
+--      syn1_sys_rst <= sys_rst;
+--      syn2_sys_rst <= syn1_sys_rst;
+--end if;
+--end process;
+             
+ uo_done_cal_sig <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
+                         hard_done_cal;
+
+
+   gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
+      mcb_soft_calibration_top_inst : mcb_soft_calibration_top
+      generic map (   C_MEM_TZQINIT_MAXCNT  => C_MEM_TZQINIT_MAXCNT,
+                      C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, 
+                      SKIP_IN_TERM_CAL      => C_SKIP_IN_TERM_CAL,
+                      SKIP_DYNAMIC_CAL      => C_SKIP_DYNAMIC_CAL,
+                      SKIP_DYN_IN_TERM      => C_SKIP_DYN_IN_TERM,
+                      C_SIMULATION          => C_SIMULATION,
+                      C_MEM_TYPE            => C_MEM_TYPE
+                   )
+  
+         PORT MAP (
+            UI_CLK                => ui_clk,
+            --RST                   => syn2_sys_rst,
+            RST                   => int_sys_rst,
+            IOCLK                 => ioclk0,
+            DONE_SOFTANDHARD_CAL  => DONE_SOFTANDHARD_CAL,
+            --PLL_LOCK              => pll_lock,
+            PLL_LOCK              => gated_pll_lock,
+
+            --SELFREFRESH_REQ       => selfrefresh_enter,     -- from user app
+            SELFREFRESH_REQ       => soft_cal_selfrefresh_req,     -- from user app
+            SELFREFRESH_MCB_MODE  => selfrefresh_mcb_mode,  -- from MCB
+            SELFREFRESH_MCB_REQ   => selfrefresh_mcb_enter, -- to mcb
+            SELFREFRESH_MODE      => selfrefresh_mode_sig,      -- to user app
+
+            MCB_UIADD             => mcb_ui_add,
+            MCB_UISDI             => mcb_ui_sdi,
+            MCB_UOSDO             => uo_sdo_xhdl24,
+            MCB_UODONECAL         => hard_done_cal,
+            MCB_UOREFRSHFLAG      => uo_refrsh_flag_xhdl23,
+            MCB_UICS              => mcb_ui_cs,
+            MCB_UIDRPUPDATE       => mcb_ui_drp_update,
+            MCB_UIBROADCAST       => mcb_ui_broadcast,
+            MCB_UIADDR            => mcb_ui_addr,
+            MCB_UICMDEN           => mcb_ui_cmd_en,
+            MCB_UIDONECAL         => mcb_ui_done_cal,
+            MCB_UIDQLOWERDEC      => mcb_ui_dq_lower_dec,
+            MCB_UIDQLOWERINC      => mcb_ui_dq_lower_inc,
+            MCB_UIDQUPPERDEC      => mcb_ui_dq_upper_dec,
+            MCB_UIDQUPPERINC      => mcb_ui_dq_upper_inc,
+            MCB_UILDQSDEC         => mcb_ui_ldqs_dec,
+            MCB_UILDQSINC         => mcb_ui_ldqs_inc,
+            MCB_UIREAD            => mcb_ui_read,
+            MCB_UIUDQSDEC         => mcb_ui_udqs_dec,
+            MCB_UIUDQSINC         => mcb_ui_udqs_inc,
+            MCB_RECAL             => mcb_recal,
+            MCB_SYSRST            => MCB_SYSRST,
+            MCB_UICMD             => mcb_ui_cmd,
+            MCB_UICMDIN           => mcb_ui_cmd_in,    
+            MCB_UIDQCOUNT         => mcb_ui_dqcount,     
+            MCB_UODATA            => uo_data_int,    
+            MCB_UODATAVALID       => uo_data_valid_int,    
+            MCB_UOCMDREADY        => uo_cmd_ready_in_int, 
+            MCB_UO_CAL_START      => uo_cal_start_int,
+            RZQ_PIN               => rzq,
+            ZIO_PIN               => zio,
+            CKE_Train             => cke_train
+         );
+         mcb_ui_clk <= ui_clk;
+   END GENERATE;
+
+
+   gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
+      DONE_SOFTANDHARD_CAL <= '0';
+      MCB_SYSRST <= int_sys_rst or not(wait_200us_counter(15));
+      mcb_recal <= calib_recal;
+      mcb_ui_read <= ui_read;
+      mcb_ui_add <= ui_add;
+      mcb_ui_cs <= ui_cs;
+      mcb_ui_clk <= ui_clk;
+      mcb_ui_sdi <= ui_sdi;
+      mcb_ui_addr <= ui_addr;
+      mcb_ui_broadcast <= ui_broadcast;
+      mcb_ui_drp_update <= ui_drp_update;
+      mcb_ui_done_cal <= ui_done_cal;
+      mcb_ui_cmd <= ui_cmd;
+      mcb_ui_cmd_in <= ui_cmd_in;
+      mcb_ui_cmd_en <= ui_cmd_en;
+      mcb_ui_dqcount <= ui_dqcount;
+      mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
+      mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
+      mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
+      mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
+      mcb_ui_udqs_inc <= ui_udqs_inc;
+      mcb_ui_udqs_dec <= ui_udqs_dec;
+      mcb_ui_ldqs_inc <= ui_ldqs_inc;
+      mcb_ui_ldqs_dec <= ui_ldqs_dec;
+      selfrefresh_mode_sig <= '0';
+
+      -- synthesis translate_off
+      init_sequence: if (C_SIMULATION = "FALSE") generate      
+      -- synthesis translate_on
+         process (ui_clk, int_sys_rst)
+         begin
+            if (int_sys_rst = '1') then
+               wait_200us_counter <= (others => '0');
+            elsif (ui_clk'event and ui_clk = '1') then   -- UI_CLK maximum is up to 100 MHz
+               if (wait_200us_counter(15) = '1') then
+                  wait_200us_counter <= wait_200us_counter;
+               else
+                  wait_200us_counter <= wait_200us_counter + '1';
+               end if;
+            end if;
+         end process;
+      -- synthesis translate_off
+      end generate;
+
+      init_sequence_skip: if (C_SIMULATION = "TRUE") generate
+         wait_200us_counter <= X"FFFF";
+         process
+         begin
+            report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
+            wait;
+         end process;
+      end generate;
+      -- synthesis translate_on
+ 
+      gen_cketrain_a: if (C_MEM_TYPE = "DDR2") generate
+         process (ui_clk)
+         begin
+            -- When wait_200us_[13] and wait_200us_[14] are both asserted,
+            -- 200 us wait should have been passed. 
+            if (ui_clk'event and ui_clk = '1') then
+               if ((wait_200us_counter(14) and wait_200us_counter(13)) = '1') then
+                  wait_200us_done_r1 <= '1';
+               else
+                  wait_200us_done_r1 <= '0';
+               end if;
+               wait_200us_done_r2 <= wait_200us_done_r1;
+            end if;
+         end process;
+
+         process (ui_clk, int_sys_rst)
+         begin
+            if (int_sys_rst = '1') then
+               cke_train_reg <= '0';
+            elsif (ui_clk'event and ui_clk = '1') then
+               if ((wait_200us_done_r1 and not(wait_200us_done_r2)) = '1') then
+                  cke_train_reg <= '1';
+               elsif (uo_done_cal_sig = '1') then
+                  cke_train_reg <= '0';
+               end if;
+            end if;
+         end process;
+
+         cke_train <= cke_train_reg;
+      end generate;      
+
+      gen_cketrain_b: if (NOT(C_MEM_TYPE = "DDR2")) generate
+         
+         cke_train <= '0';
+
+      end generate;
+
+   end generate;
+   
+
+
+--//////////////////////////////////////////////////////
+--//ODDRDES2 instantiations
+--//////////////////////////////////////////////////////
+
+--------
+--ADDR
+--------
+
+   gen_addr_oserdes2 : FOR addr_ioi IN 0 TO  C_MEM_ADDR_WIDTH - 1 GENERATE
+      
+      
+      ioi_addr_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2
+         )
+         PORT MAP (
+            OQ         => ioi_addr(addr_ioi),
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => t_addr(addr_ioi),
+            CLK0       => ioclk0,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => address_90(addr_ioi),
+            D2         => address_90(addr_ioi),
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_0,
+            OCE        => '1',
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => '0',
+            T2         => '0',
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => '0'
+         );
+   END GENERATE;
+
+--------
+--BA
+--------
+
+   gen_ba_oserdes2 : FOR ba_ioi IN 0 TO  C_MEM_BANKADDR_WIDTH - 1 GENERATE
+      
+      
+      ioi_ba_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2
+         )
+         PORT MAP (
+            OQ         => ioi_ba(ba_ioi),
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => t_ba(ba_ioi),
+            CLK0       => ioclk0,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => ba_90(ba_ioi),
+            D2         => ba_90(ba_ioi),
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_0,
+            OCE        => '1',
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => '0',
+            T2         => '0',
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => '0'
+         );
+   END GENERATE;
+   
+--------
+--CAS
+--------
+   ioi_cas_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ioi_cas,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => t_cas,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => cas_90,
+         D2         => cas_90,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--CKE
+--------
+   ioi_cke_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2,
+         TRAIN_PATTERN   => 15
+      )
+      PORT MAP (
+         OQ         => ioi_cke,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => t_cke,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => cke_90,
+         D2         => cke_90,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         --OCE        => '1',
+         OCE        => pll_lock,
+         RST        => '0', --int_sys_rst
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => cke_train
+      );
+--------
+--ODT
+--------
+   xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
+      
+      ioi_odt_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2
+--            TRAIN_PATTERN   => 0
+         )
+         PORT MAP (
+            OQ         => ioi_odt,
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => t_odt,
+            CLK0       => ioclk0,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => odt_90,
+            D2         => odt_90,
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_0,
+            OCE        => '1',
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => '0',
+            T2         => '0',
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => '0'
+         );
+   END GENERATE;
+
+--------
+--RAS
+--------
+   ioi_ras_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ioi_ras,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => t_ras,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => ras_90,
+         D2         => ras_90,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+--------
+--RST
+--------
+   xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
+      ioi_rst_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2
+         )
+         PORT MAP (
+            OQ         => ioi_rst,
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => t_rst,
+            CLK0       => ioclk0,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => rst_90,
+            D2         => rst_90,
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_0,
+            --OCE        => '1',
+            OCE        => pll_lock,
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => '0',
+            T2         => '0',
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => '0'
+         );
+   END GENERATE;
+--------
+--WE
+--------
+   ioi_we_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ioi_we,
+         TQ         => t_we,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => we_90,
+         D2         => we_90,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--CK
+--------
+   ioi_ck_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,                    
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ioi_ck,
+         SHIFTOUT1  => open,--ck_shiftout0_1,
+         SHIFTOUT2  => open,--ck_shiftout0_2,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => t_ck,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '0',
+         D2         => '1',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         --OCE        => '1',
+         OCE        => pll_lock,
+         RST        => '0', --int_sys_rst
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => '0',
+         T2         => '0',
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+----------
+----CKN
+----------
+--   ioi_ckn_0 : OSERDES2
+--      GENERIC MAP (
+--         BYPASS_GCLK_FF  => TRUE,
+--         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+--         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+--         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+--         SERDES_MODE     => C_OSERDES2_SERDES_MODE_SLAVE,
+--         DATA_WIDTH      => 2
+--      )
+--      PORT MAP (
+--         OQ         => ioi_ckn,
+--         SHIFTOUT1  => open,
+--         SHIFTOUT2  => open,
+--         SHIFTOUT3  => open,--ck_shiftout1_3,
+--         SHIFTOUT4  => open,--ck_shiftout1_4,
+--         TQ         => t_ckn,
+--         CLK0       => ioclk0,
+--         CLK1       => '0',
+--         CLKDIV     => '0',
+--         D1         => '1',
+--         D2         => '0',
+--         D3         => '0',
+--         D4         => '0',
+--         IOCE       => pll_ce_0,
+--         OCE        => '1',
+--         RST        => '0',
+--         SHIFTIN1   => '0',
+--         SHIFTIN2   => '0',
+--         SHIFTIN3   => '0',
+--         SHIFTIN4   => '0',
+--         T1         => '0',
+--         T2         => '0',
+--         T3         => '0',
+--         T4         => '0',
+--         TCE        => '1',
+--         TRAIN      => '0'
+--      );
+--   
+--------
+--UDM
+--------
+   
+   ioi_udm_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => udm_oq,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => udm_t,
+         CLK0       => ioclk90,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => dqpum,
+         D2         => dqnum,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_90,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => dqIO_w_en_0,
+         T2         => dqIO_w_en_0,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--LDM
+--------
+   ioi_ldm_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+      )
+      PORT MAP (
+         OQ         => ldm_oq,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => ldm_t,
+         CLK0       => ioclk90,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => dqplm,
+         D2         => dqnlm,
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_90,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => dqIO_w_en_0,
+         T2         => dqIO_w_en_0,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+--------
+--DQ
+--------
+   gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
+      oserdes2_dq_0 : OSERDES2
+         GENERIC MAP (
+            BYPASS_GCLK_FF  => TRUE,
+            DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+            DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+            OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+            SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+            DATA_WIDTH      => 2,
+            TRAIN_PATTERN   => 5
+         )
+         PORT MAP (
+            OQ         => dq_oq(dq),
+            SHIFTOUT1  => open,
+            SHIFTOUT2  => open,
+            SHIFTOUT3  => open,
+            SHIFTOUT4  => open,
+            TQ         => dq_tq(dq),
+            CLK0       => ioclk90,
+            CLK1       => '0',
+            CLKDIV     => '0',
+            D1         => dqo_p(dq),
+            D2         => dqo_n(dq),
+            D3         => '0',
+            D4         => '0',
+            IOCE       => pll_ce_90,
+            OCE        => '1',
+            RST        => int_sys_rst,
+            SHIFTIN1   => '0',
+            SHIFTIN2   => '0',
+            SHIFTIN3   => '0',
+            SHIFTIN4   => '0',
+            T1         => dqIO_w_en_0,
+            T2         => dqIO_w_en_0,
+            T3         => '0',
+            T4         => '0',
+            TCE        => '1',
+            TRAIN      => ioi_drp_train
+         );
+   END GENERATE;
+
+--------
+--DQSP
+--------
+   
+   
+   oserdes2_dqsp_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+     --    TRAIN_PATTERN   => 0
+      )
+      PORT MAP (
+         OQ         => dqsp_oq,
+         SHIFTOUT1  => open,--dqs_shiftout0_1,
+         SHIFTOUT2  => open,--dqs_shiftout0_2,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => dqsp_tq,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '0',
+         D2         => '1',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',--dqs_shiftout1_3,
+         SHIFTIN4   => '0',--dqs_shiftout1_4,
+         T1         => dqsIO_w_en_90_n,
+         T2         => dqsIO_w_en_90_p,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--DQSN
+--------
+   
+   oserdes2_dqsn_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_SLAVE,
+         DATA_WIDTH      => 2
+  --       TRAIN_PATTERN   => 0
+      )
+      PORT MAP (
+         OQ         => dqsn_oq,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,--dqs_shiftout1_3,
+         SHIFTOUT4  => open,--dqs_shiftout1_4,
+         TQ         => dqsn_tq,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '1',
+         D2         => '0',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',--dqs_shiftout0_1,
+         SHIFTIN2   => '0',--dqs_shiftout0_2,
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => dqsIO_w_en_90_n,
+         T2         => dqsIO_w_en_90_p,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+--------
+--UDQSP
+--------
+   
+   oserdeS2_UDQSP_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_MASTER,
+         DATA_WIDTH      => 2
+--         TRAIN_PATTERN   => 0
+      )
+      PORT MAP (
+         OQ         => udqsp_oq,
+         SHIFTOUT1  => open,--udqs_shiftout0_1,
+         SHIFTOUT2  => open,--udqs_shiftout0_2,
+         SHIFTOUT3  => open,
+         SHIFTOUT4  => open,
+         TQ         => udqsp_tq,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '0',
+         D2         => '1',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',
+         SHIFTIN2   => '0',
+         SHIFTIN3   => '0',--udqs_shiftout1_3,
+         SHIFTIN4   => '0',--udqs_shiftout1_4,
+         T1         => dqsIO_w_en_90_n,
+         t2         => dqsIO_w_en_90_p,
+         T3         => '0',
+         T4         => '0',
+         tce        => '1',
+         train      => '0'
+      );
+   
+--------
+--UDQSN
+--------
+   
+   oserdes2_udqsn_0 : OSERDES2
+      GENERIC MAP (
+         BYPASS_GCLK_FF  => TRUE,
+         DATA_RATE_OQ    => C_OSERDES2_DATA_RATE_OQ,
+         DATA_RATE_OT    => C_OSERDES2_DATA_RATE_OT,
+         OUTPUT_MODE     => C_OSERDES2_OUTPUT_MODE_SE,
+         SERDES_MODE     => C_OSERDES2_SERDES_MODE_SLAVE,
+         DATA_WIDTH      => 2
+--         TRAIN_PATTERN   => 0
+      )
+      PORT MAP (
+         OQ         => udqsn_oq,
+         SHIFTOUT1  => open,
+         SHIFTOUT2  => open,
+         SHIFTOUT3  => open,--udqs_shiftout1_3,
+         SHIFTOUT4  => open,--udqs_shiftout1_4,
+         TQ         => udqsn_tq,
+         CLK0       => ioclk0,
+         CLK1       => '0',
+         CLKDIV     => '0',
+         D1         => '1',
+         D2         => '0',
+         D3         => '0',
+         D4         => '0',
+         IOCE       => pll_ce_0,
+         OCE        => '1',
+         RST        => int_sys_rst,
+         SHIFTIN1   => '0',--udqs_shiftout0_1,
+         SHIFTIN2   => '0',--udqs_shiftout0_2,
+         SHIFTIN3   => '0',
+         SHIFTIN4   => '0',
+         T1         => dqsIO_w_en_90_n,
+         T2         => dqsIO_w_en_90_p,
+         T3         => '0',
+         T4         => '0',
+         TCE        => '1',
+         TRAIN      => '0'
+      );
+   
+------------------------------------------------------
+--*********************************** OSERDES2 instantiations end *******************************************
+------------------------------------------------------
+
+------------------------------------------------
+--&&&&&&&&&&&&&&&&&&&&&&&&&&&  IODRP2 instantiations  &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
+------------------------------------------------
+---#####################################--X16 MEMORY WIDTH-#############################################
+   
+   dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
+
+--////////////////////////////////////////////////
+--DQ14
+--////////////////////////////////////////////////
+
+   iodrp2_DQ_14 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ14_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 7,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_14,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(14),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(14),
+         SDO        => open,
+         TOUT       => t_dq(14),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_15,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(14),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(14),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(14)
+      );
+
+--////////////////////////////////////////////////
+--DQ15
+--////////////////////////////////////////////////
+   
+   
+   iodrp2_dq_15 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ15_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 7,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_15,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(15),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(15),
+         SDO        => open,
+         TOUT       => t_dq(15),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => '0',
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(15),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(15),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(15)
+      );
+   
+--////////////////////////////////////////////////
+--DQ12
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_12 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ12_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 6,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_12,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(12),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(12),
+         SDO        => open,
+         TOUT       => t_dq(12),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_13,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(12),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(12),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(12)
+      );
+   
+--////////////////////////////////////////////////
+--DQ13
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_13 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ13_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 6,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_13,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(13),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(13),
+         SDO        => open,
+         TOUT       => t_dq(13),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_14,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(13),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(13),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(13)
+      );
+   
+--/////////
+--UDQSP
+--/////////
+   
+   iodrp2_UDQSP_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => UDQSP_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 14,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_udqsp,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udqs,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_udqs_ioi_m,
+         SDO        => open,
+         TOUT       => t_udqs,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_udqsn,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_udqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udqsp_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udqsp_tq
+      );
+   
+--/////////
+--UDQSN
+--/////////
+   
+   iodrp2_udqsn_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => UDQSN_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 14,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_udqsn,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udqsn,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_udqs_ioi_s,
+         SDO        => open,
+         TOUT       => t_udqsn,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_12,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_udqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udqsn_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udqsn_tq
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ10
+--////////////////////////////////////////////////   
+   iodrp2_DQ_10 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ10_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 5,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_10,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(10),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(10),
+         SDO        => open,
+         TOUT       => t_dq(10),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_11,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(10),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(10),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(10)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ11
+--////////////////////////////////////////////////   
+   
+   iodrp2_dq_11 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ11_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 5,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_11,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(11),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(11),
+         SDO        => open,
+         TOUT       => t_dq(11),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_udqsp,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(11),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(11),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(11)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ8
+--////////////////////////////////////////////////   
+   
+   iodrp2_DQ_8 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ8_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 4,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_8,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(8),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(8),
+         SDO        => open,
+         TOUT       => t_dq(8),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_9,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(8),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(8),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(8)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ9
+--////////////////////////////////////////////////   
+   
+   iodrp2_dq_9 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ9_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 4,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_9,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(9),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(9),
+         SDO        => open,
+         TOUT       => t_dq(9),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_10,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(9),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(9),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(9)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ0
+--////////////////////////////////////////////////   
+   
+   iodrp2_DQ_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ0_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_0,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(0),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(0),
+         SDO        => open,
+         TOUT       => t_dq(0),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_1,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(0),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(0),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(0)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ1
+--////////////////////////////////////////////////   
+   
+   iodrp2_dq_1 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ1_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_1,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(1),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(1),
+         SDO        => open,
+         TOUT       => t_dq(1),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_8,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(1),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(1),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(1)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ2
+--////////////////////////////////////////////////   
+   
+   iodrp2_DQ_2 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ2_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_2,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(2),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(2),
+         SDO        => open,
+         TOUT       => t_dq(2),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_3,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(2),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(2),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(2)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ3
+--////////////////////////////////////////////////   
+   
+   iodrp2_dq_3 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ3_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_3,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(3),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(3),
+         SDO        => open,
+         TOUT       => t_dq(3),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_0,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(3),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(3),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(3)
+      );
+   
+--/////////
+--//DQSP
+--/////////
+   
+   iodrp2_DQSP_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSP_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsp,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqs,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_m,
+         SDO        => open,
+         TOUT       => t_dqs,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsn,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsp_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsp_tq
+      );
+   
+--/////////
+--//DQSN
+--/////////
+   
+   iodrp2_dqsn_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSN_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsn,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqsn,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_s,
+         SDO        => open,
+         TOUT       => t_dqsn,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_2,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsn_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsn_tq
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ6
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_6 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ6_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 3,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_6,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(6),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(6),
+         SDO        => open,
+         TOUT       => t_dq(6),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_7,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(6),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(6),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(6)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ7
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_7 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ7_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 3,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_7,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(7),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(7),
+         SDO        => open,
+         TOUT       => t_dq(7),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsp,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(7),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(7),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(7)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ4
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_4 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ4_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 2,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_4,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(4),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(4),
+         SDO        => open,
+         TOUT       => t_dq(4),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_5,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(4),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(4),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(4)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ5
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_5 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ5_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 2,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_5,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(5),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(5),
+         SDO        => open,
+         TOUT       => t_dq(5),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_6,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(5),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(5),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(5)
+      );
+   
+   
+  
+   
+--/////////////////////////////////////////////////
+--//UDM
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_udm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => ioi_drp_sdi,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_udm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_ldm,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udm_t
+      );
+
+--/////////////////////////////////////////////////
+--//LDM
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_ldm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_ldm,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_ldm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_ldm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_4,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => ldm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => ldm_t
+      );
+
+end generate;
+
+---#####################################--X8 MEMORY WIDTH-#############################################
+   
+   dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
+--/////////////////////////////////////////////////
+--//DQ0
+--////////////////////////////////////////////////
+   iodrp2_DQ_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ0_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_0,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(0),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(0),
+         SDO        => open,
+         TOUT       => t_dq(0),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_1,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(0),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(0),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(0)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ1
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_1 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ1_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_1,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(1),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(1),
+         SDO        => open,
+         TOUT       => t_dq(1),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => '0',
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(1),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(1),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(1)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ2
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_2 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ2_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_2,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(2),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(2),
+         SDO        => open,
+         TOUT       => t_dq(2),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_3,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(2),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(2),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(2)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ3
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_3 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ3_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_3,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(3),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(3),
+         SDO        => open,
+         TOUT       => t_dq(3),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_0,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(3),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(3),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(3)
+      );
+   
+--/////////
+--//DQSP
+--/////////
+   
+   iodrp2_DQSP_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSP_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsp,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqs,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_m,
+         SDO        => open,
+         TOUT       => t_dqs,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsn,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsp_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsp_tq
+      );
+   
+--/////////
+--//DQSN
+--/////////   
+   iodrp2_dqsn_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSN_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsn,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqsn,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_s,
+         SDO        => open,
+         TOUT       => t_dqsn,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_2,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsn_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsn_tq
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ6
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_6 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ6_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 3,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_6,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(6),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(6),
+         SDO        => open,
+         TOUT       => t_dq(6),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_7,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(6),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(6),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(6)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ7
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_7 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ7_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 3,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_7,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(7),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(7),
+         SDO        => open,
+         TOUT       => t_dq(7),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsp,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(7),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(7),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(7)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ4
+--////////////////////////////////////////////////
+   
+   iodrp2_DQ_4 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ4_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 2,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_4,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(4),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(4),
+         SDO        => open,
+         TOUT       => t_dq(4),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_5,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(4),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(4),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(4)
+      );
+--/////////////////////////////////////////////////
+--//DQ5
+--////////////////////////////////////////////////
+   
+   
+   iodrp2_dq_5 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ5_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 2,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_5,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(5),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(5),
+         SDO        => open,
+         TOUT       => t_dq(5),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_6,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(5),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(5),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(5)
+      );
+   
+   
+   
+--NEED TO GENERATE UDM so that user won't instantiate in this location
+   
+--/////////////////////////////////////////////////
+--//UDM
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_udm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => ioi_drp_sdi,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_udm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_ldm,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udm_t
+      );
+
+--/////////////////////////////////////////////////
+--//LDM
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_ldm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_ldm,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_ldm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_ldm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_4,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => ldm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => ldm_t
+      );
+
+end generate;
+
+---#####################################--X4 MEMORY WIDTH-#############################################
+   
+   dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
+--/////////////////////////////////////////////////
+--//DQ0
+--////////////////////////////////////////////////
+
+   iodrp2_DQ_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ0_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_0,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(0),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(0),
+         SDO        => open,
+         TOUT       => t_dq(0),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_1,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(0),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(0),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(0)
+      );
+   
+ --/////////////////////////////////////////////////
+--//DQ1
+--////////////////////////////////////////////////
+  
+   iodrp2_dq_1 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ1_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 0,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_1,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(1),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(1),
+         SDO        => open,
+         TOUT       => t_dq(1),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => '0',
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(1),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(1),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(1)
+      );
+   
+ --/////////////////////////////////////////////////
+--//DQ2
+--////////////////////////////////////////////////
+  
+   iodrp2_DQ_2 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ2_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_2,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(2),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(2),
+         SDO        => open,
+         TOUT       => t_dq(2),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_3,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(2),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(2),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(2)
+      );
+   
+--/////////////////////////////////////////////////
+--//DQ3
+--////////////////////////////////////////////////
+   
+   iodrp2_dq_3 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => DQ3_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 1,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_3,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dq(3),
+         DQSOUTN    => open,
+         DQSOUTP    => in_dq(3),
+         SDO        => open,
+         TOUT       => t_dq(3),
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_0,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dq(3),
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dq_oq(3),
+         SDI        => ioi_drp_sdo,
+         T          => dq_tq(3)
+      );
+   
+--///////////////////////////////////////////////
+--DQSP
+--///////////////////////////////////////////////
+   iodrp2_DQSP_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSP_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsp,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqs,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_m,
+         SDO        => open,
+         TOUT       => t_dqs,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_dqsn,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsp_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsp_tq
+      );
+   
+--///////////////////////////////////////////////
+--DQSN
+--///////////////////////////////////////////////
+   
+   iodrp2_dqsn_0 : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQS_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => LDQSN_TAP_DELAY_VAL,
+         MCB_ADDRESS         => 15,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQS_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_dqsn,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_dqsn,
+         DQSOUTN    => open,
+         DQSOUTP    => idelay_dqs_ioi_s,
+         SDO        => open,
+         TOUT       => t_dqsn,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_2,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => in_pre_dqsp,
+         IOCLK0     => ioclk0,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => dqsn_oq,
+         SDI        => ioi_drp_sdo,
+         T          => dqsn_tq
+      );
+--///////////////////////////////////////////////
+--UDM
+--//////////////////////////////////////////////  
+ --NEED TO GENERATE UDM so that user won't instantiate in this location
+  
+   
+   iodrp2_dq_udm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_MASTER,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => ioi_drp_sdi,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_udm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_udm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_ldm,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => udm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => udm_t
+      );
+
+--///////////////////////////////////////////////
+--LDM
+--//////////////////////////////////////////////  
+   
+   
+   iodrp2_dq_ldm : IODRP2_MCB
+      GENERIC MAP (
+         DATA_RATE           => C_DQ_IODRP2_DATA_RATE,
+         IDELAY_VALUE        => 0,
+         MCB_ADDRESS         => 8,
+         ODELAY_VALUE        => 0,
+         SERDES_MODE         => C_DQ_IODRP2_SERDES_MODE_SLAVE,
+         SIM_TAPDELAY_VALUE  => 10
+      )
+      PORT MAP (
+         AUXSDO     => aux_sdi_out_ldm,
+         DATAOUT    => open,
+         DATAOUT2   => open,
+         DOUT       => ioi_ldm,
+         DQSOUTN    => open,
+         DQSOUTP    => open,
+         SDO        => open,
+         TOUT       => t_ldm,
+         ADD        => ioi_drp_add,
+         AUXADDR    => ioi_drp_addr,
+         AUXSDOIN   => aux_sdi_out_4,
+         BKST       => ioi_drp_broadcast,
+         CLK        => ioi_drp_clk,
+         CS         => ioi_drp_cs,
+         IDATAIN    => '0',
+         IOCLK0     => ioclk90,
+         IOCLK1     => '0',
+         MEMUPDATE  => ioi_drp_update,
+         ODATAIN    => ldm_oq,
+         SDI        => ioi_drp_sdo,
+         T          => ldm_t
+      );
+
+end generate;
+
+------------------------------------------------
+--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
+------------------------------------------------   
+
+ -------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ --IOBs instantiations
+ -- this part need more inputs from design team 
+ -- for now just use as listed in fpga.v
+ -----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+-- DRAM Address
+   gen_addr_obuft : FOR addr_i IN 0 TO  C_MEM_ADDR_WIDTH - 1 GENERATE
+      iob_addr_inst : OBUFT
+         PORT MAP (
+            I  => ioi_addr(addr_i),
+            T  => t_addr(addr_i),
+            O  => mcbx_dram_addr(addr_i)
+         );
+   END GENERATE;
+   
+   gen_ba_obuft : FOR ba_i IN 0 TO  C_MEM_BANKADDR_WIDTH - 1 GENERATE
+      iob_ba_inst : OBUFT
+         PORT MAP (
+            I  => ioi_ba(ba_i),
+            T  => t_ba(ba_i),
+            O  => mcbx_dram_ba(ba_i)
+         );
+   END GENERATE;
+   
+-- DRAM control
+--RAS   
+   iob_ras : OBUFT
+      PORT MAP (
+         O  => mcbx_dram_ras_n,
+         I  => ioi_ras,
+         T  => t_ras
+      );
+   
+--CAS      
+   iob_cas : OBUFT
+      PORT MAP (
+         O  => mcbx_dram_cas_n,
+         I  => ioi_cas,
+         T  => t_cas
+      );
+   
+--WE      
+   iob_we : OBUFT
+      PORT MAP (
+         O  => mcbx_dram_we_n,
+         I  => ioi_we,
+         T  => t_we
+      );
+   
+--CKE   
+   iob_cke : OBUFT
+      PORT MAP (
+         O  => mcbx_dram_cke,
+         I  => ioi_cke,
+         T  => t_cke
+      );
+
+--DDR3 RST
+   gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
+      iob_rst : OBUFT
+         PORT MAP (
+            O  => mcbx_dram_ddr3_rst,
+            I  => ioi_rst,
+            T  => t_rst
+         );
+   END GENERATE;
+
+--ODT
+   gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF"))) 
+   OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
+      iob_odt : OBUFT
+         PORT MAP (
+            O  => mcbx_dram_odt,
+            I  => ioi_odt,
+            t  => t_odt
+         );
+   END GENERATE;
+   
+--MEMORY CLOCK   
+   iob_clk : OBUFTDS
+      PORT MAP (
+         I  => ioi_ck,
+         T  => t_ck,
+         O  => mcbx_dram_clk,
+         OB => mcbx_dram_clk_n
+      );
+   
+--DQ
+   gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
+      gen_iob_dq_inst : IOBUF
+         PORT MAP (
+            IO  => mcbx_dram_dq(dq_i),
+            I   => ioi_dq(dq_i),
+            T   => t_dq(dq_i),
+            O   => in_pre_dq(dq_i)
+         );
+   END GENERATE;
+   
+-- x4 and x8
+--DQS
+gen_dqs_iobuf :   if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
+      iob_dqs : IOBUF
+      PORT MAP (
+         IO  => mcbx_dram_dqs,
+         I   => ioi_dqs,
+         T   => t_dqs,
+         O   => in_pre_dqsp
+      );
+end generate;   
+
+--DQSP/DQSN
+gen_dqs_iobufds :   if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
+   iob_dqs : IOBUFDS
+      PORT MAP (
+         IO   => mcbx_dram_dqs,
+         IOB  => mcbx_dram_dqs_n,
+         I    => ioi_dqs,
+         T    => t_dqs,
+         O    => in_pre_dqsp
+      );
+end generate;   
+
+-- x16
+--UDQS   
+gen_udqs_iobuf :   if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
+      iob_udqs : IOBUF
+      PORT MAP (
+         IO  => mcbx_dram_udqs,
+         I   => ioi_udqs,
+         T   => t_udqs,
+         O   => in_pre_udqsp
+      );
+end generate;   
+
+----UDQSP/UDQSN
+gen_udqs_iobufds :   if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
+   iob_udqs : IOBUFDS
+      PORT MAP (
+         IO   => mcbx_dram_udqs,
+         IOB  => mcbx_dram_udqs_n,
+         I    => ioi_udqs,
+         T    => t_udqs,
+         O    => in_pre_udqsp
+      );
+end generate;   
+   
+-- DQS PULLDWON
+gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate 
+dqs_pulldown : PULLDOWN  port map (O => mcbx_dram_dqs);
+end generate;
+
+gen_dqs_pullupdn_ds :   if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
+dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
+dqs_n_pullup : PULLUP port map  (O  =>  mcbx_dram_dqs_n);   
+end generate;
+
+-- DQSN PULLUP
+gen_udqs_pullupdn :   if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and 
+(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
+udqs_pulldown : PULLDOWN  port map (O => mcbx_dram_udqs);
+end generate;
+
+gen_udqs_pullupdn_ds :   if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and 
+                                                          (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
+udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
+udqs_n_pullup : PULLUP port map  (O  =>  mcbx_dram_udqs_n);   
+end generate;
+
+--UDM   
+gen_udm : if(C_NUM_DQ_PINS = 16) generate   
+   iob_udm : OBUFT
+      PORT MAP (
+         I  => ioi_udm,
+         T  => t_udm,
+         O  => mcbx_dram_udm
+      );
+end generate;   
+--LDM   
+   iob_ldm : OBUFT
+      PORT MAP (
+         I  => ioi_ldm,
+         T  => t_ldm,
+         O  => mcbx_dram_ldm
+      );
+   
+selfrefresh_mode <= selfrefresh_mode_sig;
+
+ end aarch;    
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration.vhd
new file mode 100755
index 0000000..0e68a29
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration.vhd
@@ -0,0 +1,1774 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_soft_calibration.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:26 $
+-- \   \  /  \    Date Created: Mon Feb 9 2009
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR
+--Purpose:  Xilinx reference design for MCB Soft
+--           Calibration
+--Reference:
+--
+--  Revision:      Date:  Comment
+--       1.0:  2/06/09:   Initial version for MIG wrapper.
+--       1.1:  2/09/09:   moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working 
+--                          correctly)
+--       1.2:  2/12/09:   Many other changes.
+--       1.3:  2/26/09:   Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
+--                          STATE
+--       1.4:  3/02/09:   Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
+--       1.5:  3/16/09:   Added pll_lock port, and using it to gate reset.  Changing RST (except input port) to RST_reg and gating it with pll_lock.
+--       1.6:  6/05/09:   Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
+--       1.7:  6/24/09:   Gave RZQ and ZIO each their own unique ADD and SDI nets
+--       2.6:  12/15/09:  Changed STATE from 7-bit to 6-bit.  Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to 
+--                          RST_DELAY. 
+--                        Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
+--                          16 clocks.  Added PNSKEW option.
+--       2.7:  12/23/09:  Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
+--       2.8:  01/14/10:  Added functionality to allow for SUSPEND.  Changed MCB_SYSRST port from wire to reg.
+--       2.9:  02/01/10:  More changes to SUSPEND and Reset logic to handle SUSPEND properly.  Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced 
+--                          with 8bit TARGET_DQS_DELAY which
+--                        will track most recnet Max_Value.  Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
+--                          Changed DQS_COUNT* to DQS_DELAY*.
+--                        Changed MCB_SYSRST port back to wire (from reg).
+--       3.0:  02/10/10:  Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
+--       3.1:  02/23/10:  Registered the DONE_SOFTANDHARD_CAL for timing.
+--       3.2:  02/28/10:  Corrected the   WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
+--       3.3:  03/02/10:  Changed PNSKEW to default on (1'b1)
+--       3.4:  03/04/10:  Recoded the RST_Reg logic.
+--       3.5:  03/05/10:  Changed Result register to be 16-bits.  Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
+--       3.6   03/10/10:  Improvements to Reset logic.  
+--       3.7:  04/26/10:  Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
+--       3.8:  05/05/10:  Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
+--       3.9:  05/24/10:  Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
+--       3.10  10/22/10:  Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic.		
+--       3.11  2/14/11:   Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity.
+--       4.1   03/08/12:  Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that
+--                        MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. 
+--       4.2   05/10/12:  All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT
+--                        are set to 8 for LPDDR,DDR and DDR2 interface .
+--                        Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing
+--                        Premable detection until the second deassertion of MCB_SYSRST. 
+                        
+
+-- End Revision
+--**********************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+entity mcb_soft_calibration is
+   generic (
+      C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
+      SKIP_IN_TERM_CAL      : integer := 0;                 -- provides option to skip the input termination calibration
+      SKIP_DYNAMIC_CAL      : integer := 0;                 -- provides option to skip the dynamic delay calibration
+      SKIP_DYN_IN_TERM      : integer := 1;                 -- provides option to skip the input termination calibration
+      C_MC_CALIBRATION_MODE : string  := "CALIBRATION";     -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
+                                                            -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY 
+                                                            -- (Quarter, etc)
+      C_SIMULATION          : string  := "FALSE";           -- Tells us whether the design is being simulated or implemented
+      C_MEM_TYPE            : string  := "DDR"                                                             
+
+      
+   );
+   port (
+      UI_CLK                : in std_logic;         -- main clock input for logic and IODRP CLK pins.  At top level, this should also connect to IODRP2_MCB 
+                                                    --  CLK pins
+      RST                   : in std_logic;         -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
+      DONE_SOFTANDHARD_CAL  : out std_logic;        -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB 
+                                                    --  hard calib complete)
+      PLL_LOCK              : in std_logic;         -- Lock signal from PLL
+      SELFREFRESH_REQ       : in std_logic;
+      SELFREFRESH_MCB_MODE  : in std_logic;
+      SELFREFRESH_MCB_REQ   : out std_logic;
+      SELFREFRESH_MODE      : out std_logic;
+      IODRP_ADD             : out std_logic;        -- IODRP ADD port 
+      IODRP_SDI             : out std_logic;        -- IODRP SDI port
+      RZQ_IN                : in std_logic;         -- RZQ pin from board - expected to have a 2*R resistor to ground
+      RZQ_IODRP_SDO         : in std_logic;         -- RZQ IODRP's SDO port
+      RZQ_IODRP_CS          : out std_logic := '0'; -- RZQ IODRP's CS port
+      ZIO_IN                : in std_logic;         -- Z-stated IO pin - garanteed not to be driven externally
+      ZIO_IODRP_SDO         : in std_logic;         -- ZIO IODRP's SDO port
+      ZIO_IODRP_CS          : out std_logic := '0'; -- ZIO IODRP's CS port
+      MCB_UIADD             : out std_logic;        -- to MCB's UIADD port
+      MCB_UISDI             : out std_logic;        -- to MCB's UISDI port
+      MCB_UOSDO             : in std_logic;         -- from MCB's UOSDO port (User output SDO)
+      MCB_UODONECAL         : in std_logic;         -- indicates when MCB hard calibration process is complete
+      MCB_UOREFRSHFLAG      : in std_logic;         -- high during refresh cycle and time when MCB is innactive
+      MCB_UICS              : out std_logic;        -- to MCB's UICS port (User Input CS)
+      MCB_UIDRPUPDATE       : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used 
+                                                    --  during IODRP2_MCB writes).  Currently just trasnparent
+      MCB_UIBROADCAST       : out std_logic;        -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
+      MCB_UIADDR            : out std_logic_vector(4 downto 0) := "00000";  -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
+      MCB_UICMDEN           : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
+      MCB_UIDONECAL         : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
+      MCB_UIDQLOWERDEC      : out std_logic ;
+      MCB_UIDQLOWERINC      : out std_logic ;
+      MCB_UIDQUPPERDEC      : out std_logic ;
+      MCB_UIDQUPPERINC      : out std_logic ;
+      MCB_UILDQSDEC         : out std_logic := '0';
+      MCB_UILDQSINC         : out std_logic := '0';
+      MCB_UIREAD            : out std_logic;        -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in 
+                                                    --  regular IODRP2).  IODRPCTRLR_R_WB becomes don't-care.
+      MCB_UIUDQSDEC         : out std_logic := '0';
+      MCB_UIUDQSINC         : out std_logic := '0';
+      MCB_RECAL             : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
+      MCB_UICMD             : out std_logic;
+      MCB_UICMDIN           : out std_logic;
+      MCB_UIDQCOUNT         : out std_logic_vector(3 downto 0);
+      MCB_UODATA            : in std_logic_vector(7 downto 0);
+      MCB_UODATAVALID       : in std_logic;
+      MCB_UOCMDREADY        : in std_logic;
+      MCB_UO_CAL_START      : in std_logic;
+      MCB_SYSRST            : out std_logic;        -- drives the MCB's SYSRST pin - the main reset for MCB
+      Max_Value             : out std_logic_vector(7 downto 0);
+      CKE_Train             : out std_logic
+   );
+end entity mcb_soft_calibration;
+
+architecture trans of mcb_soft_calibration is
+
+   constant IOI_DQ0                   : std_logic_vector(4 downto 0) := ("0000" & '1');
+   constant IOI_DQ1                   : std_logic_vector(4 downto 0) := ("0000" & '0');
+   constant IOI_DQ2                   : std_logic_vector(4 downto 0) := ("0001" & '1');
+   constant IOI_DQ3                   : std_logic_vector(4 downto 0) := ("0001" & '0');
+   constant IOI_DQ4                   : std_logic_vector(4 downto 0) := ("0010" & '1');
+   constant IOI_DQ5                   : std_logic_vector(4 downto 0) := ("0010" & '0');
+   constant IOI_DQ6                   : std_logic_vector(4 downto 0) := ("0011" & '1');
+   constant IOI_DQ7                   : std_logic_vector(4 downto 0) := ("0011" & '0');
+   constant IOI_DQ8                   : std_logic_vector(4 downto 0) := ("0100" & '1');
+   constant IOI_DQ9                   : std_logic_vector(4 downto 0) := ("0100" & '0');
+   constant IOI_DQ10                  : std_logic_vector(4 downto 0) := ("0101" & '1');
+   constant IOI_DQ11                  : std_logic_vector(4 downto 0) := ("0101" & '0');
+   constant IOI_DQ12                  : std_logic_vector(4 downto 0) := ("0110" & '1');
+   constant IOI_DQ13                  : std_logic_vector(4 downto 0) := ("0110" & '0');
+   constant IOI_DQ14                  : std_logic_vector(4 downto 0) := ("0111" & '1');
+   constant IOI_DQ15                  : std_logic_vector(4 downto 0) := ("0111" & '0');
+   constant IOI_UDM                   : std_logic_vector(4 downto 0) := ("1000" & '1');
+   constant IOI_LDM                   : std_logic_vector(4 downto 0) := ("1000" & '0');
+   constant IOI_CK_P                  : std_logic_vector(4 downto 0) := ("1001" & '1');
+   constant IOI_CK_N                  : std_logic_vector(4 downto 0) := ("1001" & '0');
+   constant IOI_RESET                 : std_logic_vector(4 downto 0) := ("1010" & '1');
+   constant IOI_A11                   : std_logic_vector(4 downto 0) := ("1010" & '0');
+   constant IOI_WE                    : std_logic_vector(4 downto 0) := ("1011" & '1');
+   constant IOI_BA2                   : std_logic_vector(4 downto 0) := ("1011" & '0');
+   constant IOI_BA0                   : std_logic_vector(4 downto 0) := ("1100" & '1');
+   constant IOI_BA1                   : std_logic_vector(4 downto 0) := ("1100" & '0');
+   constant IOI_RASN                  : std_logic_vector(4 downto 0) := ("1101" & '1');
+   constant IOI_CASN                  : std_logic_vector(4 downto 0) := ("1101" & '0');
+   constant IOI_UDQS_CLK              : std_logic_vector(4 downto 0) := ("1110" & '1');
+   constant IOI_UDQS_PIN              : std_logic_vector(4 downto 0) := ("1110" & '0');
+   constant IOI_LDQS_CLK              : std_logic_vector(4 downto 0) := ("1111" & '1');
+   constant IOI_LDQS_PIN              : std_logic_vector(4 downto 0) := ("1111" & '0');
+
+   constant START                     : std_logic_vector(5 downto 0) := "000000";
+   constant LOAD_RZQ_NTERM            : std_logic_vector(5 downto 0) := "000001";
+   constant WAIT1                     : std_logic_vector(5 downto 0) := "000010";
+   constant LOAD_RZQ_PTERM            : std_logic_vector(5 downto 0) := "000011";
+   constant WAIT2                     : std_logic_vector(5 downto 0) := "000100";
+   constant INC_PTERM                 : std_logic_vector(5 downto 0) := "000101";
+   constant MULTIPLY_DIVIDE           : std_logic_vector(5 downto 0) := "000110";
+   constant LOAD_ZIO_PTERM            : std_logic_vector(5 downto 0) := "000111";
+   constant WAIT3                     : std_logic_vector(5 downto 0) := "001000";
+   constant LOAD_ZIO_NTERM            : std_logic_vector(5 downto 0) := "001001";
+   constant WAIT4                     : std_logic_vector(5 downto 0) := "001010";
+   constant INC_NTERM                 : std_logic_vector(5 downto 0) := "001011";
+   constant SKEW                      : std_logic_vector(5 downto 0) := "001100";
+   constant WAIT_FOR_START_BROADCAST  : std_logic_vector(5 downto 0) := "001101";
+   constant BROADCAST_PTERM           : std_logic_vector(5 downto 0) := "001110";
+   constant WAIT5                     : std_logic_vector(5 downto 0) := "001111";
+   constant BROADCAST_NTERM           : std_logic_vector(5 downto 0) := "010000";
+   constant WAIT6                     : std_logic_vector(5 downto 0) := "010001";
+
+   constant LDQS_CLK_WRITE_P_TERM     : std_logic_vector(5 downto 0) := "010010";
+   constant LDQS_CLK_P_TERM_WAIT      : std_logic_vector(5 downto 0) := "010011";
+   constant LDQS_CLK_WRITE_N_TERM     : std_logic_vector(5 downto 0) := "010100";
+   constant LDQS_CLK_N_TERM_WAIT      : std_logic_vector(5 downto 0) := "010101";
+   constant LDQS_PIN_WRITE_P_TERM     : std_logic_vector(5 downto 0) := "010110";
+   constant LDQS_PIN_P_TERM_WAIT      : std_logic_vector(5 downto 0) := "010111";
+   constant LDQS_PIN_WRITE_N_TERM     : std_logic_vector(5 downto 0) := "011000";
+   constant LDQS_PIN_N_TERM_WAIT      : std_logic_vector(5 downto 0) := "011001";
+   constant UDQS_CLK_WRITE_P_TERM     : std_logic_vector(5 downto 0) := "011010";
+   constant UDQS_CLK_P_TERM_WAIT      : std_logic_vector(5 downto 0) := "011011";
+   constant UDQS_CLK_WRITE_N_TERM     : std_logic_vector(5 downto 0) := "011100";
+   constant UDQS_CLK_N_TERM_WAIT      : std_logic_vector(5 downto 0) := "011101";
+   constant UDQS_PIN_WRITE_P_TERM     : std_logic_vector(5 downto 0) := "011110";
+   constant UDQS_PIN_P_TERM_WAIT      : std_logic_vector(5 downto 0) := "011111";
+   constant UDQS_PIN_WRITE_N_TERM     : std_logic_vector(5 downto 0) := "100000";
+   constant UDQS_PIN_N_TERM_WAIT      : std_logic_vector(5 downto 0) := "100001"; 
+   
+   constant OFF_RZQ_PTERM             : std_logic_vector(5 downto 0) := "100010";
+   constant WAIT7                     : std_logic_vector(5 downto 0) := "100011";
+   constant OFF_ZIO_NTERM             : std_logic_vector(5 downto 0) := "100100";
+   constant WAIT8                     : std_logic_vector(5 downto 0) := "100101";
+   constant RST_DELAY                 : std_logic_vector(5 downto 0) := "100110";
+   constant START_DYN_CAL_PRE         : std_logic_vector(5 downto 0) := "100111";
+   constant WAIT_FOR_UODONE           : std_logic_vector(5 downto 0) := "101000";
+   constant LDQS_WRITE_POS_INDELAY    : std_logic_vector(5 downto 0) := "101001";
+   constant LDQS_WAIT1                : std_logic_vector(5 downto 0) := "101010";
+   constant LDQS_WRITE_NEG_INDELAY    : std_logic_vector(5 downto 0) := "101011";
+   constant LDQS_WAIT2                : std_logic_vector(5 downto 0) := "101100";
+   constant UDQS_WRITE_POS_INDELAY    : std_logic_vector(5 downto 0) := "101101";
+   constant UDQS_WAIT1                : std_logic_vector(5 downto 0) := "101110";
+   constant UDQS_WRITE_NEG_INDELAY    : std_logic_vector(5 downto 0) := "101111";
+   constant UDQS_WAIT2                : std_logic_vector(5 downto 0) := "110000";
+   constant START_DYN_CAL             : std_logic_vector(5 downto 0) := "110001";
+   constant WRITE_CALIBRATE           : std_logic_vector(5 downto 0) := "110010";
+   constant WAIT9                     : std_logic_vector(5 downto 0) := "110011";
+   constant READ_MAX_VALUE            : std_logic_vector(5 downto 0) := "110100";
+   constant WAIT10                    : std_logic_vector(5 downto 0) := "110101";
+   constant ANALYZE_MAX_VALUE         : std_logic_vector(5 downto 0) := "110110";
+   constant FIRST_DYN_CAL             : std_logic_vector(5 downto 0) := "110111";
+   constant INCREMENT                 : std_logic_vector(5 downto 0) := "111000";
+   constant DECREMENT                 : std_logic_vector(5 downto 0) := "111001"; 
+   constant DONE                      : std_logic_vector(5 downto 0) := "111010";
+   --constant INCREMENT_TA             : std_logic_vector(5 downto 0) := "111011";
+
+   constant RZQ                       : std_logic_vector(1 downto 0) := "00";
+   constant ZIO                       : std_logic_vector(1 downto 0) := "01";
+   constant MCB_PORT                  : std_logic_vector(1 downto 0) := "11";
+   constant WRITE_MODE                : std_logic := '0';
+   constant READ_MODE                 : std_logic := '1';
+    
+    -- IOI Registers
+   constant NoOp                      : std_logic_vector(7 downto 0) := "00000000";
+   constant DelayControl              : std_logic_vector(7 downto 0) := "00000001";
+   constant PosEdgeInDly              : std_logic_vector(7 downto 0) := "00000010";
+   constant NegEdgeInDly              : std_logic_vector(7 downto 0) := "00000011";
+   constant PosEdgeOutDly             : std_logic_vector(7 downto 0) := "00000100";
+   constant NegEdgeOutDly             : std_logic_vector(7 downto 0) := "00000101";
+   constant MiscCtl1                  : std_logic_vector(7 downto 0) := "00000110";
+   constant MiscCtl2                  : std_logic_vector(7 downto 0) := "00000111";
+   constant MaxValue                  : std_logic_vector(7 downto 0) := "00001000";
+    
+    -- IOB Registers
+   constant PDrive                    : std_logic_vector(7 downto 0) := "10000000";
+   constant PTerm                     : std_logic_vector(7 downto 0) := "10000001";
+   constant NDrive                    : std_logic_vector(7 downto 0) := "10000010";
+   constant NTerm                     : std_logic_vector(7 downto 0) := "10000011";
+   constant SlewRateCtl               : std_logic_vector(7 downto 0) := "10000100";
+   constant LVDSControl               : std_logic_vector(7 downto 0) := "10000101";
+   constant MiscControl               : std_logic_vector(7 downto 0) := "10000110";
+   constant InputControl              : std_logic_vector(7 downto 0) := "10000111";
+   constant TestReadback              : std_logic_vector(7 downto 0) := "10001000";
+
+-- No multi/divide is required when a 55 ohm resister is used on RZQ
+-- localparam          MULT          = 1;
+-- localparam          DIV           = 1;
+-- use 7/4 scaling factor when the 100 ohm RZQ is used
+   constant MULT                      : integer := 7;
+   constant DIV                       : integer := 4;
+
+   constant PNSKEW                    : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
+   constant PNSKEWDQS                 : std_logic := '1';
+   
+   constant MULT_S                    : integer  := 9;
+   constant DIV_S                     : integer  := 8;
+   constant MULT_W                    : integer  := 7;
+   constant DIV_W                     : integer  := 8;
+
+   constant DQS_NUMERATOR             : integer  := 3;
+   constant DQS_DENOMINATOR           : integer  := 8;
+   constant INCDEC_THRESHOLD          : std_logic_vector(7 downto 0) := X"03"; 
+                                                          -- parameter for the threshold which triggers an inc/dec to occur.  2 for half, 4 for quarter, 
+                                                          -- 3 for three eighths
+
+   constant RST_CNT                   : std_logic_vector(9 downto 0) := "0000010000";
+ 
+   constant IN_TERM_PASS             : std_logic := '0';
+   constant DYN_CAL_PASS             : std_logic := '1';
+
+   function TZQINIT_MAXCNT_W return std_logic_vector is
+     variable temp : std_logic_vector(9 downto 0) := (others=>'0');
+   begin
+      if (C_MEM_TYPE = "DDR3") then
+         temp := C_MEM_TZQINIT_MAXCNT + RST_CNT;
+      else
+         temp := 8 + RST_CNT;
+      end if;
+         return temp(9 downto 0);
+   end function;
+
+   constant TZQINIT_MAXCNT            : std_logic_vector(9 downto 0) := TZQINIT_MAXCNT_W;
+
+   component iodrp_mcb_controller is
+      port (
+         memcell_address           : in std_logic_vector(7 downto 0);
+         write_data                : in std_logic_vector(7 downto 0);
+         read_data                 : out std_logic_vector(7 downto 0);
+         rd_not_write              : in std_logic;
+         cmd_valid                 : in std_logic;
+         rdy_busy_n                : out std_logic;
+         use_broadcast             : in std_logic;
+         drp_ioi_addr              : in std_logic_vector(4 downto 0);
+         sync_rst                  : in std_logic;
+         DRP_CLK                   : in std_logic;
+         DRP_CS                    : out std_logic;
+         DRP_SDI                   : out std_logic;
+         DRP_ADD                   : out std_logic;
+         DRP_BKST                  : out std_logic;
+         DRP_SDO                   : in std_logic;
+         MCB_UIREAD                : out std_logic
+      );
+   end component;
+   
+   component iodrp_controller is
+      port (
+         memcell_address           : in std_logic_vector(7 downto 0);
+         write_data                : in std_logic_vector(7 downto 0);
+         read_data                 : out std_logic_vector(7 downto 0);
+         rd_not_write              : in std_logic;
+         cmd_valid                 : in std_logic;
+         rdy_busy_n                : out std_logic;
+         use_broadcast             : in std_logic;
+         sync_rst                  : in std_logic;
+         DRP_CLK                   : in std_logic;
+         DRP_CS                    : out std_logic;
+         DRP_SDI                   : out std_logic;
+         DRP_ADD                   : out std_logic;
+         DRP_BKST                  : out std_logic;
+         DRP_SDO                   : in std_logic
+      );
+   end component;
+   
+   signal P_Term                       : std_logic_vector(5 downto 0) := "000000";  
+   signal N_Term                       : std_logic_vector(6 downto 0) := "0000000";   
+   signal P_Term_s                       : std_logic_vector(5 downto 0) := "000000";  
+   signal N_Term_s                       : std_logic_vector(6 downto 0) := "0000000"; 
+   signal P_Term_w                       : std_logic_vector(5 downto 0) := "000000";  
+   signal N_Term_w                       : std_logic_vector(6 downto 0) := "0000000"; 
+   signal P_Term_Prev                  : std_logic_vector(5 downto 0) := "000000";  
+   signal N_Term_Prev                  : std_logic_vector(6 downto 0) := "0000000"; 
+
+   signal STATE                        : std_logic_vector(5 downto 0);
+   signal IODRPCTRLR_MEMCELL_ADDR      : std_logic_vector(7 downto 0);              
+   signal IODRPCTRLR_WRITE_DATA        : std_logic_vector(7 downto 0);              
+   signal Active_IODRP                 : std_logic_vector(1 downto 0);
+   signal IODRPCTRLR_R_WB              : std_logic := '0';
+   signal IODRPCTRLR_CMD_VALID         : std_logic := '0';
+   signal IODRPCTRLR_USE_BKST          : std_logic := '0';
+   signal MCB_CMD_VALID                : std_logic := '0';
+   signal MCB_USE_BKST                 : std_logic := '0';
+   signal Pre_SYSRST                   : std_logic := '1';                          -- internally generated reset which will OR with RST input to drive MCB's
+                                                                                    -- SYSRST pin (MCB_SYSRST)
+   signal IODRP_SDO                    : std_logic;
+   signal Max_Value_Previous           : std_logic_vector(7 downto 0) := "00000000";
+   signal count                        : std_logic_vector(5 downto 0) := "000000";  -- counter for adding 18 extra clock cycles after setting Calibrate bit
+   signal counter_en                   : std_logic := '0';                          -- counter enable for "count"
+   signal First_Dyn_Cal_Done           : std_logic := '0';                          -- flag - high after the very first dynamic calibration is done
+   signal START_BROADCAST              : std_logic ;                          -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - 
+                                                                                    --  state machine will wait for this to be high
+   signal DQS_DELAY_INITIAL            : std_logic_vector(7 downto 0) := "00000000";
+   signal DQS_DELAY                    : std_logic_vector(7 downto 0);              -- contains the latest values written to LDQS and UDQS Input Delays
+   signal TARGET_DQS_DELAY             : std_logic_vector(7 downto 0);              -- used to track the target for DQS input delays - only gets updated if 
+                                                                                    --  the Max Value changes by more than the threshold
+   signal counter_inc                  : std_logic_vector(7 downto 0);              -- used to delay Inc signal by several ui_clk cycles (to deal with 
+                                                                                    --  latency on UOREFRSHFLAG)
+   signal counter_dec                  : std_logic_vector(7 downto 0);              -- used to delay Dec signal by several ui_clk cycles (to deal with 
+                                                                                    --  latency on UOREFRSHFLAG)
+   signal IODRPCTRLR_READ_DATA         : std_logic_vector(7 downto 0);
+   signal IODRPCTRLR_RDY_BUSY_N        : std_logic;
+   signal IODRP_CS                     : std_logic;
+   signal MCB_READ_DATA                : std_logic_vector(7 downto 0);
+   signal RST_reg                      : std_logic;
+   signal Block_Reset                  : std_logic;
+   signal MCB_UODATAVALID_U            : std_logic;
+
+   signal Inc_Dec_REFRSH_Flag          : std_logic_vector(2 downto 0);          -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
+   signal Max_Value_Delta_Up           : std_logic_vector(7 downto 0);          -- tracks amount latest Max Value has gone up from previous Max Value read
+   signal Half_MV_DU                   : std_logic_vector(7 downto 0);          -- half of Max_Value_Delta_Up
+   signal Max_Value_Delta_Dn           : std_logic_vector(7 downto 0);          -- tracks amount latest Max Value has gone down from previous Max Value read
+   signal Half_MV_DD                   : std_logic_vector(7 downto 0);          -- half of Max_Value_Delta_Dn
+
+   signal RstCounter                   : std_logic_vector(9 downto 0) := (others => '0');
+   signal rst_tmp                      : std_logic;
+   signal LastPass_DynCal              : std_logic;
+   signal First_In_Term_Done           : std_logic;
+   signal Inc_Flag                     : std_logic;                                 -- flag to increment Dynamic Delay
+   signal Dec_Flag                     : std_logic;                                 -- flag to decrement Dynamic Delay
+
+   signal CALMODE_EQ_CALIBRATION       : std_logic;                                 -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE 
+                                                                                    --  parameter = "CALIBRATION"
+   signal DQS_DELAY_LOWER_LIMIT        : std_logic_vector(7 downto 0);              -- Lower limit for DQS input delays 
+   signal DQS_DELAY_UPPER_LIMIT        : std_logic_vector(7 downto 0);              -- Upper limit for DQS input delays
+   signal SKIP_DYN_IN_TERMINATION      : std_logic;                                 -- wire to allow skipping dynamic input termination if either the 
+                                                                                    --  one-time or dynamic parameters are 1
+   signal SKIP_DYNAMIC_DQS_CAL         : std_logic;                                 -- wire allowing skipping dynamic DQS delay calibration if either 
+                                                                                    --  SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
+   signal Quarter_Max_Value            : std_logic_vector(7 downto 0);
+   signal Half_Max_Value               : std_logic_vector(7 downto 0);
+   signal PLL_LOCK_R1                  : std_logic;
+   signal PLL_LOCK_R2                  : std_logic;
+   signal MCB_RDY_BUSY_N               : std_logic;
+   
+   signal SELFREFRESH_REQ_R1                         : std_logic;
+   signal SELFREFRESH_REQ_R2                         : std_logic;
+   signal SELFREFRESH_REQ_R3                         : std_logic;
+   signal SELFREFRESH_MCB_MODE_R1                    : std_logic;
+   signal SELFREFRESH_MCB_MODE_R2                    : std_logic;
+   signal SELFREFRESH_MCB_MODE_R3                    : std_logic;
+   signal WAIT_SELFREFRESH_EXIT_DQS_CAL              : std_logic;
+   signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH    : std_logic;
+   signal START_DYN_CAL_STATE_R1                     : std_logic;
+   signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
+
+   -- Declare intermediate signals for referenced outputs
+   signal IODRP_ADD_xilinx0            : std_logic;
+   signal IODRP_SDI_xilinx1            : std_logic;
+   signal MCB_UIADD_xilinx2            : std_logic;
+   signal MCB_UISDI_xilinx11           : std_logic;
+   signal MCB_UICS_xilinx6             : std_logic;
+   signal MCB_UIBROADCAST_xilinx4      : std_logic;
+   signal MCB_UIADDR_int           : std_logic_vector(4 downto 0);
+   signal MCB_UIDONECAL_xilinx7        : std_logic;
+   signal MCB_UIREAD_xilinx10          : std_logic;
+   signal SELFREFRESH_MODE_xilinx11    : std_logic;
+   signal Max_Value_int                : std_logic_vector(7 downto 0);
+   signal Rst_condition1               : std_logic;
+   --signal Rst_condition2               : std_logic;
+   signal non_violating_rst            : std_logic;
+   signal WAIT_200us_COUNTER           : std_logic_vector(15 downto 0);
+   signal WaitTimer                    : std_logic_vector(7 downto 0);
+   signal WarmEnough                   : std_logic;
+   signal WaitCountEnable : std_logic;
+   signal State_Start_DynCal_R1 : std_logic;
+   signal State_Start_DynCal : std_logic;
+   
+   signal pre_sysrst_minpulse_width_ok : std_logic;
+   signal pre_sysrst_cnt : std_logic_vector(3 downto 0);
+
+   -- This function multiplies by a constant MULT and then divides by the DIV constant
+   function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
+     variable Result : integer := 0;
+     variable temp   : std_logic_vector(14 downto 0) := "000000000000000"; 
+   begin
+     for count in 0 to (MULT-1) loop
+       temp := temp + ("0000000" & Input);
+     end loop;
+     Result := (to_integer(unsigned(temp))) / (DIV);
+     temp   := std_logic_vector(to_unsigned(Result,15));
+     return temp(7 downto 0);
+   end function Mult_Divide;
+
+
+
+   attribute syn_preserve : boolean;
+   attribute syn_preserve of P_Term                  : signal is TRUE;
+   attribute syn_preserve of N_Term                  : signal is TRUE;
+   attribute syn_preserve of P_Term_s                  : signal is TRUE;
+   attribute syn_preserve of N_Term_s                  : signal is TRUE;
+   attribute syn_preserve of P_Term_w                  : signal is TRUE;
+   attribute syn_preserve of N_Term_w                  : signal is TRUE;
+   
+   
+   
+   
+   attribute syn_preserve of P_Term_Prev             : signal is TRUE;
+   attribute syn_preserve of N_Term_Prev             : signal is TRUE;
+   attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
+   attribute syn_preserve of IODRPCTRLR_WRITE_DATA   : signal is TRUE;
+   attribute syn_preserve of Max_Value_Previous      : signal is TRUE;
+   attribute syn_preserve of DQS_DELAY_INITIAL       : signal is TRUE;
+
+   attribute iob          : string;
+   attribute iob of DONE_SOFTANDHARD_CAL             : signal is "FALSE";
+
+begin
+
+
+-- move the default assignment here to make FORMALITY happy.
+
+   START_BROADCAST  <= '1';
+   MCB_RECAL        <= '0';
+   MCB_UIDQLOWERDEC <= '0';
+   MCB_UIADDR       <= MCB_UIADDR_int;
+   MCB_UIDQLOWERINC <= '0';
+   MCB_UIDQUPPERDEC <= '0';
+   MCB_UIDQUPPERINC <= '0';
+  
+  
+   Max_Value        <= Max_Value_int;
+   -- Drive referenced outputs
+   IODRP_ADD        <= IODRP_ADD_xilinx0;
+   IODRP_SDI        <= IODRP_SDI_xilinx1;
+   MCB_UIADD        <= MCB_UIADD_xilinx2;
+   MCB_UISDI        <= MCB_UISDI_xilinx11;
+   MCB_UICS         <= MCB_UICS_xilinx6;
+   MCB_UIBROADCAST  <= MCB_UIBROADCAST_xilinx4;
+   MCB_UIDONECAL    <= MCB_UIDONECAL_xilinx7;
+   MCB_UIREAD       <= MCB_UIREAD_xilinx10;
+   SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
+
+   Inc_Dec_REFRSH_Flag     <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
+   Max_Value_Delta_Up      <= Max_Value_int - Max_Value_Previous;
+   Half_MV_DU              <= ('0' & Max_Value_Delta_Up(7 downto 1));
+   Max_Value_Delta_Dn      <= Max_Value_Previous - Max_Value_int;
+   Half_MV_DD              <= ('0' & Max_Value_Delta_Dn(7 downto 1));
+   CALMODE_EQ_CALIBRATION  <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
+   Half_Max_Value          <= ('0' & Max_Value_int(7 downto 1));        
+   Quarter_Max_Value       <= ("00" & Max_Value_int(7 downto 2)); 
+   DQS_DELAY_LOWER_LIMIT   <= Quarter_Max_Value;    -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
+   DQS_DELAY_UPPER_LIMIT   <= Half_Max_Value;       -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
+   SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0'; 
+                                                -- skip dynamic input termination if either the one-time or dynamic parameters are 1
+   SKIP_DYNAMIC_DQS_CAL    <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0'; 
+                                                -- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then    
+            DONE_SOFTANDHARD_CAL <= MCB_UODONECAL;       -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
+         else
+            DONE_SOFTANDHARD_CAL <= '0';
+         end if;   
+      end if;
+   end process;      
+
+   iodrp_controller_inst : iodrp_controller
+      port map (
+         memcell_address  => IODRPCTRLR_MEMCELL_ADDR,
+         write_data       => IODRPCTRLR_WRITE_DATA,
+         read_data        => IODRPCTRLR_READ_DATA,
+         rd_not_write     => IODRPCTRLR_R_WB,
+         cmd_valid        => IODRPCTRLR_CMD_VALID,
+         rdy_busy_n       => IODRPCTRLR_RDY_BUSY_N,
+         use_broadcast    => '0',
+         sync_rst         => RST_reg,
+         DRP_CLK          => UI_CLK,
+         DRP_CS           => IODRP_CS,
+         DRP_SDI          => IODRP_SDI_xilinx1,
+         DRP_ADD          => IODRP_ADD_xilinx0,
+         DRP_SDO          => IODRP_SDO,
+         DRP_BKST         => open 
+      );      
+   
+   iodrp_mcb_controller_inst : iodrp_mcb_controller
+      port map (
+         memcell_address  => IODRPCTRLR_MEMCELL_ADDR,
+         write_data       => IODRPCTRLR_WRITE_DATA,
+         read_data        => MCB_READ_DATA,
+         rd_not_write     => IODRPCTRLR_R_WB,
+         cmd_valid        => MCB_CMD_VALID,
+         rdy_busy_n       => MCB_RDY_BUSY_N,
+         use_broadcast    => MCB_USE_BKST,
+         drp_ioi_addr     => MCB_UIADDR_int,
+         sync_rst         => RST_reg,
+         DRP_CLK          => UI_CLK,
+         DRP_CS           => MCB_UICS_xilinx6,
+         DRP_SDI          => MCB_UISDI_xilinx11,
+         DRP_ADD          => MCB_UIADD_xilinx2,
+         DRP_BKST         => MCB_UIBROADCAST_xilinx4,
+         DRP_SDO          => MCB_UOSDO,
+         MCB_UIREAD       => MCB_UIREAD_xilinx10
+      );
+      
+      process (UI_CLK, RST) begin
+         if (RST = '1') then
+           if (C_SIMULATION = "TRUE") then
+             WAIT_200us_COUNTER <= X"7FF0";
+           else
+             WAIT_200us_COUNTER <= (others => '0');
+           end if;
+         elsif (UI_CLK'event and UI_CLK = '1') then
+            if (WAIT_200us_COUNTER(15) = '1') then
+                 WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
+            else
+                 WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
+            end if;
+         end if;
+      end process;
+
+ --  init_sequence_skip: if (C_SIMULATION = "TRUE") generate
+ --     WAIT_200us_COUNTER <= X"FFFF";
+ --     process
+ --     begin
+ --        report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
+ --        wait;
+ --     end process;
+ --  end generate;
+            
+      
+   gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate 
+   process (UI_CLK, RST) begin
+      if (RST = '1') then
+          CKE_Train <= '0';
+      elsif (UI_CLK'event and UI_CLK = '1') then
+         if (STATE = WAIT_FOR_UODONE  and MCB_UODONECAL = '1') then
+              CKE_Train <= '0';
+         elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
+              CKE_Train <= '1';
+         else
+              CKE_Train <= '0';
+         end if;
+      end if;
+   end process;       
+   end generate  ;  
+      
+   gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate 
+   process (UI_CLK) begin
+      if (UI_CLK'event and UI_CLK = '1') then
+          CKE_Train <= '0';
+      end if;
+   end process;       
+   end generate    ;
+      
+--********************************************
+-- PLL_LOCK and RST signals
+--********************************************
+   --MCB_SYSRST <= Pre_SYSRST or RST_reg;               -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
+                                                      --  SYSRST pin (MCB_SYSRST)
+   
+   rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND 
+
+   process (UI_CLK, RST) begin
+     if (RST = '1') then
+       --Block_Reset <= '0';
+       --RstCounter  <= (others => '0');
+     --elsif (UI_CLK'event and UI_CLK = '1') then  
+       -- if (rst_tmp = '1') then                     -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3)
+          Block_Reset <= '0';
+          RstCounter  <= (others => '0');
+     elsif (UI_CLK'event and UI_CLK = '1') then  
+          Block_Reset <= '0';                      -- default to allow STATE to move out of RST_DELAY state
+          if (Pre_SYSRST = '1') then
+            RstCounter  <= RST_CNT;                -- whenever STATE wants to reset the MCB, set RstCounter to h10
+          else                                                                                                   
+            if (RstCounter < TZQINIT_MAXCNT) then  -- if RstCounter is less than d512 than this will execute
+              Block_Reset <= '1';                  -- STATE won't exit RST_DELAY state
+              RstCounter  <= RstCounter + "1";     -- and Rst_Counter increments
+            end if;
+          end if;
+        end if;
+     --end if;
+   end process;
+ 
+  -- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT
+  non_violating_rst <= RST and Rst_condition1;
+  MCB_SYSRST <= Pre_SYSRST;
+
+  process (UI_CLK) begin
+    if (UI_CLK'event and UI_CLK = '1') then
+       if (RstCounter >= TZQINIT_MAXCNT) then
+          Rst_condition1 <= '1';
+       else
+          Rst_condition1 <= '0';
+       end if;
+    end if;
+  end process;
+  
+-- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3)
+-- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization  process.   
+-- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which
+--    is gated by pll's lock signal.   When the PLL locks again, the RST_reg stays asserted for at least 200 us which
+--    will cause MCB to reset and reinitialize the memory afterwards.
+-- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at 
+--    its terminal count.  The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module
+--    The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration 
+--    state machine will not reset during SUSPEND.
+-- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to 
+--    Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. 
+--    It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT 
+--    termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration.
+  
+
+   --process (UI_CLK) begin
+   -- if (UI_CLK'event and UI_CLK = '1') then
+   --  
+   --    if (RstCounter < RST_CNT) then
+   --       Rst_condition2 <= '1';
+   --    else
+   --       Rst_condition2 <= '0';
+   --    end if;
+   -- end if;
+   --end process;
+  
+   process (UI_CLK, non_violating_rst) begin
+     if (non_violating_rst = '1') then
+        RST_reg <= '1';                                  -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND 
+     elsif (UI_CLK'event and UI_CLK = '1') then 
+       if (WAIT_200us_COUNTER(15) = '0')  then
+        RST_reg <= '1';
+       else
+        --RST_reg <= Rst_condition2 or rst_tmp;                                  -- insures RST_reg is at least h10 pulses long
+        RST_reg <= rst_tmp;                                  -- insures RST_reg is at least h10 pulses long
+       end if;
+     end if;
+   end process;
+   
+--*************************************************************
+-- Stretching the pre_sysrst to satisfy the minimum pulse width
+--*************************************************************
+
+process (UI_CLK) begin
+if (UI_CLK'event and UI_CLK = '1') then 
+  if (STATE = START_DYN_CAL_PRE) then
+    pre_sysrst_cnt <= pre_sysrst_cnt + '1';
+  else
+    pre_sysrst_cnt <= (others=>'0');
+  end if;
+end if;
+end process;
+
+pre_sysrst_minpulse_width_ok <= pre_sysrst_cnt(3);
+
+--********************************************
+-- SUSPEND Logic
+--********************************************
+   process (UI_CLK,RST)
+   begin
+      if (RST = '1') then
+
+         SELFREFRESH_MCB_MODE_R1 <= '0';
+         SELFREFRESH_MCB_MODE_R2 <= '0';
+         SELFREFRESH_MCB_MODE_R3 <= '0';
+
+         SELFREFRESH_REQ_R1      <= '0';
+         SELFREFRESH_REQ_R2      <= '0';
+         SELFREFRESH_REQ_R3      <= '0';
+         
+         PLL_LOCK_R1             <= '0';
+         PLL_LOCK_R2             <= '0';
+
+      elsif (UI_CLK'event and UI_CLK = '1') then
+         -- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
+         SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
+         SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
+         SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
+
+         -- SELFREFRESH_REQ is clocked by user's application clock
+         SELFREFRESH_REQ_R1      <= SELFREFRESH_REQ;
+         SELFREFRESH_REQ_R2      <= SELFREFRESH_REQ_R1;
+         SELFREFRESH_REQ_R3      <= SELFREFRESH_REQ_R2;
+
+         PLL_LOCK_R1             <= PLL_LOCK;
+         PLL_LOCK_R2             <= PLL_LOCK_R1;
+         
+      end if;
+   end process;      
+              
+-- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
+-- This is to make sure MCB get a locked sys_2x_clk before exiting
+-- SELFREFRESH mode.
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            SELFREFRESH_MCB_REQ <= '0';
+         --elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then
+         elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0')) then
+            SELFREFRESH_MCB_REQ <=  '0';
+         elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then  
+            SELFREFRESH_MCB_REQ <= '1';
+         end if;
+      end if;
+   end process;
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
+         elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
+            WAIT_SELFREFRESH_EXIT_DQS_CAL <=  '1';
+         elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then  
+                                                                                                                      -- START_DYN_CAL is next state
+            WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
+         end if;
+      end if;
+   end process;
+
+-- Need to detect when SM entering START_DYN_CAL
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
+            START_DYN_CAL_STATE_R1                  <= '0';
+         else
+         -- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle              
+            PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
+            if (STATE = START_DYN_CAL) then
+               START_DYN_CAL_STATE_R1   <= '1';
+            else   
+               START_DYN_CAL_STATE_R1   <= '0';
+            end if;   
+            if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
+               PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
+            elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then
+               PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
+            end if;
+         end if;
+      end if;
+   end process;      
+
+-- SELFREFRESH_MCB_MODE deasserted status is hold off
+-- until Soft_Calib has at least done one loop of DQS update.
+-- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before 
+-- deassert the status of MCB's SELFREFRESH_MODE.  This is to ensure all IOs are stable before
+-- user logic sending new commands to MCB.
+   
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            SELFREFRESH_MODE_xilinx11 <= '0';
+         elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
+            SELFREFRESH_MODE_xilinx11 <=  '1';
+         elsif (WarmEnough = '1') then
+            SELFREFRESH_MODE_xilinx11 <= '0';
+         end if;
+      end if;
+   end process;
+
+
+
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+           WaitCountEnable <= '0';
+         elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then  
+           WaitCountEnable <= '0';
+         elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then  
+           WaitCountEnable <= '1';
+         else
+           WaitCountEnable <=  WaitCountEnable;
+         end if;
+      end if;
+   end process;
+
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+           State_Start_DynCal <= '0';
+         elsif (STATE = START_DYN_CAL) then  
+           State_Start_DynCal <= '1';
+         else
+           State_Start_DynCal <= '0';
+         end if;
+       end if;
+     end process;
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+           State_Start_DynCal_R1 <= '0';
+        else 
+           State_Start_DynCal_R1 <= State_Start_DynCal;
+         end if;
+       end if;
+     end process;
+
+
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST = '1') then
+            WaitTimer <= (others => '0');
+            WarmEnough <= '1';
+          elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1'))  then
+            WaitTimer <= (others => '0');
+            WarmEnough <= '0';
+          elsif (WaitTimer = X"04") then 
+            WaitTimer <= WaitTimer ;
+            WarmEnough <= '1';
+          elsif (WaitCountEnable  = '1') then
+            WaitTimer <= WaitTimer + '1';
+          else
+            WaitTimer <= WaitTimer ;
+          end if;  
+        end if;
+      end process;
+
+--********************************************
+--Comparitor for Dynamic Calibration circuit
+--********************************************
+   Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
+   Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
+   
+--*********************************************************************************************
+--Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
+--*********************************************************************************************
+   process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST_reg = '1') then
+            count <= "000000";
+         elsif (counter_en = '1') then
+            count <= count + "000001";
+         else
+            count <= "000000";
+         end if;
+      end if;
+   end process;
+   
+--*********************************************************************************************
+-- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
+--*********************************************************************************************
+   process (UI_CLK, MCB_UODATAVALID)
+   begin
+     if(MCB_UODATAVALID = '1') then
+       MCB_UODATAVALID_U <= '1';
+     elsif(UI_CLK'event and UI_CLK = '1') then
+       MCB_UODATAVALID_U <= MCB_UODATAVALID;
+     end if;
+   end process;
+   
+--**************************************************************************************************************
+--Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
+--**************************************************************************************************************
+   process (Active_IODRP,  IODRP_CS, RZQ_IODRP_SDO,  ZIO_IODRP_SDO)
+   begin
+      case Active_IODRP is
+         when RZQ =>
+            RZQ_IODRP_CS <= IODRP_CS;
+            ZIO_IODRP_CS <= '0';
+            IODRP_SDO <= RZQ_IODRP_SDO;
+         when ZIO =>
+            RZQ_IODRP_CS <= '0';
+            ZIO_IODRP_CS <= IODRP_CS;
+            IODRP_SDO <= ZIO_IODRP_SDO;
+         when MCB_PORT =>
+            RZQ_IODRP_CS <= '0';
+            ZIO_IODRP_CS <= '0';
+            IODRP_SDO <= '0';
+         when others =>
+            RZQ_IODRP_CS <= '0';
+            ZIO_IODRP_CS <= '0';
+            IODRP_SDO <= '0';
+      end case;
+   end process;
+      
+--******************************************************************
+--State Machine's Always block / Case statement for Next State Logic
+--
+--The WAIT1,2,etc states were required after every state where the
+--DRP controller was used to do a write to the IODRPs - this is because
+--there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
+--sees IODRPCTRLR_CMD_VALID go high.  OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
+--soley for the purpose of reducing power, particularly on RZQ as
+--that pin is expected to have a permanent external resistor to gnd.
+--******************************************************************
+   NEXT_STATE_LOGIC: process (UI_CLK)
+   begin
+      if (UI_CLK'event and UI_CLK = '1') then
+         if (RST_reg = '1') then                         -- Synchronous reset
+            MCB_CMD_VALID           <= '0';
+            MCB_UIADDR_int      <= "00000";          -- take control of UI/UO port
+            MCB_UICMDEN             <= '1';              -- tells MCB that it is in Soft Cal.
+            MCB_UIDONECAL_xilinx7   <= '0';
+            MCB_USE_BKST            <= '0';
+            MCB_UIDRPUPDATE         <= '1';             
+            Pre_SYSRST              <= '1';              -- keeps MCB in reset
+            IODRPCTRLR_CMD_VALID    <= '0';
+            IODRPCTRLR_MEMCELL_ADDR <= NoOp;
+            IODRPCTRLR_WRITE_DATA   <= "00000000";
+            IODRPCTRLR_R_WB         <= WRITE_MODE;
+            IODRPCTRLR_USE_BKST     <= '0';
+            P_Term                  <= "000000";
+            N_Term                  <= "0000000";
+            P_Term_s                <= "000000";
+            N_Term_w                <= "0000000";
+            P_Term_w                <= "000000";
+            N_Term_s                <= "0000000";
+            
+            P_Term_Prev             <= "000000";
+            N_Term_Prev             <= "0000000";
+            Active_IODRP            <= RZQ;
+            MCB_UILDQSINC           <= '0';              --no inc or dec
+            MCB_UIUDQSINC           <= '0';              --no inc or dec
+            MCB_UILDQSDEC           <= '0';              --no inc or dec
+            MCB_UIUDQSDEC           <= '0';
+            counter_en              <= '0';              --flag that the First Dynamic Calibration completed
+            First_Dyn_Cal_Done      <= '0';
+            Max_Value_int           <= "00000000";
+            Max_Value_Previous      <= "00000000";
+            STATE                   <= START;
+            DQS_DELAY               <= "00000000";
+            DQS_DELAY_INITIAL       <= "00000000";
+            TARGET_DQS_DELAY        <= "00000000";
+            LastPass_DynCal         <= IN_TERM_PASS;
+            First_In_Term_Done      <= '0';
+            MCB_UICMD               <= '0';
+            MCB_UICMDIN             <= '0';
+            MCB_UIDQCOUNT           <= "0000";
+            counter_inc             <= "00000000";
+            counter_dec             <= "00000000";
+         else
+            counter_en              <= '0';
+            IODRPCTRLR_CMD_VALID    <= '0';
+            IODRPCTRLR_MEMCELL_ADDR <= NoOp;
+            IODRPCTRLR_R_WB         <= READ_MODE;
+            IODRPCTRLR_USE_BKST     <= '0';
+            MCB_CMD_VALID           <= '0';              --no inc or dec
+            MCB_UILDQSINC           <= '0';              --no inc or dec
+            MCB_UIUDQSINC           <= '0';              --no inc or dec
+            MCB_UILDQSDEC           <= '0';              --no inc or dec
+            MCB_UIUDQSDEC           <= '0';
+            MCB_USE_BKST            <= '0';
+            MCB_UICMDIN             <= '0';
+            DQS_DELAY               <= DQS_DELAY;
+            TARGET_DQS_DELAY        <= TARGET_DQS_DELAY;
+
+            case STATE is               
+               when START =>    --h00
+                  MCB_UICMDEN           <= '1';          -- take control of UI/UO port
+                  MCB_UIDONECAL_xilinx7 <= '0';          -- tells MCB that it is in Soft Cal.
+                  P_Term                <= "000000";
+                  N_Term                <= "0000000";
+                  Pre_SYSRST            <= '1';          -- keeps MCB in reset
+                  LastPass_DynCal       <= IN_TERM_PASS;
+                  if (SKIP_IN_TERM_CAL = 1) then
+                     --STATE <= WRITE_CALIBRATE;
+                     STATE <= WAIT_FOR_START_BROADCAST;
+                     P_Term                <= "000000";
+                     N_Term                <= "0000000";
+                  elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_RZQ_NTERM;
+                  else
+                     STATE <= START;
+                  end if;
+               --***************************
+               -- IOB INPUT TERMINATION CAL
+               --***************************
+               when LOAD_RZQ_NTERM =>   --h01
+                  Active_IODRP            <= RZQ;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ('0' & N_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_RZQ_NTERM;
+                  else
+                     STATE <= WAIT1;
+                  end if;
+
+               when WAIT1 =>    --h02
+                  if (IODRPCTRLR_RDY_BUSY_N = '0') then
+                     STATE <= WAIT1;
+                  else
+                     STATE <= LOAD_RZQ_PTERM;
+                  end if;
+
+               when LOAD_RZQ_PTERM =>   --h03
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ("00" & P_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_RZQ_PTERM;
+                  else
+                     STATE <= WAIT2;
+                  end if;
+
+               when WAIT2 =>    --h04
+                  if (IODRPCTRLR_RDY_BUSY_N = '0') then
+                     STATE <= WAIT2;
+                  elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
+                     STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
+                  else
+                     STATE <= INC_PTERM;
+                  end if;
+
+               when INC_PTERM =>        --h05
+                  P_Term <= P_Term + "000001";
+                  STATE <= LOAD_RZQ_PTERM;
+
+               when MULTIPLY_DIVIDE =>  -- h06 
+                  -- 13/4/2011 compensate the added sync FF
+                  P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0);
+                  STATE  <= LOAD_ZIO_PTERM;
+
+               when LOAD_ZIO_PTERM =>           --h07
+                  Active_IODRP            <= ZIO;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ("00" & P_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_ZIO_PTERM;
+                  else
+                     STATE <= WAIT3;
+                  end if;
+
+               when WAIT3 =>    --h08
+                  if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
+                     STATE <= WAIT3;
+                  else
+                     STATE <= LOAD_ZIO_NTERM;
+                  end if;
+
+               when LOAD_ZIO_NTERM =>   --h09
+                  Active_IODRP            <= ZIO;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ('0' & N_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= LOAD_ZIO_NTERM;
+                  else
+                     STATE <= WAIT4;
+                  end if;
+
+               when WAIT4 =>            --h0A
+                  if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
+                     STATE <= WAIT4;
+                  elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
+                     if (PNSKEW = '1') then       
+                        STATE <= SKEW;
+                     else
+                        STATE <= WAIT_FOR_START_BROADCAST;
+                     end if;            
+                  else
+                     STATE <= INC_NTERM;
+                  end if;
+
+               when INC_NTERM =>                --h0B
+                  N_Term <= N_Term + "0000001";
+                  STATE  <= LOAD_ZIO_NTERM;             
+
+               when SKEW =>     -- h0C
+               
+                  P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
+                  N_Term_w <= Mult_Divide(('0' & (N_Term-'1')),  MULT_W, DIV_W)(6 downto 0);
+                  P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0);
+                  N_Term_s <= Mult_Divide(('0' & (N_Term-'1')),  MULT_S, DIV_S)(6 downto 0);
+                  P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
+                  N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
+                  STATE  <= WAIT_FOR_START_BROADCAST;
+
+               when WAIT_FOR_START_BROADCAST => --h0D
+                  Pre_SYSRST <= '0';       -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while 
+                                           --  keeping the MCB in calibration mode
+                  Active_IODRP <= MCB_PORT;
+                  if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
+                    if ((P_Term /= P_Term_Prev) or (SKIP_IN_TERM_CAL = 1)) then
+                      STATE       <= BROADCAST_PTERM;
+                      P_Term_Prev <= P_Term;
+                    elsif (N_Term /= N_Term_Prev) then
+                      N_Term_Prev <= N_Term;
+                      STATE       <= BROADCAST_NTERM;
+                    else
+                      STATE <= OFF_RZQ_PTERM;
+                    end if;
+                  else
+                     STATE <= WAIT_FOR_START_BROADCAST;
+                  end if;
+
+               when BROADCAST_PTERM =>  --h0E
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ("00" & P_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  MCB_CMD_VALID           <= '1';
+                  MCB_UIDRPUPDATE         <= not First_In_Term_Done; -- Set the update flag if this is the first time through
+                  MCB_USE_BKST            <= '1';
+                  if (MCB_RDY_BUSY_N = '1') then
+                     STATE <= BROADCAST_PTERM;
+                  else
+                     STATE <= WAIT5;
+                  end if;
+
+               when WAIT5 =>    --h0F
+                  if ((not(MCB_RDY_BUSY_N)) = '1') then
+                     STATE <= WAIT5;
+                  elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
+                     if (MCB_UOREFRSHFLAG = '1')then
+                        MCB_UIDRPUPDATE <= '1';
+                        if (N_Term /= N_Term_Prev) then
+                           N_Term_Prev <= N_Term;
+                           STATE       <= BROADCAST_NTERM;
+                        else  
+                           STATE       <= OFF_RZQ_PTERM;
+                         end if;
+                     else
+                        STATE <= WAIT5;  -- wait for a Refresh cycle
+                     end if;            
+                  else
+                     N_Term_Prev <= N_Term;
+                     STATE <= BROADCAST_NTERM;
+                  end if;
+
+               when BROADCAST_NTERM =>  -- h10
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_WRITE_DATA   <= ("0" & N_Term);
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  MCB_CMD_VALID           <= '1';
+                  MCB_USE_BKST            <= '1';
+                  MCB_UIDRPUPDATE         <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
+                  if (MCB_RDY_BUSY_N = '1') then
+                     STATE <= BROADCAST_NTERM;
+                  else
+                     STATE <= WAIT6;
+                  end if;
+
+               when WAIT6 =>    -- h11
+                  if (MCB_RDY_BUSY_N = '0') then
+                     STATE <= WAIT6;
+                  elsif (First_In_Term_Done = '1') then  -- If first time through is already set, then this must be dynamic in term
+                    if (MCB_UOREFRSHFLAG = '1')then
+                      MCB_UIDRPUPDATE <= '1';
+                      STATE           <= OFF_RZQ_PTERM;
+                    else
+                      STATE <= WAIT6;   -- wait for a Refresh cycle
+                    end if;
+                  else
+                    -- if (PNSKEWDQS = '1') then
+                       STATE <= LDQS_CLK_WRITE_P_TERM;
+                   --  else
+                   --    STATE <= OFF_RZQ_PTERM;
+                   --  end if;
+                  end if;
+
+-- *********************
+               when LDQS_CLK_WRITE_P_TERM =>    -- h12
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= "00" & P_Term_w;
+                  MCB_UIADDR_int              <= IOI_LDQS_CLK;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1') then
+                    STATE <= LDQS_CLK_WRITE_P_TERM;
+                  else
+                    STATE <= LDQS_CLK_P_TERM_WAIT;
+                  end if;
+                
+        
+               when LDQS_CLK_P_TERM_WAIT =>    --7'h13  
+                 if (MCB_RDY_BUSY_N  = '0') then
+                   STATE   <= LDQS_CLK_P_TERM_WAIT;
+                 else 
+                   STATE   <= LDQS_CLK_WRITE_N_TERM;
+                 end if;        
+        
+               when  LDQS_CLK_WRITE_N_TERM =>  --7'h14
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= '0' & N_Term_s;
+                  MCB_UIADDR_int              <= IOI_LDQS_CLK;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1') then
+                    STATE <= LDQS_CLK_WRITE_N_TERM;
+                  else
+                    STATE <= LDQS_CLK_N_TERM_WAIT;
+                  end if;
+        
+   --**     
+               when  LDQS_CLK_N_TERM_WAIT =>   --7'h15
+                  if (MCB_RDY_BUSY_N  = '0') then
+                    STATE <= LDQS_CLK_N_TERM_WAIT;
+                  else 
+                    STATE           <= LDQS_PIN_WRITE_P_TERM;
+                 end if;
+                
+                
+               when   LDQS_PIN_WRITE_P_TERM => --7'h16
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= "00" & P_Term_s;
+                  MCB_UIADDR_int              <= IOI_LDQS_PIN;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1')  then
+                    STATE <= LDQS_PIN_WRITE_P_TERM;
+                  else
+                    STATE <= LDQS_PIN_P_TERM_WAIT;
+                  end if;
+                
+                
+               when  LDQS_PIN_P_TERM_WAIT =>   --7'h17
+                  if (MCB_RDY_BUSY_N  = '0')  then
+                    STATE <= LDQS_PIN_P_TERM_WAIT;
+                  else 
+                    STATE    <= LDQS_PIN_WRITE_N_TERM;
+                  end if;
+               
+                
+                when  LDQS_PIN_WRITE_N_TERM => --7'h18
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= '0' & N_Term_w;
+                  MCB_UIADDR_int              <= IOI_LDQS_PIN;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1')  then
+                    STATE <= LDQS_PIN_WRITE_N_TERM;
+                  else
+                    STATE <= LDQS_PIN_N_TERM_WAIT;
+                  end if;
+                
+                
+               when  LDQS_PIN_N_TERM_WAIT =>  --7'h19
+                  if (MCB_RDY_BUSY_N  = '0')  then
+                    STATE <= LDQS_PIN_N_TERM_WAIT;
+                  else 
+                    STATE           <= UDQS_CLK_WRITE_P_TERM;
+                  end if;
+               
+                
+                
+               when  UDQS_CLK_WRITE_P_TERM => --7'h1A
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= "00" & P_Term_w;
+                  MCB_UIADDR_int              <= IOI_UDQS_CLK;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1')  then
+                    STATE <= UDQS_CLK_WRITE_P_TERM;
+                  else
+                    STATE <= UDQS_CLK_P_TERM_WAIT;
+                  end if;
+                
+                
+               when  UDQS_CLK_P_TERM_WAIT => --7'h1B
+                  if (MCB_RDY_BUSY_N  = '0')  then
+                    STATE <= UDQS_CLK_P_TERM_WAIT;
+                  else 
+                    STATE           <= UDQS_CLK_WRITE_N_TERM;
+                  end if;
+                
+                
+               when  UDQS_CLK_WRITE_N_TERM => --7'h1C
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= '0' & N_Term_s;
+                  MCB_UIADDR_int              <= IOI_UDQS_CLK;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N  = '1')  then
+                    STATE <= UDQS_CLK_WRITE_N_TERM;
+                  else
+                    STATE <= UDQS_CLK_N_TERM_WAIT;
+                  end if;
+                
+               when UDQS_CLK_N_TERM_WAIT => --7'h1D
+                  if (MCB_RDY_BUSY_N  = '0') then
+                    STATE <= UDQS_CLK_N_TERM_WAIT;
+                  else 
+                    STATE           <= UDQS_PIN_WRITE_P_TERM;
+                  end if;
+                
+                
+                
+                when  UDQS_PIN_WRITE_P_TERM => --7'h1E
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= "00" & P_Term_s;
+                  MCB_UIADDR_int              <= IOI_UDQS_PIN;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N = '1')  then
+                    STATE <= UDQS_PIN_WRITE_P_TERM;
+                  else
+                    STATE <= UDQS_PIN_P_TERM_WAIT;
+                  end if;
+                
+                
+               when UDQS_PIN_P_TERM_WAIT =>  --7'h1F
+                  if (MCB_RDY_BUSY_N = '0')  then
+                    STATE <= UDQS_PIN_P_TERM_WAIT;
+                  else 
+                    STATE           <= UDQS_PIN_WRITE_N_TERM;
+                  end if;
+                
+                when  UDQS_PIN_WRITE_N_TERM =>  --7'h20
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  IODRPCTRLR_WRITE_DATA   <= '0' & N_Term_w;
+                  MCB_UIADDR_int              <= IOI_UDQS_PIN;
+                  MCB_CMD_VALID           <= '1';
+                  if (MCB_RDY_BUSY_N = '1')  then
+                    STATE <= UDQS_PIN_WRITE_N_TERM;
+                  else
+                    STATE <= UDQS_PIN_N_TERM_WAIT;
+                  end if;
+                
+                
+                when  UDQS_PIN_N_TERM_WAIT =>   --7'h21
+                  if (MCB_RDY_BUSY_N = '0')  then
+                    STATE <= UDQS_PIN_N_TERM_WAIT;
+                  else 
+                    STATE           <= OFF_RZQ_PTERM;
+                  end if;
+               
+-- *********************
+
+
+               when OFF_RZQ_PTERM =>    -- h22
+                  Active_IODRP            <= RZQ;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= PTerm;
+                  IODRPCTRLR_WRITE_DATA   <= "00000000";
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  P_Term                  <= "000000";
+                  N_Term                  <= "0000000";
+                  MCB_UIDRPUPDATE         <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= OFF_RZQ_PTERM;
+                  else
+                     STATE <= WAIT7;
+                  end if;
+
+               when WAIT7 =>    -- h23
+                  if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
+                     STATE <= WAIT7;
+                  else
+                     STATE <= OFF_ZIO_NTERM;
+                  end if;
+
+               when OFF_ZIO_NTERM =>    -- h24
+                  Active_IODRP            <= ZIO;
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= NTerm;
+                  IODRPCTRLR_WRITE_DATA   <= "00000000";
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= OFF_ZIO_NTERM;
+                  else
+                     STATE <= WAIT8;
+                  end if;
+
+               when WAIT8 =>    -- h25
+                  if (IODRPCTRLR_RDY_BUSY_N = '0') then
+                     STATE <= WAIT8;
+                  else   
+                     if (First_In_Term_Done = '1') then
+                        STATE <= START_DYN_CAL;    -- No need to reset the MCB if we are in InTerm tuning
+                     else
+                        STATE <= WRITE_CALIBRATE;  -- go read the first Max_Value_int from RZQ
+                     end if;
+                  end if;   
+
+              when RST_DELAY =>      -- h26
+                --MCB_UICMDEN <= '0';          -- release control of UI/UO port      
+                if (Block_Reset = '1') then  -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
+                 STATE <= RST_DELAY;
+               else 
+                 STATE <= START_DYN_CAL_PRE;
+               end if;
+
+--***************************
+--DYNAMIC CALIBRATION PORTION
+--***************************
+               when START_DYN_CAL_PRE =>        -- h27
+                  LastPass_DynCal       <= IN_TERM_PASS;
+                  MCB_UICMDEN           <= '0';          -- release UICMDEN
+                  MCB_UIDONECAL_xilinx7 <= '1';          -- release UIDONECAL - MCB will now initialize.
+                  Pre_SYSRST            <= '1';          -- SYSRST pulse
+                  if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
+                    STATE       <= START_DYN_CAL;        -- we'll skip setting the DQS delays manually
+                  elsif (pre_sysrst_minpulse_width_ok = '1') then
+                    STATE       <= WAIT_FOR_UODONE;
+                  end if;
+
+               when WAIT_FOR_UODONE =>          -- h28
+                 Pre_SYSRST    <= '0';                   -- SYSRST pulse
+                 if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
+                   MCB_UICMDEN         <= '1';           -- grab UICMDEN
+                   DQS_DELAY_INITIAL   <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
+                   STATE               <= LDQS_WRITE_POS_INDELAY;
+                 else
+                   STATE               <= WAIT_FOR_UODONE;
+                 end if;
+
+               when LDQS_WRITE_POS_INDELAY =>   -- h29 
+                 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
+                 IODRPCTRLR_R_WB         <= WRITE_MODE;
+                 IODRPCTRLR_WRITE_DATA   <= DQS_DELAY_INITIAL;
+                 MCB_UIADDR_int     <= IOI_LDQS_CLK;
+                 MCB_CMD_VALID           <= '1';
+                 if (MCB_RDY_BUSY_N = '1') then 
+                   STATE <= LDQS_WRITE_POS_INDELAY;
+                 else
+                   STATE <= LDQS_WAIT1;
+                 end if;
+
+               when LDQS_WAIT1 =>       -- h2A
+                 if (MCB_RDY_BUSY_N = '0')then
+                   STATE <= LDQS_WAIT1;
+                 else
+                   STATE <= LDQS_WRITE_NEG_INDELAY;      
+                 end if;
+
+              when LDQS_WRITE_NEG_INDELAY =>    -- h2B
+                IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
+                IODRPCTRLR_R_WB         <= WRITE_MODE;
+                IODRPCTRLR_WRITE_DATA   <= DQS_DELAY_INITIAL;
+                MCB_UIADDR_int      <= IOI_LDQS_CLK;
+                MCB_CMD_VALID           <= '1';
+                if (MCB_RDY_BUSY_N = '1')then 
+                  STATE <= LDQS_WRITE_NEG_INDELAY;
+                else
+                  STATE <= LDQS_WAIT2;
+                end if;
+
+               when LDQS_WAIT2 =>           -- 7'h2C
+                 if(MCB_RDY_BUSY_N = '0')then
+                   STATE <= LDQS_WAIT2;
+                 else
+                   STATE <= UDQS_WRITE_POS_INDELAY;
+                 end if;
+
+               when  UDQS_WRITE_POS_INDELAY =>  -- 7'h2D
+                 IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
+                 IODRPCTRLR_R_WB         <= WRITE_MODE;
+                 IODRPCTRLR_WRITE_DATA   <= DQS_DELAY_INITIAL;
+                 MCB_UIADDR_int      <= IOI_UDQS_CLK;
+                 MCB_CMD_VALID           <= '1';
+                 if (MCB_RDY_BUSY_N = '1')then
+                   STATE <= UDQS_WRITE_POS_INDELAY;
+                 else
+                   STATE <= UDQS_WAIT1;
+                 end if;
+
+               when UDQS_WAIT1 =>           -- 7'h2E
+                 if (MCB_RDY_BUSY_N = '0')then
+                   STATE <= UDQS_WAIT1;
+                 else 
+                   STATE <= UDQS_WRITE_NEG_INDELAY;
+                 end if;
+
+               when UDQS_WRITE_NEG_INDELAY => -- 7'h2F
+                 IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
+                 IODRPCTRLR_R_WB         <= WRITE_MODE;
+                 IODRPCTRLR_WRITE_DATA   <= DQS_DELAY_INITIAL;
+                 MCB_UIADDR_int     <= IOI_UDQS_CLK;
+                 MCB_CMD_VALID           <= '1';
+                 if (MCB_RDY_BUSY_N = '1')then
+                   STATE <= UDQS_WRITE_NEG_INDELAY;
+                else
+                  STATE <= UDQS_WAIT2;
+                end if;
+
+               when UDQS_WAIT2 => -- 7'h30
+                 if (MCB_RDY_BUSY_N = '0')then
+                   STATE <= UDQS_WAIT2;
+                 else 
+                    DQS_DELAY         <= DQS_DELAY_INITIAL;
+                    TARGET_DQS_DELAY  <= DQS_DELAY_INITIAL;
+                    STATE             <= START_DYN_CAL;
+                end if;
+
+               when START_DYN_CAL =>    -- h31
+                  Pre_SYSRST  <= '0';                    -- SYSRST not driven
+                  counter_inc <= (others => '0');
+                  counter_dec <= (others => '0');
+                  if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
+                     STATE <= DONE;                      --if we're skipping both dynamic algorythms, go directly to DONE
+                  elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
+                                                         --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
+                     -- Alternate between Dynamic Input Termination and Dynamic Tuning routines           
+                     if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then       
+                        LastPass_DynCal <= IN_TERM_PASS;
+                        STATE           <= LOAD_RZQ_NTERM;
+                     else 
+                        LastPass_DynCal <= DYN_CAL_PASS;
+                        STATE           <= WRITE_CALIBRATE;
+                     end if;
+                  else
+                     STATE     <= START_DYN_CAL;
+                  end if;
+
+               when WRITE_CALIBRATE =>          -- h32
+                  Pre_SYSRST              <= '0';
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
+                  IODRPCTRLR_WRITE_DATA   <= "00100000";
+                  IODRPCTRLR_R_WB         <= WRITE_MODE;
+                  Active_IODRP            <= RZQ;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= WRITE_CALIBRATE;
+                  else
+                     STATE <= WAIT9;
+                  end if;               
+
+               when WAIT9 =>    -- h33
+                  counter_en <= '1';
+                  if (count < "100110") then             -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
+                     STATE <= WAIT9;
+                  else
+                     STATE <= READ_MAX_VALUE;
+                  end if;
+
+               when READ_MAX_VALUE =>           -- h34
+                  IODRPCTRLR_CMD_VALID    <= '1';
+                  IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
+                  IODRPCTRLR_R_WB         <= READ_MODE;
+                  Max_Value_Previous      <= Max_Value_int;
+                  if (IODRPCTRLR_RDY_BUSY_N = '1') then
+                     STATE <= READ_MAX_VALUE;
+                  else
+                     STATE <= WAIT10;
+                  end if;               
+
+               when WAIT10 =>           -- h35   
+                  if (IODRPCTRLR_RDY_BUSY_N = '0') then
+                     STATE <= WAIT10;
+                  else
+                     Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
+                    if (First_In_Term_Done = '0') then
+                      STATE               <= RST_DELAY;
+                      First_In_Term_Done  <= '1';
+                    else 
+                     STATE                <= ANALYZE_MAX_VALUE;
+                    end if;
+                  end if;
+
+               when ANALYZE_MAX_VALUE =>        -- h36      only do a Inc or Dec during a REFRESH cycle.
+                 if (First_Dyn_Cal_Done = '0')then
+                   STATE <= FIRST_DYN_CAL;
+                 elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
+                    STATE            <= DECREMENT;       -- May need to Decrement
+                    TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
+                                                         -- DQS_COUNT_VIRTUAL updated (could be negative value)
+                 elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
+                    STATE            <= INCREMENT;       -- May need to Increment
+                    TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
+                 else 
+                    Max_Value_int    <= Max_Value_Previous;
+                    STATE            <= START_DYN_CAL;
+                 end if; 
+
+               when FIRST_DYN_CAL =>            -- h37
+                  First_Dyn_Cal_Done <= '1';             -- set flag that the First Dynamic Calibration has been completed
+                  STATE              <= START_DYN_CAL;
+
+               when INCREMENT =>        -- h38
+                  STATE         <= START_DYN_CAL;        -- Default case: Inc is not high or no longer in REFRSH
+                  MCB_UILDQSINC <= '0';                  -- Default case: no inc or dec
+                  MCB_UIUDQSINC <= '0';                  -- Default case: no inc or dec
+                  MCB_UILDQSDEC <= '0';                  -- Default case: no inc or dec
+                  MCB_UIUDQSDEC <= '0';                  -- Default case: no inc or dec
+                  case Inc_Dec_REFRSH_Flag is            -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
+                     when "101" =>
+                       counter_inc    <= counter_inc + '1';
+                       STATE          <= INCREMENT;      -- Increment is still high, still in REFRSH cycle      
+                       if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then 
+                                                         -- if not at the upper limit yet, and you've waited 4 clks, increment
+                          MCB_UILDQSINC <= '1';
+                          MCB_UIUDQSINC <= '1';
+                          DQS_DELAY     <= DQS_DELAY + '1';
+                       end if;
+                     when "100" =>
+                      if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
+                        STATE         <= INCREMENT;      -- Increment is still high, REFRESH ended - wait for next REFRESH
+                      end if; 
+                     when others =>
+                        STATE         <= START_DYN_CAL;
+                  end case;
+
+               when DECREMENT =>                -- h39
+                  STATE         <= START_DYN_CAL;        -- Default case: Dec is not high or no longer in REFRSH
+                  MCB_UILDQSINC <= '0';                  -- Default case: no inc or dec
+                  MCB_UIUDQSINC <= '0';                  -- Default case: no inc or dec
+                  MCB_UILDQSDEC <= '0';                  -- Default case: no inc or dec
+                  MCB_UIUDQSDEC <= '0';                  -- Default case: no inc or dec
+                  if (DQS_DELAY /= "00000000") then
+                     case Inc_Dec_REFRSH_Flag is         -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
+                        when "011" =>
+                           counter_dec    <= counter_dec + '1';
+                           STATE          <= DECREMENT;  -- Decrement is still high, still in REFRSH cycle      
+                           if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then 
+                                                         -- if not at the lower limit, and you've waited 4 clks, decrement
+                              MCB_UILDQSDEC <= '1';      -- decrement
+                              MCB_UIUDQSDEC <= '1';      -- decrement
+                              DQS_DELAY     <= DQS_DELAY - '1'; -- SBS
+                          end if;
+                        when "010" =>
+                          if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then  --if not at the lower limit, decrement
+                            STATE           <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
+                          end if;
+                        when others =>
+                           STATE            <= START_DYN_CAL;
+                     end case;
+                  end if;
+
+               when DONE =>     -- h3A
+                  Pre_SYSRST  <= '0';                    -- SYSRST cleared
+                  MCB_UICMDEN <= '0';                    -- release UICMDEN
+                  STATE       <= DONE;
+
+               when others =>
+                  MCB_UICMDEN             <= '0';        -- release UICMDEN
+                  MCB_UIDONECAL_xilinx7   <= '1';        -- release UIDONECAL - MCB will now initialize.
+                  Pre_SYSRST              <= '0';        -- SYSRST not driven
+                  IODRPCTRLR_CMD_VALID    <= '0';
+                  IODRPCTRLR_MEMCELL_ADDR <= "00000000";
+                  IODRPCTRLR_WRITE_DATA   <= "00000000";
+                  IODRPCTRLR_R_WB         <= '0';
+                  IODRPCTRLR_USE_BKST     <= '0';
+                  P_Term                  <= "000000";
+                  N_Term                  <= "0000000";
+                  Active_IODRP            <= ZIO;
+                  Max_Value_Previous      <= "00000000";
+                  MCB_UILDQSINC           <= '0';        -- no inc or dec
+                  MCB_UIUDQSINC           <= '0';        -- no inc or dec
+                  MCB_UILDQSDEC           <= '0';        -- no inc or dec
+                  MCB_UIUDQSDEC           <= '0';        -- no inc or dec
+                  counter_en              <= '0';
+                  First_Dyn_Cal_Done      <= '0';        -- flag that the First Dynamic Calibration completed
+                  Max_Value_int           <= Max_Value_int;
+                  STATE                   <= START;
+            end case;
+         end if;
+      end if;
+   end process;
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration_top.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration_top.vhd
new file mode 100755
index 0000000..10aebb4
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration_top.vhd
@@ -0,0 +1,428 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_soft_calibration_top.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:26 $
+-- \   \  /  \    Date Created: Mon Feb 9 2009
+--  \___\/\___\
+--
+--Device: Spartan6
+--Design Name: DDR/DDR2/DDR3/LPDDR
+--Purpose:  Xilinx reference design top-level simulation
+--           wrapper file for input termination calibration
+--Reference:
+--
+--  Revision:      Date:  Comment
+--     1.0:  2/06/09:  Initial version for MIG wrapper.
+--     1.1:  3/16/09: Added pll_lock port, for using it to gate reset
+--     1.2: 6/06/09:  Removed MCB_UIDQCOUNT.
+--     1.3: 6/18/09:  corrected/changed MCB_SYSRST to be an output port
+--     1.4: 6/24/09:  gave RZQ and ZIO each their own unique ADD and SDI nets
+--     1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
+--     1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
+--     1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
+--     1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
+-- End Revision
+--**********************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+library unisim;
+use unisim.vcomponents.all;
+
+entity mcb_soft_calibration_top is
+   generic (
+      C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets 
+      C_MC_CALIBRATION_MODE : string :=  "CALIBRATION";  -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
+                                                         --  and does dynamic recal,
+                                                         -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and* 
+                                                         --  no dynamic recal will be done 
+      SKIP_IN_TERM_CAL      : integer := 0;             -- provides option to skip the input termination calibration
+      SKIP_DYNAMIC_CAL      : integer := 0;             -- provides option to skip the dynamic delay calibration
+      SKIP_DYN_IN_TERM      : integer := 0;             -- provides option to skip the dynamic delay calibration
+      C_SIMULATION          : string  := "FALSE";       -- Tells us whether the design is being simulated or implemented
+      C_MEM_TYPE            : string  := "DDR"          -- provides the memory device used for the design
+
+   );
+   port (
+      UI_CLK                : in std_logic;             -- Input - global clock to be used for input_term_tuner and IODRP clock
+      RST                   : in std_logic;             -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for 
+                                                        --  IODRP (sub)controller
+      IOCLK                 : in std_logic;             -- Input - IOCLK input to the IODRP's
+      DONE_SOFTANDHARD_CAL  : out std_logic;            -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
+                                                        --  (MCB hard calib complete)
+      PLL_LOCK              : in std_logic;             -- Lock signal from PLL
+      SELFREFRESH_REQ       : in std_logic;             
+      SELFREFRESH_MCB_MODE  : in std_logic;             
+      SELFREFRESH_MCB_REQ   : out std_logic;            
+      SELFREFRESH_MODE      : out std_logic;            
+      MCB_UIADD             : out std_logic;            -- to MCB's UIADD port
+      MCB_UISDI             : out std_logic;            -- to MCB's UISDI port
+      MCB_UOSDO             : in std_logic;
+      MCB_UODONECAL         : in std_logic;
+      MCB_UOREFRSHFLAG      : in std_logic;
+      MCB_UICS              : out std_logic;
+      MCB_UIDRPUPDATE       : out std_logic;
+      MCB_UIBROADCAST       : out std_logic;
+      MCB_UIADDR            : out std_logic_vector(4 downto 0);
+      MCB_UICMDEN           : out std_logic;
+      MCB_UIDONECAL         : out std_logic;
+      MCB_UIDQLOWERDEC      : out std_logic;
+      MCB_UIDQLOWERINC      : out std_logic;
+      MCB_UIDQUPPERDEC      : out std_logic;
+      MCB_UIDQUPPERINC      : out std_logic;
+      MCB_UILDQSDEC         : out std_logic;
+      MCB_UILDQSINC         : out std_logic;
+      MCB_UIREAD            : out std_logic;
+      MCB_UIUDQSDEC         : out std_logic;
+      MCB_UIUDQSINC         : out std_logic;
+      MCB_RECAL             : out std_logic;
+      MCB_SYSRST            : out std_logic;
+
+      MCB_UICMD             : out std_logic;
+      MCB_UICMDIN           : out std_logic;
+      MCB_UIDQCOUNT         : out std_logic_vector(3 downto 0);
+      MCB_UODATA            : in std_logic_vector(7 downto 0);
+      MCB_UODATAVALID       : in std_logic;
+      MCB_UOCMDREADY        : in std_logic;
+      MCB_UO_CAL_START      : in std_logic;
+      RZQ_PIN               : inout std_logic;
+      ZIO_PIN               : inout std_logic;
+      CKE_Train             : out std_logic
+      
+   );
+end entity mcb_soft_calibration_top;
+
+architecture trans of mcb_soft_calibration_top is
+   
+component mcb_soft_calibration is
+   generic (
+      C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
+      SKIP_IN_TERM_CAL      : integer := 0;                 -- provides option to skip the input termination calibration
+      SKIP_DYNAMIC_CAL      : integer := 0;                 -- provides option to skip the dynamic delay calibration
+      SKIP_DYN_IN_TERM      : integer := 1;                 -- provides option to skip the input termination calibration
+      C_MC_CALIBRATION_MODE : string  := "CALIBRATION";      -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
+                                                            -- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY 
+                                                            -- (Quarter, etc)
+
+      C_SIMULATION          : string  := "FALSE";           -- Tells us whether the design is being simulated or implemented
+      C_MEM_TYPE            : string  := "DDR"
+   );
+   port (
+      UI_CLK                : in std_logic;         -- main clock input for logic and IODRP CLK pins.  At top level, this should also connect to IODRP2_MCB 
+                                                    --  CLK pins
+      RST                   : in std_logic;         -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
+      DONE_SOFTANDHARD_CAL  : out std_logic;        -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB 
+                                                    --  hard calib complete)
+      PLL_LOCK              : in std_logic;         -- Lock signal from PLL
+      SELFREFRESH_REQ       : in std_logic;
+      SELFREFRESH_MCB_MODE  : in std_logic;
+      SELFREFRESH_MCB_REQ   : out std_logic;
+      SELFREFRESH_MODE      : out std_logic;
+      IODRP_ADD             : out std_logic;        -- IODRP ADD port 
+      IODRP_SDI             : out std_logic;        -- IODRP SDI port
+      RZQ_IN                : in std_logic;         -- RZQ pin from board - expected to have a 2*R resistor to ground
+      RZQ_IODRP_SDO         : in std_logic;         -- RZQ IODRP's SDO port
+      RZQ_IODRP_CS          : out std_logic := '0'; -- RZQ IODRP's CS port
+      ZIO_IN                : in std_logic;         -- Z-stated IO pin - garanteed not to be driven externally
+      ZIO_IODRP_SDO         : in std_logic;         -- ZIO IODRP's SDO port
+      ZIO_IODRP_CS          : out std_logic := '0'; -- ZIO IODRP's CS port
+      MCB_UIADD             : out std_logic;        -- to MCB's UIADD port
+      MCB_UISDI             : out std_logic;        -- to MCB's UISDI port
+      MCB_UOSDO             : in std_logic;         -- from MCB's UOSDO port (User output SDO)
+      MCB_UODONECAL         : in std_logic;         -- indicates when MCB hard calibration process is complete
+      MCB_UOREFRSHFLAG      : in std_logic;         -- high during refresh cycle and time when MCB is innactive
+      MCB_UICS              : out std_logic;        -- to MCB's UICS port (User Input CS)
+      MCB_UIDRPUPDATE       : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used 
+                                                    --  during IODRP2_MCB writes).  Currently just trasnparent
+      MCB_UIBROADCAST       : out std_logic;        -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
+      MCB_UIADDR            : out std_logic_vector(4 downto 0) := "00000";  -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
+      MCB_UICMDEN           : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
+      MCB_UIDONECAL         : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
+      MCB_UIDQLOWERDEC      : out std_logic := '0';
+      MCB_UIDQLOWERINC      : out std_logic := '0';
+      MCB_UIDQUPPERDEC      : out std_logic := '0';
+      MCB_UIDQUPPERINC      : out std_logic := '0';
+      MCB_UILDQSDEC         : out std_logic := '0';
+      MCB_UILDQSINC         : out std_logic := '0';
+      MCB_UIREAD            : out std_logic;        -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in 
+                                                    --  regular IODRP2).  IODRPCTRLR_R_WB becomes don't-care.
+      MCB_UIUDQSDEC         : out std_logic := '0';
+      MCB_UIUDQSINC         : out std_logic := '0';
+      MCB_RECAL             : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
+      MCB_UICMD             : out std_logic;
+      MCB_UICMDIN           : out std_logic;
+      MCB_UIDQCOUNT         : out std_logic_vector(3 downto 0);
+      MCB_UODATA            : in std_logic_vector(7 downto 0);
+      MCB_UODATAVALID       : in std_logic;
+      MCB_UOCMDREADY        : in std_logic;
+      MCB_UO_CAL_START      : in std_logic;
+      MCB_SYSRST            : out std_logic;        -- drives the MCB's SYSRST pin - the main reset for MCB
+      Max_Value             : out std_logic_vector(7 downto 0);
+      CKE_Train             : out std_logic
+      
+   );
+end component;
+
+   signal IODRP_ADD                    : std_logic;
+   signal IODRP_SDI                    : std_logic;
+   signal RZQ_IODRP_SDO                : std_logic;
+   signal RZQ_IODRP_CS                 : std_logic;
+   signal ZIO_IODRP_SDO                : std_logic;
+   signal ZIO_IODRP_CS                 : std_logic;
+   signal IODRP_SDO                    : std_logic;
+   signal IODRP_CS                     : std_logic;
+   signal IODRP_BKST                   : std_logic;
+   signal RZQ_ZIO_ODATAIN              : std_logic;
+   signal RZQ_ZIO_TRISTATE             : std_logic;
+   signal RZQ_TOUT                     : std_logic;
+   signal ZIO_TOUT                     : std_logic;
+   signal Max_Value                    : std_logic_vector(7 downto 0);
+   
+   signal RZQ_IN                       : std_logic;             -- RZQ pin from board - expected to have a 2*R resistor to ground
+   signal RZQ_IN_R1                    : std_logic;             -- RZQ pin from board - expected to have a 2*R resistor to ground
+   signal RZQ_IN_R2                    : std_logic;             -- RZQ pin from board - expected to have a 2*R resistor to ground
+   signal ZIO_IN                       : std_logic;             -- Z-stated IO pin - garanteed not to be driven externally
+   signal ZIO_IN_R1                    : std_logic;             -- Z-stated IO pin - garanteed not to be driven externally
+   signal ZIO_IN_R2                    : std_logic;             -- Z-stated IO pin - garanteed not to be driven externally
+   signal RZQ_OUT                      : std_logic;
+   signal ZIO_OUT                      : std_logic;
+   
+   -- Declare intermediate signals for referenced outputs
+   signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
+   signal MCB_UIADD_xilinx3            : std_logic;
+   signal MCB_UISDI_xilinx17           : std_logic;
+   signal MCB_UICS_xilinx7             : std_logic;
+   signal MCB_UIDRPUPDATE_xilinx13     : std_logic;
+   signal MCB_UIBROADCAST_xilinx5      : std_logic;
+   signal MCB_UIADDR_xilinx4           : std_logic_vector(4 downto 0);
+   signal MCB_UICMDEN_xilinx6          : std_logic;
+   signal MCB_UIDONECAL_xilinx8        : std_logic;
+   signal MCB_UIDQLOWERDEC_xilinx9     : std_logic;
+   signal MCB_UIDQLOWERINC_xilinx10    : std_logic;
+   signal MCB_UIDQUPPERDEC_xilinx11    : std_logic;
+   signal MCB_UIDQUPPERINC_xilinx12    : std_logic;
+   signal MCB_UILDQSDEC_xilinx14       : std_logic;
+   signal MCB_UILDQSINC_xilinx15       : std_logic;
+   signal MCB_UIREAD_xilinx16          : std_logic;
+   signal MCB_UIUDQSDEC_xilinx18       : std_logic;
+   signal MCB_UIUDQSINC_xilinx19       : std_logic;
+   signal MCB_RECAL_xilinx1            : std_logic;
+   signal MCB_SYSRST_xilinx2           : std_logic;
+begin
+   -- Drive referenced outputs
+   DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
+   MCB_UIADD <= MCB_UIADD_xilinx3;
+   MCB_UISDI <= MCB_UISDI_xilinx17;
+   MCB_UICS <= MCB_UICS_xilinx7;
+   MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
+   MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
+   MCB_UIADDR <= MCB_UIADDR_xilinx4;
+   MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
+   MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
+   MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
+   MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
+   MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
+   MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
+   MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
+   MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
+   MCB_UIREAD <= MCB_UIREAD_xilinx16;
+   MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
+   MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
+   MCB_RECAL <= MCB_RECAL_xilinx1;
+   MCB_SYSRST <= MCB_SYSRST_xilinx2;
+   
+   RZQ_ZIO_ODATAIN  <= not(RST);
+   RZQ_ZIO_TRISTATE <= not(RST);
+   IODRP_BKST       <= '0';                -- future hook for possible BKST to ZIO and RZQ
+   
+   
+   mcb_soft_calibration_inst : mcb_soft_calibration
+      generic map (
+         C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
+         C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE, 
+         SKIP_IN_TERM_CAL     => SKIP_IN_TERM_CAL,
+         SKIP_DYNAMIC_CAL     => SKIP_DYNAMIC_CAL,
+         SKIP_DYN_IN_TERM     => SKIP_DYN_IN_TERM,
+	 C_SIMULATION         => C_SIMULATION,
+         C_MEM_TYPE           => C_MEM_TYPE
+
+      )
+      port map (
+         UI_CLK                => UI_CLK,
+         RST                   => RST,
+         PLL_LOCK              => PLL_LOCK,
+         SELFREFRESH_REQ       => SELFREFRESH_REQ,
+         SELFREFRESH_MCB_MODE  => SELFREFRESH_MCB_MODE,
+         SELFREFRESH_MCB_REQ   => SELFREFRESH_MCB_REQ,
+         SELFREFRESH_MODE      => SELFREFRESH_MODE,
+         DONE_SOFTANDHARD_CAL  => DONE_SOFTANDHARD_CAL_xilinx0,
+         IODRP_ADD             => IODRP_ADD,
+         IODRP_SDI             => IODRP_SDI,
+         RZQ_IN                => RZQ_IN_R2,
+         RZQ_IODRP_SDO         => RZQ_IODRP_SDO,
+         RZQ_IODRP_CS          => RZQ_IODRP_CS,
+         ZIO_IN                => ZIO_IN_R2,
+         ZIO_IODRP_SDO         => ZIO_IODRP_SDO,
+         ZIO_IODRP_CS          => ZIO_IODRP_CS,
+         MCB_UIADD             => MCB_UIADD_xilinx3,
+         MCB_UISDI             => MCB_UISDI_xilinx17,
+         MCB_UOSDO             => MCB_UOSDO,
+         MCB_UODONECAL         => MCB_UODONECAL,
+         MCB_UOREFRSHFLAG      => MCB_UOREFRSHFLAG,
+         MCB_UICS              => MCB_UICS_xilinx7,
+         MCB_UIDRPUPDATE       => MCB_UIDRPUPDATE_xilinx13,
+         MCB_UIBROADCAST       => MCB_UIBROADCAST_xilinx5,
+         MCB_UIADDR            => MCB_UIADDR_xilinx4,
+         MCB_UICMDEN           => MCB_UICMDEN_xilinx6,
+         MCB_UIDONECAL         => MCB_UIDONECAL_xilinx8,
+         MCB_UIDQLOWERDEC      => MCB_UIDQLOWERDEC_xilinx9,
+         MCB_UIDQLOWERINC      => MCB_UIDQLOWERINC_xilinx10,
+         MCB_UIDQUPPERDEC      => MCB_UIDQUPPERDEC_xilinx11,
+         MCB_UIDQUPPERINC      => MCB_UIDQUPPERINC_xilinx12,
+         MCB_UILDQSDEC         => MCB_UILDQSDEC_xilinx14,
+         MCB_UILDQSINC         => MCB_UILDQSINC_xilinx15,
+         MCB_UIREAD            => MCB_UIREAD_xilinx16,
+         MCB_UIUDQSDEC         => MCB_UIUDQSDEC_xilinx18,
+         MCB_UIUDQSINC         => MCB_UIUDQSINC_xilinx19,
+         MCB_RECAL             => MCB_RECAL_xilinx1,
+         MCB_UICMD             => MCB_UICMD,
+         MCB_UICMDIN           => MCB_UICMDIN,    
+         MCB_UIDQCOUNT         => MCB_UIDQCOUNT,     
+         MCB_UODATA            => MCB_UODATA,    
+         MCB_UODATAVALID       => MCB_UODATAVALID,    
+         MCB_UOCMDREADY        => MCB_UOCMDREADY,    
+         MCB_UO_CAL_START      => MCB_UO_CAL_START,
+         mcb_sysrst            => MCB_SYSRST_xilinx2,
+         Max_Value             => Max_Value,
+         CKE_Train             => CKE_Train
+      );
+   
+   process(UI_CLK,RST)
+   begin
+     if (RST = '1') then 
+        ZIO_IN_R1 <= '0'; 
+        ZIO_IN_R2 <= '0';
+        RZQ_IN_R1 <= '0'; 
+        RZQ_IN_R2 <= '0';          
+      elsif (UI_CLK'event and UI_CLK = '1') then
+        ZIO_IN_R1 <= ZIO_IN;
+        ZIO_IN_R2 <= ZIO_IN_R1;
+        RZQ_IN_R1 <= RZQ_IN;
+        RZQ_IN_R2 <= RZQ_IN_R1;
+      end if;
+   end process;
+
+   IOBUF_RZQ : IOBUF
+      port map (
+         o   => RZQ_IN,
+         io  => RZQ_PIN,
+         i   => RZQ_OUT,
+         t   => RZQ_TOUT
+      );
+   
+   IODRP2_RZQ : IODRP2
+      port map (
+         dataout   => open,
+         dataout2  => open,
+         dout      => RZQ_OUT,
+         sdo       => RZQ_IODRP_SDO,
+         tout      => RZQ_TOUT,
+         add       => IODRP_ADD,
+         bkst      => IODRP_BKST,
+         clk       => UI_CLK,
+         cs        => RZQ_IODRP_CS,
+         idatain   => RZQ_IN,
+         ioclk0    => IOCLK,
+         ioclk1    => '1',
+         odatain   => RZQ_ZIO_ODATAIN,
+         sdi       => IODRP_SDI,
+         t         => RZQ_ZIO_TRISTATE
+      );
+   
+  
+   gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
+                 (SKIP_IN_TERM_CAL = 0)) generate
+
+      IOBUF_ZIO : IOBUF
+         port map (
+            o   => ZIO_IN,
+            io  => ZIO_PIN,
+            i   => ZIO_OUT,
+            t   => ZIO_TOUT
+         );
+      
+      IODRP2_ZIO : IODRP2
+         port map (
+            dataout   => open,
+            dataout2  => open,
+            dout      => ZIO_OUT,
+            sdo       => ZIO_IODRP_SDO,
+            tout      => ZIO_TOUT,
+            add       => IODRP_ADD,
+            bkst      => IODRP_BKST,
+            clk       => UI_CLK,
+            cs        => ZIO_IODRP_CS,
+            idatain   => ZIO_IN,
+            ioclk0    => IOCLK,
+            ioclk1    => '1',
+            odatain   => RZQ_ZIO_ODATAIN,
+            sdi       => IODRP_SDI,
+            t         => RZQ_ZIO_TRISTATE
+         );
+   end generate;         
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_infrastructure.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_infrastructure.vhd
new file mode 100644
index 0000000..6f5a97f
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_infrastructure.vhd
@@ -0,0 +1,334 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : 3.92
+--  \   \         Application        : MIG
+--  /   /         Filename           : memc3_infrastructure.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:56 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+--Device           : Spartan-6
+--Design Name      : DDR/DDR2/DDR3/LPDDR
+--Purpose          : Clock generation/distribution and reset synchronization
+--Reference        :
+--Revision History :
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+library unisim;
+use unisim.vcomponents.all;
+
+entity memc3_infrastructure is
+generic
+  (
+    C_INCLK_PERIOD     : integer := 2500;
+    C_RST_ACT_LOW      : integer := 1;
+    C_INPUT_CLK_TYPE   : string  := "DIFFERENTIAL";
+    C_CLKOUT0_DIVIDE   : integer := 1;
+    C_CLKOUT1_DIVIDE   : integer := 1;
+    C_CLKOUT2_DIVIDE   : integer := 16;
+    C_CLKOUT3_DIVIDE   : integer := 8;
+    C_CLKFBOUT_MULT   : integer := 2;
+    C_DIVCLK_DIVIDE   : integer := 1
+
+  );
+port
+(
+    sys_clk_p       : in std_logic;
+    sys_clk_n       : in std_logic;
+    sys_clk       : in std_logic;
+    sys_rst_i       : in std_logic;
+    clk0            : out std_logic;
+    rst0            : out std_logic;
+    async_rst       : out std_logic;
+    sysclk_2x       : out std_logic;
+    sysclk_2x_180   : out std_logic;
+    mcb_drp_clk     : out std_logic;
+    pll_ce_0        : out std_logic;
+    pll_ce_90       : out std_logic;
+    pll_lock        : out std_logic
+  
+);
+end entity;
+architecture syn of memc3_infrastructure is
+
+  -- # of clock cycles to delay deassertion of reset. Needs to be a fairly
+  -- high number not so much for metastability protection, but to give time
+  -- for reset (i.e. stable clock cycles) to propagate through all state
+  -- machines and to all control signals (i.e. not all control signals have
+  -- resets, instead they rely on base state logic being reset, and the effect
+  -- of that reset propagating through the logic). Need this because we may not
+  -- be getting stable clock cycles while reset asserted (i.e. since reset
+  -- depends on PLL/DCM lock status)
+
+  constant RST_SYNC_NUM   : integer := 25;
+  constant CLK_PERIOD_NS  : real := (real(C_INCLK_PERIOD)) / 1000.0;
+  constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
+
+
+  signal   clk_2x_0            : std_logic;
+  signal   clk_2x_180          : std_logic;
+  signal   clk0_bufg           : std_logic;
+  signal   clk0_bufg_in        : std_logic;
+  signal   mcb_drp_clk_bufg_in : std_logic;
+  signal   clkfbout_clkfbin    : std_logic;
+  signal   rst_tmp             : std_logic;
+  signal   sys_clk_ibufg       : std_logic;
+  signal   sys_rst             : std_logic;
+  signal   rst0_sync_r         : std_logic_vector(RST_SYNC_NUM-1 downto 0);
+  signal   powerup_pll_locked  : std_logic;
+  signal   syn_clk0_powerup_pll_locked : std_logic;
+  signal   locked              : std_logic;
+  signal   bufpll_mcb_locked   : std_logic;
+  signal   mcb_drp_clk_sig     : std_logic;
+
+  attribute max_fanout : string;
+  attribute syn_maxfan : integer;
+  attribute KEEP : string; 
+  attribute max_fanout of rst0_sync_r : signal is "10";
+  attribute syn_maxfan of rst0_sync_r : signal is 10;
+  attribute KEEP of sys_clk_ibufg     : signal is "TRUE";
+
+begin 
+
+  sys_rst  <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
+  clk0     <= clk0_bufg;
+  pll_lock <= bufpll_mcb_locked;
+  mcb_drp_clk <= mcb_drp_clk_sig;
+
+  diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate   
+      --***********************************************************************
+      -- Differential input clock input buffers
+      --***********************************************************************
+      u_ibufg_sys_clk : IBUFGDS
+        generic map (
+          DIFF_TERM => TRUE		    
+        )
+        port map (
+          I  => sys_clk_p,
+          IB => sys_clk_n,
+          O  => sys_clk_ibufg
+          );
+  end generate;   
+  
+  
+  se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate   
+      --***********************************************************************
+      -- SINGLE_ENDED input clock input buffers
+      --***********************************************************************
+      u_ibufg_sys_clk : IBUFG
+        port map (
+          I  => sys_clk,
+          O  => sys_clk_ibufg
+          );
+  end generate;   
+
+  --***************************************************************************
+  -- Global clock generation and distribution
+  --***************************************************************************
+
+    u_pll_adv : PLL_ADV 
+    generic map 
+        (
+         BANDWIDTH          => "OPTIMIZED",
+         CLKIN1_PERIOD      => CLK_PERIOD_NS,
+         CLKIN2_PERIOD      => CLK_PERIOD_NS,
+         CLKOUT0_DIVIDE     => C_CLKOUT0_DIVIDE,
+         CLKOUT1_DIVIDE     => C_CLKOUT1_DIVIDE,
+         CLKOUT2_DIVIDE     => C_CLKOUT2_DIVIDE,
+         CLKOUT3_DIVIDE     => C_CLKOUT3_DIVIDE,
+         CLKOUT4_DIVIDE     => 1,
+         CLKOUT5_DIVIDE     => 1,
+         CLKOUT0_PHASE      => 0.000,
+         CLKOUT1_PHASE      => 180.000,
+         CLKOUT2_PHASE      => 0.000,
+         CLKOUT3_PHASE      => 0.000,
+         CLKOUT4_PHASE      => 0.000,
+         CLKOUT5_PHASE      => 0.000,
+         CLKOUT0_DUTY_CYCLE => 0.500,
+         CLKOUT1_DUTY_CYCLE => 0.500,
+         CLKOUT2_DUTY_CYCLE => 0.500,
+         CLKOUT3_DUTY_CYCLE => 0.500,
+         CLKOUT4_DUTY_CYCLE => 0.500,
+         CLKOUT5_DUTY_CYCLE => 0.500,
+	 SIM_DEVICE         => "SPARTAN6",
+         COMPENSATION       => "INTERNAL",
+         DIVCLK_DIVIDE      => C_DIVCLK_DIVIDE,
+         CLKFBOUT_MULT      => C_CLKFBOUT_MULT,
+         CLKFBOUT_PHASE     => 0.0,
+         REF_JITTER         => 0.005000
+         )
+        port map
+          (
+           CLKFBIN          => clkfbout_clkfbin,
+           CLKINSEL         => '1',
+           CLKIN1           => sys_clk_ibufg,
+           CLKIN2           => '0',
+           DADDR            => (others => '0'),
+           DCLK             => '0',
+           DEN              => '0',
+           DI               => (others => '0'),
+           DWE              => '0',
+           REL              => '0',
+           RST              => sys_rst,
+           CLKFBDCM         => open,
+           CLKFBOUT         => clkfbout_clkfbin,
+           CLKOUTDCM0       => open,
+           CLKOUTDCM1       => open,
+           CLKOUTDCM2       => open,
+           CLKOUTDCM3       => open,
+           CLKOUTDCM4       => open,
+           CLKOUTDCM5       => open,
+           CLKOUT0          => clk_2x_0,
+           CLKOUT1          => clk_2x_180,
+           CLKOUT2          => clk0_bufg_in,
+           CLKOUT3          => mcb_drp_clk_bufg_in,
+           CLKOUT4          => open,
+           CLKOUT5          => open,
+           DO               => open,
+           DRDY             => open,
+           LOCKED           => locked
+           );
+
+    U_BUFG_CLK0 : BUFG
+    port map
+    (
+     O => clk0_bufg,
+     I => clk0_bufg_in
+     );
+
+   --U_BUFG_CLK1 : BUFG 
+   -- port map (  
+   --  O => mcb_drp_clk_sig,
+   --  I => mcb_drp_clk_bufg_in
+   --  );
+
+   U_BUFG_CLK1 : BUFGCE 
+    port map (  
+     O => mcb_drp_clk_sig,
+     I => mcb_drp_clk_bufg_in,
+     CE => locked
+     );
+
+   process (mcb_drp_clk_sig, sys_rst)
+   begin
+      if(sys_rst = '1') then
+         powerup_pll_locked <= '0';
+      elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
+         if (bufpll_mcb_locked = '1') then
+            powerup_pll_locked <= '1';
+         end if;
+      end if;
+   end process;      
+
+
+   process (clk0_bufg, sys_rst)
+   begin
+      if(sys_rst = '1') then
+         syn_clk0_powerup_pll_locked <= '0';
+      elsif (clk0_bufg'event and clk0_bufg = '1') then
+         if (bufpll_mcb_locked = '1') then
+            syn_clk0_powerup_pll_locked <= '1';
+         end if;
+      end if;
+   end process;      
+
+
+   --***************************************************************************
+   -- Reset synchronization
+   -- NOTES:
+   --   1. shut down the whole operation if the PLL hasn't yet locked (and
+   --      by inference, this means that external sys_rst has been asserted -
+   --      PLL deasserts LOCKED as soon as sys_rst asserted)
+   --   2. asynchronously assert reset. This was we can assert reset even if
+   --      there is no clock (needed for things like 3-stating output buffers).
+   --      reset deassertion is synchronous.
+   --   3. asynchronous reset only look at pll_lock from PLL during power up. After
+   --      power up and pll_lock is asserted, the powerup_pll_locked will be asserted
+   --      forever until sys_rst is asserted again. PLL will lose lock when FPGA 
+   --      enters suspend mode. We don't want reset to MCB get
+   --      asserted in the application that needs suspend feature.
+   --***************************************************************************
+
+
+  async_rst <= sys_rst or not(powerup_pll_locked);
+  -- async_rst <= rst_tmp;
+  rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
+  -- rst_tmp <= sys_rst or not(powerup_pll_locked);
+
+process (clk0_bufg, rst_tmp)
+  begin
+    if (rst_tmp = '1') then
+      rst0_sync_r <= (others => '1');
+    elsif (rising_edge(clk0_bufg)) then      
+      rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0';  -- logical left shift by one (pads with 0)
+    end if;
+  end process;
+
+  rst0    <= rst0_sync_r(RST_SYNC_NUM-1);
+
+
+BUFPLL_MCB_INST : BUFPLL_MCB
+port map
+( IOCLK0         => sysclk_2x,	
+  IOCLK1         => sysclk_2x_180, 
+  LOCKED         => locked,
+  GCLK           => mcb_drp_clk_sig,
+  SERDESSTROBE0  => pll_ce_0, 
+  SERDESSTROBE1  => pll_ce_90, 
+  PLLIN0         => clk_2x_0,  
+  PLLIN1         => clk_2x_180,
+  LOCK           => bufpll_mcb_locked 
+  );
+
+end architecture syn;
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_wrapper.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_wrapper.vhd
new file mode 100644
index 0000000..f0d77ea
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_wrapper.vhd
@@ -0,0 +1,1013 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : 3.92
+--  \   \         Application        : MIG
+--  /   /         Filename           : memc3_wrapper.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:57 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+--Device           : Spartan-6
+--Design Name      : DDR/DDR2/DDR3/LPDDR
+--Purpose          : This module instantiates mcb_raw_wrapper module.
+--Reference        :
+--Revision History :
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity memc3_wrapper is
+generic (
+
+      C_MEMCLK_PERIOD             : integer := 2500;
+      C_P0_MASK_SIZE              : integer := 4;
+      C_P0_DATA_PORT_SIZE         : integer := 32;
+      C_P1_MASK_SIZE              : integer := 4;
+      C_P1_DATA_PORT_SIZE         : integer := 32;
+
+      C_ARB_NUM_TIME_SLOTS        : integer := 12;
+      C_ARB_TIME_SLOT_0           : bit_vector := "000";
+      C_ARB_TIME_SLOT_1           : bit_vector := "000";
+      C_ARB_TIME_SLOT_2           : bit_vector := "000";
+      C_ARB_TIME_SLOT_3           : bit_vector := "000";
+      C_ARB_TIME_SLOT_4           : bit_vector := "000";
+      C_ARB_TIME_SLOT_5           : bit_vector := "000";
+      C_ARB_TIME_SLOT_6           : bit_vector := "000";
+      C_ARB_TIME_SLOT_7           : bit_vector := "000";
+      C_ARB_TIME_SLOT_8           : bit_vector := "000";
+      C_ARB_TIME_SLOT_9           : bit_vector := "000";
+      C_ARB_TIME_SLOT_10          : bit_vector := "000";
+      C_ARB_TIME_SLOT_11          : bit_vector := "000";
+
+      C_MEM_TRAS               : integer := 45000;
+      C_MEM_TRCD               : integer := 12500;
+      C_MEM_TREFI              : integer := 7800000;
+      C_MEM_TRFC               : integer := 127500;
+      C_MEM_TRP                : integer := 12500;
+      C_MEM_TWR                : integer := 15000;
+      C_MEM_TRTP               : integer := 7500;
+      C_MEM_TWTR               : integer := 7500;
+
+      C_MEM_ADDR_ORDER         : string :="ROW_BANK_COLUMN";
+      C_MEM_TYPE               : string :="DDR2";
+      C_MEM_DENSITY            : string :="1Gb";
+      C_NUM_DQ_PINS            : integer := 4;
+      C_MEM_BURST_LEN          : integer := 8;
+      C_MEM_CAS_LATENCY        : integer := 5;
+      C_MEM_ADDR_WIDTH         : integer := 14;
+      C_MEM_BANKADDR_WIDTH     : integer := 3;
+      C_MEM_NUM_COL_BITS       : integer := 11;
+
+      C_MEM_DDR1_2_ODS          : string := "FULL";
+      C_MEM_DDR2_RTT            : string := "50OHMS";
+      C_MEM_DDR2_DIFF_DQS_EN    : string := "YES";
+      C_MEM_DDR2_3_PA_SR        : string := "FULL";
+      C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
+
+      C_MEM_DDR3_CAS_LATENCY    : integer:= 7;
+      C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
+      C_MEM_DDR3_ODS            : string := "DIV6";
+      C_MEM_DDR3_RTT            : string := "DIV2";
+      C_MEM_DDR3_AUTO_SR        : string := "ENABLED";
+      C_MEM_DDR3_DYN_WRT_ODT    : string := "OFF";
+      C_MEM_MOBILE_PA_SR        : string := "FULL";
+      C_MEM_MDDR_ODS            : string := "FULL";
+      C_MC_CALIB_BYPASS         : string := "NO";
+      C_LDQSP_TAP_DELAY_VAL		: integer := 0;
+      C_UDQSP_TAP_DELAY_VAL		: integer := 0;
+      C_LDQSN_TAP_DELAY_VAL		: integer := 0;
+      C_UDQSN_TAP_DELAY_VAL		: integer := 0;
+      C_DQ0_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ1_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ2_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ3_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ4_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ5_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ6_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ7_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ8_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ9_TAP_DELAY_VAL                 : integer := 0;  
+      C_DQ10_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ11_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ12_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ13_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ14_TAP_DELAY_VAL                : integer := 0;  
+      C_DQ15_TAP_DELAY_VAL                : integer := 0;  
+
+
+      C_SKIP_IN_TERM_CAL                 : integer := 0;  
+      C_SKIP_DYNAMIC_CAL                 : integer := 0;  
+
+      C_SIMULATION              : string  := "FALSE";  
+      C_MC_CALIBRATION_MODE     : string := "CALIBRATION";
+      C_MC_CALIBRATION_DELAY    : string := "QUARTER";
+      C_CALIB_SOFT_IP           : string := "TRUE"
+
+
+      );
+    port
+    (
+
+      -- high-speed PLL clock interface
+      sysclk_2x       : in std_logic;
+      sysclk_2x_180   : in std_logic;
+      pll_ce_0        : in std_logic;
+      pll_ce_90       : in std_logic;
+      pll_lock        : in std_logic;
+      async_rst       : in std_logic;
+
+      --User Port0 Interface Signals
+
+      p0_cmd_clk                            : in std_logic;
+      p0_cmd_en                             : in std_logic;
+      p0_cmd_instr                          : in std_logic_vector(2 downto 0) ;
+      p0_cmd_bl                             : in std_logic_vector(5 downto 0) ;
+      p0_cmd_byte_addr                      : in std_logic_vector(29 downto 0) ;
+      p0_cmd_empty                          : out std_logic;
+      p0_cmd_full                           : out std_logic;
+
+      -- Data Wr Port signals
+      p0_wr_clk                             : in std_logic;
+      p0_wr_en                              : in std_logic;
+      p0_wr_mask                            : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
+      p0_wr_data                            : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
+      p0_wr_full                            : out std_logic;
+      p0_wr_empty                           : out std_logic;
+      p0_wr_count                           : out std_logic_vector(6 downto 0) ;
+      p0_wr_underrun                        : out std_logic;
+      p0_wr_error                           : out std_logic;
+
+      --Data Rd Port signals
+      p0_rd_clk                             : in std_logic;
+      p0_rd_en                              : in std_logic;
+      p0_rd_data                            : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
+      p0_rd_full                            : out std_logic;
+      p0_rd_empty                           : out std_logic;
+      p0_rd_count                           : out std_logic_vector(6 downto 0) ;
+      p0_rd_overflow                        : out std_logic;
+      p0_rd_error                           : out std_logic;
+
+      --User Port1 Interface Signals
+
+      p1_cmd_clk                            : in std_logic;
+      p1_cmd_en                             : in std_logic;
+      p1_cmd_instr                          : in std_logic_vector(2 downto 0) ;
+      p1_cmd_bl                             : in std_logic_vector(5 downto 0) ;
+      p1_cmd_byte_addr                      : in std_logic_vector(29 downto 0) ;
+      p1_cmd_empty                          : out std_logic;
+      p1_cmd_full                           : out std_logic;
+
+      -- Data Wr Port signals
+      p1_wr_clk                             : in std_logic;
+      p1_wr_en                              : in std_logic;
+      p1_wr_mask                            : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
+      p1_wr_data                            : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
+      p1_wr_full                            : out std_logic;
+      p1_wr_empty                           : out std_logic;
+      p1_wr_count                           : out std_logic_vector(6 downto 0) ;
+      p1_wr_underrun                        : out std_logic;
+      p1_wr_error                           : out std_logic;
+
+      --Data Rd Port signals
+      p1_rd_clk                             : in std_logic;
+      p1_rd_en                              : in std_logic;
+      p1_rd_data                            : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
+      p1_rd_full                            : out std_logic;
+      p1_rd_empty                           : out std_logic;
+      p1_rd_count                           : out std_logic_vector(6 downto 0) ;
+      p1_rd_overflow                        : out std_logic;
+      p1_rd_error                           : out std_logic;
+
+      --User Port2 Interface Signals
+
+      p2_cmd_clk                            : in std_logic;
+      p2_cmd_en                             : in std_logic;
+      p2_cmd_instr                          : in std_logic_vector(2 downto 0) ;
+      p2_cmd_bl                             : in std_logic_vector(5 downto 0) ;
+      p2_cmd_byte_addr                      : in std_logic_vector(29 downto 0) ;
+      p2_cmd_empty                          : out std_logic;
+      p2_cmd_full                           : out std_logic;
+
+      -- Data Wr Port signals
+      p2_wr_clk                             : in std_logic;
+      p2_wr_en                              : in std_logic;
+      p2_wr_mask                            : in std_logic_vector(3 downto 0) ;
+      p2_wr_data                            : in std_logic_vector(31 downto 0) ;
+      p2_wr_full                            : out std_logic;
+      p2_wr_empty                           : out std_logic;
+      p2_wr_count                           : out std_logic_vector(6 downto 0) ;
+      p2_wr_underrun                        : out std_logic;
+      p2_wr_error                           : out std_logic;
+
+      --Data Rd Port signals
+      p2_rd_clk                             : in std_logic;
+      p2_rd_en                              : in std_logic;
+      p2_rd_data                            : out std_logic_vector(31 downto 0) ;
+      p2_rd_full                            : out std_logic;
+      p2_rd_empty                           : out std_logic;
+      p2_rd_count                           : out std_logic_vector(6 downto 0) ;
+      p2_rd_overflow                        : out std_logic;
+      p2_rd_error                           : out std_logic;
+
+      --User Port3 Interface Signals
+
+      p3_cmd_clk                            : in std_logic;
+      p3_cmd_en                             : in std_logic;
+      p3_cmd_instr                          : in std_logic_vector(2 downto 0) ;
+      p3_cmd_bl                             : in std_logic_vector(5 downto 0) ;
+      p3_cmd_byte_addr                      : in std_logic_vector(29 downto 0) ;
+      p3_cmd_empty                          : out std_logic;
+      p3_cmd_full                           : out std_logic;
+
+      -- Data Wr Port signals
+      p3_wr_clk                             : in std_logic;
+      p3_wr_en                              : in std_logic;
+      p3_wr_mask                            : in std_logic_vector(3 downto 0) ;
+      p3_wr_data                            : in std_logic_vector(31 downto 0) ;
+      p3_wr_full                            : out std_logic;
+      p3_wr_empty                           : out std_logic;
+      p3_wr_count                           : out std_logic_vector(6 downto 0) ;
+      p3_wr_underrun                        : out std_logic;
+      p3_wr_error                           : out std_logic;
+
+      --Data Rd Port signals
+      p3_rd_clk                             : in std_logic;
+      p3_rd_en                              : in std_logic;
+      p3_rd_data                            : out std_logic_vector(31 downto 0) ;
+      p3_rd_full                            : out std_logic;
+      p3_rd_empty                           : out std_logic;
+      p3_rd_count                           : out std_logic_vector(6 downto 0) ;
+      p3_rd_overflow                        : out std_logic;
+      p3_rd_error                           : out std_logic;
+
+
+
+      -- memory interface signals
+      mcb3_dram_ck          : out std_logic;
+      mcb3_dram_ck_n        : out std_logic;
+      mcb3_dram_a           : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
+      mcb3_dram_ba          : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
+      mcb3_dram_ras_n       : out std_logic;
+      mcb3_dram_cas_n       : out std_logic;
+      mcb3_dram_we_n        : out std_logic;
+      mcb3_dram_odt         : out std_logic;
+--      mcb3_dram_odt         : out std_logic;
+      mcb3_dram_cke         : out std_logic;
+      mcb3_dram_dq          : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
+      mcb3_dram_dqs         : inout std_logic;
+ mcb3_dram_dqs_n : inout std_logic;
+
+
+mcb3_dram_udqs   : inout std_logic;
+mcb3_dram_udm    : out std_logic; 
+
+
+ mcb3_dram_udqs_n : inout std_logic;
+
+
+
+mcb3_dram_dm : out std_logic;
+
+      mcb3_rzq                             : inout std_logic;
+      mcb3_zio                              : inout std_logic;
+
+      -- Calibration signals
+      mcb_drp_clk            : in std_logic;
+      calib_done           : out std_logic;
+      selfrefresh_enter    : in std_logic;
+      selfrefresh_mode     : out std_logic
+
+    );
+end entity;
+architecture acch of memc3_wrapper is
+component mcb_raw_wrapper IS
+   GENERIC (
+
+      C_MEMCLK_PERIOD                  : integer;
+      C_PORT_ENABLE                    : std_logic_vector(5 downto 0);
+      C_MEM_ADDR_ORDER                 : string;
+      C_ARB_NUM_TIME_SLOTS             : integer;
+      C_ARB_TIME_SLOT_0                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_1                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_2                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_3                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_4                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_5                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_6                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_7                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_8                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_9                : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_10               : bit_vector(17 downto 0);
+      C_ARB_TIME_SLOT_11               : bit_vector(17 downto 0);
+      C_PORT_CONFIG                    : string;
+
+
+      C_MEM_TRAS                       : integer;
+      C_MEM_TRCD                       : integer;
+      C_MEM_TREFI                      : integer;
+      C_MEM_TRFC                       : integer;
+      C_MEM_TRP                        : integer;
+      C_MEM_TWR                        : integer;
+      C_MEM_TRTP                       : integer;
+      C_MEM_TWTR                       : integer;
+
+      C_NUM_DQ_PINS                    : integer;
+      C_MEM_TYPE                       : string;
+      C_MEM_DENSITY                    : string;
+      C_MEM_BURST_LEN                  : integer;
+
+      C_MEM_CAS_LATENCY                : integer;
+      C_MEM_ADDR_WIDTH                 : integer;
+      C_MEM_BANKADDR_WIDTH             : integer;
+      C_MEM_NUM_COL_BITS               : integer;
+
+      C_MEM_DDR3_CAS_LATENCY           : integer;
+      C_MEM_MOBILE_PA_SR               : string;
+      C_MEM_DDR1_2_ODS                 : string;
+      C_MEM_DDR3_ODS                   : string;
+      C_MEM_DDR2_RTT                   : string;
+      C_MEM_DDR3_RTT                   : string;
+      C_MEM_MDDR_ODS                   : string;
+
+      C_MEM_DDR2_DIFF_DQS_EN           : string;
+      C_MEM_DDR2_3_PA_SR               : string;
+      C_MEM_DDR3_CAS_WR_LATENCY        : integer;
+
+      C_MEM_DDR3_AUTO_SR               : string;
+      C_MEM_DDR2_3_HIGH_TEMP_SR        : string;
+      C_MEM_DDR3_DYN_WRT_ODT           : string;
+
+      C_MC_CALIB_BYPASS                : string;
+      C_MC_CALIBRATION_RA              : bit_vector(15 DOWNTO 0);
+      C_MC_CALIBRATION_BA              : bit_vector(2 DOWNTO 0);
+      C_CALIB_SOFT_IP                  : string;
+      C_MC_CALIBRATION_CA              : bit_vector(11 DOWNTO 0);
+      C_MC_CALIBRATION_CLK_DIV         : integer;
+      C_MC_CALIBRATION_MODE            : string;
+      C_MC_CALIBRATION_DELAY           : string;
+
+     LDQSP_TAP_DELAY_VAL		: integer;
+     UDQSP_TAP_DELAY_VAL		: integer;
+     LDQSN_TAP_DELAY_VAL		: integer;
+     UDQSN_TAP_DELAY_VAL		: integer;
+     DQ0_TAP_DELAY_VAL                  : integer;  
+     DQ1_TAP_DELAY_VAL                  : integer;  
+     DQ2_TAP_DELAY_VAL                  : integer;  
+     DQ3_TAP_DELAY_VAL                  : integer;  
+     DQ4_TAP_DELAY_VAL                  : integer;  
+     DQ5_TAP_DELAY_VAL                  : integer;  
+     DQ6_TAP_DELAY_VAL                  : integer;  
+     DQ7_TAP_DELAY_VAL                  : integer;  
+     DQ8_TAP_DELAY_VAL                  : integer;  
+     DQ9_TAP_DELAY_VAL                  : integer;  
+     DQ10_TAP_DELAY_VAL                  : integer;  
+     DQ11_TAP_DELAY_VAL                  : integer;  
+     DQ12_TAP_DELAY_VAL                  : integer;  
+     DQ13_TAP_DELAY_VAL                  : integer;  
+     DQ14_TAP_DELAY_VAL                  : integer;  
+     DQ15_TAP_DELAY_VAL                  : integer;  
+
+      C_P0_MASK_SIZE                   : integer;
+      C_P0_DATA_PORT_SIZE              : integer;
+      C_P1_MASK_SIZE                   : integer;
+      C_P1_DATA_PORT_SIZE              : integer;
+
+      C_SIMULATION                       : string ;  
+      C_SKIP_IN_TERM_CAL                 : integer; 
+      C_SKIP_DYNAMIC_CAL                 : integer; 
+      C_SKIP_DYN_IN_TERM                 : integer; 
+
+      C_MEM_TZQINIT_MAXCNT              : std_logic_vector(9 downto 0)
+   );
+   PORT (
+      -- HIGH-SPEED PLL clock interface
+
+      sysclk_2x                        : in std_logic;
+      sysclk_2x_180                    : in std_logic;
+      pll_ce_0                         : in std_logic;
+      pll_ce_90                        : in std_logic;
+      pll_lock                         : in std_logic;
+      sys_rst                          : in std_logic;
+
+      p0_arb_en                        : in std_logic;
+      p0_cmd_clk                       : in std_logic;
+      p0_cmd_en                        : in std_logic;
+      p0_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p0_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p0_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p0_cmd_empty                     : out std_logic;
+      p0_cmd_full                      : out std_logic;
+      p0_wr_clk                        : in std_logic;
+      p0_wr_en                         : in std_logic;
+      p0_wr_mask                       : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
+      p0_wr_data                       : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
+      p0_wr_full                       : out std_logic;
+      p0_wr_empty                      : out std_logic;
+      p0_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p0_wr_underrun                   : out std_logic;
+      p0_wr_error                      : out std_logic;
+      p0_rd_clk                        : in std_logic;
+      p0_rd_en                         : in std_logic;
+      p0_rd_data                       : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
+      p0_rd_full                       : out std_logic;
+      p0_rd_empty                      : out std_logic;
+      p0_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p0_rd_overflow                   : out std_logic;
+      p0_rd_error                      : out std_logic;
+      p1_arb_en                        : in std_logic;
+      p1_cmd_clk                       : in std_logic;
+      p1_cmd_en                        : in std_logic;
+      p1_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p1_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p1_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p1_cmd_empty                     : out std_logic;
+      p1_cmd_full                      : out std_logic;
+      p1_wr_clk                        : in std_logic;
+      p1_wr_en                         : in std_logic;
+      p1_wr_mask                       : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
+      p1_wr_data                       : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
+      p1_wr_full                       : out std_logic;
+      p1_wr_empty                      : out std_logic;
+      p1_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p1_wr_underrun                   : out std_logic;
+      p1_wr_error                      : out std_logic;
+      p1_rd_clk                        : in std_logic;
+      p1_rd_en                         : in std_logic;
+      p1_rd_data                       : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
+      p1_rd_full                       : out std_logic;
+      p1_rd_empty                      : out std_logic;
+      p1_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p1_rd_overflow                   : out std_logic;
+      p1_rd_error                      : out std_logic;
+      p2_arb_en                        : in std_logic;
+      p2_cmd_clk                       : in std_logic;
+      p2_cmd_en                        : in std_logic;
+      p2_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p2_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p2_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p2_cmd_empty                     : out std_logic;
+      p2_cmd_full                      : out std_logic;
+      p2_wr_clk                        : in std_logic;
+      p2_wr_en                         : in std_logic;
+      p2_wr_mask                       : in std_logic_vector(3 DOWNTO 0);
+      p2_wr_data                       : in std_logic_vector(31 DOWNTO 0);
+      p2_wr_full                       : out std_logic;
+      p2_wr_empty                      : out std_logic;
+      p2_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p2_wr_underrun                   : out std_logic;
+      p2_wr_error                      : out std_logic;
+      p2_rd_clk                        : in std_logic;
+      p2_rd_en                         : in std_logic;
+      p2_rd_data                       : out std_logic_vector(31 DOWNTO 0);
+      p2_rd_full                       : out std_logic;
+      p2_rd_empty                      : out std_logic;
+      p2_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p2_rd_overflow                   : out std_logic;
+      p2_rd_error                      : out std_logic;
+      p3_arb_en                        : in std_logic;
+      p3_cmd_clk                       : in std_logic;
+      p3_cmd_en                        : in std_logic;
+      p3_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p3_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p3_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p3_cmd_empty                     : out std_logic;
+      p3_cmd_full                      : out std_logic;
+      p3_wr_clk                        : in std_logic;
+      p3_wr_en                         : in std_logic;
+      p3_wr_mask                       : in std_logic_vector(3 DOWNTO 0);
+      p3_wr_data                       : in std_logic_vector(31 DOWNTO 0);
+      p3_wr_full                       : out std_logic;
+      p3_wr_empty                      : out std_logic;
+      p3_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p3_wr_underrun                   : out std_logic;
+      p3_wr_error                      : out std_logic;
+      p3_rd_clk                        : in std_logic;
+      p3_rd_en                         : in std_logic;
+      p3_rd_data                       : out std_logic_vector(31 DOWNTO 0);
+      p3_rd_full                       : out std_logic;
+      p3_rd_empty                      : out std_logic;
+      p3_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p3_rd_overflow                   : out std_logic;
+      p3_rd_error                      : out std_logic;
+      p4_arb_en                        : in std_logic;
+      p4_cmd_clk                       : in std_logic;
+      p4_cmd_en                        : in std_logic;
+      p4_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p4_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p4_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p4_cmd_empty                     : out std_logic;
+      p4_cmd_full                      : out std_logic;
+      p4_wr_clk                        : in std_logic;
+      p4_wr_en                         : in std_logic;
+      p4_wr_mask                       : in std_logic_vector(3 DOWNTO 0);
+      p4_wr_data                       : in std_logic_vector(31 DOWNTO 0);
+      p4_wr_full                       : out std_logic;
+      p4_wr_empty                      : out std_logic;
+      p4_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p4_wr_underrun                   : out std_logic;
+      p4_wr_error                      : out std_logic;
+      p4_rd_clk                        : in std_logic;
+      p4_rd_en                         : in std_logic;
+      p4_rd_data                       : out std_logic_vector(31 DOWNTO 0);
+      p4_rd_full                       : out std_logic;
+      p4_rd_empty                      : out std_logic;
+      p4_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p4_rd_overflow                   : out std_logic;
+      p4_rd_error                      : out std_logic;
+      p5_arb_en                        : in std_logic;
+      p5_cmd_clk                       : in std_logic;
+      p5_cmd_en                        : in std_logic;
+      p5_cmd_instr                     : in std_logic_vector(2 DOWNTO 0);
+      p5_cmd_bl                        : in std_logic_vector(5 DOWNTO 0);
+      p5_cmd_byte_addr                 : in std_logic_vector(29 DOWNTO 0);
+      p5_cmd_empty                     : out std_logic;
+      p5_cmd_full                      : out std_logic;
+      p5_wr_clk                        : in std_logic;
+      p5_wr_en                         : in std_logic;
+      p5_wr_mask                       : in std_logic_vector(3 DOWNTO 0);
+      p5_wr_data                       : in std_logic_vector(31 DOWNTO 0);
+      p5_wr_full                       : out std_logic;
+      p5_wr_empty                      : out std_logic;
+      p5_wr_count                      : out std_logic_vector(6 DOWNTO 0);
+      p5_wr_underrun                   : out std_logic;
+      p5_wr_error                      : out std_logic;
+      p5_rd_clk                        : in std_logic;
+      p5_rd_en                         : in std_logic;
+      p5_rd_data                       : out std_logic_vector(31 DOWNTO 0);
+      p5_rd_full                       : out std_logic;
+      p5_rd_empty                      : out std_logic;
+      p5_rd_count                      : out std_logic_vector(6 DOWNTO 0);
+      p5_rd_overflow                   : out std_logic;
+      p5_rd_error                      : out std_logic;
+
+      mcbx_dram_addr                   : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
+      mcbx_dram_ba                     : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
+      mcbx_dram_ras_n                  : out std_logic;
+      mcbx_dram_cas_n                  : out std_logic;
+      mcbx_dram_we_n                   : out std_logic;
+      mcbx_dram_cke                    : out std_logic;
+      mcbx_dram_clk                    : out std_logic;
+      mcbx_dram_clk_n                  : out std_logic;
+      mcbx_dram_dq                     : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
+      mcbx_dram_dqs                    : inout std_logic;
+      mcbx_dram_dqs_n                  : inout std_logic;
+      mcbx_dram_udqs                   : inout std_logic;
+      mcbx_dram_udqs_n                 : inout std_logic;
+      mcbx_dram_udm                    : out std_logic;
+      mcbx_dram_ldm                    : out std_logic;
+      mcbx_dram_odt                    : out std_logic;
+      mcbx_dram_ddr3_rst               : out std_logic;
+      calib_recal                      : in std_logic;
+      rzq                              : inout std_logic;
+      zio                              : inout std_logic;
+      ui_read                          : in std_logic;
+      ui_add                           : in std_logic;
+      ui_cs                            : in std_logic;
+      ui_clk                           : in std_logic;
+      ui_sdi                           : in std_logic;
+      ui_addr                          : in std_logic_vector(4 DOWNTO 0);
+      ui_broadcast                     : in std_logic;
+      ui_drp_update                    : in std_logic;
+      ui_done_cal                      : in std_logic;
+      ui_cmd                           : in std_logic;
+      ui_cmd_in                        : in std_logic;
+      ui_cmd_en                        : in std_logic;
+      ui_dqcount                       : in std_logic_vector(3 DOWNTO 0);
+      ui_dq_lower_dec                  : in std_logic;
+      ui_dq_lower_inc                  : in std_logic;
+      ui_dq_upper_dec                  : in std_logic;
+      ui_dq_upper_inc                  : in std_logic;
+      ui_udqs_inc                      : in std_logic;
+      ui_udqs_dec                      : in std_logic;
+      ui_ldqs_inc                      : in std_logic;
+      ui_ldqs_dec                      : in std_logic;
+      uo_data                          : out std_logic_vector(7 DOWNTO 0);
+      uo_data_valid                    : out std_logic;
+      uo_done_cal                      : out std_logic;
+      uo_cmd_ready_in                  : out std_logic;
+      uo_refrsh_flag                   : out std_logic;
+      uo_cal_start                     : out std_logic;
+      uo_sdo                           : out std_logic;
+      status                           : out std_logic_vector(31 DOWNTO 0);
+      selfrefresh_enter                : in std_logic;
+      selfrefresh_mode                 : out std_logic
+   );
+end component;
+
+signal uo_data : std_logic_vector(7 downto 0);
+
+ constant C_PORT_ENABLE              : std_logic_vector(5 downto 0) := "001111";
+
+constant C_PORT_CONFIG             : string :=  "B32_B32_B32_B32";
+
+
+constant ARB_TIME_SLOT_0    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_0(11 downto 9) & C_ARB_TIME_SLOT_0(8 downto 6) & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
+constant ARB_TIME_SLOT_1    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_1(11 downto 9) & C_ARB_TIME_SLOT_1(8 downto 6) & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
+constant ARB_TIME_SLOT_2    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_2(11 downto 9) & C_ARB_TIME_SLOT_2(8 downto 6) & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
+constant ARB_TIME_SLOT_3    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_3(11 downto 9) & C_ARB_TIME_SLOT_3(8 downto 6) & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
+constant ARB_TIME_SLOT_4    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_4(11 downto 9) & C_ARB_TIME_SLOT_4(8 downto 6) & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
+constant ARB_TIME_SLOT_5    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_5(11 downto 9) & C_ARB_TIME_SLOT_5(8 downto 6) & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
+constant ARB_TIME_SLOT_6    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_6(11 downto 9) & C_ARB_TIME_SLOT_6(8 downto 6) & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
+constant ARB_TIME_SLOT_7    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_7(11 downto 9) & C_ARB_TIME_SLOT_7(8 downto 6) & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
+constant ARB_TIME_SLOT_8    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_8(11 downto 9) & C_ARB_TIME_SLOT_8(8 downto 6) & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
+constant ARB_TIME_SLOT_9    : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_9(11 downto 9) & C_ARB_TIME_SLOT_9(8 downto 6) & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
+constant ARB_TIME_SLOT_10   : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_10(11 downto 9) & C_ARB_TIME_SLOT_10(8 downto 6) & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
+constant ARB_TIME_SLOT_11   : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_11(11 downto 9) & C_ARB_TIME_SLOT_11(8 downto 6) & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
+
+
+constant C_MC_CALIBRATION_CLK_DIV  : integer  := 1;
+constant C_MEM_TZQINIT_MAXCNT  : std_logic_vector(9 downto 0) := "1000000000" + "0000010000";   -- 16 cycles are added to avoid trfc violations
+constant C_SKIP_DYN_IN_TERM : integer := 1;	  
+
+constant C_MC_CALIBRATION_RA    : bit_vector(15 downto 0) := X"0000"; 
+constant C_MC_CALIBRATION_BA    : bit_vector(2 downto 0) := o"0"; 
+constant C_MC_CALIBRATION_CA    : bit_vector(11 downto 0) := X"000"; 
+
+signal status          : std_logic_vector(31 downto 0);
+signal uo_data_valid   : std_logic;
+signal uo_cmd_ready_in : std_logic;
+signal uo_refrsh_flag  : std_logic;
+signal uo_cal_start    : std_logic;
+signal uo_sdo          : std_logic;
+
+
+
+
+
+
+
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of acch : architecture IS
+  "mig_v3_92_ddr2_s6, Coregen 14.2";
+
+attribute CORE_GENERATION_INFO : string;
+attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr2_s6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE,  NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR2_SDRAM, CLK_PERIOD=3000, MEMORY_PART=mt47h64m16xx-25e, MEMORY_DEVICE_WIDTH=16, OUTPUT_DRV=FULL, RTT_NOM=50OHMS, DQS#_ENABLE=YES, HIGH_TEMP_SR=NORMAL, PORT_CONFIG=Four 32-bit bi-directional ports, MEM_ADDR_ORDER=BANK_ROW_COLUMN, PORT_ENABLE=Port0_Port1_Port2_Port3, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=CALIB_TERM, DATA_TERMINATION=25 Ohms, CLKFBOUT_MULT_F=2, CLKOUT_DIVIDE=1, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
+
+begin
+
+
+memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
+generic map
+ (
+   C_MEMCLK_PERIOD            => C_MEMCLK_PERIOD,
+   C_P0_MASK_SIZE             => C_P0_MASK_SIZE,
+   C_P0_DATA_PORT_SIZE        => C_P0_DATA_PORT_SIZE,
+   C_P1_MASK_SIZE             => C_P1_MASK_SIZE,
+   C_P1_DATA_PORT_SIZE        => C_P1_DATA_PORT_SIZE,
+
+   C_ARB_NUM_TIME_SLOTS       => C_ARB_NUM_TIME_SLOTS,
+   C_ARB_TIME_SLOT_0          => ARB_TIME_SLOT_0,
+   C_ARB_TIME_SLOT_1          => ARB_TIME_SLOT_1,
+   C_ARB_TIME_SLOT_2          => ARB_TIME_SLOT_2,
+   C_ARB_TIME_SLOT_3          => ARB_TIME_SLOT_3,
+   C_ARB_TIME_SLOT_4          => ARB_TIME_SLOT_4,
+   C_ARB_TIME_SLOT_5          => ARB_TIME_SLOT_5,
+   C_ARB_TIME_SLOT_6          => ARB_TIME_SLOT_6,
+   C_ARB_TIME_SLOT_7          => ARB_TIME_SLOT_7,
+   C_ARB_TIME_SLOT_8          => ARB_TIME_SLOT_8,
+   C_ARB_TIME_SLOT_9          => ARB_TIME_SLOT_9,
+   C_ARB_TIME_SLOT_10         => ARB_TIME_SLOT_10,
+   C_ARB_TIME_SLOT_11         => ARB_TIME_SLOT_11,
+
+   C_PORT_CONFIG              => C_PORT_CONFIG,
+   C_PORT_ENABLE              => C_PORT_ENABLE,
+
+   C_MEM_TRAS                 => C_MEM_TRAS,
+   C_MEM_TRCD                 => C_MEM_TRCD,
+   C_MEM_TREFI                => C_MEM_TREFI,
+   C_MEM_TRFC                 => C_MEM_TRFC,
+   C_MEM_TRP                  => C_MEM_TRP,
+   C_MEM_TWR                  => C_MEM_TWR,
+   C_MEM_TRTP                 => C_MEM_TRTP,
+   C_MEM_TWTR                 => C_MEM_TWTR,
+
+   C_MEM_ADDR_ORDER           => C_MEM_ADDR_ORDER,
+   C_NUM_DQ_PINS              => C_NUM_DQ_PINS,
+   C_MEM_TYPE                 => C_MEM_TYPE,
+   C_MEM_DENSITY              => C_MEM_DENSITY,
+   C_MEM_BURST_LEN            => C_MEM_BURST_LEN,
+   C_MEM_CAS_LATENCY          => C_MEM_CAS_LATENCY,
+   C_MEM_ADDR_WIDTH           => C_MEM_ADDR_WIDTH,
+   C_MEM_BANKADDR_WIDTH       => C_MEM_BANKADDR_WIDTH,
+   C_MEM_NUM_COL_BITS         => C_MEM_NUM_COL_BITS,
+
+   C_MEM_DDR1_2_ODS           => C_MEM_DDR1_2_ODS,
+   C_MEM_DDR2_RTT             => C_MEM_DDR2_RTT,
+   C_MEM_DDR2_DIFF_DQS_EN     => C_MEM_DDR2_DIFF_DQS_EN,
+   C_MEM_DDR2_3_PA_SR         => C_MEM_DDR2_3_PA_SR,
+   C_MEM_DDR2_3_HIGH_TEMP_SR  => C_MEM_DDR2_3_HIGH_TEMP_SR,
+
+   C_MEM_DDR3_CAS_LATENCY     => C_MEM_DDR3_CAS_LATENCY,
+   C_MEM_DDR3_ODS             => C_MEM_DDR3_ODS,
+   C_MEM_DDR3_RTT             => C_MEM_DDR3_RTT,
+   C_MEM_DDR3_CAS_WR_LATENCY  => C_MEM_DDR3_CAS_WR_LATENCY,
+   C_MEM_DDR3_AUTO_SR         => C_MEM_DDR3_AUTO_SR,
+   C_MEM_DDR3_DYN_WRT_ODT     => C_MEM_DDR3_DYN_WRT_ODT,
+   C_MEM_MOBILE_PA_SR         => C_MEM_MOBILE_PA_SR,
+   C_MEM_MDDR_ODS             => C_MEM_MDDR_ODS,
+   C_MC_CALIBRATION_CLK_DIV   => C_MC_CALIBRATION_CLK_DIV,
+   C_MC_CALIBRATION_MODE      => C_MC_CALIBRATION_MODE,
+   C_MC_CALIBRATION_DELAY     => C_MC_CALIBRATION_DELAY,
+
+   C_MC_CALIB_BYPASS          => C_MC_CALIB_BYPASS,
+   C_MC_CALIBRATION_RA        => C_MC_CALIBRATION_RA,
+   C_MC_CALIBRATION_BA        => C_MC_CALIBRATION_BA,
+   C_MC_CALIBRATION_CA        => C_MC_CALIBRATION_CA,
+   C_CALIB_SOFT_IP            => C_CALIB_SOFT_IP,
+
+   C_SIMULATION               => C_SIMULATION,
+   C_SKIP_IN_TERM_CAL         => C_SKIP_IN_TERM_CAL,
+   C_SKIP_DYNAMIC_CAL         => C_SKIP_DYNAMIC_CAL,
+   C_SKIP_DYN_IN_TERM         => C_SKIP_DYN_IN_TERM, 
+   C_MEM_TZQINIT_MAXCNT       => C_MEM_TZQINIT_MAXCNT,
+
+   LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,  
+   UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,  
+   LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,  
+   UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,  
+   DQ0_TAP_DELAY_VAL   => C_DQ0_TAP_DELAY_VAL, 
+   DQ1_TAP_DELAY_VAL  => C_DQ1_TAP_DELAY_VAL,  
+   DQ2_TAP_DELAY_VAL  => C_DQ2_TAP_DELAY_VAL,  
+   DQ3_TAP_DELAY_VAL  => C_DQ3_TAP_DELAY_VAL,  
+   DQ4_TAP_DELAY_VAL  => C_DQ4_TAP_DELAY_VAL,  
+   DQ5_TAP_DELAY_VAL  => C_DQ5_TAP_DELAY_VAL,  
+   DQ6_TAP_DELAY_VAL  => C_DQ6_TAP_DELAY_VAL,  
+   DQ7_TAP_DELAY_VAL  => C_DQ7_TAP_DELAY_VAL,  
+   DQ8_TAP_DELAY_VAL  => C_DQ8_TAP_DELAY_VAL,  
+   DQ9_TAP_DELAY_VAL  => C_DQ9_TAP_DELAY_VAL,  
+   DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL, 
+   DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL, 
+   DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL, 
+   DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL, 
+   DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL, 
+   DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
+   )
+
+port map
+(
+   sys_rst                    =>  async_rst,
+   sysclk_2x                  =>  sysclk_2x,
+   sysclk_2x_180              =>  sysclk_2x_180,
+   pll_ce_0                   =>  pll_ce_0,
+   pll_ce_90                  =>  pll_ce_90,
+   pll_lock                   =>  pll_lock,
+   mcbx_dram_addr             =>  mcb3_dram_a,
+   mcbx_dram_ba               =>  mcb3_dram_ba,
+   mcbx_dram_ras_n            =>  mcb3_dram_ras_n,
+   mcbx_dram_cas_n            =>  mcb3_dram_cas_n,
+   mcbx_dram_we_n             =>  mcb3_dram_we_n,
+   mcbx_dram_cke              =>  mcb3_dram_cke,
+   mcbx_dram_clk              =>  mcb3_dram_ck,
+   mcbx_dram_clk_n            =>  mcb3_dram_ck_n,
+   mcbx_dram_dq               =>  mcb3_dram_dq,
+   mcbx_dram_odt              =>  mcb3_dram_odt,
+   mcbx_dram_ldm              =>  mcb3_dram_dm,
+   mcbx_dram_udm              =>  mcb3_dram_udm,
+   mcbx_dram_dqs              =>  mcb3_dram_dqs,
+   mcbx_dram_dqs_n            =>  mcb3_dram_dqs_n,
+   mcbx_dram_udqs             =>  mcb3_dram_udqs,
+   mcbx_dram_udqs_n           =>  mcb3_dram_udqs_n,
+   mcbx_dram_ddr3_rst         =>  open,
+   calib_recal                =>  '0',
+   rzq                        =>  mcb3_rzq,
+   zio                        =>  mcb3_zio,
+   ui_read                    =>  '0',
+   ui_add                     =>  '0',
+   ui_cs                      =>  '0',
+   ui_clk                     =>  mcb_drp_clk,
+   ui_sdi                     =>  '0',
+   ui_addr                    =>  (others => '0'),
+   ui_broadcast               =>  '0',
+   ui_drp_update              =>  '0',
+   ui_done_cal                =>  '1',
+   ui_cmd                     =>  '0',
+   ui_cmd_in                  =>  '0',
+   ui_cmd_en                  =>  '0',
+   ui_dqcount                 =>  (others => '0'),
+   ui_dq_lower_dec            =>  '0',
+   ui_dq_lower_inc            =>  '0',
+   ui_dq_upper_dec            =>  '0',
+   ui_dq_upper_inc            =>  '0',
+   ui_udqs_inc                =>  '0',
+   ui_udqs_dec                =>  '0',
+   ui_ldqs_inc                =>  '0',
+   ui_ldqs_dec                =>  '0',
+   uo_data                    =>  uo_data,
+   uo_data_valid              =>  uo_data_valid,
+   uo_done_cal                =>  calib_done,
+   uo_cmd_ready_in            =>  uo_cmd_ready_in,
+   uo_refrsh_flag             =>  uo_refrsh_flag,
+   uo_cal_start               =>  uo_cal_start,
+   uo_sdo                     =>  uo_sdo,
+   status                     =>  status,
+   selfrefresh_enter          =>  '0',
+   selfrefresh_mode           =>  selfrefresh_mode,
+
+
+      p0_arb_en                            =>  '1',
+   p0_cmd_clk                           =>  p0_cmd_clk,
+   p0_cmd_en                            =>  p0_cmd_en,
+   p0_cmd_instr                         =>  p0_cmd_instr,
+   p0_cmd_bl                            =>  p0_cmd_bl,
+   p0_cmd_byte_addr                     =>  p0_cmd_byte_addr,
+   p0_cmd_empty                         =>  p0_cmd_empty,
+   p0_cmd_full                          =>  p0_cmd_full,
+   p0_wr_clk                            =>  p0_wr_clk,
+   p0_wr_en                             =>  p0_wr_en,
+   p0_wr_mask                           =>  p0_wr_mask,
+   p0_wr_data                           =>  p0_wr_data,
+   p0_wr_full                           =>  p0_wr_full,
+   p0_wr_empty                          =>  p0_wr_empty,
+   p0_wr_count                          =>  p0_wr_count,
+   p0_wr_underrun                       =>  p0_wr_underrun,
+   p0_wr_error                          =>  p0_wr_error,
+   p0_rd_clk                            =>  p0_rd_clk,
+   p0_rd_en                             =>  p0_rd_en,
+   p0_rd_data                           =>  p0_rd_data,
+   p0_rd_full                           =>  p0_rd_full,
+   p0_rd_empty                          =>  p0_rd_empty,
+   p0_rd_count                          =>  p0_rd_count,
+   p0_rd_overflow                       =>  p0_rd_overflow,
+   p0_rd_error                          =>  p0_rd_error,
+   p1_arb_en                            =>  '1',
+   p1_cmd_clk                           =>  p1_cmd_clk,
+   p1_cmd_en                            =>  p1_cmd_en,
+   p1_cmd_instr                         =>  p1_cmd_instr,
+   p1_cmd_bl                            =>  p1_cmd_bl,
+   p1_cmd_byte_addr                     =>  p1_cmd_byte_addr,
+   p1_cmd_empty                         =>  p1_cmd_empty,
+   p1_cmd_full                          =>  p1_cmd_full,
+   p1_wr_clk                            =>  p1_wr_clk,
+   p1_wr_en                             =>  p1_wr_en,
+   p1_wr_mask                           =>  p1_wr_mask,
+   p1_wr_data                           =>  p1_wr_data,
+   p1_wr_full                           =>  p1_wr_full,
+   p1_wr_empty                          =>  p1_wr_empty,
+   p1_wr_count                          =>  p1_wr_count,
+   p1_wr_underrun                       =>  p1_wr_underrun,
+   p1_wr_error                          =>  p1_wr_error,
+   p1_rd_clk                            =>  p1_rd_clk,
+   p1_rd_en                             =>  p1_rd_en,
+   p1_rd_data                           =>  p1_rd_data,
+   p1_rd_full                           =>  p1_rd_full,
+   p1_rd_empty                          =>  p1_rd_empty,
+   p1_rd_count                          =>  p1_rd_count,
+   p1_rd_overflow                       =>  p1_rd_overflow,
+   p1_rd_error                          =>  p1_rd_error,
+   p2_arb_en                            =>  '1',
+   p2_cmd_clk                           =>  p2_cmd_clk,
+   p2_cmd_en                            =>  p2_cmd_en,
+   p2_cmd_instr                         =>  p2_cmd_instr,
+   p2_cmd_bl                            =>  p2_cmd_bl,
+   p2_cmd_byte_addr                     =>  p2_cmd_byte_addr,
+   p2_cmd_empty                         =>  p2_cmd_empty,
+   p2_cmd_full                          =>  p2_cmd_full,
+   p2_wr_clk                            =>  p2_wr_clk,
+   p2_wr_en                             =>  p2_wr_en,
+   p2_wr_mask                           =>  p2_wr_mask,
+   p2_wr_data                           =>  p2_wr_data,
+   p2_wr_full                           =>  p2_wr_full,
+   p2_wr_empty                          =>  p2_wr_empty,
+   p2_wr_count                          =>  p2_wr_count,
+   p2_wr_underrun                       =>  p2_wr_underrun,
+   p2_wr_error                          =>  p2_wr_error,
+   p2_rd_clk                            =>  p2_rd_clk,
+   p2_rd_en                             =>  p2_rd_en,
+   p2_rd_data                           =>  p2_rd_data,
+   p2_rd_full                           =>  p2_rd_full,
+   p2_rd_empty                          =>  p2_rd_empty,
+   p2_rd_count                          =>  p2_rd_count,
+   p2_rd_overflow                       =>  p2_rd_overflow,
+   p2_rd_error                          =>  p2_rd_error,
+   p3_arb_en                            =>  '1',
+   p3_cmd_clk                           =>  p3_cmd_clk,
+   p3_cmd_en                            =>  p3_cmd_en,
+   p3_cmd_instr                         =>  p3_cmd_instr,
+   p3_cmd_bl                            =>  p3_cmd_bl,
+   p3_cmd_byte_addr                     =>  p3_cmd_byte_addr,
+   p3_cmd_empty                         =>  p3_cmd_empty,
+   p3_cmd_full                          =>  p3_cmd_full,
+   p3_wr_clk                            =>  p3_wr_clk,
+   p3_wr_en                             =>  p3_wr_en,
+   p3_wr_mask                           =>  p3_wr_mask,
+   p3_wr_data                           =>  p3_wr_data,
+   p3_wr_full                           =>  p3_wr_full,
+   p3_wr_empty                          =>  p3_wr_empty,
+   p3_wr_count                          =>  p3_wr_count,
+   p3_wr_underrun                       =>  p3_wr_underrun,
+   p3_wr_error                          =>  p3_wr_error,
+   p3_rd_clk                            =>  p3_rd_clk,
+   p3_rd_en                             =>  p3_rd_en,
+   p3_rd_data                           =>  p3_rd_data,
+   p3_rd_full                           =>  p3_rd_full,
+   p3_rd_empty                          =>  p3_rd_empty,
+   p3_rd_count                          =>  p3_rd_count,
+   p3_rd_overflow                       =>  p3_rd_overflow,
+   p3_rd_error                          =>  p3_rd_error,
+   p4_arb_en                            =>  '0',
+   p4_cmd_clk                           =>  '0',
+   p4_cmd_en                            =>  '0',
+   p4_cmd_instr                         =>  (others => '0'),
+   p4_cmd_bl                            =>  (others => '0'),
+   p4_cmd_byte_addr                     =>  (others => '0'),
+   p4_cmd_empty                         =>  open,
+   p4_cmd_full                          =>  open,
+   p4_rd_clk                            =>  '0',
+   p4_rd_en                             =>  '0',
+   p4_rd_data                           =>  open,
+   p4_rd_full                           =>  open,
+   p4_rd_empty                          =>  open,
+   p4_rd_count                          =>  open,
+   p4_rd_overflow                       =>  open,
+   p4_rd_error                          =>  open,
+   p4_wr_clk                            =>  '0',
+   p4_wr_en                             =>  '0',
+   p4_wr_mask                           =>  (others => '0'),
+   p4_wr_data                           =>  (others => '0'),
+   p4_wr_full                           =>  open,
+   p4_wr_empty                          =>  open,
+   p4_wr_count                          =>  open,
+   p4_wr_underrun                       =>  open,
+   p4_wr_error                          =>  open,
+   p5_arb_en                            =>  '0',
+   p5_cmd_clk                           =>  '0',
+   p5_cmd_en                            =>  '0',
+   p5_cmd_instr                         =>  (others => '0'),
+   p5_cmd_bl                            =>  (others => '0'),
+   p5_cmd_byte_addr                     =>  (others => '0'),
+   p5_cmd_empty                         =>  open,
+   p5_cmd_full                          =>  open,
+   p5_rd_clk                            =>  '0',
+   p5_rd_en                             =>  '0',
+   p5_rd_data                           =>  open,
+   p5_rd_full                           =>  open,
+   p5_rd_empty                          =>  open,
+   p5_rd_count                          =>  open,
+   p5_rd_overflow                       =>  open,
+   p5_rd_error                          =>  open,
+   p5_wr_clk                            =>  '0',
+   p5_wr_en                             =>  '0',
+   p5_wr_mask                           =>  (others => '0'),
+   p5_wr_data                           =>  (others => '0'),
+   p5_wr_full                           =>  open,
+   p5_wr_empty                          =>  open,
+   p5_wr_count                          =>  open,
+   p5_wr_underrun                       =>  open,
+   p5_wr_error                          =>  open
+);
+
+
+
+end architecture;
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/afifo.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/afifo.vhd
new file mode 100755
index 0000000..5924354
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/afifo.vhd
@@ -0,0 +1,280 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.	   
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: afifo.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:34 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:  A generic synchronous fifo.
+-- Reference:
+-- Revision History: 2009/01/09  corrected signal "buf_avail" and "almost_full" equation.
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   use ieee.numeric_std.all;
+
+
+
+ENTITY afifo IS
+   GENERIC (
+      TCQ         : TIME   := 100 ps;
+      DSIZE       : INTEGER := 32;
+      FIFO_DEPTH  : INTEGER := 16;
+      ASIZE       : INTEGER := 4;
+      SYNC        : INTEGER := 1
+   );
+   PORT (
+      wr_clk      : IN STD_LOGIC;
+      rst         : IN STD_LOGIC;
+      wr_en       : IN STD_LOGIC;
+      wr_data     : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      rd_en       : IN STD_LOGIC;
+      rd_clk      : IN STD_LOGIC;
+      rd_data     : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      full        : OUT STD_LOGIC;
+      empty       : OUT STD_LOGIC;
+      almost_full : OUT STD_LOGIC
+   );
+END afifo;
+
+ARCHITECTURE trans OF afifo IS
+   TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+
+   
+   
+   SIGNAL mem                     : mem_array;
+   
+   SIGNAL rd_gray_nxt             : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL rd_gray                 : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL rd_capture_ptr          : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL rd_capture_gray_ptr     : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wr_gray                 : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wr_gray_nxt             : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   
+   SIGNAL wr_capture_ptr          : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wr_capture_gray_ptr     : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL buf_avail               : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL buf_filled              : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wr_addr                 : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
+   SIGNAL rd_addr                 : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
+   
+   SIGNAL wr_ptr                  : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL rd_ptr                  : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL i                       : INTEGER;
+   SIGNAL j                       : INTEGER;
+   SIGNAL k                       : INTEGER;
+   
+   SIGNAL rd_strobe               : STD_LOGIC;
+   
+   SIGNAL n                       : INTEGER;
+   SIGNAL rd_ptr_tmp              : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   
+   SIGNAL wbin                    : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wgraynext               : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL wbinnext                : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL ZERO                    : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+   SIGNAL ONE                     : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
+
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL full_xhdl1              : STD_LOGIC;
+   SIGNAL almost_full_int             : STD_LOGIC;
+   SIGNAL empty_xhdl0             : STD_LOGIC;
+BEGIN
+   -- Drive referenced outputs
+   ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
+   ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
+
+   full <= full_xhdl1;
+   empty <= empty_xhdl0;
+   xhdl3 : IF (SYNC = 1) GENERATE
+      PROCESS (rd_ptr)
+      BEGIN
+         rd_capture_ptr <= rd_ptr;
+      END PROCESS;      
+   END GENERATE;
+
+
+
+
+   xhdl4 : IF (SYNC = 1) GENERATE
+      PROCESS (wr_ptr)
+      BEGIN
+         wr_capture_ptr <= wr_ptr;
+      END PROCESS;      
+   END GENERATE;
+
+   wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
+   rd_data <= mem(conv_integer(rd_addr));
+
+
+
+   PROCESS (wr_clk)
+   BEGIN
+      IF (wr_clk'EVENT AND wr_clk = '1') THEN
+         IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
+            mem(to_integer(unsigned(wr_addr))) <= wr_data;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
+   rd_strobe <= rd_en AND NOT(empty_xhdl0);
+   PROCESS (rd_ptr)
+   BEGIN
+      rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
+      FOR n IN 0 TO  ASIZE - 1 LOOP
+         rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
+      END LOOP;
+   END PROCESS;
+   
+   PROCESS (rd_clk)
+   BEGIN
+      IF (rd_clk'EVENT AND rd_clk = '1') THEN
+         IF (rst = '1') THEN
+            rd_ptr <= (others=> '0');
+            rd_gray <= (others=> '0');
+         ELSE
+            IF (rd_strobe = '1') THEN
+               rd_ptr <= rd_ptr + 1;
+            END IF;
+            rd_ptr_tmp <= rd_ptr;
+            rd_gray <= rd_gray_nxt;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   buf_filled <= wr_capture_ptr - rd_ptr;
+   PROCESS (rd_clk)
+   BEGIN
+      IF (rd_clk'EVENT AND rd_clk = '1') THEN
+         IF (rst = '1') THEN
+            empty_xhdl0 <= '1';
+         ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
+            empty_xhdl0 <= '1';
+         ELSE
+            empty_xhdl0 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (rd_clk)
+   BEGIN
+      IF (rd_clk'EVENT AND rd_clk = '1') THEN
+         IF (rst = '1') THEN
+            wr_ptr <= (others => '0');
+            wr_gray <= (others => '0');
+         ELSE
+            IF (wr_en = '1') THEN
+               
+               wr_ptr <= wr_ptr + 1;
+            END IF;
+            wr_gray <= wr_gray_nxt;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (wr_ptr)
+   BEGIN
+      wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
+      FOR n IN 0 TO  ASIZE - 1 LOOP
+         wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
+      END LOOP;
+   END PROCESS;
+   
+   buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
+  
+   
+   PROCESS (wr_clk)
+   BEGIN
+      IF (wr_clk'EVENT AND wr_clk = '1') THEN
+         IF (rst = '1') THEN
+            full_xhdl1 <= '0';
+         ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
+            full_xhdl1 <= '1';
+         ELSE
+            full_xhdl1 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   almost_full <= almost_full_int;
+   PROCESS (wr_clk)
+   BEGIN
+      IF (wr_clk'EVENT AND wr_clk = '1') THEN
+         IF (rst = '1') THEN
+            almost_full_int <= '0';
+
+         ELSIF (buf_avail <=  3 AND wr_en = '1') THEN  --FIFO_DEPTH
+         
+            almost_full_int <= '1';
+         ELSE
+            almost_full_int <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+
+   
+END trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/cmd_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/cmd_gen.vhd
new file mode 100755
index 0000000..17ee620
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/cmd_gen.vhd
@@ -0,0 +1,1077 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: cmd_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:27 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR
+-- Purpose:  This module genreates different type of commands, address,
+--          burst_length to mcb_flow_control module.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+
+ENTITY cmd_gen IS
+   GENERIC (
+      FAMILY               : STRING := "SPARTAN6";
+      MEM_BURST_LEN        : INTEGER := 8;
+      TCQ                  : TIME := 100 ps;
+      PORT_MODE            : STRING  := "BI_MODE";
+      NUM_DQ_PINS          : INTEGER := 8;
+      DATA_PATTERN         : STRING := "DGEN_ALL";
+      CMD_PATTERN          : STRING := "CGEN_ALL";
+      ADDR_WIDTH           : INTEGER := 30;
+      DWIDTH               : INTEGER := 32;
+      PIPE_STAGES          : INTEGER := 0;
+      MEM_COL_WIDTH        : INTEGER := 10;
+      PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+      PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00002000"
+   );
+   PORT (
+      clk_i                : IN STD_LOGIC;
+      rst_i                : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      run_traffic_i        : IN STD_LOGIC;
+      rd_buff_avail_i      : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      force_wrcmd_gen_i    : IN STD_LOGIC;
+      start_addr_i         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      end_addr_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmd_seed_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      data_seed_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      load_seed_i          : IN STD_LOGIC;
+      addr_mode_i          : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      data_mode_i          : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      instr_mode_i         : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      bl_mode_i            : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      mode_load_i          : IN STD_LOGIC;
+      fixed_bl_i           : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      fixed_instr_i        : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      fixed_addr_i         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bram_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bram_instr_i         : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      bram_bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      bram_valid_i         : IN STD_LOGIC;
+      bram_rdy_o           : OUT STD_LOGIC;
+      reading_rd_data_i    : IN STD_LOGIC;
+      rdy_i                : IN STD_LOGIC;
+      addr_o               : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      instr_o              : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      bl_o                 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+--      m_addr_o             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmd_o_vld            : OUT STD_LOGIC
+   );
+END cmd_gen;
+
+ARCHITECTURE trans OF cmd_gen IS
+    constant  PRBS_ADDR_WIDTH      : INTEGER := 32;
+    constant  INSTR_PRBS_WIDTH     : INTEGER := 16;
+    constant  BL_PRBS_WIDTH        : INTEGER := 16;
+
+    constant  BRAM_DATAL_MODE      : std_logic_vector(3 downto 0)  := "0000";
+    constant  FIXED_DATA_MODE      : std_logic_vector(3 downto 0)  := "0001";
+    constant  ADDR_DATA_MODE       : std_logic_vector(3 downto 0)  := "0010";
+    constant  HAMMER_DATA_MODE     : std_logic_vector(3 downto 0)  := "0011";
+    constant  NEIGHBOR_DATA_MODE   : std_logic_vector(3 downto 0)  := "0100";
+    constant  WALKING1_DATA_MODE   : std_logic_vector(3 downto 0)  := "0101";
+    constant  WALKING0_DATA_MODE   : std_logic_vector(3 downto 0)  := "0110";
+    constant  PRBS_DATA_MODE       : std_logic_vector(3 downto 0)  := "0111";
+COMPONENT pipeline_inserter IS
+   GENERIC (
+      DATA_WIDTH            : INTEGER := 32;
+      PIPE_STAGES           : INTEGER := 1
+   );
+   PORT (
+      data_i                : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
+      clk_i                 : IN STD_LOGIC;
+      en_i                  : IN STD_LOGIC;
+
+      data_o                : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
+   );
+END COMPONENT;
+
+COMPONENT cmd_prbs_gen IS
+   GENERIC (
+      TCQ                  : time := 100 ps;
+      FAMILY               : STRING := "SPARTAN6";
+      ADDR_WIDTH           : INTEGER := 29;
+      DWIDTH               : INTEGER := 32;
+      PRBS_CMD             : STRING := "ADDRESS";
+      PRBS_WIDTH           : INTEGER := 64;
+      SEED_WIDTH           : INTEGER := 32;
+      PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+      PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00002000"
+   );
+   PORT (
+
+      clk_i                : IN STD_LOGIC;
+      prbs_seed_init       : IN STD_LOGIC;
+      clk_en               : IN STD_LOGIC;
+      prbs_seed_i          : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
+
+      prbs_o               : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
+   );
+END COMPONENT;
+
+function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
+begin
+   if A = true then
+       return '1';
+   else
+       return '0';
+   end if;
+end function BOOLEAN_TO_STD_LOGIC;
+
+   SIGNAL INC_COUNTS                    : STD_LOGIC_VECTOR(10 DOWNTO 0);
+   SIGNAL addr_mode_reg                 : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL bl_mode_reg                   : STD_LOGIC_VECTOR(1 DOWNTO 0);
+   SIGNAL addr_counts                   : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL prbs_bl                       : STD_LOGIC_VECTOR(14 DOWNTO 0);
+   SIGNAL instr_out                     : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL prbs_instr_a                  : STD_LOGIC_VECTOR(14 DOWNTO 0);
+   SIGNAL prbs_instr_b                  : STD_LOGIC_VECTOR(14 DOWNTO 0);
+   SIGNAL prbs_brlen                    : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL prbs_addr                     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL seq_addr                      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL fixed_addr                    : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL addr_out                      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL bl_out                        : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL bl_out_reg                    : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL mode_load_d1                  : STD_LOGIC;
+   SIGNAL mode_load_d2                  : STD_LOGIC;
+   SIGNAL mode_load_pulse               : STD_LOGIC;
+   SIGNAL pipe_data_o                   : STD_LOGIC_VECTOR(41 DOWNTO 0);
+   SIGNAL cmd_clk_en                    : STD_LOGIC;
+   SIGNAL pipe_out_vld                  : STD_LOGIC;
+   SIGNAL end_addr_range                : STD_LOGIC_VECTOR(15 DOWNTO 0);
+   SIGNAL force_bl1                     : STD_LOGIC;
+   SIGNAL A0_G_E0                       : STD_LOGIC;
+   SIGNAL A1_G_E1                       : STD_LOGIC;
+   SIGNAL A2_G_E2                       : STD_LOGIC;
+   SIGNAL A3_G_E3                       : STD_LOGIC;
+   SIGNAL AC3_G_E3                      : STD_LOGIC;
+   SIGNAL AC2_G_E2                      : STD_LOGIC;
+   SIGNAL AC1_G_E1                      : STD_LOGIC;
+   SIGNAL bl_out_clk_en                 : STD_LOGIC;
+   SIGNAL pipe_data_in                  : STD_LOGIC_VECTOR(41 DOWNTO 0);
+   SIGNAL instr_vld                     : STD_LOGIC;
+   SIGNAL bl_out_vld                    : STD_LOGIC;
+   SIGNAL cmd_vld                       : STD_LOGIC;
+   SIGNAL run_traffic_r                 : STD_LOGIC;
+   SIGNAL run_traffic_pulse             : STD_LOGIC;
+
+   SIGNAL pipe_data_in_vld              : STD_LOGIC;
+   SIGNAL gen_addr_larger               : STD_LOGIC;
+   SIGNAL buf_avail_r                   : STD_LOGIC_VECTOR(6 DOWNTO 0);
+   SIGNAL rd_data_received_counts       : STD_LOGIC_VECTOR(6 DOWNTO 0);
+   SIGNAL rd_data_counts_asked          : STD_LOGIC_VECTOR(6 DOWNTO 0);
+   SIGNAL rd_data_received_counts_total : STD_LOGIC_VECTOR(15 DOWNTO 0);
+   SIGNAL instr_vld_dly1                : STD_LOGIC;
+   SIGNAL first_load_pulse              : STD_LOGIC;
+   SIGNAL mem_init_done                 : STD_LOGIC;
+   SIGNAL i                             : INTEGER;
+   SIGNAL force_wrcmd_gen               : STD_LOGIC;
+   SIGNAL force_smallvalue              : STD_LOGIC;
+
+   SIGNAL end_addr_r                    : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+   SIGNAL force_rd_counts               : STD_LOGIC_VECTOR(9 DOWNTO 0);
+   SIGNAL force_rd                      : STD_LOGIC;
+   SIGNAL addr_counts_next_r            : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL refresh_cmd_en                : STD_LOGIC;
+   SIGNAL refresh_timer                 : STD_LOGIC_VECTOR(9 DOWNTO 0);
+   SIGNAL refresh_prbs                  : STD_LOGIC;
+   SIGNAL cmd_clk_en_r                  : STD_LOGIC;
+
+   signal instr_mode_reg                : std_logic_vector(3 downto 0);
+
+
+   -- X-HDL generated signals
+
+   SIGNAL xhdl4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL xhdl12 : STD_LOGIC_VECTOR(1 DOWNTO 0);
+   SIGNAL xhdl14 : STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL bl_o_xhdl0                    : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL mode_load_pulse_r1            : STD_LOGIC;
+
+BEGIN
+   -- Drive referenced outputs
+   bl_o       <= bl_o_xhdl0;
+   addr_o     <= pipe_data_o(31 DOWNTO 0);
+   instr_o    <= pipe_data_o(34 DOWNTO 32);
+   bl_o_xhdl0 <= pipe_data_o(40 DOWNTO 35);
+   cmd_o_vld  <= pipe_data_o(41) AND run_traffic_r;
+   pipe_out_vld <= pipe_data_o(41) AND run_traffic_r;
+   pipe_data_o <= pipe_data_in;
+
+
+   cv1 : IF (CMD_PATTERN = "CGEN_BRAM") GENERATE
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+           cmd_vld <= cmd_clk_en;
+      END IF;
+   END PROCESS;
+   END GENERATE;
+
+   cv3 : IF (CMD_PATTERN = "CGEN_PRBS"  OR CMD_PATTERN = "CGEN_ALL" OR CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_FIXED") GENERATE
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+           cmd_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse);
+      END IF;
+   END PROCESS;
+   END GENERATE;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+            run_traffic_r <=  run_traffic_i ;
+          IF (  run_traffic_i= '1' AND   run_traffic_r = '0' ) THEN
+               run_traffic_pulse <= '1'  ;
+          ELSE
+               run_traffic_pulse <= '0' ;
+          END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         instr_vld <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
+         bl_out_clk_en <= cmd_clk_en OR (mode_load_pulse AND first_load_pulse) ;
+         bl_out_vld <= bl_out_clk_en ;
+         pipe_data_in_vld <= instr_vld ;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0) = '1') THEN
+            first_load_pulse <= '1' ;
+         ELSIF (mode_load_pulse = '1') THEN
+            first_load_pulse <= '0' ;
+         ELSE
+            first_load_pulse <= first_load_pulse ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+
+   cmd_clk_en <= (rdy_i AND pipe_out_vld AND run_traffic_i)  OR (mode_load_pulse AND BOOLEAN_TO_STD_LOGIC(CMD_PATTERN = "CGEN_BRAM"));
+
+   pipe_in_s6 : IF (FAMILY = "SPARTAN6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF ((rst_i(0)) = '1') THEN
+               pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
+            ELSIF (instr_vld = '1') THEN
+               IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
+
+                 IF (DWIDTH = 32) THEN
+                   pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
+                 ELSIF (DWIDTH = 64) THEN
+                   pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 9) & "000000000") ;
+                 ELSE
+                   pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 10) & "0000000000") ;
+                 END IF;
+
+               ELSE
+                  IF (DWIDTH = 32) THEN
+                     pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
+                  ELSIF (DWIDTH = 64) THEN
+                     pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
+                  ELSIF (DWIDTH = 128) THEN
+                     pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
+                  END IF;
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+   END GENERATE;
+   pipe_in_v6 : IF (FAMILY = "VIRTEX6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF ((rst_i(1)) = '1') THEN
+               pipe_data_in(31 DOWNTO 0) <= start_addr_i ;
+            ELSIF (instr_vld = '1') THEN
+               IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
+                  pipe_data_in(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
+
+               ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS <= 144)) THEN
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 7) & "0000000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
+                  END IF;
+
+               ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
+
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 6) & "000000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
+                  END IF;
+
+               ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 5) & "00000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
+                  END IF;
+
+               ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 24)) THEN
+                  pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000");
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
+                  END IF;
+               ELSIF (NUM_DQ_PINS = 8)  THEN
+                  IF (MEM_BURST_LEN = 8) THEN
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
+                  ELSE
+                       pipe_data_in(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
+                  END IF;
+
+
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+   END GENERATE;
+--   pipe_m_addr_o : IF (FAMILY = "VIRTEX6") GENERATE
+--      PROCESS (clk_i)
+--      BEGIN
+--         IF (clk_i'EVENT AND clk_i = '1') THEN
+--            IF ((rst_i(1)) = '1') THEN
+--               m_addr_o(31 DOWNTO 0) <= start_addr_i ;
+--            ELSIF (instr_vld = '1') THEN
+--               IF (gen_addr_larger = '1' AND (addr_mode_reg = "100" OR addr_mode_reg = "010")) THEN
+--                  m_addr_o(31 DOWNTO 0) <= (end_addr_i(31 DOWNTO 8) & "00000000") ;
+--
+--               ELSIF ((NUM_DQ_PINS >= 128) AND (NUM_DQ_PINS < 256)) THEN
+--                  m_addr_o <= (addr_out(31 DOWNTO 6) & "000000") ;
+--
+--               ELSIF ((NUM_DQ_PINS >= 64) AND (NUM_DQ_PINS < 128)) THEN
+--                  m_addr_o <= (addr_out(31 DOWNTO 5) & "00000") ;
+--               ELSIF ((NUM_DQ_PINS = 32) OR (NUM_DQ_PINS = 40) OR (NUM_DQ_PINS = 48) OR (NUM_DQ_PINS = 56)) THEN
+--                  m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 4) & "0000") ;
+--               ELSIF ((NUM_DQ_PINS = 16) OR (NUM_DQ_PINS = 17)) THEN
+--                  m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 3) & "000") ;
+--               ELSIF ((NUM_DQ_PINS = 8) OR (NUM_DQ_PINS = 9)) THEN
+--                  m_addr_o(31 DOWNTO 0) <= (addr_out(31 DOWNTO 2) & "00") ;
+--               END IF;
+--            END IF;
+--         END IF;
+--      END PROCESS;
+--
+--   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0) = '1') THEN
+            force_wrcmd_gen <= '0' ;
+         ELSIF (buf_avail_r = "0111111") THEN
+            force_wrcmd_gen <= '0' ;
+         ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1' AND pipe_data_in(41 DOWNTO 35) > "0010000") THEN
+            force_wrcmd_gen <= '1' ;
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         instr_mode_reg <= instr_mode_i ;
+
+      END IF;
+   END PROCESS;
+            -- **********************************************
+
+   PROCESS (clk_i) BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(2)) = '1') THEN
+            pipe_data_in(40 DOWNTO 32) <= "000000000";
+            force_smallvalue <= '0';
+         ELSIF (instr_vld = '1') THEN
+
+            IF (instr_mode_reg = 0) THEN
+               pipe_data_in(34 DOWNTO 32) <= instr_out ;
+
+            ELSIF (instr_out(2) = '1') THEN
+
+               pipe_data_in(34 DOWNTO 32) <= "100" ;
+
+
+            ELSIF (FAMILY = "SPARTAN6" AND PORT_MODE = "RD_MODE") THEN
+
+               pipe_data_in(34 DOWNTO 32) <= instr_out(2 downto 1) & '1' ;
+
+            ELSIF ((force_wrcmd_gen = '1' OR buf_avail_r <= "0001111") AND FAMILY = "SPARTAN6" AND PORT_MODE /= "RD_MODE") THEN
+                  pipe_data_in(34 DOWNTO 32) <= instr_out(2) & "00";
+            ELSE
+                  pipe_data_in(34 DOWNTO 32) <= instr_out;
+
+            END IF;
+   ----********* condition the generated bl value except if TG is programmed for BRAM interface'
+   ---- if the generated address is close to end address range, the bl_out will be altered to 1.
+     --
+           IF (bl_mode_i = 0) THEN
+               pipe_data_in(40 DOWNTO 35) <= bl_out ;
+         ELSIF ( FAMILY = "VIRTEX6") THEN
+             pipe_data_in(40 DOWNTO 35)  <=  bl_out ;
+         ELSIF (force_bl1 = '1' AND (bl_mode_reg = "10") AND FAMILY = "SPARTAN6") THEN
+
+            pipe_data_in(40 DOWNTO 35) <= "000001"  ;
+
+
+         -- **********************************************
+
+      ELSIF (buf_avail_r(5 DOWNTO 0) >= "111100" AND buf_avail_r(6) = '0' AND pipe_data_in(32) = '1' AND FAMILY = "SPARTAN6") THEN
+         IF (bl_mode_reg = "10") THEN
+             force_smallvalue <= NOT(force_smallvalue) ;
+          END IF;
+          IF (buf_avail_r(6) = '1' AND bl_mode_reg = "10") THEN
+             pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 1) & '1') ;
+          ELSE
+             pipe_data_in(40 DOWNTO 35) <= bl_out ;
+          END IF;
+      ELSIF (buf_avail_r < "1000000" AND rd_buff_avail_i >= "0000000" AND instr_out(0) = '1' AND (bl_mode_reg = "10")) THEN
+         IF (FAMILY = "SPARTAN6") THEN
+           pipe_data_in(40 DOWNTO 35) <= ("00" & bl_out(3 DOWNTO 0)) + '1' ;
+        ELSE
+           pipe_data_in(40 DOWNTO 35) <= bl_out ;
+         END IF;
+         END IF; --IF (bl_mode_i = 0) THEN
+       END IF;  --IF ((rst_i(2)) = '1') THEN
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(2)) = '1') THEN
+            pipe_data_in(41) <= '0' ;
+         ELSIF (cmd_vld = '1') THEN
+            pipe_data_in(41) <= instr_vld ;
+         ELSIF ((rdy_i AND pipe_out_vld) = '1') THEN
+            pipe_data_in(41) <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         instr_vld_dly1 <= instr_vld;
+      END IF;
+   END PROCESS;
+
+
+
+ PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0) = '1') THEN
+            rd_data_counts_asked <= (others => '0') ;
+         ELSIF (instr_vld_dly1 = '1' AND pipe_data_in(32) = '1') THEN
+            IF (pipe_data_in(40 DOWNTO 35) = "000000") THEN
+               rd_data_counts_asked <= rd_data_counts_asked + 64 ;
+
+            ELSE
+               rd_data_counts_asked <= rd_data_counts_asked + ('0' & (pipe_data_in(40 DOWNTO 35)));
+
+            END IF;
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF  (rst_i(0) = '1') THEN
+            rd_data_received_counts <= (others => '0');
+            rd_data_received_counts_total <= (others => '0');
+         ELSIF (reading_rd_data_i = '1') THEN
+            rd_data_received_counts <= rd_data_received_counts + '1';
+            rd_data_received_counts_total <= rd_data_received_counts_total + "0000000000000001";
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         buf_avail_r <= (rd_data_received_counts + 64) - rd_data_counts_asked;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(3)) = '1') THEN
+           IF (CMD_PATTERN = "CGEN_BRAM") THEN
+             addr_mode_reg <= "000";
+           ELSE
+             addr_mode_reg <= "011";
+           END IF;
+         ELSIF (mode_load_pulse = '1') THEN
+            addr_mode_reg <= addr_mode_i;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (mode_load_pulse = '1') THEN
+            bl_mode_reg <= bl_mode_i;
+         END IF;
+         mode_load_d1 <= mode_load_i;
+         mode_load_d2 <= mode_load_d1;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         mode_load_pulse <= mode_load_d1 AND NOT(mode_load_d2);
+      END IF;
+   END PROCESS;
+
+   xhdl4 <= addr_mode_reg;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(3)) = '1') THEN
+            addr_out <= start_addr_i;
+         ELSE
+            CASE xhdl4 IS
+               WHEN "000" =>
+                  addr_out <= bram_addr_i;
+               WHEN "001" =>
+                  addr_out <= fixed_addr;
+               WHEN "010" =>
+                  addr_out <= prbs_addr;
+               WHEN "011" =>
+                  addr_out <= ("00" & seq_addr(29 DOWNTO 0));
+               WHEN "100" =>
+--                  addr_out <= (prbs_addr(31 DOWNTO 6) & "000000");
+                  addr_out <= ("000" & seq_addr(6 DOWNTO 2) & seq_addr(23 DOWNTO 0));--(prbs_addr(31 DOWNTO 6) & "000000");
+               WHEN "101" =>
+                  addr_out <= (prbs_addr(31 DOWNTO 20) & seq_addr(19 DOWNTO 0));
+  --                addr_out <= (prbs_addr(31 DOWNTO MEM_COL_WIDTH) & seq_addr(MEM_COL_WIDTH - 1 DOWNTO 0));
+               WHEN OTHERS =>
+                  addr_out <= (others => '0');--"00000000000000000000000000000000";
+            END CASE;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   xhdl5 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+
+
+      addr_prbs_gen : cmd_prbs_gen
+         GENERIC MAP (
+            family               => FAMILY,
+            addr_width           => 32,
+            dwidth               => DWIDTH,
+            prbs_width           => 32,
+            seed_width           => 32,
+            prbs_eaddr_mask_pos  => PRBS_EADDR_MASK_POS,
+            prbs_saddr_mask_pos  => PRBS_SADDR_MASK_POS,
+            prbs_eaddr           => PRBS_EADDR,
+            prbs_saddr           => PRBS_SADDR
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            clk_en          => cmd_clk_en,
+            prbs_seed_init  => mode_load_pulse,
+            prbs_seed_i     => cmd_seed_i(31 DOWNTO 0),
+            prbs_o          => prbs_addr
+         );
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (addr_out(31 DOWNTO 8) >= end_addr_i(31 DOWNTO 8)) THEN
+            gen_addr_larger <= '1';
+         ELSE
+            gen_addr_larger <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+   xhdl6 : IF (FAMILY = "SPARTAN6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (mem_init_done = '1') THEN
+               INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),11));
+            ELSE
+               IF (fixed_bl_i = "000000") THEN
+                  INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8)*(64), 11));
+               ELSE
+                  INC_COUNTS <= std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(fixed_bl_i))),11));
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+   END GENERATE;
+   xhdl7 : IF (FAMILY = "VIRTEX6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (NUM_DQ_PINS >= 128 AND NUM_DQ_PINS <= 144) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(64 * (MEM_BURST_LEN/4), 11));
+         
+            ELSIF (NUM_DQ_PINS >= 64 AND NUM_DQ_PINS < 128) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(32 * (MEM_BURST_LEN/4), 11));
+            ELSIF (NUM_DQ_PINS >= 32 AND NUM_DQ_PINS < 64) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(16 * (MEM_BURST_LEN/4), 11));
+            ELSIF (NUM_DQ_PINS = 16 OR NUM_DQ_PINS = 24) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(8 * (MEM_BURST_LEN/4), 11));
+            ELSIF (NUM_DQ_PINS = 8 OR NUM_DQ_PINS = 9) THEN
+                   INC_COUNTS <= std_logic_vector(to_unsigned(4 * (MEM_BURST_LEN/4), 11));
+            END IF;
+         END IF;
+      END PROCESS;
+
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+            end_addr_r <= end_addr_i - std_logic_vector(to_unsigned(DWIDTH/8*to_integer(unsigned(fixed_bl_i)),32)) + "00000000000000000000000000000001";
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (addr_out(31 DOWNTO 24) >= end_addr_r(31 DOWNTO 24)) THEN
+            AC3_G_E3 <= '1';
+         ELSE
+            AC3_G_E3 <= '0';
+         END IF;
+         IF (addr_out(23 DOWNTO 16) >= end_addr_r(23 DOWNTO 16)) THEN
+            AC2_G_E2 <= '1';
+         ELSE
+            AC2_G_E2 <= '0';
+         END IF;
+         IF (addr_out(15 DOWNTO 8) >= end_addr_r(15 DOWNTO 8)) THEN
+            AC1_G_E1 <= '1';
+         ELSE
+            AC1_G_E1 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+--   xhdl8 : IF (CMD_PATTERN = "CGEN_SEQUENTIAL" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+      seq_addr <= addr_counts;
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            mode_load_pulse_r1 <= mode_load_pulse;
+         END IF;
+      END PROCESS;
+
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+               end_addr_range <= end_addr_i(15 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8 * to_integer(unsigned(bl_out_reg))),16)) + "0000000000000001";
+         END IF;
+      END PROCESS;
+
+      PROCESS (clk_i)
+      BEGIN
+        IF (clk_i'EVENT AND clk_i = '1') THEN
+              addr_counts_next_r <=   addr_counts + (INC_COUNTS);
+
+        END IF;
+      END PROCESS;
+
+      PROCESS (clk_i)
+      BEGIN
+        IF (clk_i'EVENT AND clk_i = '1') THEN
+              cmd_clk_en_r <= cmd_clk_en;
+        END IF;
+      END PROCESS;
+
+
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF ((rst_i(4)) = '1') THEN
+               addr_counts <= start_addr_i;
+               mem_init_done <= '0';
+            ELSIF ((cmd_clk_en_r OR mode_load_pulse_r1) = '1') THEN
+--               IF ((DWIDTH = 32 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR (DWIDTH = 64 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0))) OR ((DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND FAMILY = "SPARTAN6") OR (DWIDTH = 128 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6") OR (DWIDTH >= 256 AND AC3_G_E3 = '1' AND AC2_G_E2 = '1' AND AC1_G_E1 = '1' AND (addr_counts(7 DOWNTO 0) >= end_addr_r(7 DOWNTO 0)) AND FAMILY = "VIRTEX6"))) THEN
+            IF (addr_counts_next_r >= end_addr_i) THEN
+                  addr_counts <= start_addr_i;
+                  mem_init_done <= '1';
+               ELSIF (addr_counts < end_addr_r) THEN
+                  addr_counts <= addr_counts + INC_COUNTS;
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+   --END GENERATE;
+   
+   xhdl9 : IF (CMD_PATTERN = "CGEN_FIXED" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+      fixed_addr <= (fixed_addr_i(31 DOWNTO 2) & "00") WHEN (DWIDTH = 32) ELSE
+                    (fixed_addr_i(31 DOWNTO 3) & "000") WHEN (DWIDTH = 64) ELSE
+                    (fixed_addr_i(31 DOWNTO 4) & "0000") WHEN (DWIDTH = 128) ELSE
+                    (fixed_addr_i(31 DOWNTO 5) & "00000") WHEN (DWIDTH = 256) ELSE
+                    (fixed_addr_i(31 DOWNTO 6) & "000000");
+   END GENERATE;
+   xhdl10 : IF (CMD_PATTERN = "CGEN_BRAM" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+      bram_rdy_o <= (run_traffic_i AND cmd_clk_en AND bram_valid_i) OR (mode_load_pulse);
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(4)) = '1') THEN
+            force_rd_counts <= (others => '0');--"0000000000";
+         ELSIF (instr_vld = '1') THEN
+            force_rd_counts <= force_rd_counts + "0000000001";
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(4)) = '1') THEN
+            force_rd <= '0';
+         ELSIF ((force_rd_counts(3)) = '1') THEN
+            force_rd <= '1';
+         ELSE
+            force_rd <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+
+-- adding refresh timer to limit the amount of issuing refresh command.
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(4)) = '1') THEN
+            refresh_timer <= (others => '0');
+         ELSE
+            refresh_timer <= refresh_timer + 1;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(4)) = '1') THEN
+            refresh_cmd_en <= '0';
+         ELSIF (refresh_timer = "1111111111") THEN
+            refresh_cmd_en <= '1';
+         ELSIF ((cmd_clk_en and refresh_cmd_en) = '1') THEN
+            refresh_cmd_en <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (FAMILY = "SPARTAN6") THEN
+            refresh_prbs <= prbs_instr_b(3) and refresh_cmd_en;
+         ELSE
+            refresh_prbs <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+  --synthesis translate_off
+   PROCESS (instr_mode_i)
+   BEGIN
+     IF ((instr_mode_i  > "0010") and (FAMILY = "VIRTEX6")) THEN
+       report "Error ! Not valid instruction mode";
+     END IF;
+   END PROCESS;
+  --synthesis translate_on
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         CASE instr_mode_i IS
+            WHEN "0000" =>
+               instr_out <= bram_instr_i;
+            WHEN "0001" =>
+               instr_out <= fixed_instr_i;
+            WHEN "0010" =>
+               instr_out <= ("00" & (prbs_instr_a(0) OR force_rd));
+            WHEN "0011" =>
+               instr_out <= ("00" & prbs_instr_a(0));
+            WHEN "0100" =>
+               instr_out <= ('0' & prbs_instr_b(0) & prbs_instr_a(0));
+
+            WHEN "0101" =>
+               instr_out <= (refresh_prbs & prbs_instr_b(0) & prbs_instr_a(0));
+            WHEN OTHERS =>
+               instr_out <= ("00" & prbs_instr_a(0));
+         END CASE;
+      END IF;
+   END PROCESS;
+
+
+   xhdl11 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+
+
+
+
+      instr_prbs_gen_a : cmd_prbs_gen
+         GENERIC MAP (
+            prbs_cmd    => "INSTR",
+            family      => FAMILY,
+            addr_width  => 32,
+            seed_width  => 15,
+            prbs_width  => 20
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            clk_en          => cmd_clk_en,
+            prbs_seed_init  => load_seed_i,
+            prbs_seed_i     => cmd_seed_i(14 DOWNTO 0),
+            prbs_o          => prbs_instr_a
+         );
+
+
+
+      instr_prbs_gen_b : cmd_prbs_gen
+         GENERIC MAP (
+            prbs_cmd    => "INSTR",
+            family      => FAMILY,
+            seed_width  => 15,
+            prbs_width  => 20
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            clk_en          => cmd_clk_en,
+            prbs_seed_init  => load_seed_i,
+            prbs_seed_i     => cmd_seed_i(16 DOWNTO 2),
+            prbs_o          => prbs_instr_b
+         );
+
+   END GENERATE;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (addr_out(31 DOWNTO 24) >= end_addr_i(31 DOWNTO 24)) THEN
+            A3_G_E3 <= '1' ;
+         ELSE
+
+            A3_G_E3 <= '0' ;
+         END IF;
+         IF (addr_out(23 DOWNTO 16) >= end_addr_i(23 DOWNTO 16)) THEN
+            A2_G_E2 <= '1' ;
+         ELSE
+
+            A2_G_E2 <= '0' ;
+         END IF;
+         IF (addr_out(15 DOWNTO 8) >= end_addr_i(15 DOWNTO 8)) THEN
+            A1_G_E1 <= '1' ;
+         ELSE
+
+            A1_G_E1 <= '0' ;
+                 END IF;
+         IF (addr_out(7 DOWNTO 0) > (end_addr_i(7 DOWNTO 0) - std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) + '1')  ) THEN      -- OK
+
+
+
+
+
+            A0_G_E0 <= '1' ;
+         ELSE
+
+            A0_G_E0 <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+
+--testout <= std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),testout'length)) + '1';
+
+   PROCESS (addr_out,buf_avail_r, bl_out, end_addr_i, rst_i)
+   BEGIN
+      IF ((rst_i(5)) = '1') THEN
+         force_bl1 <= '0';
+
+
+      ELSIF (addr_out + std_logic_vector(to_unsigned((DWIDTH/8)*to_integer(unsigned(bl_out) ),32)) >= end_addr_i)  OR
+            (buf_avail_r <= 50 and PORT_MODE = "RD_MODE") THEN
+         force_bl1 <= '1' ;
+      ELSE
+         force_bl1 <= '0' ;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(6)) = '1') THEN
+            bl_out_reg <= fixed_bl_i;
+         ELSIF (bl_out_vld = '1') THEN
+
+            bl_out_reg <= bl_out;
+         END IF;
+      END IF;
+   END PROCESS;
+
+   xhdl12 <= bl_mode_reg;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (mode_load_pulse = '1') THEN
+            bl_out <= fixed_bl_i;
+         ELSIF (cmd_clk_en = '1') THEN
+            CASE xhdl12 IS
+               WHEN "00" =>
+                  bl_out <= bram_bl_i;
+               WHEN "01" =>
+                  bl_out <= fixed_bl_i;
+               WHEN "10" =>
+                  bl_out <= prbs_brlen;
+               WHEN OTHERS =>
+                  bl_out <= "000001";
+            END CASE;
+         END IF;
+      END IF;
+   END PROCESS;
+
+  --synthesis translate_off
+   PROCESS (bl_out)
+   BEGIN
+      IF (bl_out > "000010" AND FAMILY = "VIRTEX6") THEN
+         report "Error ! Not valid burst length"; --severity ERROR;
+      END IF;
+   END PROCESS;
+  --synthesis translate_on
+
+   xhdl13 : IF (CMD_PATTERN = "CGEN_PRBS" OR CMD_PATTERN = "CGEN_ALL") GENERATE
+
+
+
+
+      bl_prbs_gen : cmd_prbs_gen
+         GENERIC MAP (
+            TCQ         => TCQ,
+            family      => FAMILY,
+            prbs_cmd    => "BLEN",
+            addr_width  => 32,
+            seed_width  => 15,
+            prbs_width  => 20
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            clk_en          => cmd_clk_en,
+
+            prbs_seed_init  => load_seed_i,
+            prbs_seed_i     => cmd_seed_i(16 DOWNTO 2),
+            prbs_o          => prbs_bl
+         );
+
+   END GENERATE;
+--   xhdl14 <= "000001" WHEN (prbs_bl(5 DOWNTO 0) = "000000") ELSE prbs_bl(5 DOWNTO 0);
+   PROCESS (prbs_bl) BEGIN
+      IF (FAMILY = "SPARTAN6") THEN
+         if (prbs_bl(5 DOWNTO 0) = "000000") then
+--         prbs_brlen <= xhdl14;
+           prbs_brlen <= "000001";
+         else
+           prbs_brlen <= prbs_bl(5 DOWNTO 0);
+         end if;
+      ELSE
+         prbs_brlen <= "000010";
+      END IF;
+   END PROCESS;
+   
+   
+
+END trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/cmd_prbs_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/cmd_prbs_gen.vhd
new file mode 100755
index 0000000..ddba6fc
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/cmd_prbs_gen.vhd
@@ -0,0 +1,247 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: cmd_prbs_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:37 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:  This moduel use LFSR to generate random address, isntructions 
+--          or burst_length.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+
+ENTITY cmd_prbs_gen IS
+   GENERIC (
+      TCQ                  : time := 100 ps;   
+      FAMILY               : STRING := "SPARTAN6";
+      ADDR_WIDTH           : INTEGER := 29;
+      DWIDTH               : INTEGER := 32;
+      PRBS_CMD             : STRING := "ADDRESS";
+      PRBS_WIDTH           : INTEGER := 64;
+      SEED_WIDTH           : INTEGER := 32;      
+
+      PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+      PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00002000"
+   );
+   PORT (
+      
+      clk_i                : IN STD_LOGIC;
+      prbs_seed_init       : IN STD_LOGIC;
+      clk_en               : IN STD_LOGIC;
+      prbs_seed_i          : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
+      
+      prbs_o               : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
+   );
+END cmd_prbs_gen;
+
+ARCHITECTURE trans OF cmd_prbs_gen IS
+   SIGNAL ZEROS  : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+   SIGNAL prbs   : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
+   SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
+
+ function logb2 (val : integer) return integer is
+  variable vec_con : integer;
+  variable rtn : integer := 1;
+  begin
+    vec_con  := val;
+    for index in 0 to 31 loop
+      if(vec_con = 1) then
+        rtn := rtn + 1;
+        return(rtn);
+      end if;
+      vec_con := vec_con/2;
+      rtn := rtn + 1;
+    end loop;
+  end function logb2;
+
+
+BEGIN
+   
+   ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
+   
+   xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
+      
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (prbs_seed_init = '1') THEN
+               lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
+            ELSIF (clk_en = '1') THEN
+               lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
+               lfsr_q(63) <= lfsr_q(62) ;
+               lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
+               
+               lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
+               
+               lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
+               lfsr_q(1) <= lfsr_q(64) ;
+            END IF;
+         END IF;
+      END PROCESS;
+      
+      
+      PROCESS (lfsr_q(32 DOWNTO 1))
+      BEGIN
+         prbs <= lfsr_q(32 DOWNTO 1);
+      END PROCESS;
+      
+   END GENERATE;
+   
+   
+   xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
+      
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (prbs_seed_init = '1') THEN
+               lfsr_q <= prbs_seed_i ;
+            ELSIF (clk_en = '1') THEN
+               
+               lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
+               lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
+               lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
+               
+               lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
+               lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
+               lfsr_q(2) <= lfsr_q(1) ;
+               
+               lfsr_q(1) <= lfsr_q(32) ;
+            END IF;
+         END IF;
+      END PROCESS;
+      
+      
+      
+      PROCESS (lfsr_q(32 DOWNTO 1))
+      BEGIN
+
+        IF (FAMILY = "SPARTAN6") THEN
+          FOR i IN (logb2(DWIDTH) + 1) TO  SEED_WIDTH - 1 LOOP
+            IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
+                          prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
+            ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
+                          prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
+            ELSE
+              prbs(i) <= lfsr_q(i + 1);
+            END IF;
+          END LOOP;
+          prbs(logb2(DWIDTH) downto 0) <= (others => '0');
+        ELSE 
+          FOR i IN (logb2(DWIDTH) - 4) TO  SEED_WIDTH - 1 LOOP
+            IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
+                          prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
+            ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
+                          prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
+            ELSE
+              prbs(i) <= lfsr_q(i + 1);
+            END IF;
+          END LOOP;
+         prbs(logb2(DWIDTH) downto 0) <= (others => '0');
+        END IF;
+
+      END PROCESS;
+      
+      
+   END GENERATE;
+   
+   
+   xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
+      
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (prbs_seed_init = '1') THEN
+               lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
+            ELSIF (clk_en = '1') THEN
+               
+               lfsr_q(20) <= lfsr_q(19) ;
+               
+               lfsr_q(19) <= lfsr_q(18) ;
+               
+               lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
+               lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
+               
+               lfsr_q(1) <= lfsr_q(20) ;
+            END IF;
+         END IF;
+      END PROCESS;
+      
+      
+      PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
+      BEGIN
+            prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
+      END PROCESS;
+      
+      
+   END GENERATE;
+   
+   prbs_o <= prbs;
+   
+END trans;
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/data_prbs_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/data_prbs_gen.vhd
new file mode 100755
index 0000000..b372d7a
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/data_prbs_gen.vhd
@@ -0,0 +1,135 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: data_prbs_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:39 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:  This module is used LFSR to generate random data for memory 
+--          data write or memory data read comparison.The first data is 
+--          seeded by the input prbs_seed_i which is connected to memory address.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+
+ENTITY data_prbs_gen IS
+   GENERIC (
+      EYE_TEST        : STRING := "FALSE";
+      PRBS_WIDTH      : INTEGER := 32;
+      SEED_WIDTH      : INTEGER := 32
+--      TAPS            : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      clk_en          : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      prbs_seed_init  : IN STD_LOGIC;
+      prbs_seed_i     : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
+      
+      prbs_o          : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
+   );
+END data_prbs_gen;
+
+ARCHITECTURE trans OF data_prbs_gen IS
+   
+   SIGNAL prbs   : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
+   SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
+   SIGNAL i      : INTEGER;
+BEGIN
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
+            
+            
+            lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
+         ELSIF (clk_en = '1') THEN
+            
+            lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
+            lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
+            lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
+            
+            lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
+            lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
+            lfsr_q(2) <= lfsr_q(1);
+            
+            lfsr_q(1) <= lfsr_q(32);
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
+   BEGIN
+      prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
+   END PROCESS;
+   
+   
+   prbs_o <= prbs;
+   
+END trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/ddr2_model_c3.v b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/ddr2_model_c3.v
new file mode 100644
index 0000000..cba3e7f
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/ddr2_model_c3.v
@@ -0,0 +1,2031 @@
+/****************************************************************************************
+*
+*    File Name:  ddr2_model.v
+*      Version:  5.82
+*        Model:  BUS Functional
+*
+* Dependencies:  ddr2_model_parameters.vh
+*
+*  Description:  Micron SDRAM DDR2 (Double Data Rate 2)
+*
+*   Limitation:  - doesn't check for average refresh timings
+*                - positive ck and ck_n edges are used to form internal clock
+*                - positive dqs and dqs_n edges are used to latch data
+*                - test mode is not modeled
+*
+*         Note:  - Set simulator resolution to "ps" accuracy
+*                - Set Debug = 0 to disable $display messages
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+* Rev   Author   Date        Changes
+* ---------------------------------------------------------------------------------------
+* 1.00  JMK      07/29/03    Initial Release
+* 1.10  JMK      08/09/03    Timing Parameter updates to tIS, tIH, tDS, tDH
+* 2.20  JMK      08/07/03    General cleanup
+* 2.30  JMK      11/26/03    Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
+*                            Added AL_MIN and AL_MAX parameters.
+*                            Removed support for OCD.
+* 2.40  JMK      01/15/04    Removed verilog 2001 constructs.
+* 2.50  JMK      01/29/04    Removed tRP checks during Precharge command.
+* 2.60  JMK      04/20/04    Fixed tWTR check.
+* 2.70  JMK      04/30/04    Added tRFC maximum check.
+*                            Combined Self Refresh and Power Down always blocks.
+*                            Added Reset Function (CKE LOW Anytime).
+* 2.80  JMK      08/19/04    Precharge is treated as NOP when bank is not active.  
+*                            Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
+*                            tRFC maximum violation will only display one time.
+* 2.90  JMK      11/05/04    Fixed DQS checking during write.
+*                            Fixed false tRFC max assertion during power up and self ref.
+*                            Added warning for 200us CKE low time during initialization.
+*                            Added -3, -3E, and -37V speed grades to ddr2_parameters.v
+* 3.00  JMK      04/22/05    Removed ODT off requirement during power down.
+*                            Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
+*                            Added ODT status messages.
+*                            Updated the initialization sequence.
+*                            Disable ODT and CLK pins during self refresh.
+*                            Disable cmd and addr pins during power down and self refresh.
+* 3.10  JMK      06/07/05    Disable trpa checking if the part does not have 8 banks.
+*                            Changed tAXPD message from error to a warning.
+*                            Added tDSS checking.
+*                            Removed tDQSL checking during tWPRE and tWPST.
+*                            Fixed a burst order error during writes.
+*                            Renamed parameters file with .vh extension.
+* 3.20  JMK      07/18/05    Removed 14 tCK requirement from LMR to READ.
+* 3.30  JMK      08/03/05    Added check for interrupting a burst with auto precharge.
+* 4.00  JMK      11/21/05    Parameter names all UPPERCASE, signal names all lowercase.
+*                            Clock jitter can be tolerated within specification range.
+*                            Clock frequency is sampled from the CK pin.
+*                            Scaleable up to 64 DQ and 16 DQS bits.
+*                            Read data can be randomly skewed using RANDOM_OUT_DELAY.
+*                            Parameterized read and write DQS, and read DQ.
+*                            Initialization can be bypassed using initialize task.
+* 4.10  JMK      11/30/05    Fixed compile errors when `MAX_MEM was defined.
+* 4.20  JMK      12/09/05    Fixed memory addressing error when `MAX_MEM was defined.
+* 4.30  JMK      02/15/06    Added dummy write to initialization sequence.
+*                            Removed tWPST maximum checking.
+*                            Rising dqs_n edge latches data when enabled in EMR.
+*                            Fixed a sign error in the tJIT(cc) calculation.
+* 4.40  JMK      02/16/06    Fixed dummy write when`MAX_MEM was defined.
+* 4.50  JMK      02/27/06    Fixed extra tDQSS assertions.
+*                            Fixed tRCD and tWTR checking.
+*                            Errors entering Power Down or Self Refresh will cause reset.
+*                            Ignore dqs_n when disabled in EMR.
+* 5.00  JMK      04/24/06    Test stimulus now included from external file (subtest.vh)
+*                            Fixed tRFC max assertion during self refresh.
+*                            Fixed tANPD checking during Power Down.
+*                            Removed dummy write from initialization sequence.
+* 5.01  JMK      04/28/06    Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
+*                            Removed Auto Precharge error message during Power Down Enter.
+* 5.10  JMK      07/26/06    Created internal clock using ck and ck_n.
+*                            RDQS can only be enabled in EMR for x8 configurations.
+*                            CAS latency is checked vs frequency when DLL locks.
+*                            tMOD changed from tCK units to ns units.
+*                            Added 50 Ohm setting for Rtt in EMR.
+*                            Improved checking of DQS during writes.
+* 5.20  JMK      10/02/06    Fixed DQS checking for interrupting write to write and x16.
+* 5.30  JMK      05/25/07    Fixed checking for 0-Z transition on write postamble.
+* 5.50  JMK      05/30/08    Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.
+*                            Added a register delay to ddr2_module.v when RDIMM is defined.
+*                            Added multi-chip package model support in ddr2_mcp.v
+*                            Added High Temp Self Refresh rate setting in EMRS2[7]
+* 5.70  JMK      04/23/09    Updated tRPA definition
+*                            Increased internal width to 72 bit DQ bus
+* 5.80  SPH      08/12/09    Fixed tRAS maximum violation (only check if bank still open)
+* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW
+* 5.82  SPH      04/08/10    Correct debug message for SRT in EMR2         
+* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW
+* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW
+****************************************************************************************/
+
+// DO NOT CHANGE THE TIMESCALE
+// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
+`timescale 1ps / 1ps
+
+module ddr2_model_c3 (
+    ck,
+    ck_n,
+    cke,
+    cs_n,
+    ras_n,
+    cas_n,
+    we_n,
+    dm_rdqs,
+    ba,
+    addr,
+    dq,
+    dqs,
+    dqs_n,
+    rdqs_n,
+    odt
+);
+
+    `include "ddr2_model_parameters_c3.vh"
+
+    // text macros
+    `define DQ_PER_DQS DQ_BITS/DQS_BITS
+    `define BANKS      (1<<BA_BITS)
+    `define MAX_BITS   (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
+    `define MAX_SIZE   (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
+    `define MEM_SIZE   (1<<MEM_BITS)
+    `define MAX_PIPE   2*(AL_MAX + CL_MAX)
+
+    // Declare Ports
+    input   ck;
+    input   ck_n;
+    input   cke;
+    input   cs_n;
+    input   ras_n;
+    input   cas_n;
+    input   we_n;
+    inout   [DM_BITS-1:0]   dm_rdqs;
+    input   [BA_BITS-1:0]   ba;
+    input   [ADDR_BITS-1:0] addr;
+    inout   [DQ_BITS-1:0]   dq;
+    inout   [DQS_BITS-1:0]  dqs;
+    inout   [DQS_BITS-1:0]  dqs_n;
+    output  [DQS_BITS-1:0]  rdqs_n;
+    input   odt;
+                            
+    // clock jitter
+    real    tck_avg;
+    time    tck_sample [TDLLK-1:0];
+    time    tch_sample [TDLLK-1:0];
+    time    tcl_sample [TDLLK-1:0];
+    time    tck_i;
+    time    tch_i;
+    time    tcl_i;
+    real    tch_avg;
+    real    tcl_avg;
+    time    tm_ck_pos;
+    time    tm_ck_neg;
+    real    tjit_per_rtime;
+    integer tjit_cc_time;
+    real    terr_nper_rtime;
+
+    // clock skew
+    real    out_delay;
+    integer dqsck [DQS_BITS-1:0];
+    integer dqsck_min;
+    integer dqsck_max;
+    integer dqsq_min;
+    integer dqsq_max;
+    integer seed;
+
+    // Mode Registers
+    reg     burst_order;
+    reg     [BL_BITS:0] burst_length;
+    integer cas_latency;
+    integer additive_latency;
+    reg     dll_reset;
+    reg     dll_locked;
+    reg     dll_en;
+    integer write_recovery;
+    reg     low_power;
+    reg     [1:0] odt_rtt;
+    reg     odt_en;
+    reg     [2:0] ocd;
+    reg     dqs_n_en;
+    reg     rdqs_en;
+    reg     out_en;
+    integer read_latency;
+    integer write_latency;
+
+    // cmd encoding
+    parameter
+        LOAD_MODE = 4'b0000,
+        REFRESH   = 4'b0001,
+        PRECHARGE = 4'b0010,
+        ACTIVATE  = 4'b0011,
+        WRITE     = 4'b0100,
+        READ      = 4'b0101,
+        NOP       = 4'b0111,
+        PWR_DOWN  = 4'b1000,
+        SELF_REF  = 4'b1001
+    ;
+
+    reg [8*9-1:0] cmd_string [9:0];
+    initial begin
+        cmd_string[LOAD_MODE] = "Load Mode";
+        cmd_string[REFRESH  ] = "Refresh  ";
+        cmd_string[PRECHARGE] = "Precharge";
+        cmd_string[ACTIVATE ] = "Activate ";
+        cmd_string[WRITE    ] = "Write    ";
+        cmd_string[READ     ] = "Read     ";
+        cmd_string[NOP      ] = "No Op    ";
+        cmd_string[PWR_DOWN ] = "Pwr Down ";
+        cmd_string[SELF_REF ] = "Self Ref ";
+    end
+
+    // command state
+    reg     [`BANKS-1:0] active_bank;
+    reg     [`BANKS-1:0] auto_precharge_bank;
+    reg     [`BANKS-1:0] write_precharge_bank;
+    reg     [`BANKS-1:0] read_precharge_bank;
+    reg     [ROW_BITS-1:0] active_row [`BANKS-1:0];
+    reg     in_power_down;
+    reg     in_self_refresh;
+    reg     [3:0] init_mode_reg;
+    reg     init_done;
+    integer init_step;
+    reg     er_trfc_max;
+    reg     odt_state;
+    reg     prev_odt;
+
+    // cmd timers/counters
+    integer ref_cntr;
+    integer ck_cntr;
+    integer ck_load_mode;
+    integer ck_write;
+    integer ck_read;
+    integer ck_write_ap;
+    integer ck_power_down;
+    integer ck_slow_exit_pd;
+    integer ck_self_refresh;
+    integer ck_cke;
+    integer ck_odt;
+    integer ck_dll_reset;
+    integer ck_bank_write     [`BANKS-1:0];
+    integer ck_bank_read      [`BANKS-1:0];
+    time    tm_refresh;
+    time    tm_precharge;
+    time    tm_precharge_all;
+    time    tm_activate;
+    time    tm_write_end;
+    time    tm_self_refresh;
+    time    tm_odt_en;
+    time    tm_bank_precharge [`BANKS-1:0];
+    time    tm_bank_activate  [`BANKS-1:0];
+    time    tm_bank_write_end [`BANKS-1:0];
+    time    tm_bank_read_end  [`BANKS-1:0];
+
+    // pipelines
+    reg     [`MAX_PIPE:0]   al_pipeline;
+    reg     [`MAX_PIPE:0]   wr_pipeline;
+    reg     [`MAX_PIPE:0]   rd_pipeline;
+    reg     [`MAX_PIPE:0]   odt_pipeline;
+    reg     [BA_BITS-1:0]   ba_pipeline  [`MAX_PIPE:0];
+    reg     [ROW_BITS-1:0]  row_pipeline [`MAX_PIPE:0];
+    reg     [COL_BITS-1:0]  col_pipeline [`MAX_PIPE:0];
+    reg     prev_cke;
+    
+    // data state
+    reg     [BL_MAX*DQ_BITS-1:0] memory_data;
+    reg     [BL_MAX*DQ_BITS-1:0] bit_mask;
+    reg     [BL_BITS-1:0]        burst_position;
+    reg     [BL_BITS:0]          burst_cntr;
+    reg     [DQ_BITS-1:0]        dq_temp;
+    reg     [35:0] check_write_postamble;
+    reg     [35:0] check_write_preamble;
+    reg     [35:0] check_write_dqs_high;
+    reg     [35:0] check_write_dqs_low;
+    reg     [17:0] check_dm_tdipw;
+    reg     [71:0] check_dq_tdipw;
+
+    // data timers/counters
+    time    tm_cke;
+    time    tm_odt;
+    time    tm_tdqss;
+    time    tm_dm        [17:0];
+    time    tm_dqs       [17:0];
+    time    tm_dqs_pos   [35:0];
+    time    tm_dqss_pos  [35:0];
+    time    tm_dqs_neg   [35:0];
+    time    tm_dq        [71:0];
+    time    tm_cmd_addr  [22:0];
+    reg [8*7-1:0] cmd_addr_string [22:0];
+    initial begin
+        cmd_addr_string[ 0] = "CS_N   ";
+        cmd_addr_string[ 1] = "RAS_N  ";
+        cmd_addr_string[ 2] = "CAS_N  ";
+        cmd_addr_string[ 3] = "WE_N   ";
+        cmd_addr_string[ 4] = "BA 0   ";
+        cmd_addr_string[ 5] = "BA 1   ";
+        cmd_addr_string[ 6] = "BA 2   ";
+        cmd_addr_string[ 7] = "ADDR  0";
+        cmd_addr_string[ 8] = "ADDR  1";
+        cmd_addr_string[ 9] = "ADDR  2";
+        cmd_addr_string[10] = "ADDR  3";
+        cmd_addr_string[11] = "ADDR  4";
+        cmd_addr_string[12] = "ADDR  5";
+        cmd_addr_string[13] = "ADDR  6";
+        cmd_addr_string[14] = "ADDR  7";
+        cmd_addr_string[15] = "ADDR  8";
+        cmd_addr_string[16] = "ADDR  9";
+        cmd_addr_string[17] = "ADDR 10";
+        cmd_addr_string[18] = "ADDR 11";
+        cmd_addr_string[19] = "ADDR 12";
+        cmd_addr_string[20] = "ADDR 13";
+        cmd_addr_string[21] = "ADDR 14";
+        cmd_addr_string[22] = "ADDR 15";
+    end
+
+    reg [8*5-1:0] dqs_string [1:0];
+    initial begin
+        dqs_string[0] = "DQS  ";
+        dqs_string[1] = "DQS_N";
+    end
+
+    // Memory Storage
+`ifdef MAX_MEM
+    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MAX_SIZE-1];
+`else
+    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MEM_SIZE-1];
+    reg     [`MAX_BITS-1:0]      address [0:`MEM_SIZE-1];
+    reg     [MEM_BITS:0]         memory_index;
+    reg     [MEM_BITS:0]         memory_used;
+`endif
+
+    // receive
+    reg            ck_in;
+    reg            ck_n_in;
+    reg            cke_in;
+    reg            cs_n_in;
+    reg            ras_n_in;
+    reg            cas_n_in;
+    reg            we_n_in;
+    reg     [17:0] dm_in;
+    reg     [2:0]  ba_in;
+    reg     [15:0] addr_in;
+    reg     [71:0] dq_in;
+    reg     [35:0] dqs_in;
+    reg            odt_in;
+
+    reg     [17:0] dm_in_pos;
+    reg     [17:0] dm_in_neg;
+    reg     [71:0] dq_in_pos;
+    reg     [71:0] dq_in_neg;
+    reg            dq_in_valid;
+    reg            dqs_in_valid;
+    integer        wdqs_cntr;
+    integer        wdq_cntr;
+    integer        wdqs_pos_cntr [35:0];
+    reg            b2b_write;
+    reg     [35:0] prev_dqs_in;
+    reg            diff_ck;
+
+    always @(ck     ) ck_in     <= #BUS_DELAY ck;
+    always @(ck_n   ) ck_n_in   <= #BUS_DELAY ck_n;
+    always @(cke    ) cke_in    <= #BUS_DELAY cke;
+    always @(cs_n   ) cs_n_in   <= #BUS_DELAY cs_n;
+    always @(ras_n  ) ras_n_in  <= #BUS_DELAY ras_n;
+    always @(cas_n  ) cas_n_in  <= #BUS_DELAY cas_n;
+    always @(we_n   ) we_n_in   <= #BUS_DELAY we_n;
+    always @(dm_rdqs) dm_in     <= #BUS_DELAY dm_rdqs;
+    always @(ba     ) ba_in     <= #BUS_DELAY ba;
+    always @(addr   ) addr_in   <= #BUS_DELAY addr;
+    always @(dq     ) dq_in     <= #BUS_DELAY dq;
+    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;
+    always @(odt    ) odt_in    <= #BUS_DELAY odt;
+    // create internal clock
+    always @(posedge ck_in)   diff_ck <= ck_in;
+    always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
+
+    wire    [17:0] dqs_even = dqs_in[17:0];
+    wire    [17:0] dqs_odd  = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];
+    wire    [3:0]  cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP;  //deselect = nop 
+
+    // transmit
+    reg                    dqs_out_en;
+    reg     [DQS_BITS-1:0] dqs_out_en_dly;
+    reg                    dqs_out;
+    reg     [DQS_BITS-1:0] dqs_out_dly;
+    reg                    dq_out_en;
+    reg     [DQ_BITS-1:0]  dq_out_en_dly;
+    reg     [DQ_BITS-1:0]  dq_out;
+    reg     [DQ_BITS-1:0]  dq_out_dly;
+    integer                rdqsen_cntr;
+    integer                rdqs_cntr;
+    integer                rdqen_cntr;
+    integer                rdq_cntr;
+
+    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}});
+    bufif1 buf_dm     [DM_BITS-1:0]  (dm_rdqs, dqs_out_dly,  dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
+    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
+    bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n,  ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
+    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}});
+
+    initial begin
+        if (BL_MAX < 2) 
+            $display("%m ERROR: BL_MAX parameter must be >= 2.  \nBL_MAX = %d", BL_MAX);
+        if ((1<<BO_BITS) > BL_MAX) 
+            $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
+        $timeformat (-12, 1, " ps", 1);
+        reset_task;
+        seed = RANDOM_SEED;
+        ck_cntr = 0;
+    end
+
+    // calculate the absolute value of a real number
+    function real abs_value;
+    input arg;
+    real arg;
+    begin
+        if (arg < 0.0)
+            abs_value = -1.0 * arg;
+        else
+            abs_value = arg;
+    end
+    endfunction
+
+`ifdef MAX_MEM
+`else
+    function get_index;
+        input [`MAX_BITS-1:0] addr;
+        begin : index
+            get_index = 0;
+            for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
+                if (address[memory_index] == addr) begin
+                    get_index = 1;
+                    disable index;
+                end
+            end
+        end
+    endfunction
+`endif
+
+    task memory_write;
+        input  [BA_BITS-1:0]  bank;
+        input  [ROW_BITS-1:0] row;
+        input  [COL_BITS-1:0] col;
+        input  [BL_MAX*DQ_BITS-1:0] data;
+        reg    [`MAX_BITS-1:0] addr;
+        begin
+            // chop off the lowest address bits
+            addr = {bank, row, col}/BL_MAX;
+`ifdef MAX_MEM
+            memory[addr] = data;
+`else
+            if (get_index(addr)) begin
+                address[memory_index] = addr;
+                memory[memory_index] = data;
+            end else if (memory_used == `MEM_SIZE) begin
+                $display ("%m: at time %t ERROR: Memory overflow.  Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
+                if (STOP_ON_ERROR) $stop(0);
+            end else begin
+                address[memory_used] = addr;
+                memory[memory_used] = data;
+                memory_used = memory_used + 1;
+            end
+`endif
+        end
+    endtask
+
+    task memory_read;
+        input  [BA_BITS-1:0]  bank;
+        input  [ROW_BITS-1:0] row;
+        input  [COL_BITS-1:0] col;
+        output [BL_MAX*DQ_BITS-1:0] data;
+        reg    [`MAX_BITS-1:0] addr;
+        begin
+            // chop off the lowest address bits
+            addr = {bank, row, col}/BL_MAX;
+`ifdef MAX_MEM
+            data = memory[addr];
+`else
+            if (get_index(addr)) begin
+                data = memory[memory_index];
+            end else begin
+                data = {BL_MAX*DQ_BITS{1'bx}};
+            end
+`endif
+        end
+    endtask
+
+    // Before this task runs, the model must be in a valid state for precharge power down.
+    // After this task runs, NOP commands must be issued until tRFC has been met
+    task initialize;
+        input [ADDR_BITS-1:0] mode_reg0;
+        input [ADDR_BITS-1:0] mode_reg1;
+        input [ADDR_BITS-1:0] mode_reg2;
+        input [ADDR_BITS-1:0] mode_reg3;
+        begin
+            if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
+            cmd_task(1,       NOP, 'bx, 'bx);
+            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL
+            cmd_task(1, LOAD_MODE, 3, mode_reg3);
+            cmd_task(1, LOAD_MODE, 2, mode_reg2);
+            cmd_task(1, LOAD_MODE, 1, mode_reg1);
+            cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
+            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL
+            cmd_task(1,   REFRESH, 'bx, 'bx);
+            cmd_task(1,   REFRESH, 'bx, 'bx);
+            cmd_task(1, LOAD_MODE, 0, mode_reg0);
+            cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
+            cmd_task(1, LOAD_MODE, 1, mode_reg1);
+            cmd_task(0,       NOP, 'bx, 'bx);
+        end
+    endtask
+    
+    task reset_task;
+        integer i;
+        begin
+            // disable inputs
+            dq_in_valid          = 0;
+            dqs_in_valid        <= 0;
+            wdqs_cntr            = 0;
+            wdq_cntr             = 0;
+            for (i=0; i<36; i=i+1) begin
+                wdqs_pos_cntr[i]    <= 0;
+            end
+            b2b_write           <= 0;
+            // disable outputs
+            out_en               = 0;
+            dqs_n_en             = 0;
+            rdqs_en              = 0;
+            dq_out_en            = 0;
+            rdq_cntr             = 0;
+            dqs_out_en           = 0;
+            rdqs_cntr            = 0;
+            // disable ODT
+            odt_en               = 0;
+            odt_state            = 0;
+            // reset bank state
+            active_bank          = {`BANKS{1'b1}};
+            auto_precharge_bank  = 0;
+	        read_precharge_bank  = 0;
+	        write_precharge_bank = 0;
+            // require initialization sequence
+            init_done            = 0;
+            init_step            = 0;
+            init_mode_reg        = 0;
+            // reset DLL
+            dll_en               = 0;
+            dll_reset            = 0;
+            dll_locked           = 0;
+            ocd                  = 0;
+            // exit power down and self refresh
+            in_power_down        = 0;
+            in_self_refresh      = 0;
+            // clear pipelines
+            al_pipeline          = 0;
+            wr_pipeline          = 0;
+            rd_pipeline          = 0;
+            odt_pipeline         = 0;
+            // clear memory
+`ifdef MAX_MEM
+            for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
+                memory[i] <= 'bx;
+            end
+`else
+            memory_used <= 0; //erase memory
+`endif
+            // clear maximum timing checks
+            tm_refresh <= 'bx;
+            for (i=0; i<`BANKS; i=i+1) begin
+                tm_bank_activate[i] <= 'bx;
+            end
+        end
+    endtask
+
+    task chk_err;
+        input samebank;
+        input [BA_BITS-1:0] bank;
+        input [3:0] fromcmd;
+        input [3:0] cmd;
+        reg err;
+    begin
+        // all matching case expressions will be evaluated
+        casex ({samebank, fromcmd, cmd})
+            {1'b0, LOAD_MODE, 4'b0xxx  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                       $display ("%m: at time %t ERROR:  tMRD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, LOAD_MODE, 4'b100x  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                 begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time);                    init_done = 0; end end
+            {1'b0, REFRESH  , 4'b0xxx  } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                       $display ("%m: at time %t ERROR:  tRFC violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, REFRESH  , PWR_DOWN } : ; // 1 tCK
+            {1'b0, REFRESH  , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                 begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time);                       init_done = 0; end end
+            {1'b0, PRECHARGE, 4'b000x  } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);
+                                                 if ($time - tm_precharge < TRP)                                                                                          $display ("%m: at time %t ERROR:   tRP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA))                                                                          $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);
+                                                 if (DEBUG && ($time - tm_bank_precharge[bank] < TRP))                                                                    $display ("%m: at time %t INFO: Precharge bank %d interruption during %s", $time, cmd_string[cmd], bank);  end
+            {1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);
+                                                 if ($time - tm_bank_precharge[bank] < TRP)                                                                               $display ("%m: at time %t ERROR:   tRP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
+            {1'b0, PRECHARGE, SELF_REF } : begin if (($time - tm_precharge_all < TRPA) || ($time - tm_precharge < TRP))                                             begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time);                     init_done = 0; end end
+            {1'b0, ACTIVATE , REFRESH  } : begin if ($time - tm_activate < TRC)                                                                                           $display ("%m: at time %t ERROR:   tRC violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b1, ACTIVATE , PRECHARGE} : begin if (($time - tm_bank_activate[bank] > TRAS_MAX) && (active_bank[bank] === 1'b1))                                         $display ("%m: at time %t ERROR:  tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
+                                                 if ($time - tm_bank_activate[bank] < TRAS_MIN)                                                                           $display ("%m: at time %t ERROR:  tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
+            {1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD)                                                                                          $display ("%m: at time %t ERROR:  tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC)                                                                                $display ("%m: at time %t ERROR:   tRC violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b1, ACTIVATE , 4'b010x  } : ; // tRCD is checked outside this task
+            {1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
+            {1'b1, WRITE    , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR))        $display ("%m: at time %t ERROR:   tWR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , WRITE    } : begin if (ck_cntr - ck_write < TCCD)                                                                                           $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , READ     } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency))           $display ("%m: at time %t ERROR:  tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && (
+                                                    |write_precharge_bank
+                                                 || (ck_cntr - ck_write_ap < 1)
+                                                 || (ck_cntr - ck_write < write_latency + burst_length/2 + 2) 
+                                                 || ($time - tm_write_end < TWTR)))                                                                                 begin $display ("%m: at time %t INFO: Write to Reset condition", $time);                         init_done = 0; end end
+            {1'b1, READ     , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP))       $display ("%m: at time %t ERROR:  tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , WRITE    } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency))                 $display ("%m: at time %t ERROR:  tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , READ     } : begin if (ck_cntr - ck_read < TCCD)                                                                                            $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1))                           begin $display ("%m: at time %t INFO: Read to Reset condition", $time);                          init_done = 0; end end
+            {1'b0, PWR_DOWN , 4'b00xx  } : begin if (ck_cntr - ck_power_down < TXP)                                                                                       $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, PWR_DOWN , WRITE    } : begin if (ck_cntr - ck_power_down < TXP)                                                                                       $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, PWR_DOWN , READ     } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency)                                                               $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
+                                            else if (ck_cntr - ck_power_down < TXARD)                                                                                     $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , 4'b00xx  } : begin if ($time - tm_self_refresh < TXSNR)                                                                                     $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , WRITE    } : begin if ($time - tm_self_refresh < TXSNR)                                                                                     $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , READ     } : begin if (ck_cntr - ck_self_refresh < TXSRD)                                                                                   $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, 4'b100x  , 4'b100x  } : begin if (ck_cntr - ck_cke < TCKE)                                                                                       begin $display ("%m: at time %t ERROR:  tCKE violation on CKE", $time);                          init_done = 0; end end
+        endcase
+    end
+    endtask
+
+    task cmd_task;
+        input cke;
+        input [2:0] cmd;
+        input [BA_BITS-1:0] bank;
+        input [ADDR_BITS-1:0] addr;
+        reg [`BANKS:0] i;
+        integer j;
+        reg [`BANKS:0] tfaw_cntr;
+        reg [COL_BITS-1:0] col;
+        begin
+
+            // tRFC max check
+            if (!er_trfc_max && !in_self_refresh) begin
+                if ($time - tm_refresh > TRFC_MAX) begin
+                    $display ("%m: at time %t ERROR:  tRFC maximum violation during %s", $time, cmd_string[cmd]);
+                    er_trfc_max = 1;
+                end
+            end
+            if (cke) begin
+                if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin
+                    for (j=0; j<NOP; j=j+1) begin
+                        chk_err(1'b0, bank, j, cmd);
+                        chk_err(1'b1, bank, j, cmd);
+                    end
+                    chk_err(1'b0, bank, PWR_DOWN, cmd);
+                    chk_err(1'b0, bank, SELF_REF, cmd);
+                end
+
+                case (cmd)
+                    LOAD_MODE : begin
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
+                            case (bank)
+                                0 : begin
+                                    // Burst Length
+                                    burst_length = 1<<addr[2:0];
+                                    if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
+                                    end
+                                    // Burst Order
+                                    burst_order = addr[3];
+                                    if (!burst_order) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
+                                    end else if (burst_order) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
+                                    end
+                                    // CAS Latency
+                                    cas_latency = addr[6:4];
+                                    read_latency = cas_latency + additive_latency;
+                                    write_latency = read_latency - 1;
+                                    if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
+                                    end
+                                    // Test Mode
+                                    if (!addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
+                                    end
+                                    // DLL Reset
+                                    dll_reset = addr[8];
+                                    if (!dll_reset) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
+                                    end else if (dll_reset) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
+                                        dll_locked = 0;
+                                        ck_dll_reset <= ck_cntr;
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
+                                    end
+                                    // Write Recovery
+                                    write_recovery  = addr[11:9] + 1;
+                                    if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
+                                    end
+                                    // Power Down Mode
+                                    low_power = addr[12];
+                                    if (!low_power) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
+                                    end else if (low_power) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
+                                    end
+                                end
+                                1 : begin
+                                    // DLL Enable
+                                    dll_en = !addr[0];
+                                    if (!dll_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (dll_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
+                                    end
+                                    // Output Drive Strength
+                                    if (!addr[1]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
+                                    end else if (addr[1]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
+                                    end
+                                    // ODT Rtt
+                                    odt_rtt = {addr[6], addr[2]};
+                                    if (odt_rtt == 2'b00) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
+                                        odt_en = 0;
+                                    end else if (odt_rtt == 2'b01) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else if (odt_rtt == 2'b10) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else if (odt_rtt == 2'b11) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
+                                        odt_en = 0;
+                                    end
+                                    // Additive Latency
+                                    additive_latency = addr[5:3];
+                                    read_latency = cas_latency + additive_latency;
+                                    write_latency = read_latency - 1;
+                                    if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
+                                    end
+                                    // OCD Program
+                                    ocd = addr[9:7];
+                                    if (ocd == 3'b000) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
+                                    end else if (ocd == 3'b111) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
+                                    end
+
+                                    // DQS_N Enable
+                                    dqs_n_en = !addr[10];
+                                    if (!dqs_n_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (dqs_n_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
+                                    end 
+                                    // RDQS Enable
+                                    rdqs_en = addr[11];
+                                    if (!rdqs_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (rdqs_en) begin
+`ifdef x8
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
+`else
+                                        $display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable.  RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
+                                        rdqs_en = 0;
+`endif
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
+                                    end 
+                                    // Output Enable
+                                    out_en = !addr[12];
+                                    if (!out_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (out_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
+                                    end 
+                                end
+                                2 : begin
+                                    // High Temperature Self Refresh rate
+                                    if (!addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 1X (0C-85C)", $time, cmd_string[cmd], bank);
+                                    end else if (addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 2X (>85C)", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]);
+                                    end
+                                    if ((addr & ~(1<<7)) !== 0) begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
+                                    end
+                                end
+                                3 : begin
+                                    if (addr !== 0) begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
+                                    end
+                                end
+                            endcase
+                            init_mode_reg[bank] = 1;
+                            ck_load_mode <= ck_cntr;
+                        end
+                    end
+                    REFRESH : begin
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
+                            er_trfc_max = 0;
+                            ref_cntr = ref_cntr + 1;
+                            tm_refresh <= $time;
+                        end
+                    end
+                    PRECHARGE : begin
+                        if (addr[AP]) begin
+                            // tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
+                            // the number of banks already open or closed.
+                            for (i=0; i<`BANKS; i=i+1) begin
+                                for (j=0; j<NOP; j=j+1) begin
+                                    chk_err(1'b0, i, j, cmd);
+                                    chk_err(1'b1, i, j, cmd);
+                                end
+                                chk_err(1'b0, i, PWR_DOWN, cmd);
+                                chk_err(1'b0, i, SELF_REF, cmd);
+                            end
+                            if (|auto_precharge_bank) begin
+                                $display ("%m: at time %t ERROR: %s All Failure.  Auto Precharge is scheduled.", $time, cmd_string[cmd]);
+                                if (STOP_ON_ERROR) $stop(0);
+                            end else begin
+                                if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
+                                active_bank = 0;
+                                tm_precharge_all <= $time;
+                            end
+                        end else begin
+                            // A PRECHARGE command is allowed if there is no open row in that bank (idle state) 
+                            // or if the previously open row is already in the process of precharging. 
+                            // However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
+                            if (auto_precharge_bank[bank]) begin
+                                $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                                if (STOP_ON_ERROR) $stop(0);
+                            end else begin
+                                if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], bank);
+                                active_bank[bank] = 1'b0;
+                                tm_bank_precharge[bank] <= $time;
+                                tm_precharge <= $time;
+                            end
+                        end
+                    end
+                    ACTIVATE : begin
+                        if (`BANKS == 8) begin
+                            tfaw_cntr = 0;
+                            for (i=0; i<`BANKS; i=i+1) begin
+                                if ($time - tm_bank_activate[i] < TFAW) begin
+                                    tfaw_cntr = tfaw_cntr + 1;
+                                end
+                            end
+                            if (tfaw_cntr > 3) begin
+                                $display ("%m: at time %t ERROR:  tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
+                            end
+                        end
+
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr >= 1<<ROW_BITS) begin
+                                $display ("%m: at time %t WARNING: row = %h does not exist.  Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
+                            active_bank[bank] = 1'b1;
+                            active_row[bank] = addr;
+                            tm_bank_activate[bank] <= $time;
+                            tm_activate <= $time;
+                        end
+                        
+                    end
+                    WRITE : begin
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (!active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (auto_precharge_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr[AP]) begin
+                                auto_precharge_bank[bank] = 1'b1;
+                                write_precharge_bank[bank] = 1'b1;
+                            end
+                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
+                            if (col >= 1<<COL_BITS) begin
+                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
+                            wr_pipeline[2*write_latency + 1]  = 1;
+                            ba_pipeline[2*write_latency + 1]  = bank;
+                            row_pipeline[2*write_latency + 1] = active_row[bank];
+                            col_pipeline[2*write_latency + 1] = col;
+                            ck_bank_write[bank] <= ck_cntr;
+                            ck_write <= ck_cntr;
+                        end
+                    end
+                    READ : begin
+                        if (!dll_locked)
+                            $display ("%m: at time %t WARNING: %s prior to DLL locked.  Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (!active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (auto_precharge_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr[AP]) begin
+                                auto_precharge_bank[bank] = 1'b1;
+                                read_precharge_bank[bank] = 1'b1;
+                            end
+                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
+                            if (col >= 1<<COL_BITS) begin
+                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
+                            rd_pipeline[2*read_latency - 1]  = 1;
+                            ba_pipeline[2*read_latency - 1]  = bank;
+                            row_pipeline[2*read_latency - 1] = active_row[bank];
+                            col_pipeline[2*read_latency - 1] = col;
+                            ck_bank_read[bank] <= ck_cntr;
+                            ck_read <= ck_cntr;
+                        end
+                    end
+                    NOP: begin
+                        if (in_power_down) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
+                            in_power_down = 0;
+                            if (|active_bank & low_power) begin // slow exit active power down
+                                ck_slow_exit_pd <= ck_cntr;
+                            end
+                            ck_power_down <= ck_cntr;
+                        end
+                        if (in_self_refresh) begin
+                            if ($time - tm_cke < TISXR)
+                                $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
+                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
+                            in_self_refresh = 0;
+                            ck_dll_reset <= ck_cntr;
+                            ck_self_refresh <= ck_cntr;
+                            tm_self_refresh <= $time;
+                            tm_refresh <= $time;
+                        end
+                    end
+                endcase
+                if ((prev_cke !== 1) && (cmd !== NOP)) begin
+                    $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
+                end
+                if (!init_done) begin
+                    case (init_step)
+                        0 : begin
+                            if ($time < 200000000) 
+                                $display ("%m: at time %t WARNING: 200 us is required before CKE goes active.", $time);
+//                          if (cmd_chk + 200000000 > $time)
+//                              $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
+                            init_step = init_step + 1;
+                        end
+                        1 : if (dll_en)        init_step = init_step + 1;
+                        2 : begin
+                            if (&init_mode_reg && dll_reset) begin
+                                active_bank = {`BANKS{1'b1}};   // require Precharge All or bank Precharges
+                                ref_cntr = 0;                   // require refresh
+                                init_step = init_step + 1;
+                            end
+                        end
+                        3 : if (ref_cntr == 2) begin
+                            init_step = init_step + 1;
+                        end
+                        4 : if (!dll_reset)    init_step = init_step + 1;
+                        5 : if (ocd == 3'b111) init_step = init_step + 1;
+                        6 : begin
+                            if (ocd == 3'b000) begin
+                                if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
+                                init_done = 1;
+                            end
+                        end
+                    endcase
+                end
+            end else if (prev_cke) begin
+                if ((!init_done) && (init_step > 1)) begin
+                    $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
+                    if (STOP_ON_ERROR) $stop(0);
+                end
+                case (cmd)
+                    REFRESH : begin
+                        for (j=0; j<NOP; j=j+1) begin
+                            chk_err(1'b0, bank, j, SELF_REF);
+                        end
+                        chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
+                        chk_err(1'b0, bank, SELF_REF, SELF_REF);
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: Self Refresh Failure.  All banks must be Precharged.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                            init_done = 0;
+                        end else if (odt_en && odt_state) begin
+                            $display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                            init_done = 0;
+                        end else if (!init_done) begin
+                            $display ("%m: at time %t ERROR: Self Refresh Failure.  Initialization sequence is not complete.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
+                            in_self_refresh = 1;
+                            dll_locked = 0;
+                        end
+                    end
+                    NOP : begin
+                        // entering slow_exit or precharge power down and tANPD has not been satisfied
+                        if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
+                            $display ("%m: at time %t WARNING: tANPD violation during %s.  Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
+                        for (j=0; j<NOP; j=j+1) begin
+                            chk_err(1'b0, bank, j, PWR_DOWN);
+                        end
+                        chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
+                        chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
+
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: Power Down Failure.  Initialization sequence is not complete.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) begin
+                                if (|active_bank) begin
+                                    $display ("%m: at time %t INFO: Active Power Down Enter", $time);
+                                end else begin
+                                    $display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
+                                end
+                            end
+                            in_power_down = 1;
+                        end
+                    end
+                    default : begin
+                        $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
+                        init_done = 0;
+                    end
+                endcase
+                if (!init_done) begin
+                    if (DEBUG) $display ("%m: at time %t WARNING: Reset has occurred.  Device must be re-initialized.", $time);
+                    reset_task;
+                end
+            end
+            prev_cke  = cke;
+        end
+    endtask
+
+    task data_task;
+        reg [BA_BITS-1:0] bank;
+        reg [ROW_BITS-1:0] row;
+        reg [COL_BITS-1:0] col;
+        integer i;
+        integer j;
+        begin
+
+            if (diff_ck) begin
+                for (i=0; i<36; i=i+1) begin
+                    if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
+                        $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    if (check_write_dqs_high[i])
+                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/18], i%18);
+                end
+                check_write_dqs_high <= 0;
+            end else begin
+                for (i=0; i<36; i=i+1) begin
+                    if (dll_locked && dq_in_valid) begin
+                        tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
+                        if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
+                            $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18); 
+                    end
+                    if (check_write_dqs_low[i])
+                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18);
+                end
+                check_write_preamble <= 0;
+                check_write_postamble <= 0;
+                check_write_dqs_low <= 0;
+            end
+
+            if (wr_pipeline[0] || rd_pipeline[0]) begin
+                bank = ba_pipeline[0];
+                row = row_pipeline[0];
+                col = col_pipeline[0];
+                burst_cntr = 0;
+                memory_read(bank, row, col, memory_data);
+            end
+
+            // burst counter
+            if (burst_cntr < burst_length) begin
+                burst_position = col ^ burst_cntr;
+                if (!burst_order) begin
+                    burst_position[BO_BITS-1:0] = col + burst_cntr;
+                end
+                burst_cntr = burst_cntr + 1;
+            end
+
+            // write dqs counter
+            if (wr_pipeline[WDQS_PRE + 1]) begin
+                wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
+            end
+            // write dqs
+            if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
+                check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+            end
+            if (wdqs_cntr > 1) begin  // write data
+                if ((wdqs_cntr - WDQS_PST)%2) begin
+                    check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+                end else begin
+                    check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+                end
+            end
+            if (wdqs_cntr == WDQS_PST) begin // write postamble
+                check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+            end 
+            if (wdqs_cntr > 0) begin
+                wdqs_cntr = wdqs_cntr - 1;
+            end
+
+            // write dq
+            if (dq_in_valid) begin // write data
+                bit_mask = 0;
+                if (diff_ck) begin
+                    for (i=0; i<DM_BITS; i=i+1) begin
+                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
+                    end
+                    memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
+                end else begin
+                    for (i=0; i<DM_BITS; i=i+1) begin
+                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
+                    end
+                    memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
+                end
+                dq_temp = memory_data>>(burst_position*DQ_BITS);
+                if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
+                if (burst_cntr%BL_MIN == 0) begin
+                    memory_write(bank, row, col, memory_data);
+                end
+            end
+            if (wr_pipeline[1]) begin
+                wdq_cntr = burst_length;
+            end
+            if (wdq_cntr > 0) begin
+                wdq_cntr = wdq_cntr - 1;
+                dq_in_valid = 1'b1;
+            end else begin
+                dq_in_valid = 1'b0;
+                dqs_in_valid <= 1'b0;
+                for (i=0; i<36; i=i+1) begin
+                    wdqs_pos_cntr[i] <= 0;
+                end
+            end
+            if (wr_pipeline[0]) begin
+                b2b_write <= 1'b0;
+            end
+            if (wr_pipeline[2]) begin
+                if (dqs_in_valid) begin
+                    b2b_write <= 1'b1;
+                end
+                dqs_in_valid <= 1'b1;
+            end
+            // read dqs enable counter
+            if (rd_pipeline[RDQSEN_PRE]) begin
+                rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
+            end
+            if (rdqsen_cntr > 0) begin
+                rdqsen_cntr = rdqsen_cntr - 1;
+                dqs_out_en = 1'b1;
+            end else begin
+                dqs_out_en = 1'b0;
+            end
+            
+            // read dqs counter
+            if (rd_pipeline[RDQS_PRE]) begin
+                rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
+            end
+            // read dqs
+            if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
+                dqs_out = 1'b0;
+            end else if (rdqs_cntr > RDQS_PST) begin // read data
+                dqs_out = rdqs_cntr - RDQS_PST;
+            end else if (rdqs_cntr > 0) begin // read postamble
+                dqs_out = 1'b0;
+            end else begin
+                dqs_out = 1'b1;
+            end
+            if (rdqs_cntr > 0) begin
+                rdqs_cntr = rdqs_cntr - 1;
+            end
+
+            // read dq enable counter
+            if (rd_pipeline[RDQEN_PRE]) begin
+                rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
+            end
+            if (rdqen_cntr > 0) begin
+                rdqen_cntr = rdqen_cntr - 1;
+                dq_out_en = 1'b1;
+            end else begin
+                dq_out_en = 1'b0;
+            end
+            // read dq
+            if (rd_pipeline[0]) begin
+                rdq_cntr = burst_length;
+            end
+            if (rdq_cntr > 0) begin // read data
+                dq_temp = memory_data>>(burst_position*DQ_BITS);
+                dq_out = dq_temp;
+                if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
+                rdq_cntr = rdq_cntr - 1;
+            end else begin
+                dq_out = {DQ_BITS{1'b1}};
+            end
+
+            // delay signals prior to output
+            if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
+                for (i=0; i<DQS_BITS; i=i+1) begin
+                    // DQSCK requirements
+                    // 1.) less than tDQSCK
+                    // 2.) greater than -tDQSCK
+                    // 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
+                    dqsck_max = TDQSCK;
+                    if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
+                        dqsck_max = dqsck[i] + TQHS + TDQSQ;
+                    end
+                    dqsck_min = -1*TDQSCK;
+                    if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
+                        dqsck_min = dqsck[i] - TQHS - TDQSQ;
+                    end
+
+                    // DQSQ requirements
+                    // 1.) less than tAC - DQSCK
+                    // 2.) less than tDQSQ
+                    // 3.) greater than -tAC
+                    // 4.) greater than tQH from previous DQS edge
+                    dqsq_min = -1*TAC;
+                    if (dqsq_min < dqsck[i] - TQHS) begin
+                        dqsq_min = dqsck[i] - TQHS;
+                    end
+                    if (dqsck_min == dqsck_max) begin
+                        dqsck[i] = dqsck_min;
+                    end else begin
+                        dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
+                    end
+                    dqsq_max = TAC;
+                    if (dqsq_max > TDQSQ + dqsck[i]) begin
+                        dqsq_max = TDQSQ + dqsck[i];
+                    end
+
+                    dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en;
+                    dqs_out_dly[i]    <= #(tck_avg/2.0 + dqsck[i]) dqs_out;
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if (dq_out_en) begin // tLZ2
+                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en;
+                        end else begin // tHZ
+                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en;
+                        end
+                        if (dqsq_min == dqsq_max) begin
+                            dq_out_dly   [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
+                        end else begin
+                            dq_out_dly   [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
+                        end
+                    end
+                end
+            end else begin
+                out_delay = tck_avg/2.0;
+                dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
+                dqs_out_dly    <= #(out_delay) {DQS_BITS{dqs_out   }};
+                dq_out_en_dly  <= #(out_delay) {DQ_BITS {dq_out_en }};
+                dq_out_dly     <= #(out_delay) {DQ_BITS {dq_out    }};
+            end
+        end
+    endtask
+
+    always @(diff_ck) begin : main
+        integer i;
+
+        if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
+            $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
+        data_task;
+        if (diff_ck) begin
+            // check setup of command signals
+            if ($time > TIS) begin
+                if ($time - tm_cke < TIS) 
+                    $display ("%m: at time %t ERROR:   tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
+                if (cke_in) begin
+                    for (i=0; i<22; i=i+1) begin
+                        if ($time - tm_cmd_addr[i] < TIS) 
+                            $display ("%m: at time %t ERROR:   tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
+                    end
+                end
+            end
+
+            // update current state
+            if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
+                // check CL value against the clock frequency
+                if (cas_latency*tck_avg < CL_TIME)
+                    $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
+                // check WR value against the clock frequency
+                if (write_recovery*tck_avg < TWR)
+                    $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
+                dll_locked = 1;
+            end
+            if (|auto_precharge_bank) begin
+                for (i=0; i<`BANKS; i=i+1) begin
+                    // Write with Auto Precharge Calculation
+                    // 1.  Meet minimum tRAS requirement
+                    // 2.  Write Latency PLUS BL/2 cycles PLUS WR after Write command
+                    if (write_precharge_bank[i]
+                        && ($time - tm_bank_activate[i] >= TRAS_MIN)
+                        && (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin
+
+                        if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
+                        write_precharge_bank[i] = 0;
+                        active_bank[i] = 0;
+                        auto_precharge_bank[i] = 0;
+                        ck_write_ap = ck_cntr;
+                        tm_bank_precharge[i] = $time;
+                        tm_precharge = $time;
+                    end
+                    // Read with Auto Precharge Calculation
+                    // 1.  Meet minimum tRAS requirement
+                    // 2.  Additive Latency plus BL/2 cycles after Read command
+                    // 3.  tRTP after the last 4-bit prefetch
+                    if (read_precharge_bank[i]
+                        && ($time - tm_bank_activate[i] >= TRAS_MIN) 
+                        && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
+
+                        read_precharge_bank[i] = 0;
+                        // In case the internal precharge is pushed out by tRTP, tRP starts at the point where
+                        // the internal precharge happens (not at the next rising clock edge after this event).
+                        if ($time - tm_bank_read_end[i] < TRTP) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
+                            active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
+                            auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
+                            tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
+                            tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
+                            active_bank[i] = 0;
+                            auto_precharge_bank[i] = 0;
+                            tm_bank_precharge[i] = $time;
+                            tm_precharge = $time;
+                        end
+                    end
+                end
+            end
+
+            // respond to incoming command
+            if (cke_in ^ prev_cke) begin
+                ck_cke <= ck_cntr;
+            end
+
+            cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
+            if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
+                al_pipeline[2*additive_latency] = 1'b1;
+            end
+            if (al_pipeline[0]) begin
+                // check tRCD after additive latency
+                if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
+                    if (rd_pipeline[2*cas_latency - 1]) begin
+                        $display ("%m: at time %t ERROR:  tRCD violation during %s", $time, cmd_string[READ]);
+                    end else begin
+                        $display ("%m: at time %t ERROR:  tRCD violation during %s", $time, cmd_string[WRITE]);
+                    end
+                end
+                // check tWTR after additive latency
+                if (rd_pipeline[2*cas_latency - 1]) begin
+                    if ($time - tm_write_end < TWTR)
+                        $display ("%m: at time %t ERROR:  tWTR violation during %s", $time, cmd_string[READ]);
+                end
+            end
+            if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
+                tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
+            end
+            for (i=0; i<`BANKS; i=i+1) begin
+                if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
+                    tm_bank_write_end[i] <= $time;
+                    tm_write_end <= $time;
+                end
+            end
+
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh) begin
+                tjit_cc_time = $time - tm_ck_pos - tck_i;
+                tck_i   = $time - tm_ck_pos;
+                tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tck_avg = tck_avg + tck_i/$itor(TDLLK);
+                tck_sample[ck_cntr%TDLLK] = tck_i;
+                tjit_per_rtime = tck_i - tck_avg;
+
+                if (dll_locked) begin
+                    // check accumulated error
+                    terr_nper_rtime = 0;
+                    for (i=0; i<50; i=i+1) begin
+                        terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
+                        terr_nper_rtime = abs_value(terr_nper_rtime);
+                        case (i)
+                                  0 :;
+                                  1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
+                                  2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
+                                  3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
+                                  4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
+                          5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
+                            default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
+                        endcase
+                    end
+
+                    // check tCK min/max/jitter
+                    if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) 
+                        $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
+                    if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) 
+                        $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
+                    if (TCK_MIN - tck_avg >= 1.0)
+                        $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
+                    if (tck_avg - TCK_MAX >= 1.0) 
+                        $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
+                    if (tm_ck_pos + TCK_MIN - TJIT_PER > $time) 
+                        $display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
+                    if (tm_ck_pos + TCK_MAX + TJIT_PER < $time) 
+                        $display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
+
+                    // check tCL
+                    if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time) 
+                        $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
+                    if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time) 
+                        $display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
+                    if (tcl_avg < TCL_MIN*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
+                    if (tcl_avg > TCL_MAX*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
+                end
+
+                // calculate the tch avg jitter
+                tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tch_avg = tch_avg + tch_i/$itor(TDLLK);
+                tch_sample[ck_cntr%TDLLK] = tch_i;
+
+                // update timers/counters
+                tcl_i <= $time - tm_ck_neg;
+            end
+
+            prev_odt <= odt_in;
+            // update timers/counters
+            ck_cntr <= ck_cntr + 1;
+            tm_ck_pos <= $time;
+        end else begin
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh) begin
+                if (dll_locked) begin
+                    if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time) 
+                        $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
+                    if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time) 
+                        $display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
+                    if (tch_avg < TCH_MIN*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
+                    if (tch_avg > TCH_MAX*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
+                end
+
+                // calculate the tcl avg jitter
+                tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
+                tcl_sample[ck_cntr%TDLLK] = tcl_i;
+
+                // update timers/counters
+                tch_i <= $time - tm_ck_pos;
+            end
+            tm_ck_neg <= $time;
+        end
+
+        // on die termination
+        if (odt_en) begin
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh && diff_ck) begin
+                if ($time - tm_odt < TIS) begin
+                    $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
+                end
+                if (prev_odt ^ odt_in) begin
+                    if (!dll_locked)
+                        $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
+                    if (odt_in && ($time - tm_odt_en  < TMOD))
+                        $display ("%m: at time %t ERROR:  tMOD violation during ODT transition", $time);
+                    if ($time - tm_self_refresh < TXSNR)
+                        $display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
+                    if (in_self_refresh)
+                        $display ("%m: at time %t ERROR:  Illegal ODT transition during Self Refresh.", $time);
+
+                    // async ODT mode applies:
+                    // 1.) during active power down with slow exit
+                    // 2.) during precharge power down
+                    // 3.) if tANPD has not been satisfied
+                    // 4.) until tAXPD has been satisfied
+                    if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
+                        if (ck_cntr - ck_slow_exit_pd < TAXPD)
+                            $display ("%m: at time %t WARNING: tAXPD violation during ODT transition.  Synchronous or asynchronous change in termination resistance is possible.", $time);
+                        if (odt_in) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
+                            odt_state <= #(TAONPD) 1'b1;
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
+                            odt_state <= #(TAOFPD) 1'b0;
+                        end
+                    // sync ODT mode applies:
+                    // 1.) during normal operation
+                    // 2.) during active power down with fast exit
+                    end else begin
+                        if (odt_in) begin
+                            i = TAOND*2;
+                            odt_pipeline[i] = 1'b1;
+                        end else begin
+                            i = TAOFD*2;
+                            odt_pipeline[i] = 1'b1;
+                        end
+                    end
+                    ck_odt <= ck_cntr;
+                end
+            end
+            if (odt_pipeline[0]) begin
+                odt_state = ~odt_state;
+                if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
+            end
+        end
+
+        // shift pipelines
+        if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
+            al_pipeline = al_pipeline>>1;
+            wr_pipeline = wr_pipeline>>1;
+            rd_pipeline = rd_pipeline>>1;
+            for (i=0; i<`MAX_PIPE; i=i+1) begin
+                ba_pipeline[i] = ba_pipeline[i+1];
+                row_pipeline[i] = row_pipeline[i+1];
+                col_pipeline[i] = col_pipeline[i+1];
+            end
+        end
+        if (|odt_pipeline) begin
+            odt_pipeline = odt_pipeline>>1;
+        end
+    end
+
+    // receiver(s)
+    task dqs_even_receiver;
+        input [4:0] i;
+        reg [71:0] bit_mask;
+        begin
+            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
+            if (dqs_even[i]) begin
+                if (rdqs_en) begin // rdqs disables dm
+                    dm_in_pos[i] = 1'b0;
+                end else begin
+                    dm_in_pos[i] = dm_in[i];
+                end
+                dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
+            end
+        end
+    endtask
+
+    always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
+    always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
+    always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
+    always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
+    always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
+    always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
+    always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
+    always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
+    always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
+    always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
+    always @(posedge dqs_even[10]) dqs_even_receiver(10);
+    always @(posedge dqs_even[11]) dqs_even_receiver(11);
+    always @(posedge dqs_even[12]) dqs_even_receiver(12);
+    always @(posedge dqs_even[13]) dqs_even_receiver(13);
+    always @(posedge dqs_even[14]) dqs_even_receiver(14);
+    always @(posedge dqs_even[15]) dqs_even_receiver(15);
+    always @(posedge dqs_even[16]) dqs_even_receiver(16);
+    always @(posedge dqs_even[17]) dqs_even_receiver(17);
+
+    task dqs_odd_receiver;
+        input [4:0] i;
+        reg [71:0] bit_mask;
+        begin
+            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
+            if (dqs_odd[i]) begin
+                if (rdqs_en) begin // rdqs disables dm
+                    dm_in_neg[i] = 1'b0;
+                end else begin
+                    dm_in_neg[i] = dm_in[i];
+                end
+                dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
+            end
+        end
+    endtask
+
+    always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
+    always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
+    always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
+    always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
+    always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
+    always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
+    always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
+    always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
+    always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
+    always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
+    always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
+    always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
+    always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
+    always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
+    always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
+    always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
+    always @(posedge dqs_odd[16]) dqs_odd_receiver(16);
+    always @(posedge dqs_odd[17]) dqs_odd_receiver(17);
+ 
+    // Processes to check hold and pulse width of control signals
+    always @(cke_in) begin
+        if ($time > TIH) begin
+            if ($time - tm_ck_pos < TIH) 
+                $display ("%m: at time %t ERROR:  tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
+        end
+        if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
+            $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
+        tm_cke = $time;
+    end
+    always @(odt_in) begin
+        if (odt_en && !in_self_refresh) begin
+            if ($time - tm_ck_pos < TIH) 
+                $display ("%m: at time %t ERROR:  tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
+            if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
+                $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
+        end
+        tm_odt = $time;
+    end
+
+    task cmd_addr_timing_check;
+    input i;
+    reg [4:0] i;
+    begin
+        if (prev_cke) begin
+            if ((i == 0) && ($time - tm_ck_pos < TIH))                      // Always check tIH for CS#
+                $display ("%m: at time %t ERROR:  tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
+            if ((i > 0) && (cs_n_in == 1'b0) && ($time - tm_ck_pos < TIH))  // Only check tIH for cmd_addr if CS# low
+                $display ("%m: at time %t ERROR:  tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
+            if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
+                $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
+        end
+        tm_cmd_addr[i] = $time;
+    end
+    endtask
+
+    always @(cs_n_in    ) cmd_addr_timing_check( 0);
+    always @(ras_n_in   ) cmd_addr_timing_check( 1);
+    always @(cas_n_in   ) cmd_addr_timing_check( 2);
+    always @(we_n_in    ) cmd_addr_timing_check( 3);
+    always @(ba_in  [ 0]) cmd_addr_timing_check( 4);
+    always @(ba_in  [ 1]) cmd_addr_timing_check( 5);
+    always @(ba_in  [ 2]) cmd_addr_timing_check( 6);
+    always @(addr_in[ 0]) cmd_addr_timing_check( 7);
+    always @(addr_in[ 1]) cmd_addr_timing_check( 8);
+    always @(addr_in[ 2]) cmd_addr_timing_check( 9);
+    always @(addr_in[ 3]) cmd_addr_timing_check(10);
+    always @(addr_in[ 4]) cmd_addr_timing_check(11);
+    always @(addr_in[ 5]) cmd_addr_timing_check(12);
+    always @(addr_in[ 6]) cmd_addr_timing_check(13);
+    always @(addr_in[ 7]) cmd_addr_timing_check(14);
+    always @(addr_in[ 8]) cmd_addr_timing_check(15);
+    always @(addr_in[ 9]) cmd_addr_timing_check(16);
+    always @(addr_in[10]) cmd_addr_timing_check(17);
+    always @(addr_in[11]) cmd_addr_timing_check(18);
+    always @(addr_in[12]) cmd_addr_timing_check(19);
+    always @(addr_in[13]) cmd_addr_timing_check(20);
+    always @(addr_in[14]) cmd_addr_timing_check(21);
+    always @(addr_in[15]) cmd_addr_timing_check(22);
+
+    // Processes to check setup and hold of data signals
+    task dm_timing_check;
+    input i;
+    reg [4:0] i;
+    begin
+        if (dqs_in_valid) begin
+            if ($time - tm_dqs[i] < TDH) 
+                $display ("%m: at time %t ERROR:   tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
+            if (check_dm_tdipw[i]) begin
+                if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
+                    $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
+            end
+        end
+        check_dm_tdipw[i] <= 1'b0;
+        tm_dm[i] = $time;
+    end
+    endtask
+
+    always @(dm_in[ 0]) dm_timing_check( 0);
+    always @(dm_in[ 1]) dm_timing_check( 1);
+    always @(dm_in[ 2]) dm_timing_check( 2);
+    always @(dm_in[ 3]) dm_timing_check( 3);
+    always @(dm_in[ 4]) dm_timing_check( 4);
+    always @(dm_in[ 5]) dm_timing_check( 5);
+    always @(dm_in[ 6]) dm_timing_check( 6);
+    always @(dm_in[ 7]) dm_timing_check( 7);
+    always @(dm_in[ 8]) dm_timing_check( 8);
+    always @(dm_in[ 9]) dm_timing_check( 9);
+    always @(dm_in[10]) dm_timing_check(10);
+    always @(dm_in[11]) dm_timing_check(11);
+    always @(dm_in[12]) dm_timing_check(12);
+    always @(dm_in[13]) dm_timing_check(13);
+    always @(dm_in[14]) dm_timing_check(14);
+    always @(dm_in[15]) dm_timing_check(15);
+    always @(dm_in[16]) dm_timing_check(16);
+    always @(dm_in[17]) dm_timing_check(17);
+
+    task dq_timing_check;
+    input i;
+    reg [6:0] i;
+    begin
+        if (dqs_in_valid) begin
+            if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) 
+                $display ("%m: at time %t ERROR:   tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
+            if (check_dq_tdipw[i]) begin
+                if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
+                    $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
+            end
+        end
+        check_dq_tdipw[i] <= 1'b0;
+        tm_dq[i] = $time;
+    end 
+    endtask
+
+    always @(dq_in[ 0]) dq_timing_check( 0);
+    always @(dq_in[ 1]) dq_timing_check( 1);
+    always @(dq_in[ 2]) dq_timing_check( 2);
+    always @(dq_in[ 3]) dq_timing_check( 3);
+    always @(dq_in[ 4]) dq_timing_check( 4);
+    always @(dq_in[ 5]) dq_timing_check( 5);
+    always @(dq_in[ 6]) dq_timing_check( 6);
+    always @(dq_in[ 7]) dq_timing_check( 7);
+    always @(dq_in[ 8]) dq_timing_check( 8);
+    always @(dq_in[ 9]) dq_timing_check( 9);
+    always @(dq_in[10]) dq_timing_check(10);
+    always @(dq_in[11]) dq_timing_check(11);
+    always @(dq_in[12]) dq_timing_check(12);
+    always @(dq_in[13]) dq_timing_check(13);
+    always @(dq_in[14]) dq_timing_check(14);
+    always @(dq_in[15]) dq_timing_check(15);
+    always @(dq_in[16]) dq_timing_check(16);
+    always @(dq_in[17]) dq_timing_check(17);
+    always @(dq_in[18]) dq_timing_check(18);
+    always @(dq_in[19]) dq_timing_check(19);
+    always @(dq_in[20]) dq_timing_check(20);
+    always @(dq_in[21]) dq_timing_check(21);
+    always @(dq_in[22]) dq_timing_check(22);
+    always @(dq_in[23]) dq_timing_check(23);
+    always @(dq_in[24]) dq_timing_check(24);
+    always @(dq_in[25]) dq_timing_check(25);
+    always @(dq_in[26]) dq_timing_check(26);
+    always @(dq_in[27]) dq_timing_check(27);
+    always @(dq_in[28]) dq_timing_check(28);
+    always @(dq_in[29]) dq_timing_check(29);
+    always @(dq_in[30]) dq_timing_check(30);
+    always @(dq_in[31]) dq_timing_check(31);
+    always @(dq_in[32]) dq_timing_check(32);
+    always @(dq_in[33]) dq_timing_check(33);
+    always @(dq_in[34]) dq_timing_check(34);
+    always @(dq_in[35]) dq_timing_check(35);
+    always @(dq_in[36]) dq_timing_check(36);
+    always @(dq_in[37]) dq_timing_check(37);
+    always @(dq_in[38]) dq_timing_check(38);
+    always @(dq_in[39]) dq_timing_check(39);
+    always @(dq_in[40]) dq_timing_check(40);
+    always @(dq_in[41]) dq_timing_check(41);
+    always @(dq_in[42]) dq_timing_check(42);
+    always @(dq_in[43]) dq_timing_check(43);
+    always @(dq_in[44]) dq_timing_check(44);
+    always @(dq_in[45]) dq_timing_check(45);
+    always @(dq_in[46]) dq_timing_check(46);
+    always @(dq_in[47]) dq_timing_check(47);
+    always @(dq_in[48]) dq_timing_check(48);
+    always @(dq_in[49]) dq_timing_check(49);
+    always @(dq_in[50]) dq_timing_check(50);
+    always @(dq_in[51]) dq_timing_check(51);
+    always @(dq_in[52]) dq_timing_check(52);
+    always @(dq_in[53]) dq_timing_check(53);
+    always @(dq_in[54]) dq_timing_check(54);
+    always @(dq_in[55]) dq_timing_check(55);
+    always @(dq_in[56]) dq_timing_check(56);
+    always @(dq_in[57]) dq_timing_check(57);
+    always @(dq_in[58]) dq_timing_check(58);
+    always @(dq_in[59]) dq_timing_check(59);
+    always @(dq_in[60]) dq_timing_check(60);
+    always @(dq_in[61]) dq_timing_check(61);
+    always @(dq_in[62]) dq_timing_check(62);
+    always @(dq_in[63]) dq_timing_check(63);
+    always @(dq_in[64]) dq_timing_check(64);
+    always @(dq_in[65]) dq_timing_check(65);
+    always @(dq_in[66]) dq_timing_check(66);
+    always @(dq_in[67]) dq_timing_check(67);
+    always @(dq_in[68]) dq_timing_check(68);
+    always @(dq_in[69]) dq_timing_check(69);
+    always @(dq_in[70]) dq_timing_check(70);
+    always @(dq_in[71]) dq_timing_check(71);
+
+    task dqs_pos_timing_check;
+    input i;
+    reg [5:0] i;
+    reg [3:0] j;
+    begin
+        if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin
+            if (dqs_in[i] ^ prev_dqs_in[i]) begin
+                if (dll_locked) begin
+                    if (check_write_preamble[i]) begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
+                            $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18);
+                    end else if (check_write_postamble[i]) begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
+                            $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    end else begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
+                            $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    end
+                end
+                if ($time - tm_dm[i%18] < TDS) 
+                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i,  tm_dm[i%18] + TDS - $time);
+                if (!dq_out_en) begin
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) 
+                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
+                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
+                    end
+                end
+                if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
+                    wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
+                end else begin
+                    wdqs_pos_cntr[i] <= 1;
+                end
+                check_dm_tdipw[i%18] <= 1'b1;
+                check_write_preamble[i] <= 1'b0;
+                check_write_postamble[i] <= 1'b0;
+                check_write_dqs_low[i] <= 1'b0;
+                tm_dqs[i%18] <= $time;
+            end else begin
+                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
+            end
+        end
+        tm_dqss_pos[i] <= $time;
+        tm_dqs_pos[i] = $time;
+        prev_dqs_in[i] <= dqs_in[i];
+    end
+    endtask
+
+    always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
+    always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
+    always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
+    always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
+    always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
+    always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
+    always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
+    always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
+    always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
+    always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
+    always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
+    always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
+    always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
+    always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
+    always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
+    always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
+    always @(posedge dqs_in[16]) dqs_pos_timing_check(16);
+    always @(posedge dqs_in[17]) dqs_pos_timing_check(17);
+    always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
+    always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
+    always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
+    always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
+    always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
+    always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
+    always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
+    always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
+    always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
+    always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
+    always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
+    always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
+    always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
+    always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
+    always @(negedge dqs_in[32]) dqs_neg_timing_check(32);
+    always @(negedge dqs_in[33]) dqs_neg_timing_check(33);
+    always @(negedge dqs_in[34]) dqs_neg_timing_check(34);
+    always @(negedge dqs_in[35]) dqs_neg_timing_check(35);
+
+    task dqs_neg_timing_check;
+    input i;
+    reg [5:0] i;
+    reg [3:0] j;
+    begin
+        if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin
+            if (dqs_in[i] ^ prev_dqs_in[i]) begin
+                if (dll_locked) begin
+                    if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
+                        $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
+                        $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18); 
+                end
+                if ($time - tm_dm[i%18] < TDS) 
+                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i,  tm_dm[i%18] + TDS - $time);
+                if (!dq_out_en) begin
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) 
+                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
+                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
+                    end
+                end
+                check_dm_tdipw[i%18] <= 1'b1;
+                check_write_dqs_high[i] <= 1'b0;
+                tm_dqs[i%18] <= $time;
+            end else begin
+                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
+            end
+        end
+        tm_dqs_neg[i] = $time;
+        prev_dqs_in[i] <= dqs_in[i];
+    end
+    endtask
+
+    always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
+    always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
+    always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
+    always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
+    always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
+    always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
+    always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
+    always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
+    always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
+    always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
+    always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
+    always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
+    always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
+    always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
+    always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
+    always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
+    always @(negedge dqs_in[16]) dqs_neg_timing_check(16);
+    always @(negedge dqs_in[17]) dqs_neg_timing_check(17);
+    always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
+    always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
+    always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
+    always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
+    always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
+    always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
+    always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
+    always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
+    always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
+    always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
+    always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
+    always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
+    always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
+    always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
+    always @(posedge dqs_in[32]) dqs_neg_timing_check(32);
+    always @(posedge dqs_in[33]) dqs_neg_timing_check(33);
+    always @(posedge dqs_in[34]) dqs_neg_timing_check(34);
+    always @(posedge dqs_in[35]) dqs_neg_timing_check(35);
+
+endmodule
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/ddr2_model_parameters_c3.vh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/ddr2_model_parameters_c3.vh
new file mode 100644
index 0000000..1c8e277
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/ddr2_model_parameters_c3.vh
@@ -0,0 +1,1394 @@
+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or
+*                limitation of liability for consequential or incidental damages, the
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+
+    // Timing parameters based on Speed Grade
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef x256Mb
+
+    `ifdef sg187E
+        parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     125; // tIS    ps    Input Setup Time
+        parameter TIH              =     200; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   13125; // tRP    ps    Precharge command period
+        parameter TRPA             =   13125; // tRPA   ps    Precharge All period
+        parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25E
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12500; // tRP    ps    Precharge command period
+        parameter TRPA             =   12500; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3E
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12000; // tRP    ps    Precharge command period
+        parameter TRPA             =   12000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg37E
+        parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     250; // tIS    ps    Input Setup Time
+        parameter TIH              =     375; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `define sg5E
+        parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     350; // tIS    ps    Input Setup Time
+        parameter TIH              =     475; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `endif `endif `endif `endif `endif `endif
+
+    `ifdef x16
+      `ifdef sg187E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `else // x4, x8
+      `ifdef sg187E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `endif
+
+        // Timing Parameters
+
+        // Mode Register
+        parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+        parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+        parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+        parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+        parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+        parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+        parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+        parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+        // Clock
+        parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+        parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+        parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+        parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+        parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+        // Data
+        parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+        parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+        parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+        // Data Strobe
+        parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+        parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+        parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+        parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+        parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+        parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+        parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+        // Command and Address
+        parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
+        parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+        parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+        parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+        parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+        parameter TWR              =   15000; // tWR    ps    Write recovery time
+        parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+        parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+        // Refresh
+        parameter TRFC_MIN         =   75000; // tRFC   ps    Refresh to Refresh Command interval minimum value
+        parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+        // Self Refresh
+        parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+        parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+        parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+        // ODT
+        parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+        parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+        parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+        parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+        parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+        // Power Down
+        parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+        // Size Parameters based on Part Width
+
+    `ifdef x4
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =      11; // Number of Column bits
+        parameter DQ_BITS          =       4; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `ifdef x8
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DQ_BITS          =       8; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `define x16
+        parameter DM_BITS          =       2; // Number of Data Mask bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =       9; // Number of Column bits
+        parameter DQ_BITS          =      16; // Number of Data bits
+        parameter DQS_BITS         =       2; // Number of Dqs bits
+        parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+    `endif `endif
+
+    `ifdef QUAD_RANK
+        `define DUAL_RANK // also define DUAL_RANK
+        parameter CS_BITS          =       4; // Number of Chip Select Bits
+        parameter RANKS            =       4; // Number of Chip Select Bits
+    `else `ifdef DUAL_RANK
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       2; // Number of Chip Select Bits
+    `else
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       1; // Number of Chip Select Bits
+    `endif `endif
+
+        // Size Parameters
+        parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits
+        parameter ADDR_BITS        =      13; // Address Bits
+        parameter MEM_BITS         =      15; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+        parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+        parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+        parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+`else `ifdef x512Mb
+
+    `ifdef sg187E
+        parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     125; // tIS    ps    Input Setup Time
+        parameter TIH              =     200; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   13125; // tRP    ps    Precharge command period
+        parameter TRPA             =   13125; // tRPA   ps    Precharge All period
+        parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25E
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12500; // tRP    ps    Precharge command period
+        parameter TRPA             =   12500; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3E
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12000; // tRP    ps    Precharge command period
+        parameter TRPA             =   12000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg37E
+        parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     250; // tIS    ps    Input Setup Time
+        parameter TIH              =     375; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `define sg5E
+        parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     350; // tIS    ps    Input Setup Time
+        parameter TIH              =     475; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `endif `endif `endif `endif `endif `endif
+
+    `ifdef x16
+      `ifdef sg187E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `else // x4, x8
+      `ifdef sg187E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `endif
+
+        // Timing Parameters
+
+        // Mode Register
+        parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+        parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+        parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+        parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+        parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+        parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+        parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+        parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+        // Clock
+        parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+        parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+        parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+        parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+        parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+        // Data
+        parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+        parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+        parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+        // Data Strobe
+        parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+        parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+        parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+        parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+        parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+        parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+        parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+        // Command and Address
+        parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
+        parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+        parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+        parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+        parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+        parameter TWR              =   15000; // tWR    ps    Write recovery time
+        parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+        parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+        // Refresh
+        parameter TRFC_MIN         =  105000; // tRFC   ps    Refresh to Refresh Command interval minimum value
+        parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+        // Self Refresh
+        parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+        parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+        parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+        // ODT
+        parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+        parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+        parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+        parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+        parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+        // Power Down
+        parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+        // Size Parameters based on Part Width
+
+    `ifdef x4
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      11; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       4; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `ifdef x8
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       8; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `define x16
+        parameter ADDR_BITS        =      13; // Address Bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       2; // Number of Data Mask bits
+        parameter DQ_BITS          =      16; // Number of Data bits
+        parameter DQS_BITS         =       2; // Number of Dqs bits
+        parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+    `endif `endif
+
+    `ifdef QUAD_RANK
+        `define DUAL_RANK // also define DUAL_RANK
+        parameter CS_BITS          =       4; // Number of Chip Select Bits
+        parameter RANKS            =       4; // Number of Chip Select Bits
+    `else `ifdef DUAL_RANK
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       2; // Number of Chip Select Bits
+    `else
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       1; // Number of Chip Select Bits
+    `endif `endif
+
+        // Size Parameters
+        parameter BA_BITS          =       2; // Set this parmaeter to control how many Bank Address bits
+        parameter MEM_BITS         =      15; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+        parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+        parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+        parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+`else `ifdef x1Gb
+
+    `ifdef sg187E
+        parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     125; // tIS    ps    Input Setup Time
+        parameter TIH              =     200; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   13125; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25E
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12500; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   17500; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3E
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   18000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg37E
+        parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     250; // tIS    ps    Input Setup Time
+        parameter TIH              =     375; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   18750; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `define sg5E
+        parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     350; // tIS    ps    Input Setup Time
+        parameter TIH              =     475; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   20000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `endif `endif `endif `endif `endif `endif
+
+    `ifdef x16
+      `ifdef sg187E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `else // x4, x8
+      `ifdef sg187E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `endif
+
+        // Timing Parameters
+
+        // Mode Register
+        parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+        parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+        parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+        parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+        parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+        parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+        parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+        parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+        // Clock
+        parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+        parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+        parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+        parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+        parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+        // Data
+        parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+        parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+        parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+        // Data Strobe
+        parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+        parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+        parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+        parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+        parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+        parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+        parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+        // Command and Address
+        parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
+        parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+        parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+        parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+        parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+        parameter TWR              =   15000; // tWR    ps    Write recovery time
+        parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+        parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+        // Refresh
+        parameter TRFC_MIN         =  127500; // tRFC   ps    Refresh to Refresh Command interval minimum value
+        parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+        // Self Refresh
+        parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+        parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+        parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+        // ODT
+        parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+        parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+        parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+        parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+        parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+        // Power Down
+        parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+        // Size Parameters based on Part Width
+
+    `ifdef x4
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      11; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       4; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `ifdef x8
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       8; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `define x16
+        parameter ADDR_BITS        =      13; // Address Bits
+        parameter ROW_BITS         =      13; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       2; // Number of Data Mask bits
+        parameter DQ_BITS          =      16; // Number of Data bits
+        parameter DQS_BITS         =       2; // Number of Dqs bits
+        parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+    `endif `endif
+
+    `ifdef QUAD_RANK
+        `define DUAL_RANK // also define DUAL_RANK
+        parameter CS_BITS          =       4; // Number of Chip Select Bits
+        parameter RANKS            =       4; // Number of Chip Select Bits
+    `else `ifdef DUAL_RANK
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       2; // Number of Chip Select Bits
+    `else
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       1; // Number of Chip Select Bits
+    `endif `endif
+
+        // Size Parameters
+        parameter BA_BITS          =       3; // Set this parmaeter to control how many Bank Address bits
+        parameter MEM_BITS         =      15; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+        parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+        parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+        parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+`else `define x2Gb
+
+    `ifdef sg187E
+        parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     125; // tIS    ps    Input Setup Time
+        parameter TIH              =     200; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   13125; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25E
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12500; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg25
+        parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     175; // tIS    ps    Input Setup Time
+        parameter TIH              =     250; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   17500; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3E
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   12000; // tRP    ps    Precharge command period
+        parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg3
+        parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     200; // tIS    ps    Input Setup Time
+        parameter TIH              =     275; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   18000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `ifdef sg37E
+        parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     250; // tIS    ps    Input Setup Time
+        parameter TIH              =     375; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   18750; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `else `define sg5E
+        parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+        parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+        parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+        parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+        parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+        parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+        parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+        parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+        parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+        parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+        parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+        parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+        parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+        parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+        parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+        parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+        parameter TIS              =     350; // tIS    ps    Input Setup Time
+        parameter TIH              =     475; // tIH    ps    Input Hold Time
+        parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+        parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+        parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+        parameter TRP              =   15000; // tRP    ps    Precharge command period
+        parameter TRPA             =   20000; // tRPA   ps    Precharge All period
+        parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+        parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+        parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+        parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+        parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+        parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+    `endif `endif `endif `endif `endif `endif
+
+    `ifdef x16
+      `ifdef sg187E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `else // x4, x8
+      `ifdef sg187E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25E
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else `ifdef sg25
+        parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+      `else // sg3E, sg3, sg37E, sg5E
+        parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+      `endif `endif `endif
+    `endif
+
+        // Timing Parameters
+
+        // Mode Register
+        parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+        parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+        parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+        parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+        parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+        parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+        parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+        parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+        // Clock
+        parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+        parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+        parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+        parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+        parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+        // Data
+        parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+        parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+        parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+        // Data Strobe
+        parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+        parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+        parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+        parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+        parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+        parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+        parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+        // Command and Address
+        parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width
+        parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+        parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+        parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+        parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+        parameter TWR              =   15000; // tWR    ps    Write recovery time
+        parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+        parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+        // Refresh
+        parameter TRFC_MIN         =  197500; // tRFC   ps    Refresh to Refresh Command interval minimum value
+        parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+        // Self Refresh
+        parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+        parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+        parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+        // ODT
+        parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+        parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+        parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+        parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+        parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+        // Power Down
+        parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+        // Size Parameters based on Part Width
+
+    `ifdef x4
+        parameter ADDR_BITS        =      15; // Address Bits
+        parameter ROW_BITS         =      15; // Number of Address bits
+        parameter COL_BITS         =      11; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       4; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `ifdef x8
+        parameter ADDR_BITS        =      15; // Address Bits
+        parameter ROW_BITS         =      15; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       1; // Number of Data Mask bits
+        parameter DQ_BITS          =       8; // Number of Data bits
+        parameter DQS_BITS         =       1; // Number of Dqs bits
+        parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+    `else `define x16
+        parameter ADDR_BITS        =      14; // Address Bits
+        parameter ROW_BITS         =      14; // Number of Address bits
+        parameter COL_BITS         =      10; // Number of Column bits
+        parameter DM_BITS          =       2; // Number of Data Mask bits
+        parameter DQ_BITS          =      16; // Number of Data bits
+        parameter DQS_BITS         =       2; // Number of Dqs bits
+        parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+    `endif `endif
+
+    `ifdef QUAD_RANK
+        `define DUAL_RANK // also define DUAL_RANK
+        parameter CS_BITS          =       4; // Number of Chip Select Bits
+        parameter RANKS            =       4; // Number of Chip Select Bits
+    `else `ifdef DUAL_RANK
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       2; // Number of Chip Select Bits
+    `else
+        parameter CS_BITS          =       2; // Number of Chip Select Bits
+        parameter RANKS            =       1; // Number of Chip Select Bits
+    `endif `endif
+
+        // Size Parameters
+        parameter BA_BITS          =       3; // Set this parmaeter to control how many Bank Address bits
+        parameter MEM_BITS         =      15; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+        parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+        parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+        parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+`endif `endif `endif
+
+    // Simulation parameters
+    parameter STOP_ON_ERROR    =       1; // If set to 1, the model will halt on command sequence/major errors
+    parameter DEBUG            =       1; // Turn on Debug messages
+    parameter BUS_DELAY        =       0; // delay in nanoseconds
+    parameter RANDOM_OUT_DELAY =       0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
+    parameter RANDOM_SEED      = 711689044; //seed value for random generator.
+
+    parameter RDQSEN_PRE       =       2; // DQS driving time prior to first read strobe
+    parameter RDQSEN_PST       =       1; // DQS driving time after last read strobe
+    parameter RDQS_PRE         =       2; // DQS low time prior to first read strobe
+    parameter RDQS_PST         =       1; // DQS low time after last valid read strobe
+    parameter RDQEN_PRE        =       0; // DQ/DM driving time prior to first read data
+    parameter RDQEN_PST        =       0; // DQ/DM driving time after last read data
+    parameter WDQS_PRE         =       1; // DQS half clock periods prior to first write strobe
+    parameter WDQS_PST         =       1; // DQS half clock periods after last valid write strobe
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/init_mem_pattern_ctr.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/init_mem_pattern_ctr.vhd
new file mode 100755
index 0000000..49d24e3
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/init_mem_pattern_ctr.vhd
@@ -0,0 +1,620 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: init_mem_pattern_ctr.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:39 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This moduel has a small FSM to control the operation of 
+--         mcb_traffic_gen module.It first fill up the memory with a selected 
+--         DATA pattern and then starts the memory testing state.
+-- Reference:
+-- Revision History:  1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
+--                      and the fixed_bl_o is fixed at 64 if data_mode_o == PRBS and FAMILY == "SPARTAN6"
+--                      The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
+--                    1.2  05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
+--                                    "OTF" Burst Mode and TG will only generate BL 8 traffic.
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+
+ENTITY init_mem_pattern_ctr IS
+   GENERIC (
+      FAMILY                         : STRING := "SPARTAN6";
+      TST_MEM_INSTR_MODE             : STRING := "R_W_INSTR_MODE";
+      MEM_BURST_LEN                  : INTEGER := 8;
+      CMD_PATTERN                    : STRING := "CGEN_ALL";
+      BEGIN_ADDRESS                  : std_logic_vector(31 downto 0) := X"00000000";
+      END_ADDRESS                    : std_logic_vector(31 downto 0) := X"00000fff";
+      ADDR_WIDTH                     : INTEGER := 30;
+      DWIDTH                         : INTEGER := 32;
+      CMD_SEED_VALUE                 : std_logic_vector(31 downto 0) := X"12345678";
+      DATA_SEED_VALUE                : std_logic_vector(31 downto 0) := X"ca345675";
+      DATA_MODE                      : std_logic_vector(3 downto 0) := "0010";
+      PORT_MODE                      : STRING := "BI_MODE";
+      EYE_TEST                       : STRING := "FALSE"
+      
+   );
+   PORT (
+      clk_i                          : IN STD_LOGIC;
+      rst_i                          : IN STD_LOGIC;
+      mcb_cmd_bl_i                   : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      mcb_cmd_en_i                   : IN STD_LOGIC;
+      mcb_cmd_instr_i                : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      mcb_wr_en_i                    : IN STD_LOGIC;
+      vio_modify_enable              : IN STD_LOGIC;
+      vio_data_mode_value            : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      vio_addr_mode_value            : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      vio_bl_mode_value              : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      vio_fixed_bl_value             : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      mcb_init_done_i                : IN STD_LOGIC;
+      cmp_error                      : IN STD_LOGIC;
+      run_traffic_o                  : OUT STD_LOGIC;
+      start_addr_o                   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      end_addr_o                     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmd_seed_o                     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      data_seed_o                    : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      load_seed_o                    : OUT STD_LOGIC;
+      addr_mode_o                    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      instr_mode_o                   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      bl_mode_o                      : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      data_mode_o                    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      mode_load_o                    : OUT STD_LOGIC;
+      fixed_bl_o                     : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+      fixed_instr_o                  : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      fixed_addr_o                   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+   );
+END init_mem_pattern_ctr;
+
+ARCHITECTURE trans OF init_mem_pattern_ctr IS
+
+      constant IDLE                           : std_logic_vector(4 downto 0)  := "00001";
+      constant INIT_MEM_WRITE                 : std_logic_vector(4 downto 0)  := "00010";
+      constant INIT_MEM_READ                  : std_logic_vector(4 downto 0)  := "00100";
+      constant TEST_MEM                       : std_logic_vector(4 downto 0)  := "01000";
+      constant CMP_ERROR1                     : std_logic_vector(4 downto 0)  := "10000";
+
+      constant BRAM_ADDR                      : std_logic_vector(1 downto 0)  := "00";
+      constant FIXED_ADDR                     : std_logic_vector(2 downto 0)  := "001";
+      constant PRBS_ADDR                      : std_logic_vector(2 downto 0)  := "010";
+      constant SEQUENTIAL_ADDR                : std_logic_vector(2 downto 0)  := "011";
+
+      constant BRAM_INSTR_MODE                : std_logic_vector(3 downto 0)  := "0000";
+      constant FIXED_INSTR_MODE               : std_logic_vector(3 downto 0)  := "0001";
+      constant FIXED_INSTR_MODE_WITH_REFRESH  : std_logic_vector(3 downto 0)  := "0110";
+
+      constant R_W_INSTR_MODE                 : std_logic_vector(3 downto 0)  := "0010";
+      constant RP_WP_INSTR_MODE               : std_logic_vector(3 downto 0)  := "0011";
+      constant R_RP_W_WP_INSTR_MODE           : std_logic_vector(3 downto 0)  := "0100";
+      constant R_RP_W_WP_REF_INSTR_MODE       : std_logic_vector(3 downto 0)  := "0101";
+
+      constant BRAM_BL_MODE                   : std_logic_vector(1 downto 0)  := "00";
+      constant FIXED_BL_MODE                  : std_logic_vector(1 downto 0)  := "01";
+      constant PRBS_BL_MODE                   : std_logic_vector(1 downto 0)  := "10";
+          
+      constant BRAM_DATAL_MODE                : std_logic_vector(3 downto 0)  := "0000";
+      constant FIXED_DATA_MODE                : std_logic_vector(3 downto 0)  := "0001";
+      constant ADDR_DATA_MODE                 : std_logic_vector(3 downto 0)  := "0010";
+      constant HAMMER_DATA_MODE               : std_logic_vector(3 downto 0)  := "0011";
+      constant NEIGHBOR_DATA_MODE             : std_logic_vector(3 downto 0)  := "0100";
+      constant WALKING1_DATA_MODE             : std_logic_vector(3 downto 0)  := "0101";
+      constant WALKING0_DATA_MODE             : std_logic_vector(3 downto 0)  := "0110";
+      constant PRBS_DATA_MODE                 : std_logic_vector(3 downto 0)  := "0111";
+
+      constant RD_INSTR                       : std_logic_vector(2 downto 0)  := "001";
+      constant RDP_INSTR                      : std_logic_vector(2 downto 0)  := "011";
+      constant WR_INSTR                       : std_logic_vector(2 downto 0)  := "000";
+      
+      constant WRP_INSTR                      : std_logic_vector(2 downto 0)  := "010";
+      constant REFRESH_INSTR                  : std_logic_vector(2 downto 0)  := "100";
+      constant NOP_WR_INSTR                   : std_logic_vector(2 downto 0)  := "101";
+   
+   SIGNAL current_state            : STD_LOGIC_VECTOR(4 DOWNTO 0);
+   SIGNAL next_state               : STD_LOGIC_VECTOR(4 DOWNTO 0);
+   SIGNAL mcb_init_done_reg        : STD_LOGIC;
+   SIGNAL mcb_init_done_reg1        : STD_LOGIC;
+   SIGNAL AC2_G_E2                 : STD_LOGIC;
+   SIGNAL AC1_G_E1                 : STD_LOGIC;
+   SIGNAL AC3_G_E3                 : STD_LOGIC;
+   SIGNAL upper_end_matched        : STD_LOGIC;
+   SIGNAL end_boundary_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   
+   SIGNAL mcb_cmd_en_r             : STD_LOGIC;
+   SIGNAL mcb_cmd_bl_r             : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL lower_end_matched        : STD_LOGIC;
+   SIGNAL end_addr_reached         : STD_LOGIC;
+   SIGNAL run_traffic              : STD_LOGIC;
+   SIGNAL current_address          : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL fix_bl_value             : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL data_mode_sel            : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL addr_mode_sel            : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL bl_mode_sel              : STD_LOGIC_VECTOR(1 DOWNTO 0);
+   SIGNAL addr_mode                : STD_LOGIC_VECTOR(2 DOWNTO 0);
+--   SIGNAL data_mode1                : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL INC_COUNTS               : STD_LOGIC_VECTOR(10 DOWNTO 0);
+   SIGNAL FIXEDBL                  : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL  FIXED_BL_VALUE           : STD_LOGIC_VECTOR(6 DOWNTO 0);
+   
+   SIGNAL bram_mode_enable         : STD_LOGIC;
+   SIGNAL syn1_vio_data_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL syn1_vio_addr_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL test_mem_instr_mode      : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL bl_mode_o_xhdl0          : STD_LOGIC_VECTOR(1 DOWNTO 0);
+   SIGNAL data_mode_reg          : STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+BEGIN
+
+
+test_mem_instr_mode <= "0000" when TST_MEM_INSTR_MODE = "BRAM_INSTR_MODE" else
+                       "0001" when (TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") OR
+                                   (TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") else
+                       "0010" when TST_MEM_INSTR_MODE = "R_W_INSTR_MODE" else
+                       "0011" when (TST_MEM_INSTR_MODE = "RP_WP_INSTR_MODE" AND
+                                   FAMILY = "SPARTAN6") else
+                       "0100" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_INSTR_MODE" AND
+                                   FAMILY = "SPARTAN6")else
+                       "0101" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_REF_INSTR_MODE"AND
+                                   FAMILY = "SPARTAN6") else
+                       "0010" ;
+   -- Drive referenced outputs
+   bl_mode_o <= bl_mode_o_xhdl0;
+   FIXEDBL <= "000000";
+   xhdl1 : IF (FAMILY = "SPARTAN6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            INC_COUNTS <= std_logic_vector(to_unsigned(DWIDTH/8,11));
+         END IF;
+      END PROCESS;
+      
+   END GENERATE;
+   xhdl2 : IF (FAMILY = "VIRTEX6") GENERATE
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (DWIDTH >= 256 AND DWIDTH <= 576) THEN
+               INC_COUNTS <= "00000100000";
+            ELSIF ((DWIDTH >= 128) AND (DWIDTH <= 224)) THEN
+               INC_COUNTS <= "00000010000";
+            ELSIF ((DWIDTH = 64) OR (DWIDTH = 96)) THEN
+               INC_COUNTS <= "00000001000";
+            ELSIF (DWIDTH = 32) THEN
+               INC_COUNTS <= "00000000100";
+            END IF;
+         END IF;
+      END PROCESS;
+      
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            current_address <= BEGIN_ADDRESS;
+         ELSIF (
+--                ((mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND ((PORT_MODE = "WR_MODE") OR (PORT_MODE = "BI_MODE")))) OR
+                 (mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE"))) OR
+
+                 (mcb_wr_en_i = '1' AND (current_state = IDLE AND PORT_MODE = "RD_MODE" ))
+               ) THEN
+            current_address <= current_address + ("000000000000000000000" & INC_COUNTS);
+         ELSE
+            current_address <= current_address;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (current_address(29 DOWNTO 24) >= end_boundary_addr(29 DOWNTO 24)) THEN
+            AC3_G_E3 <= '1';
+         ELSE
+            AC3_G_E3 <= '0';
+         END IF;
+         IF (current_address(23 DOWNTO 16) >= end_boundary_addr(23 DOWNTO 16)) THEN
+            AC2_G_E2 <= '1';
+         ELSE
+            AC2_G_E2 <= '0';
+         END IF;
+         IF (current_address(15 DOWNTO 8) >= end_boundary_addr(15 DOWNTO 8)) THEN
+            AC1_G_E1 <= '1';
+         ELSE
+            AC1_G_E1 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            upper_end_matched <= '0'; 
+         ELSIF (mcb_cmd_en_i = '1') THEN
+            upper_end_matched <= AC3_G_E3 AND AC2_G_E2 AND AC1_G_E1;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   FIXED_BL_VALUE <= "0000010" WHEN ((FAMILY = "VIRTEX6") AND ((MEM_BURST_LEN = 8) OR (MEM_BURST_LEN = 0))) ELSE 
+                     "0000001" WHEN ((FAMILY = "VIRTEX6") AND (MEM_BURST_LEN = 4)) ELSE
+                     ('0' & FIXEDBL);
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         end_boundary_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(END_ADDRESS)) - (DWIDTH / 8) + 1),32));
+
+
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (current_address(7 DOWNTO 0) >= end_boundary_addr(7 DOWNTO 0)) THEN
+            lower_end_matched <= '1';
+         ELSE
+            lower_end_matched <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (mcb_cmd_en_i = '1') THEN
+            mcb_cmd_bl_r <= mcb_cmd_bl_i;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 32)) OR   
+             ((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 64)) OR 
+             (upper_end_matched = '1' AND DWIDTH = 128 AND FAMILY = "SPARTAN6") OR
+             ((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "VIRTEX6")) THEN
+            end_addr_reached <= '1';
+         ELSE
+            end_addr_reached <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   fixed_addr_o <= "00000000000000000001001000110100";
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         mcb_init_done_reg1 <= mcb_init_done_i;
+         mcb_init_done_reg <= mcb_init_done_reg1;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         run_traffic_o <= run_traffic;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            current_state <= "00001";
+         ELSE
+            current_state <= next_state;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   start_addr_o <= BEGIN_ADDRESS;
+   end_addr_o <= END_ADDRESS;
+   cmd_seed_o <= CMD_SEED_VALUE;
+   data_seed_o <= DATA_SEED_VALUE;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            syn1_vio_data_mode_value <= "011";
+            syn1_vio_addr_mode_value <= "011";
+         ELSIF (vio_modify_enable = '1') THEN
+            syn1_vio_data_mode_value <= vio_data_mode_value;
+            syn1_vio_addr_mode_value <= vio_addr_mode_value;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1') THEN
+            data_mode_sel <= DATA_MODE; --"0101" ADDR_DATA_MODE;
+            addr_mode_sel <= "011";
+         ELSIF (vio_modify_enable = '1') THEN
+            data_mode_sel <= '0' & syn1_vio_data_mode_value(2 DOWNTO 0);
+            addr_mode_sel <= vio_addr_mode_value;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i = '1') OR (FAMILY = "VIRTEX6")) THEN
+            fix_bl_value <= FIXED_BL_VALUE(5 DOWNTO 0);
+         ELSIF (vio_modify_enable = '1') THEN
+            fix_bl_value <= vio_fixed_bl_value;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i = '1' OR (FAMILY = "VIRTEX6")) THEN
+            IF (FAMILY = "VIRTEX6") THEN
+               bl_mode_sel <= FIXED_BL_MODE;
+            ELSE
+               bl_mode_sel <= PRBS_BL_MODE;
+            END IF;
+         ELSIF (vio_modify_enable = '1') THEN
+            bl_mode_sel <= vio_bl_mode_value;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   data_mode_o <= data_mode_reg;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         data_mode_reg <=  data_mode_sel;
+         addr_mode_o <= addr_mode;
+         IF (syn1_vio_addr_mode_value = 0 AND vio_modify_enable = '1') THEN
+             bram_mode_enable <=  '1';
+         ELSE
+             bram_mode_enable <=  '0';
+         END IF;
+        
+         
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (FIXED_BL_VALUE,fix_bl_value,bram_mode_enable,test_mem_instr_mode, current_state, mcb_init_done_reg, end_addr_reached, cmp_error, bl_mode_sel, addr_mode_sel, data_mode_reg,bl_mode_o_xhdl0)
+   BEGIN
+      load_seed_o <= '0';
+      IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
+          addr_mode <= (others => '0');
+      ELSE
+          addr_mode <= SEQUENTIAL_ADDR;
+      END IF;
+      
+      IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
+          instr_mode_o <= (others => '0');
+      ELSE
+          instr_mode_o <= FIXED_INSTR_MODE;
+      END IF;
+      
+      
+      IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
+          bl_mode_o_xhdl0 <= (others => '0');
+      ELSE
+          bl_mode_o_xhdl0 <= FIXED_BL_MODE;
+      END IF;
+--      data_mode1 <= WALKING1_DATA_MODE;
+
+      IF (FAMILY = "VIRTEX6") THEN
+        fixed_bl_o <= FIXED_BL_VALUE(5 downto 0); --"000010"; --2
+        -- PRBS mode
+      else if (data_mode_reg(2 downto 0) = "111" and FAMILY = "SPARTAN6") then
+             fixed_bl_o <= "000000";-- 64  Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
+           else
+             fixed_bl_o <= fix_bl_value;
+           end if;
+      end if;
+
+      mode_load_o <= '0';
+      run_traffic <= '0';
+      
+      next_state <= IDLE;
+      IF (PORT_MODE = "RD_MODE") THEN
+         fixed_instr_o <= RD_INSTR;
+      ELSIF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
+         fixed_instr_o <= WR_INSTR;
+      END IF;
+      
+      CASE current_state IS
+         
+         WHEN IDLE =>
+            IF (mcb_init_done_reg = '1') THEN
+               IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
+                  next_state <= INIT_MEM_WRITE;
+                  mode_load_o <= '1';
+                  run_traffic <= '0';
+                  load_seed_o <= '1';
+               ELSIF (PORT_MODE = "RD_MODE" AND end_addr_reached = '1') THEN
+                  next_state <= TEST_MEM;
+                  mode_load_o <= '1';
+                  run_traffic <= '1';
+                  load_seed_o <= '1';
+               END IF;
+            ELSE
+               next_state <= IDLE;
+               run_traffic <= '0';
+               load_seed_o <= '0';
+            END IF;
+         
+         WHEN INIT_MEM_WRITE =>
+            IF (end_addr_reached = '1' AND EYE_TEST = "FALSE") THEN
+               next_state <= TEST_MEM;
+               mode_load_o <= '1';
+               load_seed_o <= '1';
+               run_traffic <= '1';
+            ELSE
+               next_state <= INIT_MEM_WRITE;
+               run_traffic <= '1';
+               mode_load_o <= '0';
+               load_seed_o <= '0';
+               IF (EYE_TEST = "TRUE") THEN
+                  addr_mode <= FIXED_ADDR;
+               ELSIF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
+                  addr_mode <= "000";
+               ELSE
+                  addr_mode <= SEQUENTIAL_ADDR;
+               END IF;
+            END IF;
+         
+         WHEN INIT_MEM_READ =>
+            IF (end_addr_reached = '1') THEN
+               next_state <= TEST_MEM;
+               mode_load_o <= '1';
+               load_seed_o <= '1';
+            ELSE
+               next_state <= INIT_MEM_READ;
+               run_traffic <= '0';
+               mode_load_o <= '0';
+               load_seed_o <= '0';
+            END IF;
+         
+         WHEN TEST_MEM =>
+            IF (cmp_error = '1') THEN
+               next_state <= CMP_ERROR1;
+            ELSE
+               next_state <= TEST_MEM;
+            END IF;
+
+            run_traffic <= '1';
+
+
+            IF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") THEN
+               fixed_instr_o <= WR_INSTR;
+            ELSIF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") THEN
+               fixed_instr_o <= RD_INSTR;
+               
+            ELSIF (PORT_MODE = "RD_MODE") THEN
+               fixed_instr_o <= RD_INSTR;
+            ELSIF (PORT_MODE = "WR_MODE") THEN
+               fixed_instr_o <= WR_INSTR;
+            END IF;
+
+            if (FAMILY = "VIRTEX6") then
+              fixed_bl_o <= fix_bl_value; --"000010"; 2
+            else if ((data_mode_reg = "0111") and (FAMILY = "SPARTAN6")) then
+                   fixed_bl_o <= "000000";  -- 64  Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
+                 else
+                   fixed_bl_o <= fix_bl_value;
+                 end if; 
+            end if;
+
+            bl_mode_o_xhdl0 <= bl_mode_sel;
+            IF (bl_mode_o_xhdl0 = PRBS_BL_MODE) THEN
+               addr_mode <= PRBS_ADDR;
+            ELSE
+               addr_mode <= addr_mode_sel;
+            END IF;
+
+            IF (PORT_MODE = "BI_MODE") THEN
+               IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
+                  instr_mode_o <= BRAM_INSTR_MODE;
+               ELSE
+                  instr_mode_o  <= test_mem_instr_mode;
+                  --R_RP_W_WP_REF_INSTR_MODE;--FIXED_INSTR_MODE;--R_W_INSTR_MODE;--R_RP_W_WP_INSTR_MODE;--R_W_INSTR_MODE;
+                  --R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
+               END IF;      
+            ELSIF (PORT_MODE = "RD_MODE" OR PORT_MODE = "WR_MODE") THEN
+               instr_mode_o <= FIXED_INSTR_MODE;
+            END IF;
+         
+         WHEN CMP_ERROR1 =>
+            next_state <= CMP_ERROR1;
+            bl_mode_o_xhdl0 <= bl_mode_sel;
+            fixed_instr_o <= RD_INSTR;
+            addr_mode <= SEQUENTIAL_ADDR;
+            IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
+                  instr_mode_o <= BRAM_INSTR_MODE;
+            ELSE
+                  instr_mode_o  <= test_mem_instr_mode;
+               --R_W_INSTR_MODE;--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
+            END IF;
+            run_traffic <= '1';
+         
+         WHEN OTHERS =>
+            next_state <= IDLE;
+      END CASE;
+   END PROCESS;
+   
+   
+END trans;
+
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/isim.sh b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/isim.sh
new file mode 100755
index 0000000..4c23a30
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/isim.sh
@@ -0,0 +1,70 @@
+#!/bin/csh -f
+#*****************************************************************************
+# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# ****************************************************************************
+#   ____  ____
+#  /   /\/   /
+# /___/  \  /    Vendor                : Xilinx
+# \   \   \/     Version               : 3.92
+#  \   \         Application           : MIG
+#  /   /         Filename              : isim.bat
+# /___/   /\     Date Last Modified    : $Date: 2011/06/02 07:16:55 $
+# \   \  /  \    Date Created          : Fri Feb 06 2009
+#  \___\/\___\
+#
+# Device            : Spartan-6
+# Design Name       : DDR/DDR2/DDR3/LPDDR
+# Purpose           : Batch file to run Simulation through ISIM
+# Reference         :
+# Revision History  :
+# ****************************************************************************
+
+echo Simulation Tool: ISIM
+fuse work.sim_tb_top work.glbl -prj ddr2.prj -L unisim -L secureip -timeprecision_vhdl fs -o ddr2
+./ddr2 -gui -tclbatch isim.tcl -wdb ddr2.wdb
+echo done
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/isim.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/isim.tcl
new file mode 100644
index 0000000..dc37142
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/isim.tcl
@@ -0,0 +1,72 @@
+###############################################################################
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+###############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor             : Xilinx
+## \   \   \/     Version            : 3.92
+##  \   \         Application	     : MIG
+##  /   /         Filename           : isim.tcl
+## /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:55 $
+## \   \  /  \    Date Created       : Mon Mar 2 2009
+##  \___\/\___\
+##
+## Device          : Spartan-6
+## Design Name     : DDR/DDR2/DDR3/LPDDR
+## Purpose         : To give commands to ISIM Simulator through batch mode
+## Assumptions:
+##      - Simulation takes place in \sim folder of MIG output directory
+## Reference       :
+## Revision History:
+###############################################################################
+
+onerror {resume}
+isim set radix hex
+wave add /sim_tb_top
+run 200 us
+quit
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/mcb_flow_control.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/mcb_flow_control.vhd
new file mode 100755
index 0000000..123ba93
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/mcb_flow_control.vhd
@@ -0,0 +1,539 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_flow_control.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:40 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This module is the main flow control between cmd_gen.v, 
+--         write_data_path and read_data_path modules.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+
+ENTITY mcb_flow_control IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+      FAMILY          : STRING := "SPARTAN6"
+   );
+   PORT (
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      cmd_rdy_o       : OUT STD_LOGIC;
+      cmd_valid_i     : IN STD_LOGIC;
+      cmd_i           : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      mcb_cmd_full    : IN STD_LOGIC;
+      cmd_o           : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      addr_o          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bl_o            : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+      cmd_en_o        : OUT STD_LOGIC;
+      last_word_wr_i  : IN STD_LOGIC;
+      wdp_rdy_i       : IN STD_LOGIC;
+      wdp_valid_o     : OUT STD_LOGIC;
+      wdp_validB_o    : OUT STD_LOGIC;
+      wdp_validC_o    : OUT STD_LOGIC;
+      wr_addr_o       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      wr_bl_o         : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+      last_word_rd_i  : IN STD_LOGIC;
+      rdp_rdy_i       : IN STD_LOGIC;
+      rdp_valid_o     : OUT STD_LOGIC;
+      rd_addr_o       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      rd_bl_o         : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+   );
+END mcb_flow_control;
+
+ARCHITECTURE trans OF mcb_flow_control IS
+
+   constant    READY           : std_logic_vector(4 downto 0)  := "00001";
+   constant    READ            : std_logic_vector(4 downto 0)  := "00010";
+   constant    WRITE           : std_logic_vector(4 downto 0)  := "00100";
+   constant    CMD_WAIT        : std_logic_vector(4 downto 0)  := "01000";
+   constant    REFRESH_ST      : std_logic_vector(4 downto 0)  := "10000";
+      
+   constant    RD              : std_logic_vector(2 downto 0)  := "001";
+   constant    RDP             : std_logic_vector(2 downto 0)  := "011";
+   constant    WR              : std_logic_vector(2 downto 0)  := "000";
+   constant    WRP             : std_logic_vector(2 downto 0)  := "010";
+   constant    REFRESH         : std_logic_vector(2 downto 0)  := "100";
+   constant    NOP             : std_logic_vector(2 downto 0)  := "101";
+   
+   SIGNAL cmd_fifo_rdy      : STD_LOGIC;
+   SIGNAL cmd_rd            : STD_LOGIC;
+   SIGNAL cmd_wr            : STD_LOGIC;
+   SIGNAL cmd_others        : STD_LOGIC;
+   SIGNAL push_cmd          : STD_LOGIC;
+   SIGNAL xfer_cmd          : STD_LOGIC;
+   SIGNAL rd_vld            : STD_LOGIC;
+   SIGNAL wr_vld            : STD_LOGIC;
+   SIGNAL cmd_rdy           : STD_LOGIC;
+   SIGNAL cmd_reg           : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL addr_reg          : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL bl_reg            : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   
+   SIGNAL rdp_valid         : STD_LOGIC;
+   SIGNAL wdp_valid         : STD_LOGIC;
+   SIGNAL wdp_validB        : STD_LOGIC;
+   SIGNAL wdp_validC        : STD_LOGIC;
+   
+   SIGNAL current_state     : STD_LOGIC_VECTOR(4 DOWNTO 0);
+   SIGNAL next_state        : STD_LOGIC_VECTOR(4 DOWNTO 0);
+   SIGNAL tstpointA         : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL push_cmd_r        : STD_LOGIC;
+   SIGNAL wait_done         : STD_LOGIC;
+   SIGNAL cmd_en_r1         : STD_LOGIC;
+   SIGNAL wr_in_progress    : STD_LOGIC;
+   SIGNAL tst_cmd_rdy_o     : STD_LOGIC;
+   
+   SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
+   SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
+   
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL cmd_rdy_o_xhdl0   : STD_LOGIC;
+BEGIN
+   -- Drive referenced outputs
+   cmd_rdy_o <= cmd_rdy_o_xhdl0;
+   cmd_en_o <= cmd_en_r1;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         cmd_rdy_o_xhdl0 <= cmd_rdy;
+         tst_cmd_rdy_o <= cmd_rdy;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(8)) = '1') THEN
+            cmd_en_r1 <= '0' ;
+         ELSIF (xfer_cmd = '1') THEN
+            cmd_en_r1 <= '1' ;
+         ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
+            cmd_en_r1 <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(9)) = '1') THEN
+            cmd_fifo_rdy <= '1';
+         ELSIF (xfer_cmd = '1') THEN
+            cmd_fifo_rdy <= '0';
+         ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
+            cmd_fifo_rdy <= '1';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(9)) = '1') THEN
+            addr_o <= (others => '0');
+            cmd_o <= (others => '0');
+            bl_o <= (others => '0');
+         ELSIF (xfer_cmd = '1') THEN
+            addr_o <= addr_reg;
+            IF (FAMILY = "SPARTAN6") THEN
+               cmd_o <= cmd_reg;
+            ELSE
+               cmd_o <= ("00" & cmd_reg(0));
+            END IF;
+            bl_o <= bl_reg;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   wr_addr_o <= addr_i;
+   rd_addr_o <= addr_i;
+   rd_bl_o <= bl_i;
+   wr_bl_o <= bl_i;
+   wdp_valid_o <= wdp_valid;
+   wdp_validB_o <= wdp_validB;
+   wdp_validC_o <= wdp_validC;
+   rdp_valid_o <= rdp_valid;
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_i(8)) = '1') THEN
+            wait_done <= '1' ;
+         ELSIF (push_cmd_r = '1') THEN
+            wait_done <= '1' ;
+         ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
+            wait_done <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         push_cmd_r <= push_cmd ;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (push_cmd = '1') THEN
+            cmd_reg <= cmd_i ;
+            addr_reg <= addr_i ;
+            bl_reg <= bl_i - "000001" ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
+             '0';                        
+   cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
+             '0';
+   cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
+                 '0';
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0)= '1') THEN
+            
+            cmd_wr_pending_r1 <= '0' ;
+         ELSIF (last_word_wr_i = '1') THEN
+            
+            cmd_wr_pending_r1 <= '1' ;
+         ELSIF (push_cmd = '1') THEN
+            cmd_wr_pending_r1 <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((cmd_rd AND push_cmd) = '1') THEN
+            cmd_rd_pending_r1 <= '1' ;
+         ELSIF (xfer_cmd = '1') THEN
+            
+            cmd_rd_pending_r1 <= '0' ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0)= '1') THEN
+            wr_in_progress <= '0';
+         ELSIF (last_word_wr_i = '1') THEN
+            wr_in_progress <= '0';
+         ELSIF (current_state = WRITE) THEN
+            
+            wr_in_progress <= '1';
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF (rst_i(0)= '1') THEN
+            current_state <= "00001" ;
+         ELSE
+            current_state <= next_state ;
+         END IF;
+      END IF;
+   END PROCESS;
+   
+   
+   PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
+   BEGIN
+      push_cmd <= '0';
+      
+      xfer_cmd <= '0';
+      wdp_valid <= '0';
+      wdp_validB <= '0';
+      
+      wdp_validC <= '0';
+      rdp_valid <= '0';
+      cmd_rdy <= '0';
+      next_state <= current_state;
+      CASE current_state IS
+         
+         WHEN READY =>
+            IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               xfer_cmd <= '0';
+               rdp_valid <= '1';
+
+            ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
+               next_state <= WRITE;
+               push_cmd <= '1';
+               wdp_valid <= '1';
+               wdp_validB <= '1';
+               wdp_validC <= '1';
+
+            ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
+               next_state <= REFRESH_ST;
+               push_cmd <= '1';
+               xfer_cmd <= '0';
+
+            ELSE
+               next_state <= READY;
+               push_cmd <= '0';
+            END IF;
+
+            IF (cmd_fifo_rdy = '1') THEN
+               cmd_rdy <= '1';
+            ELSE
+               cmd_rdy <= '0';
+            END IF;
+
+         WHEN REFRESH_ST =>
+            IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               rdp_valid <= '1';
+               wdp_valid <= '0';
+               xfer_cmd <= '1';
+               
+            ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
+               next_state <= WRITE;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               
+               wdp_valid     <= '1';
+               wdp_validB    <= '1';
+               wdp_validC    <= '1';               
+             
+            ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+
+            ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
+               next_state <= CMD_WAIT;
+               tstpointA  <= "1001";
+
+            ELSE
+               next_state <= READ; 
+
+            END IF;
+               
+            IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
+              cmd_rdy <= '1';
+            ELSE 
+              cmd_rdy <= '0';
+            END IF;
+
+         WHEN READ =>
+            IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               rdp_valid <= '1';
+               wdp_valid <= '0';
+               xfer_cmd <= '1';
+               tstpointA <= "0101";
+            ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
+               next_state <= WRITE;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               wdp_valid <= '1';
+               wdp_validB <= '1';
+               wdp_validC <= '1';
+               tstpointA <= "0110";
+            ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '0';
+               xfer_cmd <= '0';
+               tstpointA <= "0111";
+               wdp_valid <= '0';
+               wdp_validB <= '0';
+               wdp_validC <= '0';
+               rdp_valid <= '0';
+            ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
+               next_state <= REFRESH_ST;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               wdp_valid <= '0';
+               wdp_validB <= '0';
+               wdp_validC <= '0';
+               rdp_valid <= '0';
+               tstpointA <= "1000";
+            ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
+               next_state <= CMD_WAIT;
+               tstpointA <= "1001";
+            ELSE
+               next_state <= READ;
+            END IF;
+
+            IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
+             cmd_rdy <= wait_done; --'1';
+            ELSE
+               cmd_rdy <= '0';
+            END IF;
+         
+         WHEN WRITE =>
+            IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               rdp_valid <= '1';
+               tstpointA <= "0000";
+            ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
+               next_state <= WRITE;
+               tstpointA <= "0001";
+               IF ((cmd_wr AND last_word_wr_i) = '1') THEN
+                  wdp_valid <= '1';
+                  wdp_validB <= '1';
+                  wdp_validC <= '1';
+               ELSE
+                  wdp_valid <= '0';
+                  wdp_validB <= '0';
+                  wdp_validC <= '0';
+               END IF;
+               IF (last_word_wr_i = '1') THEN
+                  push_cmd <= '1';
+                  xfer_cmd <= '1';
+               ELSE
+                  push_cmd <= '0';
+                  xfer_cmd <= '0';
+               END IF;
+            ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
+               next_state <= REFRESH_ST;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               tstpointA <= "0010";
+               wdp_valid <= '0';
+               wdp_validB <= '0';
+               wdp_validC <= '0';
+               rdp_valid <= '0';
+            ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
+               next_state <= CMD_WAIT;
+               push_cmd <= '0';
+               xfer_cmd <= '0';
+               tstpointA <= "0011";
+            ELSE
+               next_state <= WRITE;
+               tstpointA <= "0100";
+            END IF;
+            IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
+               cmd_rdy <= wait_done;
+            ELSE
+               cmd_rdy <= '0';
+            END IF;
+         
+         WHEN CMD_WAIT =>
+            IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
+               next_state <= CMD_WAIT;
+               cmd_rdy <= '0';
+               tstpointA <= "1010";
+            ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
+               next_state <= READ;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               cmd_rdy <= '1';
+               rdp_valid <= '1';
+               tstpointA <= "1011";
+            ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
+               next_state <= WRITE;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               wdp_valid <= '1';
+               wdp_validB <= '1';
+               wdp_validC <= '1';
+               cmd_rdy <= '1';
+               tstpointA <= "1100";
+            ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
+               next_state <= REFRESH_ST;
+               push_cmd <= '1';
+               xfer_cmd <= '1';
+               tstpointA <= "1101";
+               cmd_rdy <= '1';
+            ELSE
+               next_state <= CMD_WAIT;
+               tstpointA <= "1110";
+               IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
+                  cmd_rdy <= '1';
+               ELSE
+                  cmd_rdy <= '0';
+               END IF;
+            END IF;
+         
+         WHEN OTHERS =>
+            push_cmd <= '0';
+            xfer_cmd <= '0';
+            wdp_valid <= '0';
+            wdp_validB <= '0';
+            wdp_validC <= '0';
+            next_state <= READY;
+      END CASE;
+   END PROCESS;
+   
+   
+END trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/mcb_traffic_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/mcb_traffic_gen.vhd
new file mode 100755
index 0000000..bb23d62
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/mcb_traffic_gen.vhd
@@ -0,0 +1,1001 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: mcb_traffic_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR
+-- Purpose: This is top level module of memory traffic generator which can
+--         generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
+--         hard memory controller core.
+-- Reference:
+-- Revision History:      2009      Brought out internal signals cmp_data and cmp_error as outputs.
+--                        2010/01/09  Removed the rd_mdata_afull_set term in signal rdpath_data_valid_i .
+--                        2010/05/03  Removed local generated version of  mcb_rd_empty and mcb_wr_full in TG.
+--                        2010/05/20  If MEM_BURST_LEN value is passed with value of zero, it is treated as
+--                                    "OTF" Burst Mode and TG will only generate BL 8 traffic.
+
+--*****************************************************************************
+
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+ENTITY mcb_traffic_gen IS
+   GENERIC (
+      TCQ                   : TIME := 100 ps;
+      FAMILY                : STRING := "SPARTAN6";
+      SIMULATION            : STRING := "FALSE";
+      MEM_BURST_LEN         : INTEGER := 8;
+      PORT_MODE             : STRING := "BI_MODE";
+      DATA_PATTERN          : STRING := "DGEN_ADDR";
+      CMD_PATTERN           : STRING := "CGEN_ALL";
+
+      ADDR_WIDTH            : INTEGER := 30;
+
+      CMP_DATA_PIPE_STAGES  : INTEGER := 0;
+
+      MEM_COL_WIDTH         : INTEGER := 10;
+      NUM_DQ_PINS           : INTEGER := 16;
+      DQ_ERROR_WIDTH        : integer := 1;
+
+      SEL_VICTIM_LINE       : INTEGER := 3;
+      DWIDTH                : INTEGER := 32;
+
+      EYE_TEST              : STRING  := "FALSE";
+
+
+      PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+      PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+      PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00005000"
+   );
+   PORT (
+
+      clk_i                 : IN STD_LOGIC;
+      rst_i                 : IN STD_LOGIC;
+      run_traffic_i         : IN STD_LOGIC;
+      manual_clear_error    : IN STD_LOGIC;
+      start_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      end_addr_i            : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmd_seed_i            : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      data_seed_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      load_seed_i           : IN STD_LOGIC;
+
+      addr_mode_i           : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+
+      instr_mode_i          : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+      bl_mode_i             : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+
+      data_mode_i           : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+      mode_load_i           : IN STD_LOGIC;
+
+      fixed_bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      fixed_instr_i         : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+
+      fixed_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      fixed_data_i          : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0) := (others => '0');
+      bram_cmd_i            : IN STD_LOGIC_VECTOR(38 DOWNTO 0);
+      bram_valid_i          : IN STD_LOGIC;
+      bram_rdy_o            : OUT STD_LOGIC;
+
+      mcb_cmd_en_o          : OUT STD_LOGIC;
+      mcb_cmd_instr_o       : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      mcb_cmd_addr_o        : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      mcb_cmd_bl_o          : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+      mcb_cmd_full_i        : IN STD_LOGIC;
+
+      mcb_wr_en_o           : OUT STD_LOGIC;
+      mcb_wr_data_o         : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      mcb_wr_data_end_o     : OUT STD_LOGIC;
+      mcb_wr_mask_o         : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
+
+      mcb_wr_full_i         : IN STD_LOGIC;
+      mcb_wr_fifo_counts    : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+      mcb_rd_en_o           : OUT STD_LOGIC;
+      mcb_rd_data_i         : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      mcb_rd_empty_i        : IN STD_LOGIC;
+      mcb_rd_fifo_counts    : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+      counts_rst            : IN STD_LOGIC;
+      wr_data_counts        : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+      rd_data_counts        : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+
+      error                 : OUT STD_LOGIC;
+      cmp_data_valid        : OUT STD_LOGIC;
+
+      error_status          : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
+      cmp_error             : out std_logic;
+      cmp_data              : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
+      mem_rd_data           : OUT STD_LOGIC_VECTOR( DWIDTH - 1 DOWNTO 0);
+      dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
+      cumlative_dq_lane_error  :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
+
+
+   );
+END mcb_traffic_gen;
+
+ARCHITECTURE trans OF mcb_traffic_gen IS
+   COMPONENT mcb_flow_control IS
+     GENERIC (
+         TCQ             : TIME   := 100 ps;
+         FAMILY                         : string := "SPARTAN6"
+      );
+      PORT (
+         clk_i                 : IN STD_LOGIC;
+         rst_i                 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+         cmd_rdy_o             : OUT STD_LOGIC;
+         cmd_valid_i           : IN STD_LOGIC;
+         cmd_i                 : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         addr_i                : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         bl_i                  : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+         mcb_cmd_full          : IN STD_LOGIC;
+         cmd_o                 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+         addr_o                : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         bl_o                  : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+         cmd_en_o              : OUT STD_LOGIC;
+         last_word_wr_i        : IN STD_LOGIC;
+         wdp_rdy_i             : IN STD_LOGIC;
+         wdp_valid_o           : OUT STD_LOGIC;
+         wdp_validB_o          : OUT STD_LOGIC;
+         wdp_validC_o          : OUT STD_LOGIC;
+         wr_addr_o             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         wr_bl_o               : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+         last_word_rd_i        : IN STD_LOGIC;
+         rdp_rdy_i             : IN STD_LOGIC;
+         rdp_valid_o           : OUT STD_LOGIC;
+         rd_addr_o             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         rd_bl_o               : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+      );
+   END COMPONENT;
+
+   COMPONENT cmd_gen IS
+      GENERIC (
+         TCQ             : TIME   := 100 ps;
+         PORT_MODE            : STRING  := "BI_MODE";
+         FAMILY                : STRING := "SPARTAN6";
+         MEM_BURST_LEN         : INTEGER := 8;
+         NUM_DQ_PINS           : INTEGER := 8;
+         DATA_PATTERN          : STRING := "DGEN_PRBS";
+         CMD_PATTERN           : STRING := "CGEN_ALL";
+         ADDR_WIDTH            : INTEGER := 30;
+         DWIDTH                : INTEGER := 32;
+         PIPE_STAGES           : INTEGER := 0;
+         MEM_COL_WIDTH         : INTEGER := 10;
+         PRBS_EADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"FFFFD000";
+         PRBS_SADDR_MASK_POS  : std_logic_vector(31 downto 0)  := X"00002000";
+         PRBS_EADDR           : std_logic_vector(31 downto 0)  := X"00002000";
+         PRBS_SADDR           : std_logic_vector(31 downto 0)  := X"00005000"
+      );
+      PORT (
+         clk_i                 : IN STD_LOGIC;
+         rst_i                 : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+         run_traffic_i         : IN STD_LOGIC;
+         rd_buff_avail_i       : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+         force_wrcmd_gen_i     : IN STD_LOGIC;
+         start_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         end_addr_i            : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         cmd_seed_i            : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         data_seed_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         load_seed_i           : IN STD_LOGIC;
+         addr_mode_i           : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         data_mode_i           : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+         instr_mode_i          : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+         bl_mode_i             : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+         mode_load_i           : IN STD_LOGIC;
+         fixed_bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+         fixed_instr_i         : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         fixed_addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         bram_addr_i           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         bram_instr_i          : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         bram_bl_i             : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+         bram_valid_i          : IN STD_LOGIC;
+         bram_rdy_o            : OUT STD_LOGIC;
+         reading_rd_data_i     : IN STD_LOGIC;
+         rdy_i                 : IN STD_LOGIC;
+         addr_o                : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         instr_o               : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+         bl_o                  : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+--         m_addr_o              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+         cmd_o_vld             : OUT STD_LOGIC
+      );
+   END COMPONENT;
+
+
+   component afifo IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+      DSIZE       : INTEGER := 32;
+      FIFO_DEPTH  : INTEGER := 16;
+      ASIZE       : INTEGER := 4;
+      SYNC        : INTEGER := 1
+   );
+   PORT (
+      wr_clk      : IN STD_LOGIC;
+      rst         : IN STD_LOGIC;
+      wr_en       : IN STD_LOGIC;
+      wr_data     : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      rd_en       : IN STD_LOGIC;
+      rd_clk      : IN STD_LOGIC;
+      rd_data     : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      full        : OUT STD_LOGIC;
+      almost_full : OUT STD_LOGIC;
+      empty       : OUT STD_LOGIC
+   );
+END component;
+
+component read_data_path IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+
+      FAMILY                : STRING := "SPARTAN6";
+      MEM_BURST_LEN         : INTEGER := 8;
+      ADDR_WIDTH            : INTEGER := 32;
+      CMP_DATA_PIPE_STAGES  : INTEGER := 3;
+      DWIDTH                : INTEGER := 32;
+      DATA_PATTERN          : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
+      NUM_DQ_PINS           : INTEGER := 8;
+      DQ_ERROR_WIDTH        : INTEGER := 1;
+      SEL_VICTIM_LINE       : integer := 3;
+      MEM_COL_WIDTH         : INTEGER := 10
+   );
+   PORT (
+
+      clk_i                 : IN STD_LOGIC;
+      rst_i                 : in std_logic_vector(9 downto 0);
+      manual_clear_error    : IN STD_LOGIC;
+      cmd_rdy_o             : OUT STD_LOGIC;
+      cmd_valid_i           : IN STD_LOGIC;
+      prbs_fseed_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+      data_mode_i           : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      cmd_sent              : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      bl_sent               : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      cmd_en_i              : IN STD_LOGIC;
+--      m_addr_i              : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      fixed_data_i          : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
+
+      addr_i                : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bl_i                  : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+      data_rdy_o            : OUT STD_LOGIC;
+      data_valid_i          : IN STD_LOGIC;
+      data_i                : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      last_word_rd_o        : OUT STD_LOGIC;
+      data_error_o          : OUT STD_LOGIC;
+      cmp_data_o            : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      rd_mdata_o            : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      cmp_data_valid        : OUT STD_LOGIC;
+      cmp_addr_o            : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+      cmp_bl_o              : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+      force_wrcmd_gen_o              : out std_logic;
+      rd_buff_avail_o                : out std_logic_vector(6 downto 0);
+      dq_error_bytelane_cmp :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0);
+      cumlative_dq_lane_error_r  :OUT STD_LOGIC_VECTOR(DQ_ERROR_WIDTH - 1 DOWNTO 0)
+
+
+   );
+END component;
+
+component write_data_path IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+      FAMILY          : STRING := "SPARTAN6";
+      MEM_BURST_LEN   : INTEGER := 8;
+      ADDR_WIDTH      : INTEGER := 32;
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_ALL";
+      NUM_DQ_PINS     : INTEGER := 8;
+      SEL_VICTIM_LINE : INTEGER := 3;
+      MEM_COL_WIDTH   : INTEGER := 10;
+      EYE_TEST        : string := "FALSE"
+   );
+   PORT (
+
+      clk_i           : IN STD_LOGIC;
+      rst_i           : in std_logic_vector(9 downto 0);
+      cmd_rdy_o       : OUT STD_LOGIC;
+      cmd_valid_i     : IN STD_LOGIC;
+      cmd_validB_i    : IN STD_LOGIC;
+      cmd_validC_i    : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+--      m_addr_i        : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      fixed_data_i          : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
+
+      addr_i          : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      bl_i            : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      data_valid_o    : OUT STD_LOGIC;
+      last_word_wr_o  : OUT STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      data_mask_o     : OUT STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
+      data_wr_end_o   : out std_logic
+   );
+END component;
+
+component tg_status IS
+   GENERIC (
+      TCQ             : TIME   := 100 ps;
+      DWIDTH          : INTEGER := 32
+   );
+   PORT (
+
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      manual_clear_error : IN STD_LOGIC;
+      data_error_i    : IN STD_LOGIC;
+      cmp_data_i      : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      rd_data_i       : IN STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+      cmp_addr_i      : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      cmp_bl_i        : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+      mcb_cmd_full_i  : IN STD_LOGIC;
+      mcb_wr_full_i   : IN STD_LOGIC;
+      mcb_rd_empty_i  : IN STD_LOGIC;
+      error_status    : OUT STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
+      error           : OUT STD_LOGIC
+   );
+
+
+END component;
+
+   attribute KEEP                 : STRING;
+   attribute MAX_FANOUT           : STRING;
+
+
+function MEM_BLENGTH return integer is
+  begin
+    if (MEM_BURST_LEN = 4) then
+      return 4;
+    elsif (MEM_BURST_LEN = 8) then
+      return 8;
+    else
+      return 8;
+    end if;
+  end function MEM_BLENGTH;
+
+   
+   constant MEM_BLEN : INTEGER := MEM_BLENGTH;
+
+   SIGNAL mcb_wr_en               : STD_LOGIC;
+   SIGNAL cmd2flow_valid          : STD_LOGIC;
+   SIGNAL cmd2flow_cmd            : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL cmd2flow_addr           : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL cmd2flow_bl             : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL last_word_rd            : STD_LOGIC;
+   SIGNAL last_word_wr            : STD_LOGIC;
+   SIGNAL flow2cmd_rdy            : STD_LOGIC;
+   SIGNAL wr_addr                 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL rd_addr                 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL wr_bl                   : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL rd_bl                   : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL run_traffic_reg         : STD_LOGIC;
+   SIGNAL wr_validB               : STD_LOGIC;
+   SIGNAL wr_valid                : STD_LOGIC;
+   SIGNAL wr_validC               : STD_LOGIC;
+   SIGNAL bram_addr_i             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL bram_instr_i            : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL bram_bl_i               : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL AC2_G_E2                : STD_LOGIC;
+   SIGNAL AC1_G_E1                : STD_LOGIC;
+   SIGNAL AC3_G_E3                : STD_LOGIC;
+   SIGNAL upper_end_matched       : STD_LOGIC;
+   SIGNAL end_boundary_addr       : STD_LOGIC_VECTOR(7 DOWNTO 0);
+   SIGNAL lower_end_matched       : STD_LOGIC;
+   SIGNAL addr_o                  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--   SIGNAL m_addr                  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL dcount_rst              : STD_LOGIC;
+   SIGNAL rd_addr_error           : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL rd_rdy                  : STD_LOGIC;
+   SIGNAL cmp_error_int               : STD_LOGIC;
+   SIGNAL cmd_full                : STD_LOGIC;
+
+   SIGNAL cmp_data_int                : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+   SIGNAL mem_rd_data_i             : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+   SIGNAL cmp_addr                : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL cmp_bl                  : STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+   SIGNAL rst_ra                  : STD_LOGIC_VECTOR(9 DOWNTO 0);
+   SIGNAL rst_rb                  : STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+   SIGNAL mcb_wr_full_r1          : STD_LOGIC;
+   SIGNAL mcb_wr_full_r2          : STD_LOGIC;
+   SIGNAL mcb_rd_empty_r          : STD_LOGIC;
+   SIGNAL force_wrcmd_gen         : STD_LOGIC;
+   SIGNAL rd_buff_avail           : STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+   SIGNAL data_mode_r_a           : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL data_mode_r_b           : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL data_mode_r_c           : STD_LOGIC_VECTOR(3 DOWNTO 0);
+   SIGNAL tmp_address             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL error_access_range      : STD_LOGIC ;
+
+   SIGNAL mcb_rd_empty            : STD_LOGIC;
+
+   SIGNAL mcb_wr_full             : STD_LOGIC;
+
+   SIGNAL end_addr_r              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+   SIGNAL wr_rdy                  : STD_LOGIC;
+
+   SIGNAL rd_valid                : STD_LOGIC;
+
+   SIGNAL cmd_rd_en               : STD_LOGIC;
+   -- X-HDL generated signals
+
+   SIGNAL xhdl14 : STD_LOGIC_VECTOR(37 DOWNTO 0);
+   SIGNAL xhdl15 : STD_LOGIC_VECTOR(32 DOWNTO 0);
+   SIGNAL xhdl17 : STD_LOGIC;
+   SIGNAL xhdl19 : STD_LOGIC;
+   SIGNAL ZEROS  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+   -- Declare intermediate signals for referenced outputs
+   SIGNAL bram_rdy_o_xhdl0        : STD_LOGIC;
+   SIGNAL mcb_cmd_en_o_xhdl5      : STD_LOGIC;
+   SIGNAL mcb_cmd_instr_o_xhdl6   : STD_LOGIC_VECTOR(2 DOWNTO 0);
+   SIGNAL mcb_cmd_addr_o_xhdl3    : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+   SIGNAL mcb_cmd_bl_o_xhdl4      : STD_LOGIC_VECTOR(5 DOWNTO 0);
+   SIGNAL mcb_wr_data_o_xhdl9     : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+   SIGNAL mcb_wr_data_end_o_xhdl8 : STD_LOGIC;
+   SIGNAL mcb_wr_mask_o_xhdl10    : STD_LOGIC_VECTOR((DWIDTH / 8) - 1 DOWNTO 0);
+   SIGNAL mcb_rd_en       : STD_LOGIC;
+   SIGNAL wr_data_counts_xhdl12   : STD_LOGIC_VECTOR(47 DOWNTO 0);
+   SIGNAL rd_data_counts_xhdl11   : STD_LOGIC_VECTOR(47 DOWNTO 0);
+   SIGNAL error_xhdl1             : STD_LOGIC;
+   SIGNAL error_status_xhdl2      : STD_LOGIC_VECTOR(64 + (2 * DWIDTH - 1) DOWNTO 0);
+
+   SIGNAL cmd_fifo_wr             : STD_LOGIC;
+   SIGNAL xfer_addr               : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL fifo_error              : STD_LOGIC;
+   SIGNAL cmd_fifo_rd             : STD_LOGIC;
+   SIGNAL cmd_fifo_empty          : STD_LOGIC;
+   SIGNAL xfer_cmd_bl             : STD_LOGIC;
+   SIGNAL cmd_fifo_full           : STD_LOGIC;
+   SIGNAL rd_mdata_afull_set      :  STD_LOGIC;
+   SIGNAL rd_mdata_fifo_afull     :  STD_LOGIC;
+   SIGNAL rdpath_data_valid_i : STD_LOGIC;
+   SIGNAL rdpath_rd_data_i : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+    SIGNAL rd_mdata_fifo_empty : STD_LOGIC;
+   SIGNAL rd_v6_mdata             : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+   SIGNAL mdata_wren              : STD_LOGIC;
+   attribute KEEP            of rst_ra : signal is "TRUE";
+   attribute KEEP            of rst_rb : signal is "TRUE";
+   attribute KEEP            of mcb_wr_full_r1 : signal is "TRUE";
+   attribute KEEP            of mcb_wr_full_r2 : signal is "TRUE";
+   attribute MAX_FANOUT      of rst_ra : signal is "20";
+   attribute MAX_FANOUT      of rst_rb : signal is "20";
+
+
+BEGIN
+
+
+   mem_rd_data <= mem_rd_data_i;
+   ZEROS <= (others => '0');
+
+   cmp_data <= cmp_data_int;
+   cmp_error <= cmp_error_int;
+   -- Drive referenced outputs
+   bram_rdy_o <= bram_rdy_o_xhdl0;
+   mcb_cmd_en_o <= mcb_cmd_en_o_xhdl5;
+   mcb_cmd_instr_o <= mcb_cmd_instr_o_xhdl6;
+   mcb_cmd_addr_o <= mcb_cmd_addr_o_xhdl3;
+   mcb_cmd_bl_o <= mcb_cmd_bl_o_xhdl4;
+   mcb_wr_data_o <= mcb_wr_data_o_xhdl9;
+   mcb_wr_data_end_o <= mcb_wr_data_end_o_xhdl8;
+   mcb_wr_mask_o <= mcb_wr_mask_o_xhdl10;
+   mcb_rd_en_o <= mcb_rd_en;
+   wr_data_counts <= wr_data_counts_xhdl12;
+   rd_data_counts <= std_logic_vector(rd_data_counts_xhdl11);
+   error <= error_xhdl1;
+   error_status <= error_status_xhdl2;
+   tmp_address <= std_logic_vector(to_unsigned((to_integer(unsigned(mcb_cmd_addr_o_xhdl3)) + to_integer(unsigned(mcb_cmd_bl_o_xhdl4)) * (DWIDTH / 8)),32));
+--   tmp_address <= ("00" & mcb_cmd_addr_o_xhdl3 + ("000000000000000000000000" & mcb_cmd_bl_o_xhdl4 * to_stdlogicvector(DWIDTH, 6) / "001000"));
+
+--synthesis translate_off
+   PROCESS
+   BEGIN
+     IF ((MEM_BURST_LEN /= 4) AND (MEM_BURST_LEN /= 8)) THEN
+       report "Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!";
+       report "If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic.";
+       
+     END IF;
+     WAIT;
+   END PROCESS;
+
+   PROCESS (mcb_cmd_en_o_xhdl5, mcb_cmd_addr_o_xhdl3, mcb_cmd_bl_o_xhdl4, end_addr_i,tmp_address)
+   BEGIN
+      IF (mcb_cmd_en_o_xhdl5 = '1' AND (tmp_address > end_addr_i)) THEN
+         report "Error ! Data access beyond address range"; -- severity ERROR;
+         error_access_range <= '1';
+         -- $stop();
+      END IF;
+   END PROCESS;
+--synthesis translate_on
+
+    mcb_rd_empty <= mcb_rd_empty_i;
+
+    mcb_wr_full <= mcb_wr_full_i;
+
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         data_mode_r_a <= data_mode_i;
+         data_mode_r_b <= data_mode_i;
+         data_mode_r_c <= data_mode_i;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_ra(0)) = '1') THEN
+            mcb_wr_full_r1 <= '0';
+         ELSIF (mcb_wr_fifo_counts >= "0111111") THEN
+            mcb_wr_full_r1 <= '1';
+            mcb_wr_full_r2 <= '1';
+         ELSE
+            mcb_wr_full_r1 <= '0';
+            mcb_wr_full_r2 <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         IF ((rst_ra(0)) = '1') THEN
+            mcb_rd_empty_r <= '1';
+         ELSIF (mcb_rd_fifo_counts <= "0000001") THEN
+            mcb_rd_empty_r <= '1';
+         ELSE
+            mcb_rd_empty_r <= '0';
+         END IF;
+      END IF;
+   END PROCESS;
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         rst_ra <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
+         rst_rb <= (rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i & rst_i);
+      END IF;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') THEN
+         run_traffic_reg <= run_traffic_i;
+      END IF;
+   END PROCESS;
+
+   bram_addr_i <= (bram_cmd_i(29 DOWNTO 0) & "00");
+   bram_instr_i <= bram_cmd_i(32 DOWNTO 30);
+   bram_bl_i(5 DOWNTO 0) <= bram_cmd_i(38 DOWNTO 33);
+   dcount_rst <= counts_rst OR rst_ra(0);
+
+
+
+
+   PROCESS (clk_i)
+   BEGIN
+      IF (clk_i'EVENT AND clk_i = '1') then
+      IF (dcount_rst = '1') THEN
+         wr_data_counts_xhdl12 <= (OTHERS => '0');
+      ELSIF (mcb_wr_en = '1') THEN
+            wr_data_counts_xhdl12 <= wr_data_counts_xhdl12 + std_logic_vector(to_unsigned(DWIDTH/8,48));
+      END IF;
+      end if;
+   END PROCESS;
+
+   PROCESS (clk_i)
+   BEGIN
+     IF (clk_i'EVENT AND clk_i = '1') then
+      IF (dcount_rst = '1') THEN
+         rd_data_counts_xhdl11 <= (others => '0');
+      ELSIF (mcb_rd_en = '1') THEN
+            rd_data_counts_xhdl11 <= rd_data_counts_xhdl11 + std_logic_vector(to_unsigned(DWIDTH/8,48));
+      END IF;
+    end if;
+   END PROCESS;
+
+   xhdl13 : IF (SIMULATION = "TRUE") GENERATE
+      cmd_fifo_wr <= flow2cmd_rdy AND cmd2flow_valid;
+      PROCESS (clk_i)
+      BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            IF (mcb_cmd_en_o_xhdl5 = '1') THEN
+                       if (xfer_addr /= (ZEROS(31 downto ADDR_WIDTH) & mcb_cmd_addr_o_xhdl3)) then
+                  fifo_error <= '1';
+               ELSE
+                  fifo_error <= '0';
+               END IF;
+            END IF;
+         END IF;
+      END PROCESS;
+
+      cmd_fifo_rd <= mcb_cmd_en_o_xhdl5 AND NOT(mcb_cmd_full_i) AND NOT(cmd_fifo_empty);
+
+
+      xhdl14 <= (cmd2flow_bl & cmd2flow_addr);
+      xfer_cmd_bl <= xhdl15(32);
+           xfer_addr  <= xhdl15(31 downto 0);
+      cmd_fifo : afifo
+         GENERIC MAP (
+            TCQ                   => TCQ,
+            DSIZE       => 38,
+            FIFO_DEPTH  => 16,
+            ASIZE       => 4,
+            SYNC        => 1
+         )
+         PORT MAP (
+            wr_clk   => clk_i,
+            rst      => rst_ra(0),
+            wr_en    => cmd_fifo_wr,
+            wr_data  => xhdl14,
+            rd_en    => cmd_fifo_rd,
+            rd_clk   => clk_i,
+            rd_data  => xhdl15,
+            full     => cmd_fifo_full,
+            almost_full => open,
+            empty    => cmd_fifo_empty
+         );
+   END GENERATE;
+   PROCESS (clk_i)
+   BEGIN
+         IF (clk_i'EVENT AND clk_i = '1') THEN
+            end_addr_r <= end_addr_i;
+         END IF;
+   END PROCESS;
+
+
+
+   u_c_gen : cmd_gen
+      GENERIC MAP (
+         TCQ                   => TCQ,
+         FAMILY               => FAMILY,
+         PORT_MODE            => PORT_MODE,
+         MEM_BURST_LEN        => MEM_BLEN,
+         NUM_DQ_PINS          => NUM_DQ_PINS,
+         DATA_PATTERN         => DATA_PATTERN,
+         CMD_PATTERN          => CMD_PATTERN,
+         ADDR_WIDTH           => ADDR_WIDTH,
+         DWIDTH               => DWIDTH,
+         MEM_COL_WIDTH        => MEM_COL_WIDTH,
+         PRBS_EADDR_MASK_POS  => PRBS_EADDR_MASK_POS,
+         PRBS_SADDR_MASK_POS  => PRBS_SADDR_MASK_POS,
+         PRBS_EADDR           => PRBS_EADDR,
+         PRBS_SADDR           => PRBS_SADDR
+      )
+      PORT MAP (
+         clk_i              => clk_i,
+         rst_i              => rst_ra,
+         rd_buff_avail_i    => rd_buff_avail,
+         reading_rd_data_i  => mcb_rd_en,
+         force_wrcmd_gen_i  => force_wrcmd_gen,
+         run_traffic_i      => run_traffic_reg,
+         start_addr_i       => start_addr_i,
+         end_addr_i         => end_addr_r,
+         cmd_seed_i         => cmd_seed_i,
+         data_seed_i        => data_seed_i,
+         load_seed_i        => load_seed_i,
+         addr_mode_i        => addr_mode_i,
+         data_mode_i        => data_mode_r_a,
+         instr_mode_i       => instr_mode_i,
+         bl_mode_i          => bl_mode_i,
+         mode_load_i        => mode_load_i,
+         fixed_bl_i         => fixed_bl_i,
+         fixed_addr_i       => fixed_addr_i,
+         fixed_instr_i      => fixed_instr_i,
+         bram_addr_i        => bram_addr_i,
+         bram_instr_i       => bram_instr_i,
+         bram_bl_i          => bram_bl_i,
+         bram_valid_i       => bram_valid_i,
+         bram_rdy_o         => bram_rdy_o_xhdl0,
+         rdy_i              => flow2cmd_rdy,
+         instr_o            => cmd2flow_cmd,
+         addr_o             => cmd2flow_addr,
+         bl_o               => cmd2flow_bl,
+--         m_addr_o           => m_addr,
+         cmd_o_vld          => cmd2flow_valid
+      );
+   mcb_cmd_addr_o_xhdl3 <= addr_o(ADDR_WIDTH - 1 DOWNTO 0);
+   cmd_full <= mcb_cmd_full_i;
+
+
+   mcb_control : mcb_flow_control
+      GENERIC MAP (
+         TCQ                   => TCQ,
+         FAMILY  => FAMILY
+      )
+      PORT MAP (
+         clk_i           => clk_i,
+         rst_i           => rst_ra,
+         cmd_rdy_o       => flow2cmd_rdy,
+         cmd_valid_i     => cmd2flow_valid,
+         cmd_i           => cmd2flow_cmd,
+         addr_i          => cmd2flow_addr,
+         bl_i            => cmd2flow_bl,
+         mcb_cmd_full    => cmd_full,
+         cmd_o           => mcb_cmd_instr_o_xhdl6,
+         addr_o          => addr_o,
+         bl_o            => mcb_cmd_bl_o_xhdl4,
+         cmd_en_o        => mcb_cmd_en_o_xhdl5,
+         last_word_wr_i  => last_word_wr,
+         wdp_rdy_i       => wr_rdy,
+         wdp_valid_o     => wr_valid,
+         wdp_validB_o    => wr_validB,
+         wdp_validC_o    => wr_validC,
+         wr_addr_o       => wr_addr,
+         wr_bl_o         => wr_bl,
+         last_word_rd_i  => last_word_rd,
+         rdp_rdy_i       => rd_rdy,
+         rdp_valid_o     => rd_valid,
+         rd_addr_o       => rd_addr,
+         rd_bl_o         => rd_bl
+      );
+
+     mdata_wren <= not mcb_rd_empty; 
+
+      rd_mdata_fifo : afifo
+         GENERIC MAP (
+            TCQ                   => TCQ,
+            DSIZE       => DWIDTH,
+            FIFO_DEPTH  => 32,
+            ASIZE       => 5,
+            SYNC        => 1
+         )
+         PORT MAP (
+            wr_clk   => clk_i,
+            rst      => rst_rb(0),
+            wr_en    => mdata_wren,
+            wr_data  => mcb_rd_data_i,
+            rd_en    => mcb_rd_en,
+            rd_clk   => clk_i,
+            rd_data  => rd_v6_mdata,
+            full     => open,
+            almost_full => open,
+            empty    => rd_mdata_fifo_empty
+         );
+
+
+
+   cmd_rd_en <= NOT(mcb_cmd_full_i) AND mcb_cmd_en_o_xhdl5;
+
+  PROCESS (clk_i)
+  BEGIN
+  IF (clk_i'EVENT AND clk_i = '1') THEN  
+   IF (rst_rb(0) = '1') THEN
+       rd_mdata_afull_set <= '0';
+    ELSIF (rd_mdata_fifo_afull = '1') THEN
+       rd_mdata_afull_set <= '1';
+    END IF;
+  END IF;
+  END PROCESS;
+
+
+  PROCESS(rd_mdata_fifo_empty,rd_mdata_afull_set,mcb_rd_empty)
+  BEGIN
+  
+  IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
+       rdpath_data_valid_i <= not(rd_mdata_fifo_empty);
+  ELSE
+       rdpath_data_valid_i <= not(mcb_rd_empty);
+  
+  END IF;
+  END PROCESS;
+  
+  PROCESS(rd_v6_mdata,mcb_rd_data_i)
+  BEGIN
+  
+  IF (FAMILY = "VIRTEX6" AND MEM_BLEN = 4) THEN
+       rdpath_rd_data_i <= rd_v6_mdata;
+  ELSE
+       rdpath_rd_data_i <= mcb_rd_data_i;
+  
+  END IF;
+  END PROCESS;
+
+   RD_PATH : IF (PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE") GENERATE
+
+      xhdl17 <= NOT(mcb_rd_empty);
+      read_data_path_inst : read_data_path
+         GENERIC MAP (
+            TCQ                   => TCQ,
+            family                => FAMILY,
+            MEM_BURST_LEN         => MEM_BLEN,
+            cmp_data_pipe_stages  => CMP_DATA_PIPE_STAGES,
+            addr_width            => ADDR_WIDTH,
+            sel_victim_line       => SEL_VICTIM_LINE,
+            data_pattern          => DATA_PATTERN,
+            dwidth                => DWIDTH,
+            num_dq_pins           => NUM_DQ_PINS,
+            DQ_ERROR_WIDTH        => DQ_ERROR_WIDTH,
+            mem_col_width         => MEM_COL_WIDTH
+         )
+         PORT MAP (
+            clk_i              => clk_i,
+            rst_i              => rst_rb,
+            manual_clear_error => manual_clear_error,
+            cmd_rdy_o          => rd_rdy,
+            cmd_valid_i        => rd_valid,
+            prbs_fseed_i       => data_seed_i,
+            cmd_sent           => mcb_cmd_instr_o_xhdl6,
+            bl_sent            => mcb_cmd_bl_o_xhdl4,
+            cmd_en_i           => cmd_rd_en,
+            data_mode_i        => data_mode_r_b,
+            last_word_rd_o     => last_word_rd,
+--            m_addr_i           => m_addr,
+            fixed_data_i       => fixed_data_i,
+
+            addr_i             => rd_addr,
+            bl_i               => rd_bl,
+            data_rdy_o         => mcb_rd_en,
+            data_valid_i       => rdpath_data_valid_i,
+            data_i             => rdpath_rd_data_i,
+            data_error_o       => cmp_error_int,
+            cmp_data_o         => cmp_data_int,
+            rd_mdata_o         => mem_rd_data_i,
+            cmp_data_valid     => cmp_data_valid,
+            cmp_addr_o         => cmp_addr,
+            cmp_bl_o           => cmp_bl,
+            force_wrcmd_gen_o  => force_wrcmd_gen,
+            rd_buff_avail_o    => rd_buff_avail,
+            dq_error_bytelane_cmp      => dq_error_bytelane_cmp,
+            cumlative_dq_lane_error_r  => cumlative_dq_lane_error
+         );
+   END GENERATE;
+  
+   write_only_path_inst: IF ( NOT(PORT_MODE = "RD_MODE" OR PORT_MODE = "BI_MODE")) GENERATE
+
+      cmp_error_int <= '0';
+   END GENERATE;
+
+   xhdl18 : IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") GENERATE
+
+      xhdl19        <= NOT(mcb_wr_full);
+      write_data_path_inst : write_data_path
+         GENERIC MAP (
+            TCQ                   => TCQ,
+            family           => FAMILY,
+            MEM_BURST_LEN    => MEM_BLEN,
+            
+            addr_width       => ADDR_WIDTH,
+            data_pattern     => DATA_PATTERN,
+            dwidth           => DWIDTH,
+            num_dq_pins      => NUM_DQ_PINS,
+            sel_victim_line  => SEL_VICTIM_LINE,
+            mem_col_width    => MEM_COL_WIDTH,
+            eye_test         => EYE_TEST
+         )
+         PORT MAP (
+            clk_i           => clk_i,
+            rst_i           => rst_rb,
+            cmd_rdy_o       => wr_rdy,
+            cmd_valid_i     => wr_valid,
+            cmd_validb_i    => wr_validB,
+            cmd_validc_i    => wr_validC,
+            prbs_fseed_i    => data_seed_i,
+            data_mode_i     => data_mode_r_c,
+            last_word_wr_o  => last_word_wr,
+--            m_addr_i        => m_addr,
+            fixed_data_i       => fixed_data_i,
+
+            addr_i          => wr_addr,
+            bl_i            => wr_bl,
+            data_rdy_i      => xhdl19,
+            data_valid_o    => mcb_wr_en,
+            data_o          => mcb_wr_data_o_xhdl9,
+            data_mask_o     => mcb_wr_mask_o_xhdl10,
+            data_wr_end_o   => mcb_wr_data_end_o_xhdl8
+--            tpt_hdata       =>
+         );
+
+   END GENERATE;
+
+   mcb_wr_en_o <= mcb_wr_en;
+
+
+
+   tg_status_inst : tg_status
+      GENERIC MAP (
+         dwidth  => DWIDTH
+      )
+      PORT MAP (
+         clk_i               => clk_i,
+         rst_i               => rst_ra(2),
+         manual_clear_error  => manual_clear_error,
+         data_error_i        => cmp_error_int,
+         cmp_data_i          => cmp_data_int,
+         rd_data_i           => mem_rd_data_i,
+         cmp_addr_i          => cmp_addr,
+         cmp_bl_i            => cmp_bl,
+         mcb_cmd_full_i      => mcb_cmd_full_i,
+         mcb_wr_full_i       => mcb_wr_full,
+         mcb_rd_empty_i      => mcb_rd_empty,
+         error_status        => error_status_xhdl2,
+         error               => error_xhdl1
+      );
+
+END trans;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/memc3_tb_top.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/memc3_tb_top.vhd
new file mode 100644
index 0000000..6cb946b
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/memc3_tb_top.vhd
@@ -0,0 +1,1070 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : 3.92
+--  \   \         Application        : MIG
+--  /   /         Filename           : memc3_tb_top.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:56 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+--Device           : Spartan-6
+--Design Name      : DDR/DDR2/DDR3/LPDDR
+--Purpose          : This is top level module for test bench. which instantiates 
+--                   init_mem_pattern_ctr and mcb_traffic_gen modules for each user
+--                   port.
+--Reference        :
+--Revision History :
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity memc3_tb_top is
+generic
+  (
+      C_P0_MASK_SIZE                   : integer := 4;
+      C_P0_DATA_PORT_SIZE              : integer := 32;
+      C_P1_MASK_SIZE                   : integer := 4;
+      C_P1_DATA_PORT_SIZE              : integer := 32;
+      C_MEM_BURST_LEN                  : integer := 8;
+      C_SIMULATION                     : string  := "FALSE";
+      C_MEM_NUM_COL_BITS               : integer := 11;
+      C_NUM_DQ_PINS                    : integer := 8;
+      C_SMALL_DEVICE                   : string := "FALSE";
+            C_p0_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000100";
+      C_p0_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p0_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000002ff";
+      C_p0_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffffc00";
+      C_p0_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000100";
+      C_p1_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000300";
+      C_p1_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p1_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000004ff";
+      C_p1_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff800";
+      C_p1_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000300";
+      C_p2_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000500";
+      C_p2_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p2_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000006ff";
+      C_p2_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff800";
+      C_p2_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000500";
+      C_p3_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000700";
+      C_p3_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p3_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000008ff";
+      C_p3_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff000";
+      C_p3_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000700"
+  );
+port
+(
+   clk0            : in std_logic;
+   rst0            : in std_logic;
+   calib_done      : in std_logic;
+      p0_mcb_cmd_en_o                           : out std_logic;
+      p0_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p0_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p0_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p0_mcb_cmd_full_i                         : in std_logic;
+
+      p0_mcb_wr_en_o                            : out std_logic;
+      p0_mcb_wr_mask_o                          : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+      p0_mcb_wr_data_o                          : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_mcb_wr_full_i                          : in std_logic;
+      p0_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p0_mcb_rd_en_o                            : out std_logic;
+      p0_mcb_rd_data_i                          : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_mcb_rd_empty_i                         : in std_logic;
+      p0_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p1_mcb_cmd_en_o                           : out std_logic;
+      p1_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p1_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p1_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p1_mcb_cmd_full_i                         : in std_logic;
+
+      p1_mcb_wr_en_o                            : out std_logic;
+      p1_mcb_wr_mask_o                          : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+      p1_mcb_wr_data_o                          : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_mcb_wr_full_i                          : in std_logic;
+      p1_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p1_mcb_rd_en_o                            : out std_logic;
+      p1_mcb_rd_data_i                          : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_mcb_rd_empty_i                         : in std_logic;
+      p1_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p2_mcb_cmd_en_o                           : out std_logic;
+      p2_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p2_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p2_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p2_mcb_cmd_full_i                         : in std_logic;
+
+      p2_mcb_wr_en_o                            : out std_logic;
+      p2_mcb_wr_mask_o                          : out std_logic_vector(3 downto 0);
+      p2_mcb_wr_data_o                          : out std_logic_vector(31 downto 0);
+      p2_mcb_wr_full_i                          : in std_logic;
+      p2_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p2_mcb_rd_en_o                            : out std_logic;
+      p2_mcb_rd_data_i                          : in std_logic_vector(31 downto 0);
+      p2_mcb_rd_empty_i                         : in std_logic;
+      p2_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p3_mcb_cmd_en_o                           : out std_logic;
+      p3_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p3_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p3_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p3_mcb_cmd_full_i                         : in std_logic;
+
+      p3_mcb_wr_en_o                            : out std_logic;
+      p3_mcb_wr_mask_o                          : out std_logic_vector(3 downto 0);
+      p3_mcb_wr_data_o                          : out std_logic_vector(31 downto 0);
+      p3_mcb_wr_full_i                          : in std_logic;
+      p3_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p3_mcb_rd_en_o                            : out std_logic;
+      p3_mcb_rd_data_i                          : in std_logic_vector(31 downto 0);
+      p3_mcb_rd_empty_i                         : in std_logic;
+      p3_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+
+
+   vio_modify_enable   : in std_logic;
+   vio_data_mode_value : in std_logic_vector(2 downto 0);
+   vio_addr_mode_value : in std_logic_vector(2 downto 0);
+   cmp_error       : out std_logic;
+   cmp_data        : out std_logic_vector(31 downto 0);
+   cmp_data_valid  : out std_logic;
+   error           : out std_logic;
+   error_status    : out std_logic_vector(127 downto 0)
+);
+end memc3_tb_top;
+
+architecture arc of memc3_tb_top is
+
+function ERROR_DQWIDTH (val_i : integer) return integer is
+begin
+  if (val_i = 4) then
+    return 1;
+  else
+    return val_i/8;
+  end if;
+end function ERROR_DQWIDTH;
+
+constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
+
+component init_mem_pattern_ctr IS
+   generic (
+      FAMILY                         : string;
+      BEGIN_ADDRESS                  : std_logic_vector(31 downto 0);
+      END_ADDRESS                    : std_logic_vector(31 downto 0);
+      DWIDTH                         : integer;
+      CMD_SEED_VALUE                 : std_logic_vector(31 downto 0);
+      DATA_SEED_VALUE                : std_logic_vector(31 downto 0);
+      DATA_MODE                      : std_logic_vector(3 downto 0);
+      PORT_MODE                      : string
+   );
+   PORT (
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic;
+      mcb_cmd_bl_i                   : in std_logic_vector(5 downto 0);
+      mcb_cmd_en_i                   : in std_logic;
+      mcb_cmd_instr_i                : in std_logic_vector(2 downto 0);
+      mcb_init_done_i                : in std_logic;
+      mcb_wr_en_i                    : in std_logic;
+      vio_modify_enable              : in std_logic;
+      vio_data_mode_value            : in std_logic_vector(2 downto 0);
+      vio_addr_mode_value            : in std_logic_vector(2 downto 0);
+      vio_bl_mode_value              : in STD_LOGIC_VECTOR(1 downto 0);
+      vio_fixed_bl_value             : in STD_LOGIC_VECTOR(5 downto 0);
+      cmp_error                      : in std_logic;
+      run_traffic_o                  : out std_logic;
+      start_addr_o                   : out std_logic_vector(31 downto 0);
+      end_addr_o                     : out std_logic_vector(31 downto 0);
+      cmd_seed_o                     : out std_logic_vector(31 downto 0);
+      data_seed_o                    : out std_logic_vector(31 downto 0);
+      load_seed_o                    : out std_logic;
+      addr_mode_o                    : out std_logic_vector(2 downto 0);
+      instr_mode_o                   : out std_logic_vector(3 downto 0);
+      bl_mode_o                      : out std_logic_vector(1 downto 0);
+      data_mode_o                    : out std_logic_vector(3 downto 0);
+      mode_load_o                    : out std_logic;
+      fixed_bl_o                     : out std_logic_vector(5 downto 0);
+      fixed_instr_o                  : out std_logic_vector(2 downto 0);
+      fixed_addr_o                   : out std_logic_vector(31 downto 0)
+   );
+end component;
+
+component mcb_traffic_gen is
+   generic (
+
+      FAMILY                         : string;
+      SIMULATION                     : string;
+      MEM_BURST_LEN                  : integer;
+      PORT_MODE                      : string;
+      DATA_PATTERN                   : string;
+      CMD_PATTERN                    : string;
+      ADDR_WIDTH                     : integer;
+      CMP_DATA_PIPE_STAGES           : integer;
+      MEM_COL_WIDTH                  : integer;
+      NUM_DQ_PINS                    : integer;
+      DQ_ERROR_WIDTH                 : integer;
+      DWIDTH                         : integer;
+      PRBS_EADDR_MASK_POS            : std_logic_vector(31 downto 0);
+      PRBS_SADDR_MASK_POS            : std_logic_vector(31 downto 0);
+      PRBS_EADDR                     : std_logic_vector(31 downto 0);
+      PRBS_SADDR                     : std_logic_vector(31 downto 0)
+   );
+   port (
+
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic;
+      run_traffic_i                  : in std_logic;
+      manual_clear_error             : in std_logic;
+      -- *** runtime parameter ***
+      start_addr_i                   : in std_logic_vector(31 downto 0);
+      end_addr_i                     : in std_logic_vector(31 downto 0);
+      cmd_seed_i                     : in std_logic_vector(31 downto 0);
+      data_seed_i                    : in std_logic_vector(31 downto 0);
+      load_seed_i                    : in std_logic;
+
+      addr_mode_i                    : in std_logic_vector(2 downto 0);
+      instr_mode_i                   : in std_logic_vector(3 downto 0);
+      bl_mode_i                      : in std_logic_vector(1 downto 0);
+      data_mode_i                    : in std_logic_vector(3 downto 0);
+      mode_load_i                    : in std_logic;
+
+      -- fixed pattern inputs interface
+      fixed_bl_i                     : in std_logic_vector(5 downto 0);
+      fixed_instr_i                  : in std_logic_vector(2 downto 0);
+      fixed_addr_i                   : in std_logic_vector(31 downto 0);
+      fixed_data_i                   : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
+
+      bram_cmd_i                     : in std_logic_vector(38 downto 0);
+      bram_valid_i                   : in std_logic;
+      bram_rdy_o                     : out std_logic;
+
+      --///////////////////////////////////////////////////////////////////////////
+      --  MCB INTERFACE
+      -- interface to mcb command port
+      mcb_cmd_en_o                   : out std_logic;
+      mcb_cmd_instr_o                : out std_logic_vector(2 downto 0);
+      mcb_cmd_addr_o                 : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      mcb_cmd_bl_o                   : out std_logic_vector(5 downto 0);
+      mcb_cmd_full_i                 : in std_logic;
+      -- interface to mcb wr data port
+      mcb_wr_en_o                    : out std_logic;
+      mcb_wr_data_o                  : out std_logic_vector(DWIDTH - 1 downto 0);
+      mcb_wr_mask_o                  : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
+      mcb_wr_data_end_o              : OUT std_logic;
+
+      mcb_wr_full_i                  : in std_logic;
+      mcb_wr_fifo_counts             : in std_logic_vector(6 downto 0);
+
+      -- interface to mcb rd data port
+      mcb_rd_en_o                    : out std_logic;
+      mcb_rd_data_i                  : in std_logic_vector(DWIDTH - 1 downto 0);
+      mcb_rd_empty_i                 : in std_logic;
+      mcb_rd_fifo_counts             : in std_logic_vector(6 downto 0);
+      --///////////////////////////////////////////////////////////////////////////
+      -- status feedback
+      counts_rst                     : in std_logic;
+      wr_data_counts                 : out std_logic_vector(47 downto 0);
+      rd_data_counts                 : out std_logic_vector(47 downto 0);
+      cmp_data                       : out std_logic_vector(DWIDTH - 1 downto 0);
+      cmp_data_valid                 : out std_logic;
+      cmp_error			     : out std_logic;
+      error                          : out std_logic;
+      error_status                   : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
+      mem_rd_data                    : out std_logic_vector(DWIDTH - 1 downto 0);
+      dq_error_bytelane_cmp          : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
+      cumlative_dq_lane_error        : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)      
+
+   );
+end component;
+
+   -- Function to determine the number of data patterns to be generated
+   function DATA_PATTERN_CALC return string is
+   begin
+      if (C_SMALL_DEVICE = "FALSE") then
+         return "DGEN_ALL";
+      else
+         return "DGEN_ADDR";
+      end if;
+   end function;
+
+   constant FAMILY                        : string := "SPARTAN6";
+   constant DATA_PATTERN                  : string := DATA_PATTERN_CALC;
+   constant CMD_PATTERN                   : string := "CGEN_ALL";
+   constant ADDR_WIDTH                    : integer := 30;
+   constant CMP_DATA_PIPE_STAGES          : integer := 0;
+   constant PRBS_SADDR_MASK_POS           : std_logic_vector(31 downto 0)  := X"00007000";
+   constant PRBS_EADDR_MASK_POS           : std_logic_vector(31 downto 0)  := X"FFFF8000";
+   constant PRBS_SADDR                    : std_logic_vector(31 downto 0)  := X"00005000";
+   constant PRBS_EADDR                    : std_logic_vector(31 downto 0)  := X"00007fff";
+   constant BEGIN_ADDRESS                 : std_logic_vector(31 downto 0)  := X"00000000";
+   constant END_ADDRESS                   : std_logic_vector(31 downto 0)  := X"00000fff";
+   constant DATA_MODE                     : std_logic_vector(3 downto 0) := "0010";
+
+
+       
+    
+
+  
+   constant p0_DWIDTH : integer := 32;
+ 
+   constant p1_DWIDTH : integer := 32;
+ 
+   constant p2_DWIDTH : integer := 32;
+ 
+   constant p3_DWIDTH : integer := 32;
+
+  
+   constant p0_PORT_MODE                  : string := "BI_MODE";           
+  
+   constant p1_PORT_MODE                  : string := "BI_MODE";           
+ 
+   constant p2_PORT_MODE                  : string := "BI_MODE";           
+  
+   constant p3_PORT_MODE                  : string := "BI_MODE";           
+
+
+    
+     
+
+   
+    
+
+  
+  
+
+  
+
+
+	
+--p0 Signal declarations
+signal p0_tg_run_traffic           : std_logic;
+signal p0_tg_start_addr            : std_logic_vector(31 downto 0);
+signal p0_tg_end_addr              : std_logic_vector(31 downto 0);
+signal p0_tg_cmd_seed              : std_logic_vector(31 downto 0);
+signal p0_tg_data_seed             : std_logic_vector(31 downto 0);
+signal p0_tg_load_seed             : std_logic;
+signal p0_tg_addr_mode             : std_logic_vector(2 downto 0);
+signal p0_tg_instr_mode            : std_logic_vector(3 downto 0);
+signal p0_tg_bl_mode               : std_logic_vector(1 downto 0);
+signal p0_tg_data_mode             : std_logic_vector(3 downto 0);
+signal p0_tg_mode_load             : std_logic;
+signal p0_tg_fixed_bl              : std_logic_vector(5 downto 0);
+signal p0_tg_fixed_instr           : std_logic_vector(2 downto 0);
+signal p0_tg_fixed_addr            : std_logic_vector(31 downto 0);
+signal p0_error_status             : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
+signal p0_error                    : std_logic;
+signal p0_cmp_error                : std_logic;
+signal p0_cmp_data                 : std_logic_vector(p0_DWIDTH-1 downto 0);  
+signal p0_cmp_data_valid           : std_logic;  
+
+signal p0_mcb_cmd_en_o_int         : std_logic;
+signal p0_mcb_cmd_instr_o_int      : std_logic_vector(2 downto 0);
+signal p0_mcb_cmd_bl_o_int         : std_logic_vector(5 downto 0);
+signal p0_mcb_cmd_addr_o_int       : std_logic_vector(29 downto 0);
+signal p0_mcb_wr_en_o_int          : std_logic;
+
+	
+--p1 Signal declarations
+signal p1_tg_run_traffic           : std_logic;
+signal p1_tg_start_addr            : std_logic_vector(31 downto 0);
+signal p1_tg_end_addr              : std_logic_vector(31 downto 0);
+signal p1_tg_cmd_seed              : std_logic_vector(31 downto 0);
+signal p1_tg_data_seed             : std_logic_vector(31 downto 0);
+signal p1_tg_load_seed             : std_logic;
+signal p1_tg_addr_mode             : std_logic_vector(2 downto 0);
+signal p1_tg_instr_mode            : std_logic_vector(3 downto 0);
+signal p1_tg_bl_mode               : std_logic_vector(1 downto 0);
+signal p1_tg_data_mode             : std_logic_vector(3 downto 0);
+signal p1_tg_mode_load             : std_logic;
+signal p1_tg_fixed_bl              : std_logic_vector(5 downto 0);
+signal p1_tg_fixed_instr           : std_logic_vector(2 downto 0);
+signal p1_tg_fixed_addr            : std_logic_vector(31 downto 0);
+signal p1_error_status             : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
+signal p1_error                    : std_logic;
+signal p1_cmp_error                : std_logic;
+signal p1_cmp_data                 : std_logic_vector(p1_DWIDTH-1 downto 0);  
+signal p1_cmp_data_valid           : std_logic;  
+
+signal p1_mcb_cmd_en_o_int         : std_logic;
+signal p1_mcb_cmd_instr_o_int      : std_logic_vector(2 downto 0);
+signal p1_mcb_cmd_bl_o_int         : std_logic_vector(5 downto 0);
+signal p1_mcb_cmd_addr_o_int       : std_logic_vector(29 downto 0);
+signal p1_mcb_wr_en_o_int          : std_logic;
+
+	
+--p2 Signal declarations
+signal p2_tg_run_traffic           : std_logic;
+signal p2_tg_start_addr            : std_logic_vector(31 downto 0);
+signal p2_tg_end_addr              : std_logic_vector(31 downto 0);
+signal p2_tg_cmd_seed              : std_logic_vector(31 downto 0);
+signal p2_tg_data_seed             : std_logic_vector(31 downto 0);
+signal p2_tg_load_seed             : std_logic;
+signal p2_tg_addr_mode             : std_logic_vector(2 downto 0);
+signal p2_tg_instr_mode            : std_logic_vector(3 downto 0);
+signal p2_tg_bl_mode               : std_logic_vector(1 downto 0);
+signal p2_tg_data_mode             : std_logic_vector(3 downto 0);
+signal p2_tg_mode_load             : std_logic;
+signal p2_tg_fixed_bl              : std_logic_vector(5 downto 0);
+signal p2_tg_fixed_instr           : std_logic_vector(2 downto 0);
+signal p2_tg_fixed_addr            : std_logic_vector(31 downto 0);
+signal p2_error_status             : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
+signal p2_error                    : std_logic;
+signal p2_cmp_error                : std_logic;
+signal p2_cmp_data                 : std_logic_vector(p2_DWIDTH-1 downto 0);  
+signal p2_cmp_data_valid           : std_logic;  
+
+signal p2_mcb_cmd_en_o_int         : std_logic;
+signal p2_mcb_cmd_instr_o_int      : std_logic_vector(2 downto 0);
+signal p2_mcb_cmd_bl_o_int         : std_logic_vector(5 downto 0);
+signal p2_mcb_cmd_addr_o_int       : std_logic_vector(29 downto 0);
+signal p2_mcb_wr_en_o_int          : std_logic;
+
+	
+--p3 Signal declarations
+signal p3_tg_run_traffic           : std_logic;
+signal p3_tg_start_addr            : std_logic_vector(31 downto 0);
+signal p3_tg_end_addr              : std_logic_vector(31 downto 0);
+signal p3_tg_cmd_seed              : std_logic_vector(31 downto 0);
+signal p3_tg_data_seed             : std_logic_vector(31 downto 0);
+signal p3_tg_load_seed             : std_logic;
+signal p3_tg_addr_mode             : std_logic_vector(2 downto 0);
+signal p3_tg_instr_mode            : std_logic_vector(3 downto 0);
+signal p3_tg_bl_mode               : std_logic_vector(1 downto 0);
+signal p3_tg_data_mode             : std_logic_vector(3 downto 0);
+signal p3_tg_mode_load             : std_logic;
+signal p3_tg_fixed_bl              : std_logic_vector(5 downto 0);
+signal p3_tg_fixed_instr           : std_logic_vector(2 downto 0);
+signal p3_tg_fixed_addr            : std_logic_vector(31 downto 0);
+signal p3_error_status             : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
+signal p3_error                    : std_logic;
+signal p3_cmp_error                : std_logic;
+signal p3_cmp_data                 : std_logic_vector(p3_DWIDTH-1 downto 0);  
+signal p3_cmp_data_valid           : std_logic;  
+
+signal p3_mcb_cmd_en_o_int         : std_logic;
+signal p3_mcb_cmd_instr_o_int      : std_logic_vector(2 downto 0);
+signal p3_mcb_cmd_bl_o_int         : std_logic_vector(5 downto 0);
+signal p3_mcb_cmd_addr_o_int       : std_logic_vector(29 downto 0);
+signal p3_mcb_wr_en_o_int          : std_logic;
+
+
+
+
+
+
+
+
+
+--signal cmp_data : std_logic_vector(31 downto 0);
+begin
+
+   cmp_error       <= p0_cmp_error or p1_cmp_error or p2_cmp_error or p3_cmp_error;
+   error           <= p0_error or p1_error or p2_error or p3_error;
+   error_status    <= p0_error_status;
+   cmp_data        <= p0_cmp_data(31 downto 0);
+   cmp_data_valid  <= p0_cmp_data_valid;
+
+
+p0_mcb_cmd_en_o     <= p0_mcb_cmd_en_o_int;
+p0_mcb_cmd_instr_o  <= p0_mcb_cmd_instr_o_int;
+p0_mcb_cmd_bl_o     <= p0_mcb_cmd_bl_o_int;
+p0_mcb_cmd_addr_o   <= p0_mcb_cmd_addr_o_int;
+p0_mcb_wr_en_o     <= p0_mcb_wr_en_o_int;
+
+ init_mem_pattern_ctr_p0 :init_mem_pattern_ctr 
+ generic map
+ 	 (
+    DWIDTH            =>    p0_DWIDTH,
+    FAMILY            =>    FAMILY,
+    BEGIN_ADDRESS     =>    C_p0_BEGIN_ADDRESS,
+    END_ADDRESS       =>    C_p0_END_ADDRESS,
+    CMD_SEED_VALUE    =>    X"56456783",
+    DATA_SEED_VALUE   =>    X"12345678",
+    DATA_MODE         =>    C_p0_DATA_MODE,
+    PORT_MODE         =>    p0_PORT_MODE
+	
+   )
+ port map
+    (
+    clk_i              =>   clk0,
+    rst_i              =>   rst0,
+                       
+    mcb_cmd_en_i       =>   p0_mcb_cmd_en_o_int,
+    mcb_cmd_instr_i    =>   p0_mcb_cmd_instr_o_int,
+    mcb_cmd_bl_i       =>   p0_mcb_cmd_bl_o_int,
+    mcb_wr_en_i        =>   p0_mcb_wr_en_o_int,
+
+    vio_modify_enable  =>	vio_modify_enable,
+    vio_data_mode_value =>  vio_data_mode_value,
+    vio_addr_mode_value =>  vio_addr_mode_value,
+    vio_bl_mode_value	=>  "10",--vio_bl_mode_value,
+    vio_fixed_bl_value	=>  "000000",--vio_fixed_bl_value,  
+                       
+    mcb_init_done_i    =>   calib_done,
+    cmp_error          =>   p0_error,
+    run_traffic_o      =>   p0_tg_run_traffic, 
+    start_addr_o       =>   p0_tg_start_addr,
+    end_addr_o         =>   p0_tg_end_addr   ,
+    cmd_seed_o         =>   p0_tg_cmd_seed   , 
+    data_seed_o        =>   p0_tg_data_seed  ,
+    load_seed_o        =>   p0_tg_load_seed  ,
+    addr_mode_o        =>   p0_tg_addr_mode  ,
+    instr_mode_o       =>   p0_tg_instr_mode ,
+    bl_mode_o          =>   p0_tg_bl_mode    ,
+    data_mode_o        =>   p0_tg_data_mode  ,
+    mode_load_o        =>   p0_tg_mode_load  ,
+    fixed_bl_o         =>   p0_tg_fixed_bl   ,
+    fixed_instr_o      =>   p0_tg_fixed_instr,
+    fixed_addr_o       =>   p0_tg_fixed_addr 
+  );
+
+ m_traffic_gen_p0 :  mcb_traffic_gen 
+ generic map(  
+    MEM_BURST_LEN        => C_MEM_BURST_LEN, 
+    MEM_COL_WIDTH        => C_MEM_NUM_COL_BITS,
+    NUM_DQ_PINS          => C_NUM_DQ_PINS,
+    DQ_ERROR_WIDTH       => DQ_ERROR_WIDTH,
+                         
+    PORT_MODE            => p0_PORT_MODE,    
+    DWIDTH               => p0_DWIDTH,
+    CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,                     
+    FAMILY               => FAMILY,
+    SIMULATION           => "FALSE",
+    DATA_PATTERN         => DATA_PATTERN,  
+    CMD_PATTERN          => "CGEN_ALL",
+    ADDR_WIDTH           => 30,
+    PRBS_SADDR_MASK_POS  => C_p0_PRBS_SADDR_MASK_POS,
+    PRBS_EADDR_MASK_POS  => C_p0_PRBS_EADDR_MASK_POS,
+    PRBS_SADDR           => C_p0_BEGIN_ADDRESS,
+    PRBS_EADDR           => C_p0_END_ADDRESS
+  )  
+ port map
+  (  
+    clk_i                =>  clk0,
+    rst_i                =>  rst0,
+    run_traffic_i        =>  p0_tg_run_traffic,
+    manual_clear_error   =>  rst0,
+   -- runtime parameter  
+    start_addr_i         =>  p0_tg_start_addr ,
+    end_addr_i           =>  p0_tg_end_addr   ,
+    cmd_seed_i           =>  p0_tg_cmd_seed   ,
+    data_seed_i          =>  p0_tg_data_seed  ,
+    load_seed_i          =>  p0_tg_load_seed,
+    addr_mode_i          =>  p0_tg_addr_mode,
+                         
+    instr_mode_i         =>  p0_tg_instr_mode ,
+    bl_mode_i            =>  p0_tg_bl_mode    ,
+    data_mode_i          =>  p0_tg_data_mode  ,
+    mode_load_i          =>  p0_tg_mode_load  ,
+    
+    -- fixed pattern inputs interface  
+    fixed_bl_i           =>  p0_tg_fixed_bl,      
+    fixed_instr_i        =>  p0_tg_fixed_instr,   
+    fixed_addr_i         =>  p0_tg_fixed_addr,
+    fixed_data_i         =>  (others => '0'),
+    -- BRAM interface. 
+    bram_cmd_i           =>  (others => '0'),
+    bram_valid_i         =>  '0',
+    bram_rdy_o           =>  open, 
+    
+    --  MCB INTERFACE  
+    mcb_cmd_en_o	 =>  p0_mcb_cmd_en_o_int, 
+    mcb_cmd_instr_o	 =>  p0_mcb_cmd_instr_o_int, 
+    mcb_cmd_bl_o	 =>  p0_mcb_cmd_bl_o_int, 
+    mcb_cmd_addr_o	 =>  p0_mcb_cmd_addr_o_int, 
+    mcb_cmd_full_i	 =>  p0_mcb_cmd_full_i, 
+    
+    mcb_wr_en_o		 =>  p0_mcb_wr_en_o_int, 
+    mcb_wr_mask_o	 =>  p0_mcb_wr_mask_o, 
+    mcb_wr_data_o	 =>  p0_mcb_wr_data_o, 
+    mcb_wr_data_end_o    =>  open, 
+    mcb_wr_full_i	 =>  p0_mcb_wr_full_i, 
+    mcb_wr_fifo_counts	 =>  p0_mcb_wr_fifo_counts, 
+    
+    mcb_rd_en_o		 =>  p0_mcb_rd_en_o, 
+    mcb_rd_data_i	 =>  p0_mcb_rd_data_i, 
+    mcb_rd_empty_i	 =>  p0_mcb_rd_empty_i, 
+    mcb_rd_fifo_counts	 =>  p0_mcb_rd_fifo_counts, 
+
+    -- status feedback   
+    counts_rst           =>  rst0,
+    wr_data_counts       =>  open,
+    rd_data_counts       =>  open,
+    cmp_data             =>  p0_cmp_data,      
+    cmp_data_valid       =>  p0_cmp_data_valid,      
+    cmp_error            =>  p0_cmp_error,        
+    error                =>  p0_error,        
+    error_status         =>  p0_error_status,
+    mem_rd_data          =>  open,
+    dq_error_bytelane_cmp   => open,
+    cumlative_dq_lane_error => open
+  );         
+
+
+
+p1_mcb_cmd_en_o     <= p1_mcb_cmd_en_o_int;
+p1_mcb_cmd_instr_o  <= p1_mcb_cmd_instr_o_int;
+p1_mcb_cmd_bl_o     <= p1_mcb_cmd_bl_o_int;
+p1_mcb_cmd_addr_o   <= p1_mcb_cmd_addr_o_int;
+p1_mcb_wr_en_o     <= p1_mcb_wr_en_o_int;
+
+ init_mem_pattern_ctr_p1 :init_mem_pattern_ctr 
+ generic map
+ 	 (
+    DWIDTH            =>    p1_DWIDTH,
+    FAMILY            =>    FAMILY,
+    BEGIN_ADDRESS     =>    C_p1_BEGIN_ADDRESS,
+    END_ADDRESS       =>    C_p1_END_ADDRESS,
+    CMD_SEED_VALUE    =>    X"56456783",
+    DATA_SEED_VALUE   =>    X"12345678",
+    DATA_MODE         =>    C_p1_DATA_MODE,
+    PORT_MODE         =>    p1_PORT_MODE
+	
+   )
+ port map
+    (
+    clk_i              =>   clk0,
+    rst_i              =>   rst0,
+                       
+    mcb_cmd_en_i       =>   p1_mcb_cmd_en_o_int,
+    mcb_cmd_instr_i    =>   p1_mcb_cmd_instr_o_int,
+    mcb_cmd_bl_i       =>   p1_mcb_cmd_bl_o_int,
+    mcb_wr_en_i        =>   p1_mcb_wr_en_o_int,
+
+    vio_modify_enable  =>	vio_modify_enable,
+    vio_data_mode_value =>  vio_data_mode_value,
+    vio_addr_mode_value =>  vio_addr_mode_value,
+    vio_bl_mode_value	=>  "10",--vio_bl_mode_value,
+    vio_fixed_bl_value	=>  "000000",--vio_fixed_bl_value,  
+                       
+    mcb_init_done_i    =>   calib_done,
+    cmp_error          =>   p1_error,
+    run_traffic_o      =>   p1_tg_run_traffic, 
+    start_addr_o       =>   p1_tg_start_addr,
+    end_addr_o         =>   p1_tg_end_addr   ,
+    cmd_seed_o         =>   p1_tg_cmd_seed   , 
+    data_seed_o        =>   p1_tg_data_seed  ,
+    load_seed_o        =>   p1_tg_load_seed  ,
+    addr_mode_o        =>   p1_tg_addr_mode  ,
+    instr_mode_o       =>   p1_tg_instr_mode ,
+    bl_mode_o          =>   p1_tg_bl_mode    ,
+    data_mode_o        =>   p1_tg_data_mode  ,
+    mode_load_o        =>   p1_tg_mode_load  ,
+    fixed_bl_o         =>   p1_tg_fixed_bl   ,
+    fixed_instr_o      =>   p1_tg_fixed_instr,
+    fixed_addr_o       =>   p1_tg_fixed_addr 
+  );
+
+ m_traffic_gen_p1 :  mcb_traffic_gen 
+ generic map(  
+    MEM_BURST_LEN        => C_MEM_BURST_LEN, 
+    MEM_COL_WIDTH        => C_MEM_NUM_COL_BITS,
+    NUM_DQ_PINS          => C_NUM_DQ_PINS,
+    DQ_ERROR_WIDTH       => DQ_ERROR_WIDTH,
+                         
+    PORT_MODE            => p1_PORT_MODE,    
+    DWIDTH               => p1_DWIDTH,
+    CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,                     
+    FAMILY               => FAMILY,
+    SIMULATION           => "FALSE",
+    DATA_PATTERN         => DATA_PATTERN,  
+    CMD_PATTERN          => "CGEN_ALL",
+    ADDR_WIDTH           => 30,
+    PRBS_SADDR_MASK_POS  => C_p1_PRBS_SADDR_MASK_POS,
+    PRBS_EADDR_MASK_POS  => C_p1_PRBS_EADDR_MASK_POS,
+    PRBS_SADDR           => C_p1_BEGIN_ADDRESS,
+    PRBS_EADDR           => C_p1_END_ADDRESS
+  )  
+ port map
+  (  
+    clk_i                =>  clk0,
+    rst_i                =>  rst0,
+    run_traffic_i        =>  p1_tg_run_traffic,
+    manual_clear_error   =>  rst0,
+   -- runtime parameter  
+    start_addr_i         =>  p1_tg_start_addr ,
+    end_addr_i           =>  p1_tg_end_addr   ,
+    cmd_seed_i           =>  p1_tg_cmd_seed   ,
+    data_seed_i          =>  p1_tg_data_seed  ,
+    load_seed_i          =>  p1_tg_load_seed,
+    addr_mode_i          =>  p1_tg_addr_mode,
+                         
+    instr_mode_i         =>  p1_tg_instr_mode ,
+    bl_mode_i            =>  p1_tg_bl_mode    ,
+    data_mode_i          =>  p1_tg_data_mode  ,
+    mode_load_i          =>  p1_tg_mode_load  ,
+    
+    -- fixed pattern inputs interface  
+    fixed_bl_i           =>  p1_tg_fixed_bl,      
+    fixed_instr_i        =>  p1_tg_fixed_instr,   
+    fixed_addr_i         =>  p1_tg_fixed_addr,
+    fixed_data_i         =>  (others => '0'),
+    -- BRAM interface. 
+    bram_cmd_i           =>  (others => '0'),
+    bram_valid_i         =>  '0',
+    bram_rdy_o           =>  open, 
+    
+    --  MCB INTERFACE  
+    mcb_cmd_en_o	 =>  p1_mcb_cmd_en_o_int, 
+    mcb_cmd_instr_o	 =>  p1_mcb_cmd_instr_o_int, 
+    mcb_cmd_bl_o	 =>  p1_mcb_cmd_bl_o_int, 
+    mcb_cmd_addr_o	 =>  p1_mcb_cmd_addr_o_int, 
+    mcb_cmd_full_i	 =>  p1_mcb_cmd_full_i, 
+    
+    mcb_wr_en_o		 =>  p1_mcb_wr_en_o_int, 
+    mcb_wr_mask_o	 =>  p1_mcb_wr_mask_o, 
+    mcb_wr_data_o	 =>  p1_mcb_wr_data_o, 
+    mcb_wr_data_end_o    =>  open, 
+    mcb_wr_full_i	 =>  p1_mcb_wr_full_i, 
+    mcb_wr_fifo_counts	 =>  p1_mcb_wr_fifo_counts, 
+    
+    mcb_rd_en_o		 =>  p1_mcb_rd_en_o, 
+    mcb_rd_data_i	 =>  p1_mcb_rd_data_i, 
+    mcb_rd_empty_i	 =>  p1_mcb_rd_empty_i, 
+    mcb_rd_fifo_counts	 =>  p1_mcb_rd_fifo_counts, 
+
+    -- status feedback   
+    counts_rst           =>  rst0,
+    wr_data_counts       =>  open,
+    rd_data_counts       =>  open,
+    cmp_data             =>  p1_cmp_data,      
+    cmp_data_valid       =>  p1_cmp_data_valid,      
+    cmp_error            =>  p1_cmp_error,        
+    error                =>  p1_error,        
+    error_status         =>  p1_error_status,
+    mem_rd_data          =>  open,
+    dq_error_bytelane_cmp   => open,
+    cumlative_dq_lane_error => open
+  );         
+
+
+
+p2_mcb_cmd_en_o     <= p2_mcb_cmd_en_o_int;
+p2_mcb_cmd_instr_o  <= p2_mcb_cmd_instr_o_int;
+p2_mcb_cmd_bl_o     <= p2_mcb_cmd_bl_o_int;
+p2_mcb_cmd_addr_o   <= p2_mcb_cmd_addr_o_int;
+p2_mcb_wr_en_o     <= p2_mcb_wr_en_o_int;
+
+ init_mem_pattern_ctr_p2 :init_mem_pattern_ctr 
+ generic map
+ 	 (
+    DWIDTH            =>    p2_DWIDTH,
+    FAMILY            =>    FAMILY,
+    BEGIN_ADDRESS     =>    C_p2_BEGIN_ADDRESS,
+    END_ADDRESS       =>    C_p2_END_ADDRESS,
+    CMD_SEED_VALUE    =>    X"56456783",
+    DATA_SEED_VALUE   =>    X"12345678",
+    DATA_MODE         =>    C_p2_DATA_MODE,
+    PORT_MODE         =>    p2_PORT_MODE
+	
+   )
+ port map
+    (
+    clk_i              =>   clk0,
+    rst_i              =>   rst0,
+                       
+    mcb_cmd_en_i       =>   p2_mcb_cmd_en_o_int,
+    mcb_cmd_instr_i    =>   p2_mcb_cmd_instr_o_int,
+    mcb_cmd_bl_i       =>   p2_mcb_cmd_bl_o_int,
+    mcb_wr_en_i        =>   p2_mcb_wr_en_o_int,
+
+    vio_modify_enable  =>	vio_modify_enable,
+    vio_data_mode_value =>  vio_data_mode_value,
+    vio_addr_mode_value =>  vio_addr_mode_value,
+    vio_bl_mode_value	=>  "10",--vio_bl_mode_value,
+    vio_fixed_bl_value	=>  "000000",--vio_fixed_bl_value,  
+                       
+    mcb_init_done_i    =>   calib_done,
+    cmp_error          =>   p2_error,
+    run_traffic_o      =>   p2_tg_run_traffic, 
+    start_addr_o       =>   p2_tg_start_addr,
+    end_addr_o         =>   p2_tg_end_addr   ,
+    cmd_seed_o         =>   p2_tg_cmd_seed   , 
+    data_seed_o        =>   p2_tg_data_seed  ,
+    load_seed_o        =>   p2_tg_load_seed  ,
+    addr_mode_o        =>   p2_tg_addr_mode  ,
+    instr_mode_o       =>   p2_tg_instr_mode ,
+    bl_mode_o          =>   p2_tg_bl_mode    ,
+    data_mode_o        =>   p2_tg_data_mode  ,
+    mode_load_o        =>   p2_tg_mode_load  ,
+    fixed_bl_o         =>   p2_tg_fixed_bl   ,
+    fixed_instr_o      =>   p2_tg_fixed_instr,
+    fixed_addr_o       =>   p2_tg_fixed_addr 
+  );
+
+ m_traffic_gen_p2 :  mcb_traffic_gen 
+ generic map(  
+    MEM_BURST_LEN        => C_MEM_BURST_LEN, 
+    MEM_COL_WIDTH        => C_MEM_NUM_COL_BITS,
+    NUM_DQ_PINS          => C_NUM_DQ_PINS,
+    DQ_ERROR_WIDTH       => DQ_ERROR_WIDTH,
+                         
+    PORT_MODE            => p2_PORT_MODE,    
+    DWIDTH               => p2_DWIDTH,
+    CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,                     
+    FAMILY               => FAMILY,
+    SIMULATION           => "FALSE",
+    DATA_PATTERN         => DATA_PATTERN,  
+    CMD_PATTERN          => "CGEN_ALL",
+    ADDR_WIDTH           => 30,
+    PRBS_SADDR_MASK_POS  => C_p2_PRBS_SADDR_MASK_POS,
+    PRBS_EADDR_MASK_POS  => C_p2_PRBS_EADDR_MASK_POS,
+    PRBS_SADDR           => C_p2_BEGIN_ADDRESS,
+    PRBS_EADDR           => C_p2_END_ADDRESS
+  )  
+ port map
+  (  
+    clk_i                =>  clk0,
+    rst_i                =>  rst0,
+    run_traffic_i        =>  p2_tg_run_traffic,
+    manual_clear_error   =>  rst0,
+   -- runtime parameter  
+    start_addr_i         =>  p2_tg_start_addr ,
+    end_addr_i           =>  p2_tg_end_addr   ,
+    cmd_seed_i           =>  p2_tg_cmd_seed   ,
+    data_seed_i          =>  p2_tg_data_seed  ,
+    load_seed_i          =>  p2_tg_load_seed,
+    addr_mode_i          =>  p2_tg_addr_mode,
+                         
+    instr_mode_i         =>  p2_tg_instr_mode ,
+    bl_mode_i            =>  p2_tg_bl_mode    ,
+    data_mode_i          =>  p2_tg_data_mode  ,
+    mode_load_i          =>  p2_tg_mode_load  ,
+    
+    -- fixed pattern inputs interface  
+    fixed_bl_i           =>  p2_tg_fixed_bl,      
+    fixed_instr_i        =>  p2_tg_fixed_instr,   
+    fixed_addr_i         =>  p2_tg_fixed_addr,
+    fixed_data_i         =>  (others => '0'),
+    -- BRAM interface. 
+    bram_cmd_i           =>  (others => '0'),
+    bram_valid_i         =>  '0',
+    bram_rdy_o           =>  open, 
+    
+    --  MCB INTERFACE  
+    mcb_cmd_en_o	 =>  p2_mcb_cmd_en_o_int, 
+    mcb_cmd_instr_o	 =>  p2_mcb_cmd_instr_o_int, 
+    mcb_cmd_bl_o	 =>  p2_mcb_cmd_bl_o_int, 
+    mcb_cmd_addr_o	 =>  p2_mcb_cmd_addr_o_int, 
+    mcb_cmd_full_i	 =>  p2_mcb_cmd_full_i, 
+    
+    mcb_wr_en_o		 =>  p2_mcb_wr_en_o_int, 
+    mcb_wr_mask_o	 =>  p2_mcb_wr_mask_o, 
+    mcb_wr_data_o	 =>  p2_mcb_wr_data_o, 
+    mcb_wr_data_end_o    =>  open, 
+    mcb_wr_full_i	 =>  p2_mcb_wr_full_i, 
+    mcb_wr_fifo_counts	 =>  p2_mcb_wr_fifo_counts, 
+    
+    mcb_rd_en_o		 =>  p2_mcb_rd_en_o, 
+    mcb_rd_data_i	 =>  p2_mcb_rd_data_i, 
+    mcb_rd_empty_i	 =>  p2_mcb_rd_empty_i, 
+    mcb_rd_fifo_counts	 =>  p2_mcb_rd_fifo_counts, 
+
+    -- status feedback   
+    counts_rst           =>  rst0,
+    wr_data_counts       =>  open,
+    rd_data_counts       =>  open,
+    cmp_data             =>  p2_cmp_data,      
+    cmp_data_valid       =>  p2_cmp_data_valid,      
+    cmp_error            =>  p2_cmp_error,        
+    error                =>  p2_error,        
+    error_status         =>  p2_error_status,
+    mem_rd_data          =>  open,
+    dq_error_bytelane_cmp   => open,
+    cumlative_dq_lane_error => open
+  );         
+
+
+
+p3_mcb_cmd_en_o     <= p3_mcb_cmd_en_o_int;
+p3_mcb_cmd_instr_o  <= p3_mcb_cmd_instr_o_int;
+p3_mcb_cmd_bl_o     <= p3_mcb_cmd_bl_o_int;
+p3_mcb_cmd_addr_o   <= p3_mcb_cmd_addr_o_int;
+p3_mcb_wr_en_o     <= p3_mcb_wr_en_o_int;
+
+ init_mem_pattern_ctr_p3 :init_mem_pattern_ctr 
+ generic map
+ 	 (
+    DWIDTH            =>    p3_DWIDTH,
+    FAMILY            =>    FAMILY,
+    BEGIN_ADDRESS     =>    C_p3_BEGIN_ADDRESS,
+    END_ADDRESS       =>    C_p3_END_ADDRESS,
+    CMD_SEED_VALUE    =>    X"56456783",
+    DATA_SEED_VALUE   =>    X"12345678",
+    DATA_MODE         =>    C_p3_DATA_MODE,
+    PORT_MODE         =>    p3_PORT_MODE
+	
+   )
+ port map
+    (
+    clk_i              =>   clk0,
+    rst_i              =>   rst0,
+                       
+    mcb_cmd_en_i       =>   p3_mcb_cmd_en_o_int,
+    mcb_cmd_instr_i    =>   p3_mcb_cmd_instr_o_int,
+    mcb_cmd_bl_i       =>   p3_mcb_cmd_bl_o_int,
+    mcb_wr_en_i        =>   p3_mcb_wr_en_o_int,
+
+    vio_modify_enable  =>	vio_modify_enable,
+    vio_data_mode_value =>  vio_data_mode_value,
+    vio_addr_mode_value =>  vio_addr_mode_value,
+    vio_bl_mode_value	=>  "10",--vio_bl_mode_value,
+    vio_fixed_bl_value	=>  "000000",--vio_fixed_bl_value,  
+                       
+    mcb_init_done_i    =>   calib_done,
+    cmp_error          =>   p3_error,
+    run_traffic_o      =>   p3_tg_run_traffic, 
+    start_addr_o       =>   p3_tg_start_addr,
+    end_addr_o         =>   p3_tg_end_addr   ,
+    cmd_seed_o         =>   p3_tg_cmd_seed   , 
+    data_seed_o        =>   p3_tg_data_seed  ,
+    load_seed_o        =>   p3_tg_load_seed  ,
+    addr_mode_o        =>   p3_tg_addr_mode  ,
+    instr_mode_o       =>   p3_tg_instr_mode ,
+    bl_mode_o          =>   p3_tg_bl_mode    ,
+    data_mode_o        =>   p3_tg_data_mode  ,
+    mode_load_o        =>   p3_tg_mode_load  ,
+    fixed_bl_o         =>   p3_tg_fixed_bl   ,
+    fixed_instr_o      =>   p3_tg_fixed_instr,
+    fixed_addr_o       =>   p3_tg_fixed_addr 
+  );
+
+ m_traffic_gen_p3 :  mcb_traffic_gen 
+ generic map(  
+    MEM_BURST_LEN        => C_MEM_BURST_LEN, 
+    MEM_COL_WIDTH        => C_MEM_NUM_COL_BITS,
+    NUM_DQ_PINS          => C_NUM_DQ_PINS,
+    DQ_ERROR_WIDTH       => DQ_ERROR_WIDTH,
+                         
+    PORT_MODE            => p3_PORT_MODE,    
+    DWIDTH               => p3_DWIDTH,
+    CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,                     
+    FAMILY               => FAMILY,
+    SIMULATION           => "FALSE",
+    DATA_PATTERN         => DATA_PATTERN,  
+    CMD_PATTERN          => "CGEN_ALL",
+    ADDR_WIDTH           => 30,
+    PRBS_SADDR_MASK_POS  => C_p3_PRBS_SADDR_MASK_POS,
+    PRBS_EADDR_MASK_POS  => C_p3_PRBS_EADDR_MASK_POS,
+    PRBS_SADDR           => C_p3_BEGIN_ADDRESS,
+    PRBS_EADDR           => C_p3_END_ADDRESS
+  )  
+ port map
+  (  
+    clk_i                =>  clk0,
+    rst_i                =>  rst0,
+    run_traffic_i        =>  p3_tg_run_traffic,
+    manual_clear_error   =>  rst0,
+   -- runtime parameter  
+    start_addr_i         =>  p3_tg_start_addr ,
+    end_addr_i           =>  p3_tg_end_addr   ,
+    cmd_seed_i           =>  p3_tg_cmd_seed   ,
+    data_seed_i          =>  p3_tg_data_seed  ,
+    load_seed_i          =>  p3_tg_load_seed,
+    addr_mode_i          =>  p3_tg_addr_mode,
+                         
+    instr_mode_i         =>  p3_tg_instr_mode ,
+    bl_mode_i            =>  p3_tg_bl_mode    ,
+    data_mode_i          =>  p3_tg_data_mode  ,
+    mode_load_i          =>  p3_tg_mode_load  ,
+    
+    -- fixed pattern inputs interface  
+    fixed_bl_i           =>  p3_tg_fixed_bl,      
+    fixed_instr_i        =>  p3_tg_fixed_instr,   
+    fixed_addr_i         =>  p3_tg_fixed_addr,
+    fixed_data_i         =>  (others => '0'),
+    -- BRAM interface. 
+    bram_cmd_i           =>  (others => '0'),
+    bram_valid_i         =>  '0',
+    bram_rdy_o           =>  open, 
+    
+    --  MCB INTERFACE  
+    mcb_cmd_en_o	 =>  p3_mcb_cmd_en_o_int, 
+    mcb_cmd_instr_o	 =>  p3_mcb_cmd_instr_o_int, 
+    mcb_cmd_bl_o	 =>  p3_mcb_cmd_bl_o_int, 
+    mcb_cmd_addr_o	 =>  p3_mcb_cmd_addr_o_int, 
+    mcb_cmd_full_i	 =>  p3_mcb_cmd_full_i, 
+    
+    mcb_wr_en_o		 =>  p3_mcb_wr_en_o_int, 
+    mcb_wr_mask_o	 =>  p3_mcb_wr_mask_o, 
+    mcb_wr_data_o	 =>  p3_mcb_wr_data_o, 
+    mcb_wr_data_end_o    =>  open, 
+    mcb_wr_full_i	 =>  p3_mcb_wr_full_i, 
+    mcb_wr_fifo_counts	 =>  p3_mcb_wr_fifo_counts, 
+    
+    mcb_rd_en_o		 =>  p3_mcb_rd_en_o, 
+    mcb_rd_data_i	 =>  p3_mcb_rd_data_i, 
+    mcb_rd_empty_i	 =>  p3_mcb_rd_empty_i, 
+    mcb_rd_fifo_counts	 =>  p3_mcb_rd_fifo_counts, 
+
+    -- status feedback   
+    counts_rst           =>  rst0,
+    wr_data_counts       =>  open,
+    rd_data_counts       =>  open,
+    cmp_data             =>  p3_cmp_data,      
+    cmp_data_valid       =>  p3_cmp_data_valid,      
+    cmp_error            =>  p3_cmp_error,        
+    error                =>  p3_error,        
+    error_status         =>  p3_error_status,
+    mem_rd_data          =>  open,
+    dq_error_bytelane_cmp   => open,
+    cumlative_dq_lane_error => open
+  );         
+
+
+end architecture;
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/rd_data_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/rd_data_gen.vhd
new file mode 100755
index 0000000..5559ade
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/rd_data_gen.vhd
@@ -0,0 +1,434 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: rd_data_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This module has all the timing control for generating "compare data" 
+--         to compare the read data from memory.
+-- Reference:
+-- Revision History: 2010/01/09  parameter MEM_BURST_LEN is missing in v6_data_gen instance module.
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+entity rd_data_gen is
+   generic (
+      
+      FAMILY                         : string := "SPARTAN6";            -- "SPARTAN6", "VIRTEX6"
+      MEM_BURST_LEN                  : integer := 8;
+      ADDR_WIDTH                     : integer := 32;
+      BL_WIDTH                       : integer := 6;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_PRBS";           --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      SEL_VICTIM_LINE                : integer := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+      
+      COLUMN_WIDTH                   : integer := 10
+   );
+   port (
+      
+      clk_i                          : in std_logic;            --
+      rst_i                          : in std_logic_vector(4 downto 0);
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      data_mode_i                    : in std_logic_vector(3 downto 0);         -- "00" = bram; 
+      rd_mdata_en                    :  in std_logic;
+      
+      cmd_rdy_o                      : out std_logic;           -- ready to receive command. It should assert when data_port is ready at the                                        // beginning and will be deasserted once see the cmd_valid_i is asserted. 
+      -- And then it should reasserted when 
+      -- it is generating the last_word.
+      cmd_valid_i                    : in std_logic;            -- when both cmd_valid_i and cmd_rdy_o is high, the command  is valid.
+      last_word_o                    : out std_logic;
+      
+--      m_addr_i                       : in std_logic_vector(ADDR_WIDTH - 1 downto 0);            -- generated address used to determine data pattern.
+      fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);
+      
+      addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);            -- generated address used to determine data pattern.
+      bl_i                           : in std_logic_vector(BL_WIDTH - 1 downto 0);              -- generated burst length for control the burst data
+      user_bl_cnt_is_1_o             : out std_logic;
+      data_rdy_i                     : in std_logic;            -- connect from mcb_wr_full when used as wr_data_gen in sp6
+      -- connect from mcb_rd_empty when used as rd_data_gen in sp6
+      -- connect from rd_data_valid in v6
+      -- When both data_rdy and data_valid is asserted, the ouput data is valid.
+      data_valid_o                   : out std_logic;           -- connect to wr_en or rd_en and is asserted whenever the 
+      -- pattern is available.
+      data_o                         : out std_logic_vector(DWIDTH - 1 downto 0)                -- generated data pattern   
+   );
+end entity rd_data_gen;
+
+ARCHITECTURE trans OF rd_data_gen IS
+
+COMPONENT sp6_data_gen IS
+   GENERIC (
+      
+      ADDR_WIDTH      : INTEGER := 32;
+      BL_WIDTH        : INTEGER := 6;
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_PRBS";
+      NUM_DQ_PINS     : INTEGER := 8;
+      COLUMN_WIDTH    : INTEGER := 10
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      cmd_startA      : IN STD_LOGIC;
+      cmd_startB      : IN STD_LOGIC;
+      cmd_startC      : IN STD_LOGIC;
+      cmd_startD      : IN STD_LOGIC;
+      cmd_startE      : IN STD_LOGIC;
+      fixed_data_i    : in std_logic_vector(DWIDTH - 1 downto 0);  
+      addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      user_burst_cnt  : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
+      
+      fifo_rdy_i      : IN STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
+   );
+END COMPONENT;      
+
+COMPONENT v6_data_gen IS
+   GENERIC (
+      
+      ADDR_WIDTH      : INTEGER := 32;
+      MEM_BURST_LEN   : integer := 8;
+      
+      BL_WIDTH        : INTEGER := 6;
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_ALL";
+      NUM_DQ_PINS     : INTEGER := 8;
+      SEL_VICTIM_LINE : INTEGER := 3;
+      COLUMN_WIDTH    : INTEGER := 10
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      cmd_startA      : IN STD_LOGIC;
+      cmd_startB      : IN STD_LOGIC;
+      cmd_startC      : IN STD_LOGIC;
+      cmd_startD      : IN STD_LOGIC;
+      cmd_startE      : IN STD_LOGIC;
+      fixed_data_i    : in std_logic_vector(DWIDTH - 1 downto 0);  
+      
+      m_addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      user_burst_cnt  : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
+      
+      fifo_rdy_i      : IN STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
+   );
+END COMPONENT;      
+
+
+   SIGNAL prbs_data          : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL cmd_start          : STD_LOGIC;
+   SIGNAL adata              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL hdata              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL ndata              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL w1data             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+   SIGNAL v6_w1data          : STD_LOGIC_VECTOR(NUM_DQ_PINS * 4 - 1 DOWNTO 0);
+   
+   signal w0data                        : std_logic_vector(31 downto 0);
+   signal data                          : std_logic_vector(DWIDTH - 1 downto 0);
+   signal cmd_rdy                       : std_logic;
+   signal data_valid                    : std_logic;
+   signal user_burst_cnt                : std_logic_vector(6 downto 0);
+   signal data_rdy_r1                   : std_logic;
+   signal data_rdy_r2                   : std_logic;
+   signal next_count_is_one             : std_logic;
+   signal cmd_valid_r1                  : std_logic;
+   signal w3data                        : std_logic_vector(31 downto 0);
+   
+   signal data_port_fifo_rdy            : std_logic;
+   
+   --assign cmd_start = cmd_valid_i & cmd_rdy ;
+   
+   signal user_bl_cnt_is_1              : std_logic;
+   
+   signal cmd_start_b                   : std_logic;
+   
+   --  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
+   --  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
+   
+   -- counter to count user burst length
+   
+   signal u_bcount_2                    : std_logic;
+   
+   -- Declare intermediate signals for referenced outputs
+   signal last_word_o_xhdl1             : std_logic;
+   signal data_o_xhdl0                  : std_logic_vector(DWIDTH - 1 downto 0);
+begin
+   -- Drive referenced outputs
+   last_word_o <= last_word_o_xhdl1;
+   data_port_fifo_rdy <= data_rdy_i;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         data_rdy_r1 <= data_rdy_i;
+         data_rdy_r2 <= data_rdy_r1;
+         cmd_valid_r1 <= cmd_valid_i;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (user_burst_cnt = "0000010" and data_rdy_i = '1') then
+            next_count_is_one <= '1';
+         else
+            next_count_is_one <= '0';
+         end if;
+      end if;
+   end process;
+   
+   user_bl_cnt_is_1_o <= user_bl_cnt_is_1;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "SPARTAN6") or
+         (user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "VIRTEX6") ) then
+            user_bl_cnt_is_1 <= '1';
+         else
+            user_bl_cnt_is_1 <= '0';
+         end if;
+      end if;
+   end process;
+   
+   process (cmd_valid_i, cmd_valid_r1, cmd_rdy, user_bl_cnt_is_1, rd_mdata_en)
+   begin
+      if (FAMILY = "SPARTAN6") then
+         cmd_start <= cmd_valid_i and cmd_rdy;
+         cmd_start_b <= cmd_valid_i and cmd_rdy;
+      else
+        if (MEM_BURST_LEN = 4) then 
+          cmd_start <= rd_mdata_en;
+        else
+          cmd_start <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
+          cmd_start_b <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
+        end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            user_burst_cnt <= "0000000";
+         elsif (cmd_start = '1') then
+            if (bl_i = "000000") then
+               user_burst_cnt <= "1000000" ;
+            else
+               user_burst_cnt <= ('0' & bl_i) ;
+            end if;
+         elsif (data_port_fifo_rdy = '1') then
+            if (user_burst_cnt /= "0000000") then
+               user_burst_cnt <= user_burst_cnt - "0000001";
+            else
+               user_burst_cnt <= "0000000";
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((user_burst_cnt = "0000010" and data_rdy_i = '1') or (cmd_start = '1' and bl_i = "000001")) then
+            u_bcount_2 <= '1';
+         elsif (last_word_o_xhdl1 = '1') then
+            u_bcount_2 <= '0';
+         end if;
+      end if;
+   end process;
+   
+   
+   last_word_o_xhdl1 <= u_bcount_2 and data_rdy_i;
+   
+   -- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
+   -- is assert and reassert during the last data
+   
+   --data_valid_o logic
+   
+   cmd_rdy_o <= cmd_rdy;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdy <= '1';
+         elsif (cmd_start = '1') then
+            cmd_rdy <= '0';
+         elsif (data_port_fifo_rdy = '1' and user_burst_cnt = "0000001") then
+            
+            cmd_rdy <= '1';
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            data_valid <= '0';
+         elsif (user_burst_cnt = "0000001" and data_port_fifo_rdy = '1') then
+            data_valid <= '0';
+         elsif ((user_burst_cnt >= "0000001") or cmd_start = '1') then
+            data_valid <= '1';
+         end if;
+      end if;
+   end process;
+   
+   
+   process (data_valid, data_port_fifo_rdy)
+   begin
+      if (FAMILY = "SPARTAN6") then
+         data_valid_o <= data_valid;
+      else
+         
+         data_valid_o <= data_port_fifo_rdy;
+      end if;
+   end process;
+   
+   xhdl2 : if (FAMILY = "SPARTAN6") generate
+      
+      
+      
+      sp6_data_gen_inst : sp6_data_gen
+         generic map (
+            ADDR_WIDTH    => 32,
+            BL_WIDTH      => BL_WIDTH,
+            DWIDTH        => DWIDTH,
+            DATA_PATTERN  => DATA_PATTERN,
+            NUM_DQ_PINS   => NUM_DQ_PINS,
+            COLUMN_WIDTH  => COLUMN_WIDTH
+         )
+         port map (
+            clk_i           => clk_i,
+            rst_i           => rst_i(1),
+            data_rdy_i      => data_rdy_i,
+            prbs_fseed_i    => prbs_fseed_i,
+            
+            data_mode_i     => data_mode_i,
+            cmd_startA      => cmd_start,
+            cmd_startB      => cmd_start,
+            cmd_startC      => cmd_start,
+            cmd_startD      => cmd_start,
+            cmd_startE      => cmd_start,
+            fixed_data_i    => fixed_data_i,
+            
+            addr_i          => addr_i,
+            user_burst_cnt  => user_burst_cnt,
+            fifo_rdy_i      => data_port_fifo_rdy,
+            data_o          => data_o
+         );
+      
+   end generate;
+   xhdl3 : if (FAMILY = "VIRTEX6") generate
+      
+      
+      
+      v6_data_gen_inst : v6_data_gen
+         generic map (
+            ADDR_WIDTH       => 32,
+            BL_WIDTH         => BL_WIDTH,
+            MEM_BURST_LEN    => MEM_BURST_LEN,
+            
+            DWIDTH           => DWIDTH,
+            DATA_PATTERN     => DATA_PATTERN,
+            NUM_DQ_PINS      => NUM_DQ_PINS,
+            SEL_VICTIM_LINE  => SEL_VICTIM_LINE,
+            COLUMN_WIDTH     => COLUMN_WIDTH
+         )
+         port map (
+            clk_i           => clk_i,
+            rst_i           => rst_i(1),
+            data_rdy_i      => data_rdy_i,
+            prbs_fseed_i    => prbs_fseed_i,
+            
+            data_mode_i     => data_mode_i,
+            cmd_startA      => cmd_start,
+            cmd_startB      => cmd_start,
+            cmd_startC      => cmd_start,
+            cmd_startD      => cmd_start,
+            cmd_startE      => cmd_start,
+            fixed_data_i    => fixed_data_i,
+            
+            m_addr_i        => addr_i,          --(m_addr_i        ),          
+            addr_i          => addr_i,
+            user_burst_cnt  => user_burst_cnt,
+            fifo_rdy_i      => data_port_fifo_rdy,
+            data_o          => data_o
+         );
+      
+   end generate;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/read_data_path.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/read_data_path.vhd
new file mode 100755
index 0000000..0e21887
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/read_data_path.vhd
@@ -0,0 +1,638 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: read_data_path.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This is top level of read path and also consist of comparison logic
+--         for read data. 
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+entity read_data_path is
+   generic (
+      TCQ                            : time := 100 ps;      
+      FAMILY                         : string := "VIRTEX6";
+      MEM_BURST_LEN                  : integer := 8;
+      ADDR_WIDTH                     : integer := 32;
+      CMP_DATA_PIPE_STAGES           : integer := 3;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_ALL";           --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      DQ_ERROR_WIDTH                 : integer := 1;
+      SEL_VICTIM_LINE                : integer := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+      
+      MEM_COL_WIDTH                  : integer := 10
+   );
+   port (
+      
+      clk_i                          : in std_logic;
+      manual_clear_error             : in std_logic;
+      rst_i                          : in std_logic_vector(9 downto 0);
+      cmd_rdy_o                      : out std_logic;
+      cmd_valid_i                    : in std_logic;
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      
+      data_mode_i                    : in std_logic_vector(3 downto 0);
+      cmd_sent                       : in std_logic_vector(2 downto 0);
+      bl_sent                        : in std_logic_vector(5 downto 0);
+      cmd_en_i                       : in std_logic;
+--      m_addr_i                       : in std_logic_vector(31 downto 0);
+      fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);
+      
+      addr_i                         : in std_logic_vector(31 downto 0);
+      bl_i                           : in std_logic_vector(5 downto 0);
+      --   input [5:0]            port_data_counts_i,// connect to data port fifo counts
+      
+      data_rdy_o                     : out std_logic;
+      data_valid_i                   : in std_logic;
+      data_i                         : in std_logic_vector(DWIDTH - 1 downto 0);
+      last_word_rd_o                 : out std_logic;
+      data_error_o                   : out std_logic;
+      cmp_data_o                     : out std_logic_vector(DWIDTH - 1 downto 0);
+      rd_mdata_o                     : out std_logic_vector(DWIDTH - 1 downto 0);
+      cmp_data_valid                 : out std_logic;
+      cmp_addr_o                     : out std_logic_vector(31 downto 0);
+      cmp_bl_o                       : out std_logic_vector(5 downto 0);
+      force_wrcmd_gen_o              : out std_logic;
+      
+      rd_buff_avail_o                : out std_logic_vector(6 downto 0);
+      dq_error_bytelane_cmp          : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
+       cumlative_dq_lane_error_r     : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
+
+      
+      
+   );
+end entity read_data_path;
+
+architecture trans of read_data_path is
+
+function REDUCTION_OR( A: in std_logic_vector) return std_logic is
+  variable tmp : std_logic := '0';
+begin
+  for i in A'range loop
+       tmp := tmp or A(i);
+  end loop;
+  return tmp;
+end function REDUCTION_OR;
+
+   COMPONENT read_posted_fifo IS
+      GENERIC (
+         TCQ                   : time   := 100 ps;
+         MEM_BURST_LEN         : integer := 4;
+         FAMILY                : STRING := "SPARTAN6";
+         ADDR_WIDTH            : INTEGER := 32;
+         BL_WIDTH              : INTEGER := 6
+      );
+      PORT (
+         clk_i                 : IN STD_LOGIC;
+         rst_i                 : IN STD_LOGIC;
+         cmd_rdy_o             : OUT STD_LOGIC;
+         cmd_valid_i           : IN STD_LOGIC;
+         data_valid_i          : IN STD_LOGIC;
+         addr_i                : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+         bl_i                  : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
+         user_bl_cnt_is_1      : IN STD_LOGIC;
+         cmd_sent              : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+         bl_sent               : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+         cmd_en_i              : IN STD_LOGIC;
+         gen_rdy_i             : IN STD_LOGIC;
+         gen_valid_o           : OUT STD_LOGIC;
+         gen_addr_o            : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+         gen_bl_o              : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
+         rd_buff_avail_o       : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
+         rd_mdata_fifo_empty   : IN STD_LOGIC;
+         rd_mdata_en           : OUT STD_LOGIC   
+      );
+   END COMPONENT;
+
+   component rd_data_gen is
+      generic (
+         FAMILY                         : string := "SPARTAN6";
+         MEM_BURST_LEN                  : integer := 8;
+         ADDR_WIDTH                     : integer := 32;
+         BL_WIDTH                       : integer := 6;
+         DWIDTH                         : integer := 32;
+         DATA_PATTERN                   : string := "DGEN_PRBS";
+         NUM_DQ_PINS                    : integer := 8;
+         SEL_VICTIM_LINE                : integer := 3;
+         COLUMN_WIDTH                   : integer := 10
+      );
+      port (
+         clk_i                          : in std_logic;
+         rst_i                          : in std_logic_vector(4 downto 0);
+         prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+         rd_mdata_en                    : in std_logic;
+         data_mode_i                    : in std_logic_vector(3 downto 0);
+         cmd_rdy_o                      : out std_logic;
+         cmd_valid_i                    : in std_logic;
+         last_word_o                    : out std_logic;
+--         m_addr_i                       : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+         fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);  
+         
+         addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+         bl_i                           : in std_logic_vector(BL_WIDTH - 1 downto 0);
+         user_bl_cnt_is_1_o             : out std_logic;
+         data_rdy_i                     : in std_logic;
+         data_valid_o                   : out std_logic;
+         data_o                         : out std_logic_vector(DWIDTH - 1 downto 0)
+      );
+   end component;
+
+   component afifo IS
+   GENERIC (
+      DSIZE       : INTEGER := 32;
+      FIFO_DEPTH  : INTEGER := 16;
+      ASIZE       : INTEGER := 5;
+      SYNC        : INTEGER := 1
+   );
+   PORT (
+      wr_clk      : IN STD_LOGIC;
+      rst         : IN STD_LOGIC;
+      wr_en       : IN STD_LOGIC;
+      wr_data     : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      rd_en       : IN STD_LOGIC;
+      rd_clk      : IN STD_LOGIC;
+      rd_data     : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
+      almost_full : OUT STD_LOGIC;
+      full        : OUT STD_LOGIC;
+      empty       : OUT STD_LOGIC
+   );
+END component;
+   
+   signal gen_rdy                  : std_logic;
+   signal gen_valid                : std_logic;
+   signal gen_addr                 : std_logic_vector(31 downto 0);
+   signal gen_bl                   : std_logic_vector(5 downto 0);
+   
+   signal cmp_rdy                  : std_logic;
+   signal cmp_valid                : std_logic;
+   signal cmp_addr                 : std_logic_vector(31 downto 0);
+   signal cmp_bl                   : std_logic_vector(5 downto 0);
+   
+   signal data_error               : std_logic;
+   signal cmp_data                 : std_logic_vector(DWIDTH - 1 downto 0);
+   signal last_word_rd             : std_logic;
+   signal bl_counter               : std_logic_vector(5 downto 0);
+   signal cmd_rdy                  : std_logic;
+   signal user_bl_cnt_is_1         : std_logic;
+   signal data_rdy                 : std_logic;
+   signal delayed_data             : std_logic_vector(DWIDTH downto 0);
+--   signal cmp_data_piped           : std_logic_vector(DWIDTH downto 0);
+   signal cmp_data_r               : std_logic_vector(DWIDTH-1 downto 0);    
+   signal rd_mdata_en              : std_logic;   
+   signal rd_data_r                : std_logic_vector(DWIDTH - 1 downto 0);
+   signal force_wrcmd_gen          : std_logic;
+   signal wait_bl_end              : std_logic;
+   signal wait_bl_end_r1           : std_logic;
+
+   signal v6_data_cmp_valid        : std_logic;
+   signal rd_v6_mdata              : std_logic_vector(DWIDTH-1 downto 0);    
+   signal cmpdata_r                : std_logic_vector(DWIDTH-1 downto 0);    
+   signal rd_mdata                 : std_logic_vector(DWIDTH-1 downto 0);    
+   signal l_data_error             : std_logic;
+   signal u_data_error             : std_logic;
+   signal cmp_data_en              : std_logic;
+   
+   signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
+
+   signal error_byte               : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
+   signal error_byte_r1             : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
+   signal dq_lane_error            : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal dq_lane_error_r1         : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal dq_lane_error_r2         : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal cum_dq_lane_error_mask   : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal cumlative_dq_lane_error_reg  : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0); 
+   signal cumlative_dq_lane_error_c     : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
+  signal  rd_mdata_fifo_empty      : std_logic;
+   signal data_valid_r             : std_logic;
+   -- Declare intermediate signals for referenced outputs
+--   SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
+--   SIGNAL tmp_sig : STD_LOGIC;
+   signal last_word_rd_o_xhdl0     : std_logic;
+   signal rd_buff_avail_o_xhdl1    : std_logic_vector(6 downto 0);
+begin
+   -- Drive referenced outputs
+   last_word_rd_o <= last_word_rd_o_xhdl0;
+   rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         wait_bl_end_r1 <= wait_bl_end;
+         rd_data_r <= data_i;
+      end if;
+   end process;
+   
+   force_wrcmd_gen_o <= force_wrcmd_gen;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i(0) = '1') then
+            force_wrcmd_gen <= '0';
+         elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
+            force_wrcmd_gen <= '0';
+         elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
+            force_wrcmd_gen <= '1';
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i(0) = '1') then
+            force_wrcmd_timeout_cnts <= "00000000";
+         elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
+            force_wrcmd_timeout_cnts <= "00000000";
+         elsif (force_wrcmd_gen = '1') then
+            force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i(0) = '1') then
+            wait_bl_end <= '0';
+         elsif (force_wrcmd_timeout_cnts = "11111111") then
+            wait_bl_end <= '0';
+         elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
+            wait_bl_end <= '1';
+         elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
+            wait_bl_end <= '0';
+         end if;
+      end if;
+   end process;
+   
+   cmd_rdy_o <= cmd_rdy;
+   
+   
+   read_postedfifo : read_posted_fifo
+      GENERIC MAP (
+         TCQ         => TCQ,
+         FAMILY      => FAMILY,
+         MEM_BURST_LEN => MEM_BURST_LEN,
+         ADDR_WIDTH  => 32,
+         BL_WIDTH    => 6
+      )
+      port map (
+         clk_i             => clk_i,
+         rst_i             => rst_i(0),
+         cmd_rdy_o         => cmd_rdy,
+         cmd_valid_i       => cmd_valid_i,
+         data_valid_i      => data_rdy,
+         addr_i            => addr_i,
+         bl_i              => bl_i,
+         cmd_sent          => cmd_sent,
+         bl_sent           => bl_sent,
+         cmd_en_i          => cmd_en_i,
+         user_bl_cnt_is_1  => user_bl_cnt_is_1,
+         gen_rdy_i         => gen_rdy,
+         gen_valid_o       => gen_valid,
+         gen_addr_o        => gen_addr,
+         gen_bl_o          => gen_bl,
+         rd_buff_avail_o   => rd_buff_avail_o_xhdl1,
+         rd_mdata_fifo_empty => rd_mdata_fifo_empty,
+         rd_mdata_en       => rd_mdata_en
+      );
+   
+   
+   rd_datagen : rd_data_gen
+      generic map (
+         FAMILY           => FAMILY,
+         MEM_BURST_LEN    => MEM_BURST_LEN,
+         NUM_DQ_PINS      => NUM_DQ_PINS,
+         SEL_VICTIM_LINE  => SEL_VICTIM_LINE,
+         DATA_PATTERN     => DATA_PATTERN,
+         DWIDTH           => DWIDTH,
+         COLUMN_WIDTH     => MEM_COL_WIDTH
+      )
+      port map (
+         clk_i               => clk_i,
+         rst_i               => rst_i(4 downto 0),
+         prbs_fseed_i        => prbs_fseed_i,
+         data_mode_i         => data_mode_i,
+         cmd_rdy_o           => gen_rdy,
+         cmd_valid_i         => gen_valid,
+         last_word_o         => last_word_rd_o_xhdl0,
+--         m_addr_i            => m_addr_i,
+         fixed_data_i        => fixed_data_i,
+         addr_i              => gen_addr,
+         bl_i                => gen_bl,
+         user_bl_cnt_is_1_o  => user_bl_cnt_is_1,
+         data_rdy_i          => data_valid_i,
+         data_valid_o        => cmp_valid,
+         data_o              => cmp_data,
+         rd_mdata_en         => rd_mdata_en
+      );
+
+      rd_mdata_fifo : afifo
+         GENERIC MAP (
+            DSIZE       => DWIDTH,
+            FIFO_DEPTH  => 32,
+            ASIZE       => 5,
+            SYNC        => 1
+         )
+         PORT MAP (
+            wr_clk   => clk_i,
+            rst      => rst_i(0),
+            wr_en    => data_valid_i,
+            wr_data  => data_i,
+            rd_en    => rd_mdata_en,
+            rd_clk   => clk_i,
+            rd_data  => rd_v6_mdata,
+            full     => open,
+            empty    => rd_mdata_fifo_empty,
+            almost_full => open
+         );
+  
+--  tmp_sig <= cmp_valid AND data_valid_i; 
+--   xhdl2 <= ( tmp_sig & cmp_data);
+ 
+  process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+--         delayed_data <= (tmp_sig & cmp_data);
+         cmp_data_r <= cmp_data;
+      end if;
+   end process;
+   
+   rd_mdata_o <= rd_mdata;
+
+   rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata 
+               WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
+
+   cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid 
+               WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
+
+
+   cmp_data_o <= cmp_data_r;
+   cmp_addr_o <= gen_addr;
+   cmp_bl_o <= gen_bl;
+
+--   xhdl4 : if (FAMILY = "SPARTAN6") generate
+--      rd_data_o <= rd_data_r;
+--   end generate;
+--   xhdl5 : if (FAMILY /= "SPARTAN6") generate
+--      rd_data_o <= data_i;
+--   end generate;
+
+   data_rdy_o <= data_rdy;
+   data_rdy <= cmp_valid and data_valid_i;
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         v6_data_cmp_valid <= rd_mdata_en;
+      end if;
+   end process;
+    
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         cmp_data_en <= data_rdy;
+      end if;
+   end process;
+   
+   xhdl6 : if (FAMILY = "SPARTAN6") generate
+      process (clk_i)
+      begin
+         if (clk_i'event and clk_i = '1') then
+            if (cmp_data_en = '1') then
+              IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
+                l_data_error <= '1' ;
+              ELSE 
+                l_data_error <= '0' ;
+              END IF; 
+            else
+               l_data_error <= '0' ;
+            end if;
+            if (cmp_data_en = '1') then
+              IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
+                u_data_error <= '1' ;
+              ELSE
+                u_data_error <= '0' ;
+              END IF;
+            else
+               u_data_error <= '0' ;
+            end if;
+            data_error <= l_data_error or u_data_error;
+            --synthesis translate_off
+            if (data_error = '1') then
+              report ("DATA ERROR");
+            end if;
+            --synthesis translate_on
+
+         end if;
+      end process;
+      
+   end generate;
+   
+   gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
+      
+      
+      gen_cmp : FOR i IN 0 TO  NUM_DQ_PINS / 2 - 1 GENERATE
+         error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
+         
+      end generate;
+      process (clk_i)
+      begin
+         if (clk_i'event and clk_i = '1') then
+             IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
+                 error_byte_r1 <= (others => '0');
+                 data_error    <= '0';
+             ELSE
+             
+              error_byte_r1 <= error_byte;
+           -- FOR i IN 0 TO  DWIDTH - 1 LOOP
+              data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
+           -- END LOOP;
+        
+            
+            END IF;
+         end if;
+      end process;
+      
+
+      process (data_error)
+      begin
+         
+         --synthesis translate_off   
+            IF (data_error = '1') THEN               
+               
+               report "DATA ERROR"; -- severity ERROR;
+            END IF;
+         --synthesis translate_on
+      end process;
+      
+      
+      gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
+         dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
+                              error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR 
+                              error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
+                              
+         cumlative_dq_lane_error_c(i) <=  cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
+      end  generate;
+      
+     
+      process (clk_i)
+      begin
+         IF (clk_i'event and clk_i = '1') then
+             IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
+                
+               dq_lane_error_r1 <=  (others => '0');
+               dq_lane_error_r2 <=  (others => '0');
+               data_valid_r <=  '0';
+               cumlative_dq_lane_error_reg <=  (others => '0');
+               
+             ELSE 
+               data_valid_r <=  data_valid_i;
+             
+               dq_lane_error_r1 <=  dq_lane_error;
+               cumlative_dq_lane_error_reg <=  cumlative_dq_lane_error_c;
+             END IF;
+           
+      
+         END IF;
+      end process;
+      
+      
+      
+   end generate;
+
+   xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
+      
+      gen_cmp_8 : FOR i IN 0 TO  NUM_DQ_PINS / 2 - 1 GENERATE
+         error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
+      end generate;
+
+      process (clk_i)
+      begin
+         if (clk_i'event and clk_i = '1') then
+             IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
+                    error_byte_r1 <= (others => '0');
+                    data_error    <= '0';
+             ELSE
+         
+                    error_byte_r1 <= error_byte;
+                    --FOR i IN 0 TO  DWIDTH - 1 LOOP
+                    --  data_error <= error_byte_r1(i) OR data_error;
+                    --END LOOP;
+                    data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
+                
+                         --synthesis translate_off   
+                    IF (data_error = '1') THEN               
+                       
+                       report "DATA ERROR"; -- severity ERROR;
+                    end if;
+                 --synthesis translate_on
+             END IF;
+         end if;
+      end process;
+      
+      
+      gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
+         dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
+                              error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR 
+                              error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
+                              
+         cumlative_dq_lane_error_c(i) <=  cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
+      end  generate;
+      
+      process (clk_i)
+      begin
+         IF (clk_i'event and clk_i = '1') then
+             IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
+                
+               dq_lane_error_r1 <=  (others => '0');
+               dq_lane_error_r2 <=  (others => '0');
+               data_valid_r <=  '0';
+               cumlative_dq_lane_error_reg <=  (others => '0');
+               
+             ELSE 
+               data_valid_r <=  data_valid_i;
+             
+               dq_lane_error_r1 <=  dq_lane_error;
+               cumlative_dq_lane_error_reg <=  cumlative_dq_lane_error_c;
+             END IF;
+           
+      
+         END IF;
+      end process;
+            
+   end generate;
+   cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
+   
+   dq_error_bytelane_cmp <= dq_lane_error_r1;     
+
+   data_error_o <= data_error;
+   
+end architecture trans;
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/read_posted_fifo.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/read_posted_fifo.vhd
new file mode 100755
index 0000000..694ed0d
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/read_posted_fifo.vhd
@@ -0,0 +1,339 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: read_posted_fifo.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:40 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This module instantiated by read_data_path module and sits between 
+--         mcb_flow_control module and read_data_gen module to buffer up the 
+--         commands that has sent to memory controller.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+entity read_posted_fifo is
+   generic (
+      TCQ                            : time := 100 ps;
+      MEM_BURST_LEN                  : integer := 4;
+      FAMILY                         : string := "SPARTAN6";
+      ADDR_WIDTH                     : integer := 32;
+      BL_WIDTH                       : integer := 6
+   );
+   port (
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic;
+      cmd_rdy_o                      : out std_logic;
+      cmd_valid_i                    : in std_logic;
+      data_valid_i                   : in std_logic;
+      addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      bl_i                           : in std_logic_vector(BL_WIDTH - 1 downto 0);
+      user_bl_cnt_is_1               : in std_logic;
+      cmd_sent                       : in std_logic_vector(2 downto 0);
+      bl_sent                        : in std_logic_vector(5 downto 0);
+      cmd_en_i                       : in std_logic;
+      
+      gen_rdy_i                      : in std_logic;
+      gen_valid_o                    : out std_logic;
+      gen_addr_o                     : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      gen_bl_o                       : out std_logic_vector(BL_WIDTH - 1 downto 0);
+      
+      rd_buff_avail_o                : out std_logic_vector(6 downto 0);
+      rd_mdata_fifo_empty            : in  std_logic;
+      rd_mdata_en                    : out std_logic
+   );
+end entity read_posted_fifo;
+
+architecture trans of read_posted_fifo is
+   component afifo is
+      generic (
+         DSIZE                          : integer := 32;
+         FIFO_DEPTH                     : integer := 16;
+         ASIZE                          : integer := 4;
+         SYNC                           : integer := 1
+      );
+      port (
+         wr_clk                         : in std_logic;
+         rst                            : in std_logic;
+         wr_en                          : in std_logic;
+         wr_data                        : in std_logic_vector(DSIZE - 1 downto 0);
+         rd_en                          : in std_logic;
+         rd_clk                         : in std_logic;
+         rd_data                        : out std_logic_vector(DSIZE - 1 downto 0);
+         full                           : out std_logic;
+         empty                          : out std_logic;
+         almost_full                    : out std_logic
+      );
+   end component;
+   
+   
+   signal full                          : std_logic;
+   signal empty                         : std_logic;
+   signal wr_en                         : std_logic;
+   signal rd_en                         : std_logic;
+   signal data_valid_r                  : std_logic;
+   signal user_bl_cnt_not_1             : std_logic;
+   signal buf_avail_r                   : std_logic_vector(6 downto 0);
+   signal rd_data_received_counts       : std_logic_vector(6 downto 0);
+   signal rd_data_counts_asked          : std_logic_vector(6 downto 0);
+   
+   signal dfifo_has_enough_room         : std_logic;
+   signal wait_cnt                      : std_logic_vector(1 downto 0);
+   signal wait_done                     : std_logic;
+   
+   signal dfifo_has_enough_room_d1      : std_logic;
+   signal empty_r                       : std_logic;
+   signal rd_first_data                 : std_logic;
+   -- current count is 1 and data_is_valie, then next cycle is not 1
+   
+   -- calculate how many buf still available
+   -- assign buf_avail = 64 - (rd_data_counts_asked - rd_data_received_counts);
+   
+--   signal tmp_buf_avil                  : std_logic_vector(5 downto 0);
+   -- X-HDL generated signals
+
+   signal xhdl3 : std_logic;
+   signal xhdl4 : std_logic;
+   signal xhdl5 : std_logic_vector(37 downto 0);
+   signal xhdl6 : std_logic_vector(37 downto 0);
+   
+   -- Declare intermediate signals for referenced outputs
+   signal cmd_rdy_o_xhdl0               : std_logic;
+   signal gen_addr_o_xhdl1              : std_logic_vector(ADDR_WIDTH - 1 downto 0);
+   signal gen_bl_o_xhdl2                : std_logic_vector(BL_WIDTH - 1 downto 0);
+begin
+   -- Drive referenced outputs
+   cmd_rdy_o <= cmd_rdy_o_xhdl0;
+--   gen_addr_o <= gen_addr_o_xhdl1;
+--   gen_bl_o <= gen_bl_o_xhdl2;
+
+   gen_bl_o <= xhdl6(BL_WIDTH+ADDR_WIDTH-1 downto ADDR_WIDTH);
+   gen_addr_o <= xhdl6(ADDR_WIDTH-1 downto 0);
+   
+   rd_mdata_en <= rd_en;
+   rd_buff_avail_o <= buf_avail_r;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         cmd_rdy_o_xhdl0 <= not(full) and dfifo_has_enough_room and wait_done;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i = '1') then
+            wait_cnt <= "00";
+         elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
+            wait_cnt <= "10";
+         elsif (wait_cnt > "00") then
+            wait_cnt <= wait_cnt - "01";
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i = '1') then
+            wait_done <= '1';
+         elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
+            wait_done <= '0';
+         elsif (wait_cnt = "00") then
+            wait_done <= '1';
+         else
+            wait_done <= '0';
+         end if;
+      end if;
+   end process;
+   
+   xhdl3 <= '1' when (buf_avail_r >= "0111110") else
+            '0';
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         dfifo_has_enough_room <= xhdl3;
+         dfifo_has_enough_room_d1 <= dfifo_has_enough_room;
+      end if;
+   end process;
+   
+   wr_en <= cmd_valid_i and not(full) and dfifo_has_enough_room_d1 and wait_done;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         data_valid_r <= data_valid_i;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((data_valid_i and user_bl_cnt_is_1) = '1') then
+            user_bl_cnt_not_1 <= '1';
+         else
+            user_bl_cnt_not_1 <= '0';
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i = '1') then
+            rd_data_counts_asked <= (others => '0');
+         elsif (cmd_en_i = '1' and cmd_sent(0) = '1') then
+           rd_data_counts_asked <= rd_data_counts_asked +  (bl_sent + "0000001" );
+
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (rst_i = '1') then
+            rd_data_received_counts <= "0000000";
+         elsif (data_valid_i = '1') then
+            rd_data_received_counts <= rd_data_received_counts + "0000001";
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         buf_avail_r <= "1000000" - (rd_data_counts_asked - rd_data_received_counts);
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         empty_r <= empty;
+      end if;
+   end process;
+   
+  process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+   
+         if (rst_i = '1') then
+            rd_first_data <= '0';
+         elsif ( empty = '0' AND empty_r = '1') then
+            rd_first_data <= '1';
+         end if;
+      end if;
+   end process;   
+   
+   process (gen_rdy_i, empty,empty_r, data_valid_i, data_valid_r, user_bl_cnt_not_1,rd_mdata_fifo_empty,rd_first_data)
+   begin
+      if (FAMILY = "SPARTAN6") then
+         rd_en <= gen_rdy_i and not(empty);
+      else
+         IF (MEM_BURST_LEN = 4) then
+             rd_en <= (not(empty) and empty_r and not(rd_first_data)) or (not(rd_mdata_fifo_empty) and not(empty)) or
+                     (user_bl_cnt_not_1 and data_valid_i);
+         ELSE
+             rd_en <= (data_valid_i and not(data_valid_r)) or (user_bl_cnt_not_1 and data_valid_i);
+         END IF;
+      end if;
+   end process;
+   
+   
+   
+   
+   gen_valid_o <= not(empty);
+   -- set the SYNC to 1 because rd_clk = wr_clk to reduce latency 
+   
+   
+--   xhdl4 <= to_integer(to_stdlogic(BL_WIDTH) + to_stdlogic(ADDR_WIDTH));
+   
+   xhdl5 <= (bl_i & addr_i);
+--   (gen_bl_o_xhdl2, gen_addr_o_xhdl1) <= xhdl6;
+
+   rd_fifo : afifo
+      GENERIC MAP (
+         DSIZE       => (BL_WIDTH + ADDR_WIDTH),--xhdl4,
+         FIFO_DEPTH  => 16,
+         ASIZE       => 4,
+         SYNC        => 1
+      )
+      port map (
+         wr_clk   => clk_i,
+         rst      => rst_i,
+         wr_en    => wr_en,
+         wr_data  => xhdl5,
+         rd_en    => rd_en,
+         rd_clk   => clk_i,
+         rd_data  => xhdl6,
+         full     => full,
+         empty    => empty,
+         almost_full => open
+      );
+   
+end architecture trans;
+
+
+
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/readme.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/readme.txt
new file mode 100644
index 0000000..139937a
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/readme.txt
@@ -0,0 +1,131 @@
+###############################################################################
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+###############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor             : Xilinx
+## \   \   \/     Version            : 3.92
+##  \   \         Application	     : MIG
+##  /   /         Filename           : readme.txt
+## /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:55 $
+## \   \  /  \    Date Created       : Mon Oct 19 2009
+##  \___\/\___\
+##
+## Device          : Spartan-6
+## Design Name     : DDR/DDR2/DDR3/LPDDR
+## Purpose         : Steps to run simulation using ISIM/Modelsim simualtor in this folder
+## Assumptions:
+##      - Simulation takes place in \sim\<functional/timing> folder of MIG output directory
+## Reference       :
+## Revision History:
+###############################################################################
+
+The sim/functional folder has files to perform functional simulation of the design.
+
+1. Simulation using Modelsim simulator
+
+A) sim.do File :
+   
+   1) The 'sim.do' file has commands to compile and simulate memory interface
+      design and run the simulation for specified period of time. 
+    
+   2) It has the syntax to Map the required libraries.
+      Also, $XILINX environment variable must be set in order to compile glbl.v file
+
+   3) Displays the waveforms that are listed with "add wave" command.
+     
+B) Steps to run the Modelsim simulation:
+
+   1) The user should invoke the Modelsim simulator GUI.
+   2) Change the present working directory path to the sim/functional folder.
+      In Transcript window, at Modelsim prompt, type the following command to 
+      change directory path.
+           cd <sim/functional directory path>
+
+   2) Run the simulation using sim.do file.
+      At Modelsim prompt, type the following command:
+           do sim.do      
+
+   3) To exit simulation, type the following command at Modelsim prompt:
+           quit -f
+
+   4) Verify the transcript file for the memory transactions.
+
+C) For simulation with Elpida parts perform the following steps and then
+   the above mentioned steps in 'B'
+
+   1) Download the Elpida memory model from Elpida webpage.
+
+   2) Update the memorymodel name in the vlog command given in sim.do file.
+
+
+2. Simulation using ISIM simulator
+  
+A) Following files are provided :
+   
+   1) The '.prj' file contains the list of all the files associated with the design.
+      It also contains the hdl, library and the source file name.       
+    
+   2) The '.tcl' file contains the Tcl commands for simulation and 
+      resume on error. 
+
+   3) The 'isim.bat' has commands which use '.prj' and '.tcl' files. 
+
+     
+B) Steps to run the ISIM simulation:
+
+   The user should execute the file isim.bat, which does the following steps:
+   1) Compiles, elaborates the design and generates the simulation executable using
+      the fuse command in 'isim.bat' file.
+
+   2) Invokes the ISIM GUI.
+
+   3) User can add required signals from objects window to the waveform viewer and run 
+      simulation for specified time using the command "run <time>" in ISIM GUI.
+
+C) Simulations using ISIM simulator is not supported for Elpida parts. 
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sim.do b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sim.do
new file mode 100644
index 0000000..03e55a8
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sim.do
@@ -0,0 +1,141 @@
+###############################################################################
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+###############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor             : Xilinx
+## \   \   \/     Version            : 3.92
+##  \   \         Application	     : MIG
+##  /   /         Filename           : sim.do
+## /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:56 $
+## \   \  /  \    Date Created       : Mon Mar 2 2009
+##  \___\/\___\
+##
+## Device: Spartan-6
+## Design Name : DDR/DDR2/DDR3/LPDDR
+## Purpose:
+##    Sample sim .do file to compile and simulate memory interface
+##    design and run the simulation for specified period of time. Display the
+##    waveforms that are listed with "add wave" command.
+##    Assumptions:
+##      - Simulation takes place in \sim folder of MIG output directory
+## Reference:
+## Revision History:
+###############################################################################
+
+vlib work
+
+#Map the required libraries here.#
+#vmap unisim <unisim lib path>
+#vmap secureip <secureip lib path> 
+
+#Compile all rtl modules#
+vcom ../rtl/*.vhd
+
+
+
+
+
+#Compile files in sim folder (excluding model parameter file)#
+#$XILINX variable must be set
+vlog  $env(XILINX)/verilog/src/glbl.v
+vcom  ../sim/*.vhd
+
+#Pass the parameters for memory model parameter file#
+vlog  +incdir+. +define+x1Gb +define+sg25E +define+x16 ddr2_model_c3.v
+
+#Load the design. Use required libraries.#
+vsim -t ps -novopt +notimingchecks -L unisim -L secureip work.sim_tb_top glbl
+
+onerror {resume}
+
+#Log all the objects in design. These will appear in .wlf file#
+log -r /*
+
+#View sim_tb_top signals in waveform#
+add wave sim:/sim_tb_top/*
+
+#Change radix to Hexadecimal#
+radix hex
+#Supress Numeric Std package and Arith package warnings.#
+#For VHDL designs we get some warnings due to unknown values on some signals at startup#
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
+#We may also get some Arithmetic packeage warnings because of unknown values on#
+#some of the signals that are used in an Arithmetic operation.#
+#In order to suppress these warnings, we use following two commands#
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+#Choose simulation run time by inserting a breakpoint and then run for specified #
+#period. Refer simulation_help file.#
+when {/sim_tb_top/calib_done = 1} {
+echo "Calibration Done"
+  if {[when -label a_100] == ""} {
+    when -label a_100 { $now = 50 us } {
+      nowhen a_100
+      report simulator control
+      report simulator state
+      if {[examine /sim_tb_top/error] == 0} {
+        echo "TEST PASSED"
+        stop
+        }
+      if {[examine /sim_tb_top/error] != 0} {
+        echo "TEST FAILED: DATA ERROR"
+        stop
+        }
+      }
+    }
+  }
+
+#In case calibration fails to complete, choose the run time and then quit#
+when {$now = @500 us and /sim_tb_top/calib_done != 1} {
+echo "TEST FAILED: INITIALIZATION DID NOT COMPLETE"
+stop
+}
+run -all
+stop
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sim_tb_top.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sim_tb_top.vhd
new file mode 100644
index 0000000..98954eb
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sim_tb_top.vhd
@@ -0,0 +1,975 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /   Vendor             : Xilinx
+-- \   \   \/    Version            : 3.92
+--  \   \        Application        : MIG
+--  /   /        Filename           : sim_tb_top.vhd
+-- /___/   /\    Date Last Modified : $Date: 2011/06/02 07:16:56 $
+-- \   \  /  \   Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+-- Device      : Spartan-6
+-- Design Name : DDR/DDR2/DDR3/LPDDR
+-- Purpose     : This is the simulation testbench which is used to verify the
+--               design. The basic clocks and resets to the interface are
+--               generated here. This also connects the memory interface to the
+--               memory model.
+--*****************************************************************************
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity sim_tb_top is
+
+end entity sim_tb_top;
+
+architecture arch of sim_tb_top is
+
+
+
+-- ========================================================================== --
+-- Parameters                                                                 --
+-- ========================================================================== --
+   constant DEBUG_EN              : integer :=0;   
+   
+   constant C3_HW_TESTING      : string := "FALSE";
+ 
+function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) )  return  std_logic_vector is
+   begin
+   if (C3_HW_TESTING = "FALSE") then
+     return val1;
+   else
+     return val2;
+   end if;
+   end function;		
+
+   constant  C3_MEMCLK_PERIOD : integer    := 3000;
+   constant C3_RST_ACT_LOW : integer := 0;
+   constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
+   constant C3_CLK_PERIOD_NS   : real := 3000.0 / 1000.0;
+   constant C3_TCYC_SYS        : real := C3_CLK_PERIOD_NS/2.0;
+   constant C3_TCYC_SYS_DIV2   : time := C3_TCYC_SYS * 1 ns;
+   constant C3_NUM_DQ_PINS        : integer := 16;
+   constant C3_MEM_ADDR_WIDTH     : integer := 13;
+   constant C3_MEM_BANKADDR_WIDTH : integer := 3;   
+   constant C3_MEM_ADDR_ORDER     : string := "BANK_ROW_COLUMN"; 
+      constant C3_P0_MASK_SIZE : integer      := 4;
+   constant C3_P0_DATA_PORT_SIZE : integer := 32;  
+   constant C3_P1_MASK_SIZE   : integer    := 4;
+   constant C3_P1_DATA_PORT_SIZE  : integer := 32;
+   constant C3_MEM_BURST_LEN	  : integer := 4;
+   constant C3_MEM_NUM_COL_BITS   : integer := 10;
+   constant C3_SIMULATION      : string := "TRUE";
+   constant C3_CALIB_SOFT_IP      : string := "TRUE";
+   constant C3_p0_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000100", x"01000000");
+   constant C3_p0_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
+   constant C3_p0_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000002ff", x"02ffffff");
+   constant C3_p0_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffffc00", x"fc000000");
+   constant C3_p0_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000100", x"01000000");
+   constant C3_p1_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000300", x"03000000");
+   constant C3_p1_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
+   constant C3_p1_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000004ff", x"04ffffff");
+   constant C3_p1_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffff800", x"f8000000");
+   constant C3_p1_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000300", x"03000000");
+   constant C3_p2_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000500", x"05000000");
+   constant C3_p2_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
+   constant C3_p2_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000006ff", x"06ffffff");
+   constant C3_p2_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffff800", x"f8000000");
+   constant C3_p2_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000500", x"05000000");
+   constant C3_p3_BEGIN_ADDRESS                   : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000700", x"01000000");
+   constant C3_p3_DATA_MODE                       : std_logic_vector(3 downto 0)  := "0010";
+   constant C3_p3_END_ADDRESS                     : std_logic_vector(31 downto 0)  := c3_sim_hw (x"000008ff", x"02ffffff");
+   constant C3_p3_PRBS_EADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"fffff000", x"fc000000");
+   constant C3_p3_PRBS_SADDR_MASK_POS             : std_logic_vector(31 downto 0)  := c3_sim_hw (x"00000700", x"01000000");
+
+-- ========================================================================== --
+-- Component Declarations
+-- ========================================================================== --
+
+
+component ddr2 is
+generic 
+(
+            C3_P0_MASK_SIZE         : integer;
+    C3_P0_DATA_PORT_SIZE    : integer;
+    C3_P1_MASK_SIZE         : integer;
+    C3_P1_DATA_PORT_SIZE    : integer;
+    
+    C3_MEMCLK_PERIOD        : integer; 
+    C3_RST_ACT_LOW          : integer;
+    C3_INPUT_CLK_TYPE       : string;
+    DEBUG_EN                : integer;
+
+    C3_CALIB_SOFT_IP        : string;
+    C3_SIMULATION           : string;
+    C3_MEM_ADDR_ORDER       : string;
+    C3_NUM_DQ_PINS          : integer; 
+    C3_MEM_ADDR_WIDTH       : integer; 
+    C3_MEM_BANKADDR_WIDTH   : integer
+);  
+  port
+  (
+        mcb3_dram_dq                            : inout  std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
+   mcb3_dram_a                             : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+   mcb3_dram_ba                            : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
+   mcb3_dram_ras_n                         : out std_logic;
+   mcb3_dram_cas_n                         : out std_logic;
+   mcb3_dram_we_n                          : out std_logic;
+   mcb3_dram_odt                           : out std_logic;
+   mcb3_dram_cke                           : out std_logic;
+   mcb3_dram_dm                            : out std_logic;
+      mcb3_rzq    				   : inout  std_logic;
+
+      mcb3_zio    				   : inout  std_logic;
+
+        c3_sys_clk                            : in  std_logic;
+   c3_sys_rst_i                            : in  std_logic;
+	
+   c3_calib_done                           : out std_logic;
+        c3_clk0                                 : out std_logic;
+   c3_rst0                                 : out std_logic;
+ 
+   mcb3_dram_dqs                           : inout  std_logic;
+   mcb3_dram_dqs_n : inout std_logic;
+   
+		mcb3_dram_udqs                           : inout  std_logic;
+		mcb3_dram_udqs_n : inout std_logic;
+		   
+   mcb3_dram_udm                            : out std_logic;
+		
+   mcb3_dram_ck                            : out std_logic;
+   mcb3_dram_ck_n                          : out std_logic;   c3_p0_cmd_clk                           : in std_logic;
+   c3_p0_cmd_en                            : in std_logic;
+   c3_p0_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p0_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p0_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p0_cmd_empty                         : out std_logic;
+   c3_p0_cmd_full                          : out std_logic;
+   c3_p0_wr_clk                            : in std_logic;
+   c3_p0_wr_en                             : in std_logic;
+   c3_p0_wr_mask                           : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
+   c3_p0_wr_data                           : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+   c3_p0_wr_full                           : out std_logic;
+   c3_p0_wr_empty                          : out std_logic;
+   c3_p0_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p0_wr_underrun                       : out std_logic;
+   c3_p0_wr_error                          : out std_logic;
+   c3_p0_rd_clk                            : in std_logic;
+   c3_p0_rd_en                             : in std_logic;
+   c3_p0_rd_data                           : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+   c3_p0_rd_full                           : out std_logic;
+   c3_p0_rd_empty                          : out std_logic;
+   c3_p0_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p0_rd_overflow                       : out std_logic;
+   c3_p0_rd_error                          : out std_logic;
+   c3_p1_cmd_clk                           : in std_logic;
+   c3_p1_cmd_en                            : in std_logic;
+   c3_p1_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p1_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p1_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p1_cmd_empty                         : out std_logic;
+   c3_p1_cmd_full                          : out std_logic;
+   c3_p1_wr_clk                            : in std_logic;
+   c3_p1_wr_en                             : in std_logic;
+   c3_p1_wr_mask                           : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
+   c3_p1_wr_data                           : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+   c3_p1_wr_full                           : out std_logic;
+   c3_p1_wr_empty                          : out std_logic;
+   c3_p1_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p1_wr_underrun                       : out std_logic;
+   c3_p1_wr_error                          : out std_logic;
+   c3_p1_rd_clk                            : in std_logic;
+   c3_p1_rd_en                             : in std_logic;
+   c3_p1_rd_data                           : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+   c3_p1_rd_full                           : out std_logic;
+   c3_p1_rd_empty                          : out std_logic;
+   c3_p1_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p1_rd_overflow                       : out std_logic;
+   c3_p1_rd_error                          : out std_logic;
+   c3_p2_cmd_clk                           : in std_logic;
+   c3_p2_cmd_en                            : in std_logic;
+   c3_p2_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p2_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p2_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p2_cmd_empty                         : out std_logic;
+   c3_p2_cmd_full                          : out std_logic;
+   c3_p2_wr_clk                            : in std_logic;
+   c3_p2_wr_en                             : in std_logic;
+   c3_p2_wr_mask                           : in std_logic_vector(3 downto 0);
+   c3_p2_wr_data                           : in std_logic_vector(31 downto 0);
+   c3_p2_wr_full                           : out std_logic;
+   c3_p2_wr_empty                          : out std_logic;
+   c3_p2_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p2_wr_underrun                       : out std_logic;
+   c3_p2_wr_error                          : out std_logic;
+   c3_p2_rd_clk                            : in std_logic;
+   c3_p2_rd_en                             : in std_logic;
+   c3_p2_rd_data                           : out std_logic_vector(31 downto 0);
+   c3_p2_rd_full                           : out std_logic;
+   c3_p2_rd_empty                          : out std_logic;
+   c3_p2_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p2_rd_overflow                       : out std_logic;
+   c3_p2_rd_error                          : out std_logic;
+   c3_p3_cmd_clk                           : in std_logic;
+   c3_p3_cmd_en                            : in std_logic;
+   c3_p3_cmd_instr                         : in std_logic_vector(2 downto 0);
+   c3_p3_cmd_bl                            : in std_logic_vector(5 downto 0);
+   c3_p3_cmd_byte_addr                     : in std_logic_vector(29 downto 0);
+   c3_p3_cmd_empty                         : out std_logic;
+   c3_p3_cmd_full                          : out std_logic;
+   c3_p3_wr_clk                            : in std_logic;
+   c3_p3_wr_en                             : in std_logic;
+   c3_p3_wr_mask                           : in std_logic_vector(3 downto 0);
+   c3_p3_wr_data                           : in std_logic_vector(31 downto 0);
+   c3_p3_wr_full                           : out std_logic;
+   c3_p3_wr_empty                          : out std_logic;
+   c3_p3_wr_count                          : out std_logic_vector(6 downto 0);
+   c3_p3_wr_underrun                       : out std_logic;
+   c3_p3_wr_error                          : out std_logic;
+   c3_p3_rd_clk                            : in std_logic;
+   c3_p3_rd_en                             : in std_logic;
+   c3_p3_rd_data                           : out std_logic_vector(31 downto 0);
+   c3_p3_rd_full                           : out std_logic;
+   c3_p3_rd_empty                          : out std_logic;
+   c3_p3_rd_count                          : out std_logic_vector(6 downto 0);
+   c3_p3_rd_overflow                       : out std_logic;
+   c3_p3_rd_error                          : out std_logic
+  );
+end component;
+
+
+        component ddr2_model_c3 is
+    port (
+      ck      : in    std_logic;
+      ck_n    : in    std_logic;
+      cke     : in    std_logic;
+      cs_n    : in    std_logic;
+      ras_n   : in    std_logic;
+      cas_n   : in    std_logic;
+      we_n    : in    std_logic;
+      dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
+      ba      : in    std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
+      addr    : in    std_logic_vector((C3_MEM_ADDR_WIDTH  - 1) downto 0);
+      dq      : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
+      dqs     : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
+      dqs_n   : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
+      rdqs_n  : out   std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
+      odt     : in    std_logic
+      );
+  end component;
+component memc3_tb_top is
+generic
+  (
+      C_P0_MASK_SIZE                   : integer := 4;
+      C_P0_DATA_PORT_SIZE              : integer := 32;
+      C_P1_MASK_SIZE                   : integer := 4;
+      C_P1_DATA_PORT_SIZE              : integer := 32;
+      C_MEM_BURST_LEN                  : integer := 8;
+      C_MEM_NUM_COL_BITS               : integer := 11;
+      C_NUM_DQ_PINS                    : integer := 8;
+	        C_p0_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000100";
+      C_p0_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p0_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000002ff";
+      C_p0_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffffc00";
+      C_p0_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000100";
+      C_p1_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000300";
+      C_p1_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p1_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000004ff";
+      C_p1_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff800";
+      C_p1_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000300";
+      C_p2_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000500";
+      C_p2_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p2_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000006ff";
+      C_p2_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff800";
+      C_p2_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000500";
+      C_p3_BEGIN_ADDRESS                      : std_logic_vector(31 downto 0)  := X"00000700";
+      C_p3_DATA_MODE                          : std_logic_vector(3 downto 0)  := "0010";
+      C_p3_END_ADDRESS                        : std_logic_vector(31 downto 0)  := X"000008ff";
+      C_p3_PRBS_EADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"fffff000";
+      C_p3_PRBS_SADDR_MASK_POS                : std_logic_vector(31 downto 0)  := X"00000700"
+
+  );
+port
+(
+
+   clk0            : in std_logic;
+   rst0            : in std_logic;
+   calib_done      : in std_logic;
+
+         p0_mcb_cmd_en_o                           : out std_logic;
+      p0_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p0_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p0_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p0_mcb_cmd_full_i                         : in std_logic;
+
+      p0_mcb_wr_en_o                            : out std_logic;
+      p0_mcb_wr_mask_o                          : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
+      p0_mcb_wr_data_o                          : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_mcb_wr_full_i                          : in std_logic;
+      p0_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p0_mcb_rd_en_o                            : out std_logic;
+      p0_mcb_rd_data_i                          : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
+      p0_mcb_rd_empty_i                         : in std_logic;
+      p0_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p1_mcb_cmd_en_o                           : out std_logic;
+      p1_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p1_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p1_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p1_mcb_cmd_full_i                         : in std_logic;
+
+      p1_mcb_wr_en_o                            : out std_logic;
+      p1_mcb_wr_mask_o                          : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
+      p1_mcb_wr_data_o                          : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_mcb_wr_full_i                          : in std_logic;
+      p1_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p1_mcb_rd_en_o                            : out std_logic;
+      p1_mcb_rd_data_i                          : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
+      p1_mcb_rd_empty_i                         : in std_logic;
+      p1_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p2_mcb_cmd_en_o                           : out std_logic;
+      p2_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p2_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p2_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p2_mcb_cmd_full_i                         : in std_logic;
+
+      p2_mcb_wr_en_o                            : out std_logic;
+      p2_mcb_wr_mask_o                          : out std_logic_vector(3 downto 0);
+      p2_mcb_wr_data_o                          : out std_logic_vector(31 downto 0);
+      p2_mcb_wr_full_i                          : in std_logic;
+      p2_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p2_mcb_rd_en_o                            : out std_logic;
+      p2_mcb_rd_data_i                          : in std_logic_vector(31 downto 0);
+      p2_mcb_rd_empty_i                         : in std_logic;
+      p2_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p3_mcb_cmd_en_o                           : out std_logic;
+      p3_mcb_cmd_instr_o                        : out std_logic_vector(2 downto 0);
+      p3_mcb_cmd_bl_o                           : out std_logic_vector(5 downto 0);
+      p3_mcb_cmd_addr_o                         : out std_logic_vector(29 downto 0);
+      p3_mcb_cmd_full_i                         : in std_logic;
+
+      p3_mcb_wr_en_o                            : out std_logic;
+      p3_mcb_wr_mask_o                          : out std_logic_vector(3 downto 0);
+      p3_mcb_wr_data_o                          : out std_logic_vector(31 downto 0);
+      p3_mcb_wr_full_i                          : in std_logic;
+      p3_mcb_wr_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+      p3_mcb_rd_en_o                            : out std_logic;
+      p3_mcb_rd_data_i                          : in std_logic_vector(31 downto 0);
+      p3_mcb_rd_empty_i                         : in std_logic;
+      p3_mcb_rd_fifo_counts                     : in std_logic_vector(6 downto 0);
+
+
+
+   vio_modify_enable   : in std_logic;
+   vio_data_mode_value : in std_logic_vector(2 downto 0);
+   vio_addr_mode_value : in std_logic_vector(2 downto 0);
+   cmp_error       : out std_logic;
+   error           : out std_logic;
+   error_status    : out std_logic_vector(127 downto 0)
+);
+end component;
+
+-- ========================================================================== --
+-- Signal Declarations                                                        --
+-- ========================================================================== --
+
+-- Clocks
+					-- Clocks
+   signal  c3_sys_clk     : std_logic := '0';
+   signal  c3_sys_clk_p   : std_logic;
+   signal  c3_sys_clk_n   : std_logic;
+-- System Reset
+   signal  c3_sys_rst   : std_logic := '0';
+   signal  c3_sys_rst_i     : std_logic;
+
+
+
+-- Design-Top Port Map
+   signal  c3_error  : std_logic;
+   signal  c3_calib_done : std_logic;
+   signal  c3_error_status : std_logic_vector(127 downto 0); 
+   signal  mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
+   signal  mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);  
+   signal  mcb3_dram_ck : std_logic;  
+   signal  mcb3_dram_ck_n : std_logic;  
+   signal  mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);   
+   signal  mcb3_dram_dqs   : std_logic;  
+   signal  mcb3_dram_dqs_n : std_logic;
+   signal  mcb3_dram_dm    : std_logic;   
+   signal  mcb3_dram_ras_n : std_logic;   
+   signal  mcb3_dram_cas_n : std_logic;   
+   signal  mcb3_dram_we_n  : std_logic;    
+   signal  mcb3_dram_cke   : std_logic;   
+   signal  mcb3_dram_odt   : std_logic;  
+      signal  mcb3_dram_udqs   : std_logic;
+   signal  mcb3_dram_udqs_n : std_logic;
+   signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
+   signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
+      signal   mcb3_dram_udm :std_logic;     -- for X16 parts
+   signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
+   
+   
+
+-- User design  Sim
+   signal  c3_clk0 : std_logic;
+   signal  c3_rst0 : std_logic;  
+   signal  c3_cmp_error : std_logic; 
+   signal  c3_vio_modify_enable : std_logic;
+   signal  c3_vio_data_mode_value : std_logic_vector(2 downto 0);
+   signal  c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
+   signal mcb3_command               : std_logic_vector(2 downto 0);
+   signal mcb3_enable1                : std_logic;
+   signal mcb3_enable2              : std_logic;
+
+     signal  c3_p0_cmd_en                             : std_logic;
+  signal  c3_p0_cmd_instr                          : std_logic_vector(2 downto 0);
+  signal  c3_p0_cmd_bl                             : std_logic_vector(5 downto 0);
+  signal  c3_p0_cmd_byte_addr                      : std_logic_vector(29 downto 0);
+  signal  c3_p0_cmd_empty                          : std_logic;
+  signal  c3_p0_cmd_full                           : std_logic;
+  signal  c3_p0_wr_en                              : std_logic;
+  signal  c3_p0_wr_mask                            : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
+  signal  c3_p0_wr_data                            : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+  signal  c3_p0_wr_full                            : std_logic;
+  signal  c3_p0_wr_empty                           : std_logic;
+  signal  c3_p0_wr_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p0_wr_underrun                        : std_logic;
+  signal  c3_p0_wr_error                           : std_logic;
+  signal  c3_p0_rd_en                              : std_logic;
+  signal  c3_p0_rd_data                            : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
+  signal  c3_p0_rd_full                            : std_logic;
+  signal  c3_p0_rd_empty                           : std_logic;
+  signal  c3_p0_rd_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p0_rd_overflow                        : std_logic;
+  signal  c3_p0_rd_error                           : std_logic;
+
+  signal  c3_p1_cmd_en                             : std_logic;
+  signal  c3_p1_cmd_instr                          : std_logic_vector(2 downto 0);
+  signal  c3_p1_cmd_bl                             : std_logic_vector(5 downto 0);
+  signal  c3_p1_cmd_byte_addr                      : std_logic_vector(29 downto 0);
+  signal  c3_p1_cmd_empty                          : std_logic;
+  signal  c3_p1_cmd_full                           : std_logic;
+  signal  c3_p1_wr_en                              : std_logic;
+  signal  c3_p1_wr_mask                            : std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
+  signal  c3_p1_wr_data                            : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+  signal  c3_p1_wr_full                            : std_logic;
+  signal  c3_p1_wr_empty                           : std_logic;
+  signal  c3_p1_wr_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p1_wr_underrun                        : std_logic;
+  signal  c3_p1_wr_error                           : std_logic;
+  signal  c3_p1_rd_en                              : std_logic;
+  signal  c3_p1_rd_data                            : std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
+  signal  c3_p1_rd_full                            : std_logic;
+  signal  c3_p1_rd_empty                           : std_logic;
+  signal  c3_p1_rd_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p1_rd_overflow                        : std_logic;
+  signal  c3_p1_rd_error                           : std_logic;
+
+  signal  c3_p2_cmd_en                             : std_logic;
+  signal  c3_p2_cmd_instr                          : std_logic_vector(2 downto 0);
+  signal  c3_p2_cmd_bl                             : std_logic_vector(5 downto 0);
+  signal  c3_p2_cmd_byte_addr                      : std_logic_vector(29 downto 0);
+  signal  c3_p2_cmd_empty                          : std_logic;
+  signal  c3_p2_cmd_full                           : std_logic;
+  signal  c3_p2_wr_en                              : std_logic;
+  signal  c3_p2_wr_mask                            : std_logic_vector(3 downto 0);
+  signal  c3_p2_wr_data                            : std_logic_vector(31 downto 0);
+  signal  c3_p2_wr_full                            : std_logic;
+  signal  c3_p2_wr_empty                           : std_logic;
+  signal  c3_p2_wr_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p2_wr_underrun                        : std_logic;
+  signal  c3_p2_wr_error                           : std_logic;
+  signal  c3_p2_rd_en                              : std_logic;
+  signal  c3_p2_rd_data                            : std_logic_vector(31 downto 0);
+  signal  c3_p2_rd_full                            : std_logic;
+  signal  c3_p2_rd_empty                           : std_logic;
+  signal  c3_p2_rd_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p2_rd_overflow                        : std_logic;
+  signal  c3_p2_rd_error                           : std_logic;
+
+  signal  c3_p3_cmd_en                             : std_logic;
+  signal  c3_p3_cmd_instr                          : std_logic_vector(2 downto 0);
+  signal  c3_p3_cmd_bl                             : std_logic_vector(5 downto 0);
+  signal  c3_p3_cmd_byte_addr                      : std_logic_vector(29 downto 0);
+  signal  c3_p3_cmd_empty                          : std_logic;
+  signal  c3_p3_cmd_full                           : std_logic;
+  signal  c3_p3_wr_en                              : std_logic;
+  signal  c3_p3_wr_mask                            : std_logic_vector(3 downto 0);
+  signal  c3_p3_wr_data                            : std_logic_vector(31 downto 0);
+  signal  c3_p3_wr_full                            : std_logic;
+  signal  c3_p3_wr_empty                           : std_logic;
+  signal  c3_p3_wr_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p3_wr_underrun                        : std_logic;
+  signal  c3_p3_wr_error                           : std_logic;
+  signal  c3_p3_rd_en                              : std_logic;
+  signal  c3_p3_rd_data                            : std_logic_vector(31 downto 0);
+  signal  c3_p3_rd_full                            : std_logic;
+  signal  c3_p3_rd_empty                           : std_logic;
+  signal  c3_p3_rd_count                           : std_logic_vector(6 downto 0);
+  signal  c3_p3_rd_overflow                        : std_logic;
+  signal  c3_p3_rd_error                           : std_logic;
+
+  signal  c3_selfrefresh_enter                     : std_logic;
+  signal  c3_selfrefresh_mode                      : std_logic;
+
+
+   signal  rzq3     : std_logic;
+      
+   signal  zio3     : std_logic;
+      
+   signal   calib_done  : std_logic;
+   signal   error  : std_logic;
+
+
+function vector (asi:std_logic) return std_logic_vector is
+  variable v : std_logic_vector(0 downto 0) ; 
+begin
+  v(0) := asi;
+  return(v); 
+end function vector; 
+
+begin
+-- ========================================================================== --
+-- Clocks Generation                                                          --
+-- ========================================================================== --
+
+
+  process
+  begin
+    c3_sys_clk <= not c3_sys_clk;
+    wait for (C3_TCYC_SYS_DIV2);
+  end process;
+
+  c3_sys_clk_p <= c3_sys_clk;
+  c3_sys_clk_n <= not c3_sys_clk;
+
+-- ========================================================================== --
+-- Reset Generation                                                           --
+-- ========================================================================== --
+ 
+ process
+  begin
+    c3_sys_rst <= '0';
+    wait for 200 ns;
+    c3_sys_rst <= '1';
+    wait;
+  end process;
+
+    c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
+
+
+error <= c3_error;
+calib_done <= c3_calib_done;
+
+   
+
+   
+   -- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
+-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
+   zio_pulldown3 : PULLDOWN port map(O => zio3);
+   rzq_pulldown3 : PULLDOWN port map(O => rzq3);
+   
+
+-- ========================================================================== --
+-- DESIGN TOP INSTANTIATION                                                    --
+-- ========================================================================== --
+
+design_top : ddr2 generic map
+(
+  
+C3_P0_MASK_SIZE  =>     C3_P0_MASK_SIZE,
+C3_P0_DATA_PORT_SIZE  => C3_P0_DATA_PORT_SIZE,
+C3_P1_MASK_SIZE       => C3_P1_MASK_SIZE,
+C3_P1_DATA_PORT_SIZE  => C3_P1_DATA_PORT_SIZE, 
+	C3_MEMCLK_PERIOD  =>       C3_MEMCLK_PERIOD,
+C3_RST_ACT_LOW    =>     C3_RST_ACT_LOW,
+C3_INPUT_CLK_TYPE =>     C3_INPUT_CLK_TYPE, 
+DEBUG_EN              => DEBUG_EN,
+
+C3_MEM_ADDR_ORDER     => C3_MEM_ADDR_ORDER,
+C3_NUM_DQ_PINS        => C3_NUM_DQ_PINS,
+C3_MEM_ADDR_WIDTH     => C3_MEM_ADDR_WIDTH,
+C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
+
+
+C3_SIMULATION   =>      C3_SIMULATION,
+
+C3_CALIB_SOFT_IP      => C3_CALIB_SOFT_IP
+) 
+port map ( 
+
+    c3_sys_clk  =>         c3_sys_clk,
+  c3_sys_rst_i    =>       c3_sys_rst_i,                        
+
+  mcb3_dram_dq       =>    mcb3_dram_dq,  
+  mcb3_dram_a        =>    mcb3_dram_a,  
+  mcb3_dram_ba       =>    mcb3_dram_ba,
+  mcb3_dram_ras_n    =>    mcb3_dram_ras_n,                        
+  mcb3_dram_cas_n    =>    mcb3_dram_cas_n,                        
+  mcb3_dram_we_n     =>    mcb3_dram_we_n,                          
+  mcb3_dram_odt    =>      mcb3_dram_odt,
+  mcb3_dram_cke      =>    mcb3_dram_cke,                          
+  mcb3_dram_ck       =>    mcb3_dram_ck,                          
+  mcb3_dram_ck_n     =>    mcb3_dram_ck_n,       
+  mcb3_dram_dqs      =>    mcb3_dram_dqs,                          
+  mcb3_dram_dqs_n  =>      mcb3_dram_dqs_n,
+  mcb3_dram_udqs  =>       mcb3_dram_udqs,    -- for X16 parts           
+  mcb3_dram_udqs_n    =>   mcb3_dram_udqs_n,  -- for X16 parts
+  mcb3_dram_udm  =>        mcb3_dram_udm,     -- for X16 parts
+  mcb3_dram_dm  =>       mcb3_dram_dm,
+    c3_clk0	=>	        c3_clk0,
+  c3_rst0		=>        c3_rst0,
+	
+ 
+  c3_calib_done      =>    c3_calib_done,
+     mcb3_rzq        =>            rzq3,
+	
+     mcb3_zio        =>            zio3,
+	
+     c3_p0_cmd_clk                           =>  (c3_clk0),
+   c3_p0_cmd_en                            =>  c3_p0_cmd_en,
+   c3_p0_cmd_instr                         =>  c3_p0_cmd_instr,
+   c3_p0_cmd_bl                            =>  c3_p0_cmd_bl,
+   c3_p0_cmd_byte_addr                     =>  c3_p0_cmd_byte_addr,
+   c3_p0_cmd_empty                         =>  c3_p0_cmd_empty,
+   c3_p0_cmd_full                          =>  c3_p0_cmd_full,
+   c3_p0_wr_clk                            =>  (c3_clk0),
+   c3_p0_wr_en                             =>  c3_p0_wr_en,
+   c3_p0_wr_mask                           =>  c3_p0_wr_mask,
+   c3_p0_wr_data                           =>  c3_p0_wr_data,
+   c3_p0_wr_full                           =>  c3_p0_wr_full,
+   c3_p0_wr_empty                          =>  c3_p0_wr_empty,
+   c3_p0_wr_count                          =>  c3_p0_wr_count,
+   c3_p0_wr_underrun                       =>  c3_p0_wr_underrun,
+   c3_p0_wr_error                          =>  c3_p0_wr_error,
+   c3_p0_rd_clk                            =>  (c3_clk0),
+   c3_p0_rd_en                             =>  c3_p0_rd_en,
+   c3_p0_rd_data                           =>  c3_p0_rd_data,
+   c3_p0_rd_full                           =>  c3_p0_rd_full,
+   c3_p0_rd_empty                          =>  c3_p0_rd_empty,
+   c3_p0_rd_count                          =>  c3_p0_rd_count,
+   c3_p0_rd_overflow                       =>  c3_p0_rd_overflow,
+   c3_p0_rd_error                          =>  c3_p0_rd_error,
+   c3_p1_cmd_clk                           =>  (c3_clk0),
+   c3_p1_cmd_en                            =>  c3_p1_cmd_en,
+   c3_p1_cmd_instr                         =>  c3_p1_cmd_instr,
+   c3_p1_cmd_bl                            =>  c3_p1_cmd_bl,
+   c3_p1_cmd_byte_addr                     =>  c3_p1_cmd_byte_addr,
+   c3_p1_cmd_empty                         =>  c3_p1_cmd_empty,
+   c3_p1_cmd_full                          =>  c3_p1_cmd_full,
+   c3_p1_wr_clk                            =>  (c3_clk0),
+   c3_p1_wr_en                             =>  c3_p1_wr_en,
+   c3_p1_wr_mask                           =>  c3_p1_wr_mask,
+   c3_p1_wr_data                           =>  c3_p1_wr_data,
+   c3_p1_wr_full                           =>  c3_p1_wr_full,
+   c3_p1_wr_empty                          =>  c3_p1_wr_empty,
+   c3_p1_wr_count                          =>  c3_p1_wr_count,
+   c3_p1_wr_underrun                       =>  c3_p1_wr_underrun,
+   c3_p1_wr_error                          =>  c3_p1_wr_error,
+   c3_p1_rd_clk                            =>  (c3_clk0),
+   c3_p1_rd_en                             =>  c3_p1_rd_en,
+   c3_p1_rd_data                           =>  c3_p1_rd_data,
+   c3_p1_rd_full                           =>  c3_p1_rd_full,
+   c3_p1_rd_empty                          =>  c3_p1_rd_empty,
+   c3_p1_rd_count                          =>  c3_p1_rd_count,
+   c3_p1_rd_overflow                       =>  c3_p1_rd_overflow,
+   c3_p1_rd_error                          =>  c3_p1_rd_error,
+   c3_p2_cmd_clk                           =>  (c3_clk0),
+   c3_p2_cmd_en                            =>  c3_p2_cmd_en,
+   c3_p2_cmd_instr                         =>  c3_p2_cmd_instr,
+   c3_p2_cmd_bl                            =>  c3_p2_cmd_bl,
+   c3_p2_cmd_byte_addr                     =>  c3_p2_cmd_byte_addr,
+   c3_p2_cmd_empty                         =>  c3_p2_cmd_empty,
+   c3_p2_cmd_full                          =>  c3_p2_cmd_full,
+   c3_p2_wr_clk                            =>  (c3_clk0),
+   c3_p2_wr_en                             =>  c3_p2_wr_en,
+   c3_p2_wr_mask                           =>  c3_p2_wr_mask,
+   c3_p2_wr_data                           =>  c3_p2_wr_data,
+   c3_p2_wr_full                           =>  c3_p2_wr_full,
+   c3_p2_wr_empty                          =>  c3_p2_wr_empty,
+   c3_p2_wr_count                          =>  c3_p2_wr_count,
+   c3_p2_wr_underrun                       =>  c3_p2_wr_underrun,
+   c3_p2_wr_error                          =>  c3_p2_wr_error,
+   c3_p2_rd_clk                            =>  (c3_clk0),
+   c3_p2_rd_en                             =>  c3_p2_rd_en,
+   c3_p2_rd_data                           =>  c3_p2_rd_data,
+   c3_p2_rd_full                           =>  c3_p2_rd_full,
+   c3_p2_rd_empty                          =>  c3_p2_rd_empty,
+   c3_p2_rd_count                          =>  c3_p2_rd_count,
+   c3_p2_rd_overflow                       =>  c3_p2_rd_overflow,
+   c3_p2_rd_error                          =>  c3_p2_rd_error,
+   c3_p3_cmd_clk                           =>  (c3_clk0),
+   c3_p3_cmd_en                            =>  c3_p3_cmd_en,
+   c3_p3_cmd_instr                         =>  c3_p3_cmd_instr,
+   c3_p3_cmd_bl                            =>  c3_p3_cmd_bl,
+   c3_p3_cmd_byte_addr                     =>  c3_p3_cmd_byte_addr,
+   c3_p3_cmd_empty                         =>  c3_p3_cmd_empty,
+   c3_p3_cmd_full                          =>  c3_p3_cmd_full,
+   c3_p3_wr_clk                            =>  (c3_clk0),
+   c3_p3_wr_en                             =>  c3_p3_wr_en,
+   c3_p3_wr_mask                           =>  c3_p3_wr_mask,
+   c3_p3_wr_data                           =>  c3_p3_wr_data,
+   c3_p3_wr_full                           =>  c3_p3_wr_full,
+   c3_p3_wr_empty                          =>  c3_p3_wr_empty,
+   c3_p3_wr_count                          =>  c3_p3_wr_count,
+   c3_p3_wr_underrun                       =>  c3_p3_wr_underrun,
+   c3_p3_wr_error                          =>  c3_p3_wr_error,
+   c3_p3_rd_clk                            =>  (c3_clk0),
+   c3_p3_rd_en                             =>  c3_p3_rd_en,
+   c3_p3_rd_data                           =>  c3_p3_rd_data,
+   c3_p3_rd_full                           =>  c3_p3_rd_full,
+   c3_p3_rd_empty                          =>  c3_p3_rd_empty,
+   c3_p3_rd_count                          =>  c3_p3_rd_count,
+   c3_p3_rd_overflow                       =>  c3_p3_rd_overflow,
+   c3_p3_rd_error                          =>  c3_p3_rd_error
+);      
+
+-- user interface
+
+memc3_tb_top_inst :  memc3_tb_top generic map
+ (
+   C_NUM_DQ_PINS       =>     C3_NUM_DQ_PINS,
+   C_MEM_BURST_LEN     =>     C3_MEM_BURST_LEN,
+   C_MEM_NUM_COL_BITS  =>     C3_MEM_NUM_COL_BITS,
+   C_P0_MASK_SIZE      =>     C3_P0_MASK_SIZE,
+   C_P0_DATA_PORT_SIZE =>     C3_P0_DATA_PORT_SIZE,        
+   C_P1_MASK_SIZE      =>     C3_P1_MASK_SIZE,        
+   C_P1_DATA_PORT_SIZE =>     C3_P1_DATA_PORT_SIZE,        
+   C_p0_BEGIN_ADDRESS                      => C3_p0_BEGIN_ADDRESS,
+   C_p0_DATA_MODE                          => C3_p0_DATA_MODE,
+   C_p0_END_ADDRESS                        => C3_p0_END_ADDRESS,
+   C_p0_PRBS_EADDR_MASK_POS                => C3_p0_PRBS_EADDR_MASK_POS,
+   C_p0_PRBS_SADDR_MASK_POS                => C3_p0_PRBS_SADDR_MASK_POS,
+   C_p1_BEGIN_ADDRESS                      => C3_p1_BEGIN_ADDRESS,
+   C_p1_DATA_MODE                          => C3_p1_DATA_MODE,
+   C_p1_END_ADDRESS                        => C3_p1_END_ADDRESS,
+   C_p1_PRBS_EADDR_MASK_POS                => C3_p1_PRBS_EADDR_MASK_POS,
+   C_p1_PRBS_SADDR_MASK_POS                => C3_p1_PRBS_SADDR_MASK_POS,
+   C_p2_BEGIN_ADDRESS                      => C3_p2_BEGIN_ADDRESS,
+   C_p2_DATA_MODE                          => C3_p2_DATA_MODE,
+   C_p2_END_ADDRESS                        => C3_p2_END_ADDRESS,
+   C_p2_PRBS_EADDR_MASK_POS                => C3_p2_PRBS_EADDR_MASK_POS,
+   C_p2_PRBS_SADDR_MASK_POS                => C3_p2_PRBS_SADDR_MASK_POS,
+   C_p3_BEGIN_ADDRESS                      => C3_p3_BEGIN_ADDRESS,
+   C_p3_DATA_MODE                          => C3_p3_DATA_MODE,
+   C_p3_END_ADDRESS                        => C3_p3_END_ADDRESS,
+   C_p3_PRBS_EADDR_MASK_POS                => C3_p3_PRBS_EADDR_MASK_POS,
+   C_p3_PRBS_SADDR_MASK_POS                => C3_p3_PRBS_SADDR_MASK_POS
+   )
+port map
+(
+   clk0			         => c3_clk0,
+   rst0			         => c3_rst0,
+   calib_done            => c3_calib_done, 
+   cmp_error             => c3_cmp_error,
+   error                 => c3_error,
+   error_status          => c3_error_status,
+   vio_modify_enable     => c3_vio_modify_enable,
+   vio_data_mode_value   => c3_vio_data_mode_value,
+   vio_addr_mode_value   => c3_vio_addr_mode_value,
+   p0_mcb_cmd_en_o                          =>  c3_p0_cmd_en,
+   p0_mcb_cmd_instr_o                       =>  c3_p0_cmd_instr,
+   p0_mcb_cmd_bl_o                          =>  c3_p0_cmd_bl,
+   p0_mcb_cmd_addr_o                        =>  c3_p0_cmd_byte_addr,
+   p0_mcb_cmd_full_i                        =>  c3_p0_cmd_full,
+   p0_mcb_wr_en_o                           =>  c3_p0_wr_en,
+   p0_mcb_wr_mask_o                         =>  c3_p0_wr_mask,
+   p0_mcb_wr_data_o                         =>  c3_p0_wr_data,
+   p0_mcb_wr_full_i                         =>  c3_p0_wr_full,
+   p0_mcb_wr_fifo_counts                    =>  c3_p0_wr_count,
+   p0_mcb_rd_en_o                           =>  c3_p0_rd_en,
+   p0_mcb_rd_data_i                         =>  c3_p0_rd_data,
+   p0_mcb_rd_empty_i                        =>  c3_p0_rd_empty,
+   p0_mcb_rd_fifo_counts                    =>  c3_p0_rd_count,
+   p1_mcb_cmd_en_o                          =>  c3_p1_cmd_en,
+   p1_mcb_cmd_instr_o                       =>  c3_p1_cmd_instr,
+   p1_mcb_cmd_bl_o                          =>  c3_p1_cmd_bl,
+   p1_mcb_cmd_addr_o                        =>  c3_p1_cmd_byte_addr,
+   p1_mcb_cmd_full_i                        =>  c3_p1_cmd_full,
+   p1_mcb_wr_en_o                           =>  c3_p1_wr_en,
+   p1_mcb_wr_mask_o                         =>  c3_p1_wr_mask,
+   p1_mcb_wr_data_o                         =>  c3_p1_wr_data,
+   p1_mcb_wr_full_i                         =>  c3_p1_wr_full,
+   p1_mcb_wr_fifo_counts                    =>  c3_p1_wr_count,
+   p1_mcb_rd_en_o                           =>  c3_p1_rd_en,
+   p1_mcb_rd_data_i                         =>  c3_p1_rd_data,
+   p1_mcb_rd_empty_i                        =>  c3_p1_rd_empty,
+   p1_mcb_rd_fifo_counts                    =>  c3_p1_rd_count,
+   p2_mcb_cmd_en_o                          =>  c3_p2_cmd_en,
+   p2_mcb_cmd_instr_o                       =>  c3_p2_cmd_instr,
+   p2_mcb_cmd_bl_o                          =>  c3_p2_cmd_bl,
+   p2_mcb_cmd_addr_o                        =>  c3_p2_cmd_byte_addr,
+   p2_mcb_cmd_full_i                        =>  c3_p2_cmd_full,
+   p2_mcb_wr_en_o                           =>  c3_p2_wr_en,
+   p2_mcb_wr_mask_o                         =>  c3_p2_wr_mask,
+   p2_mcb_wr_data_o                         =>  c3_p2_wr_data,
+   p2_mcb_wr_full_i                         =>  c3_p2_wr_full,
+   p2_mcb_wr_fifo_counts                    =>  c3_p2_wr_count,
+   p2_mcb_rd_en_o                           =>  c3_p2_rd_en,
+   p2_mcb_rd_data_i                         =>  c3_p2_rd_data,
+   p2_mcb_rd_empty_i                        =>  c3_p2_rd_empty,
+   p2_mcb_rd_fifo_counts                    =>  c3_p2_rd_count,
+   p3_mcb_cmd_en_o                          =>  c3_p3_cmd_en,
+   p3_mcb_cmd_instr_o                       =>  c3_p3_cmd_instr,
+   p3_mcb_cmd_bl_o                          =>  c3_p3_cmd_bl,
+   p3_mcb_cmd_addr_o                        =>  c3_p3_cmd_byte_addr,
+   p3_mcb_cmd_full_i                        =>  c3_p3_cmd_full,
+   p3_mcb_wr_en_o                           =>  c3_p3_wr_en,
+   p3_mcb_wr_mask_o                         =>  c3_p3_wr_mask,
+   p3_mcb_wr_data_o                         =>  c3_p3_wr_data,
+   p3_mcb_wr_full_i                         =>  c3_p3_wr_full,
+   p3_mcb_wr_fifo_counts                    =>  c3_p3_wr_count,
+   p3_mcb_rd_en_o                           =>  c3_p3_rd_en,
+   p3_mcb_rd_data_i                         =>  c3_p3_rd_data,
+   p3_mcb_rd_empty_i                        =>  c3_p3_rd_empty,
+   p3_mcb_rd_fifo_counts                    =>  c3_p3_rd_count
+  
+
+  );
+
+-- ========================================================================== --
+-- Memory model instances                                                     -- 
+-- ========================================================================== --
+
+    mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
+
+    process(mcb3_dram_ck)
+    begin
+      if (rising_edge(mcb3_dram_ck)) then
+        if (c3_sys_rst = '0') then
+          mcb3_enable1   <= '0';
+          mcb3_enable2 <= '0';
+        elsif (mcb3_command = "100") then
+          mcb3_enable2 <= '0';
+        elsif (mcb3_command = "101") then
+          mcb3_enable2 <= '1';
+        else
+          mcb3_enable2 <= mcb3_enable2;
+        end if;
+        mcb3_enable1     <= mcb3_enable2;
+      end if;
+    end process;
+
+-----------------------------------------------------------------------------
+--read
+-----------------------------------------------------------------------------
+    mcb3_dram_dqs_vector(1 downto 0)               <= (mcb3_dram_udqs & mcb3_dram_dqs)
+                                                           when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
+							   else "ZZ";
+    mcb3_dram_dqs_n_vector(1 downto 0)             <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
+                                                           when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
+							   else "ZZ";
+    
+-----------------------------------------------------------------------------
+--write
+-----------------------------------------------------------------------------
+    mcb3_dram_dqs          <= mcb3_dram_dqs_vector(0)
+                              when ( mcb3_enable1 = '1') else 'Z';
+
+    mcb3_dram_udqs          <= mcb3_dram_dqs_vector(1)
+                              when (mcb3_enable1 = '1') else 'Z';
+
+
+     mcb3_dram_dqs_n        <= mcb3_dram_dqs_n_vector(0)
+                              when (mcb3_enable1 = '1') else 'Z';
+    mcb3_dram_udqs_n         <= mcb3_dram_dqs_n_vector(1)
+                              when (mcb3_enable1 = '1') else 'Z';
+
+   
+   
+mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
+
+     u_mem_c3 : ddr2_model_c3 port map(
+        ck        => mcb3_dram_ck,
+        ck_n      => mcb3_dram_ck_n,
+        cke       => mcb3_dram_cke,
+        cs_n      => '0',
+        ras_n     => mcb3_dram_ras_n,
+        cas_n     => mcb3_dram_cas_n,
+        we_n      => mcb3_dram_we_n,
+        dm_rdqs   => mcb3_dram_dm_vector ,
+        ba        => mcb3_dram_ba,
+        addr      => mcb3_dram_a,
+        dq        => mcb3_dram_dq,
+        dqs       => mcb3_dram_dqs_vector,
+        dqs_n     => mcb3_dram_dqs_n_vector,
+        rdqs_n    => open,
+        odt       => mcb3_dram_odt
+      );
+
+-----------------------------------------------------------------------------     
+-- Reporting the test case status 
+-----------------------------------------------------------------------------
+   Logging: process 
+   begin
+      wait for 200 us;
+      if (calib_done = '1') then
+         if (error = '0') then
+   	    report ("****TEST PASSED****");
+         else
+            report ("****TEST FAILED: DATA ERROR****");
+         end if;
+      else
+         report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
+      end if;
+   end process;   
+
+end architecture;
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sp6_data_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sp6_data_gen.vhd
new file mode 100755
index 0000000..d85e41b
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/sp6_data_gen.vhd
@@ -0,0 +1,793 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: sp6_data_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:40 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This module generates different data pattern as described in 
+--         parameter DATA_PATTERN and is set up for Spartan 6 family.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+   USE ieee.numeric_std.all;
+
+entity sp6_data_gen is
+   generic (
+      
+      ADDR_WIDTH                     : integer := 32;
+      BL_WIDTH                       : integer := 6;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_ALL";           --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      COLUMN_WIDTH                   : integer := 10
+   );
+   port (
+      
+      clk_i                          : in std_logic;            --
+      rst_i                          : in std_logic;
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      
+      data_mode_i                    : in std_logic_vector(3 downto 0);         -- "00" = bram; 
+      data_rdy_i                     : in std_logic;
+      cmd_startA                     : in std_logic;
+      cmd_startB                     : in std_logic;
+      cmd_startC                     : in std_logic;
+      cmd_startD                     : in std_logic;
+      cmd_startE                     : in std_logic;
+      fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);
+      addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);            -- generated address used to determine data pattern.
+      user_burst_cnt                 : in std_logic_vector(6 downto 0);         -- generated burst length for control the burst data
+      
+      fifo_rdy_i                     : in std_logic;            -- connect from mcb_wr_full when used as wr_data_gen
+      -- connect from mcb_rd_empty when used as rd_data_gen
+      -- When both data_rdy and data_valid is asserted, the ouput data is valid.
+      data_o                         : out std_logic_vector(DWIDTH - 1 downto 0)                -- generated data pattern   
+   );
+end entity sp6_data_gen;
+
+architecture trans of sp6_data_gen is
+
+COMPONENT data_prbs_gen IS
+   GENERIC (
+      EYE_TEST        : STRING := "FALSE";
+      PRBS_WIDTH      : INTEGER := 32;
+      SEED_WIDTH      : INTEGER := 32
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      clk_en          : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      prbs_seed_init  : IN STD_LOGIC;
+      prbs_seed_i     : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
+      
+      prbs_o          : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
+   );
+END COMPONENT;
+
+   -- 
+   signal prbs_data                : std_logic_vector(31 downto 0);
+   
+   signal adata                    : std_logic_vector(31 downto 0);
+   signal hdata                    : std_logic_vector(DWIDTH - 1 downto 0);
+   signal ndata                    : std_logic_vector(DWIDTH - 1 downto 0);
+   signal w1data                   : std_logic_vector(DWIDTH - 1 downto 0);
+   signal data                     : std_logic_vector(DWIDTH - 1 downto 0);
+   signal burst_count_reached2     : std_logic;
+   
+   signal data_valid               : std_logic;
+   signal walk_cnt                 : std_logic_vector(2 downto 0);
+   signal user_address             : std_logic_vector(ADDR_WIDTH - 1 downto 0);
+   
+   signal i                        : integer;
+   signal j                        : integer;
+   signal user_bl                  : std_logic_vector(BL_WIDTH - 1 downto 0);
+   signal BLANK                    : std_logic_vector(7 downto 0);
+   
+   signal SHIFT_0                  : std_logic_vector(7 downto 0);
+   signal SHIFT_1                  : std_logic_vector(7 downto 0);
+   signal SHIFT_2                  : std_logic_vector(7 downto 0);
+   signal SHIFT_3                  : std_logic_vector(7 downto 0);
+   signal SHIFT_4                  : std_logic_vector(7 downto 0);
+   signal SHIFT_5                  : std_logic_vector(7 downto 0);
+   signal SHIFT_6                  : std_logic_vector(7 downto 0);
+   signal SHIFT_7                  : std_logic_vector(7 downto 0);
+   signal SHIFTB_0                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_1                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_2                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_3                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_4                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_5                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_6                 : std_logic_vector(31 downto 0);
+   signal SHIFTB_7                 : std_logic_vector(31 downto 0);
+   signal TSTB                     : std_logic_vector(3 downto 0);
+   --*********************************************************************************************
+   
+   --  4'b0000: data = 32'b0;       //bram
+   --   4'b0001: data = 32'b0;       // fixed
+   -- address as data
+   -- DGEN_HAMMER
+   -- DGEN_NEIGHBOUR
+   -- DGEN_WALKING1
+   -- DGEN_WALKING0
+   
+   --bram
+   -- fixed
+   -- address as data
+   -- DGEN_HAMMER
+   -- DGEN_NEIGHBOUR
+   -- DGEN_WALKING1
+   -- DGEN_WALKING0
+   
+   --bram
+   -- fixed
+   -- address as data
+   -- DGEN_HAMMER
+   -- DGEN_NEIGHBOUR
+   -- DGEN_WALKING1
+   -- DGEN_WALKING0
+   
+   -- WALKING ONES:
+   
+   -- WALKING ONE
+   
+   -- NEIGHBOR ONE
+   
+   -- WALKING ZERO
+   
+   -- WALKING ONE
+   
+   -- NEIGHBOR ONE
+   
+   -- WALKING ZERO
+   
+   signal tmpdata                  : std_logic_vector(DWIDTH - 1 downto 0);
+   signal ndata_rising             : std_logic;
+   signal shift_en                 : std_logic;
+   signal data_clk_en              : std_logic;
+   SIGNAL ZEROS  : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
+   
+begin
+   ZEROS <= (others => '0');
+   data_o <= data;
+   xhdl0 : if (DWIDTH = 32) generate
+      process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
+      begin
+         case data_mode_i is
+            when "0001" =>
+               data <= fixed_data_i;
+            when "0010" =>
+               data <= adata;
+            when "0011" =>
+               data <= hdata;
+            when "0100" =>
+               data <= ndata;
+            when "0101" =>
+               data <= w1data;
+            when "0110" =>
+               data <= w1data;
+            when "0111" =>
+               data <= prbs_data;
+            WHEN OTHERS =>
+               data <= (others => '0');
+         END CASE;
+      END PROCESS;
+      
+   end generate;
+   xhdl1 : if (DWIDTH = 64) generate
+      process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
+      begin
+         case data_mode_i is
+            when "0000" =>
+               data <= (others => '0');
+            when "0001" =>
+               data <= fixed_data_i;
+            when "0010" =>
+--               data <= (adata & adata)(31 downto 0);
+               data <= (adata & adata);
+            when "0011" =>
+               data <= hdata;
+            when "0100" =>
+               data <= ndata;
+            when "0101" =>
+               data <= w1data;
+            when "0110" =>
+               data <= w1data;
+            when "0111" =>
+--               data <= (prbs_data & prbs_data)(31 downto 0);
+               data <= (prbs_data & prbs_data);
+            when others =>
+               data <= (others => '0');
+         end case;
+      end process;
+      
+   end generate;
+   xhdl2 : if (DWIDTH = 128) generate
+      process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
+      begin
+         case data_mode_i is
+            when "0000" =>
+               data <= (others => '0');
+            when "0001" =>
+               data <= fixed_data_i;
+            when "0010" =>
+--               data <= (adata & adata & adata & adata)(31 downto 0);
+               data <= (adata & adata & adata & adata);
+            when "0011" =>
+               data <= hdata;
+            when "0100" =>
+               data <= ndata;
+            when "0101" =>
+               data <= w1data;
+            when "0110" =>
+               data <= w1data;
+            when "0111" =>
+--               data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
+               data <= (prbs_data & prbs_data & prbs_data & prbs_data);
+            when others =>
+               data <= (others => '0');--"00000000000000000000000000000000";
+         end case;
+      end process;
+      
+   end generate;
+   xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
+      process (data_mode_i)
+      begin
+         if (data_mode_i = "0101" or data_mode_i = "0100") then
+            BLANK <= "00000000";
+            SHIFT_0 <= "00000001";
+            SHIFT_1 <= "00000010";
+            SHIFT_2 <= "00000100";
+            SHIFT_3 <= "00001000";
+            SHIFT_4 <= "00010000";
+            SHIFT_5 <= "00100000";
+            SHIFT_6 <= "01000000";
+            SHIFT_7 <= "10000000";
+         elsif (data_mode_i = "0100") then
+            BLANK <= "00000000";
+            SHIFT_0 <= "00000001";
+            SHIFT_1 <= "00000010";
+            SHIFT_2 <= "00000100";
+            SHIFT_3 <= "00001000";
+            SHIFT_4 <= "00010000";
+            SHIFT_5 <= "00100000";
+            SHIFT_6 <= "01000000";
+            SHIFT_7 <= "10000000";
+         elsif (data_mode_i = "0110") then
+            BLANK <= "11111111";
+            SHIFT_0 <= "11111110";
+            SHIFT_1 <= "11111101";
+            SHIFT_2 <= "11111011";
+            SHIFT_3 <= "11110111";
+            SHIFT_4 <= "11101111";
+            SHIFT_5 <= "11011111";
+            SHIFT_6 <= "10111111";
+            SHIFT_7 <= "01111111";
+         else
+            BLANK <= "11111111";
+            SHIFT_0 <= "11111110";
+            SHIFT_1 <= "11111101";
+            SHIFT_2 <= "11111011";
+            SHIFT_3 <= "11110111";
+            SHIFT_4 <= "11101111";
+            SHIFT_5 <= "11011111";
+            SHIFT_6 <= "10111111";
+            SHIFT_7 <= "01111111";
+         end if;
+      end process;
+      
+   end generate;
+   process (data_mode_i)
+   begin
+      if (data_mode_i = "0101") then
+         SHIFTB_0 <= "00000000000000100000000000000001";
+         SHIFTB_1 <= "00000000000010000000000000000100";
+         SHIFTB_2 <= "00000000001000000000000000010000";
+         SHIFTB_3 <= "00000000100000000000000001000000";
+         SHIFTB_4 <= "00000010000000000000000100000000";
+         SHIFTB_5 <= "00001000000000000000010000000000";
+         SHIFTB_6 <= "00100000000000000001000000000000";
+         SHIFTB_7 <= "10000000000000000100000000000000";
+      elsif (data_mode_i = "0100") then
+         SHIFTB_0 <= "00000000000000000000000000000001";
+         SHIFTB_1 <= "00000000000000000000000000000010";
+         SHIFTB_2 <= "00000000000000000000000000000100";
+         SHIFTB_3 <= "00000000000000000000000000001000";
+         SHIFTB_4 <= "00000000000000000000000000010000";
+         SHIFTB_5 <= "00000000000000000000000000100000";
+         SHIFTB_6 <= "00000000000000000000000001000000";
+         SHIFTB_7 <= "00000000000000000000000010000000";
+      else
+         SHIFTB_0 <= "11111111111111011111111111111110";
+         SHIFTB_1 <= "11111111111101111111111111111011";
+         SHIFTB_2 <= "11111111110111111111111111101111";
+         SHIFTB_3 <= "11111111011111111111111110111111";
+         SHIFTB_4 <= "11111101111111111111111011111111";
+         SHIFTB_5 <= "11110111111111111111101111111111";
+         SHIFTB_6 <= "11011111111111111110111111111111";
+         SHIFTB_7 <= "01111111111111111011111111111111";
+      end if;
+   end process;
+   
+   xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
+      
+      process (clk_i)
+      begin
+         if (clk_i'event and clk_i = '1') then
+            if (rst_i = '1') then
+               w1data <= (others => '0');
+               ndata_rising <= '1';
+               shift_en <= '0';
+            elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
+               if (NUM_DQ_PINS = 16) then
+                  if (cmd_startC = '1') then
+                     case addr_i(4 downto 2) is
+                        when "000" =>
+                           w1data <= SHIFTB_0;
+                        when "001" =>
+                           w1data <= SHIFTB_1;
+                        when "010" =>
+                           w1data <= SHIFTB_2;
+                        when "011" =>
+                           w1data <= SHIFTB_3;
+                        when "100" =>
+                           w1data <= SHIFTB_4;
+                        when "101" =>
+                           w1data <= SHIFTB_5;
+                        when "110" =>
+                           w1data <= SHIFTB_6;
+                        
+                        when "111" =>
+                           w1data <= SHIFTB_7;
+                        when others =>
+                           w1data <= SHIFTB_0;
+                     end case;
+                     
+                     ndata_rising <= '0';               --(NUM_DQ_PINS == 16) (cmd_startC)  
+                  --shifting
+                  elsif (data_mode_i = "0100") then
+                     w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
+                  else
+                     
+                     w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14));              --(DQ_PINS == 16 
+                  end if;
+               elsif (NUM_DQ_PINS = 8) then
+                  if (cmd_startC = '1') then            -- loading data pattern according the incoming address
+                     case addr_i(2) is
+                        when '0' =>
+                           w1data <= SHIFTB_0;
+                        when '1' =>
+                           w1data <= SHIFTB_1;
+                        when others =>
+                           w1data <= SHIFTB_0;
+                     end case;
+                  else
+                     -- (cmd_startC)   
+                     -- Shifting
+                     -- need neigbour pattern ********************
+                     
+                     w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4));              --(NUM_DQ_PINS == 8)
+                  end if;
+               elsif (NUM_DQ_PINS = 4) then             -- NUM_DQ_PINS == 4   
+                  -- need neigbour pattern ********************      
+                  if (data_mode_i = "0100") then
+                     w1data <= "00001000000001000000001000000001";
+                  else
+                     w1data <= "10000100001000011000010000100001";              -- (NUM_DQ_PINS_4    
+                  end if;
+               end if;
+            end if;
+         end if;
+      end process;
+      
+      
+--      <outdent>               -- DWIDTH == 32
+      end generate;
+      
+      xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
+         
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+                  
+               w1data <= (others => '0');
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
+                  
+                  if (NUM_DQ_PINS = 16) then
+                     if (cmd_startC = '1') then
+                        
+                        
+                        case addr_i(4 downto 3) is
+                           --  7:0
+                           
+                           when "00" =>
+                              w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
+                           
+                           when "01" =>
+                              w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
+                           when "10" =>
+                              w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
+                           
+                           when "11" =>
+                              w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
+                           --15:8 
+                           
+                           when others =>
+                              w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
+                        end case;
+                     else
+                        
+                        --(NUM_DQ_PINS == 16) (cmd_startC)      
+                        --shifting
+                        if (data_mode_i = "0100") then
+                           w1data(63 downto 48) <= "0000000000000000";
+                           w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
+                           w1data(31 downto 16) <= "0000000000000000";
+                           
+                           w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
+                        else
+                           
+--                           w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
+                           w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
+                                                            w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
+                                                           w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
+                                                            w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
+                                                           w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
+                                                            w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
+                                                           w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
+                                                            w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
+                        end if;
+                     end if;
+                  
+                  --(DQ_PINS == 16 
+                  elsif (NUM_DQ_PINS = 8) then
+                     if (cmd_startC = '1') then         -- loading data pattern according the incoming address
+                        
+                        if (data_mode_i = "0100") then
+                           
+                           case addr_i(3) is
+                              
+                              when '0' =>
+                                 w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
+                              
+                              when '1' =>
+                                 w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
+                              --15:8 
+                              
+                              when others =>
+                                 w1data <= (others => '0');--"00000000000000000000000000000000";
+                           end case;
+                        else
+                           
+                           w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001");         --**** checked
+                           w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001");         --**** checked
+                           w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001");         --**** checked
+                        end if;
+                     -- Shifting
+                     elsif (data_mode_i = "0100") then
+                        
+                        w1data(63 downto 56) <= "00000000";
+                        
+                        w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
+                        w1data(47 downto 40) <= "00000000";
+                        
+                        w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
+                        w1data(31 downto 24) <= "00000000";
+                        
+                        w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
+                        w1data(15 downto 8) <= "00000000";
+                        
+                        w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
+                     else
+                        w1data <= w1data;               --(NUM_DQ_PINS == 8)
+                     end if;
+                  elsif (NUM_DQ_PINS = 4) then          -- NUM_DQ_PINS == 4   
+                     if (data_mode_i = "0100") then
+                        w1data <=  "0000100000000100000000100000000100001000000001000000001000000001";
+                     else
+                        
+                        w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
+                     end if;
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      
+      xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
+         
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+                  
+               w1data <= (others => '0');
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
+                  
+                  if (NUM_DQ_PINS = 16) then
+                     if (cmd_startC = '1') then
+                        
+                        case addr_i(4) is
+                           
+                           --  32                                       
+                           
+                           when '0' =>
+                              w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
+                              w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
+                              w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
+                           
+                           --  32                                       
+                           
+                           when '1' =>
+                              w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
+                              w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
+                              w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
+                              w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
+                           --15:8 
+                           
+                           when others =>
+                              w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
+                        end case;
+                     else
+                        
+                        --(NUM_DQ_PINS == 16) (cmd_startC)      
+                        --shifting
+                        if (data_mode_i = "0100") then
+                           w1data(127 downto 112) <= "0000000000000000";
+                           w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
+                           w1data(95 downto 80) <= "0000000000000000";
+                           
+                           w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
+                           w1data(63 downto 48) <= "0000000000000000";
+                           w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
+                           w1data(31 downto 16) <= "0000000000000000";
+                           
+                           w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
+                        else
+                           
+                           w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
+                        end if;
+                     end if;
+                  
+                  --(DQ_PINS == 16 
+                  elsif (NUM_DQ_PINS = 8) then
+                     if (cmd_startC = '1') then         -- loading data pattern according the incoming address
+                        if (data_mode_i = "0100") then
+                           w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
+                        else
+                           
+                           w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0);           -- (cmd_startC) 
+                        end if;
+                     else
+                        -- Shifting
+                        
+                        --{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]}; 
+                        w1data <= w1data;               -- else
+                     end if;
+                  --(NUM_DQ_PINS == 8)
+                  elsif (data_mode_i = "0100") then
+                     w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
+                  else
+                     
+                     w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      -- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins 
+      --                 => the rsing data pattern will be    32'b11111111_11111111_11111111_11111111
+      --                 => the falling data pattern will be  32'b00000000_00000000_00000000_00000000
+      xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+                  hdata <= (others => '0');
+--               elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
+
+                  if (NUM_DQ_PINS = 16) then
+                     hdata <= "00000000000000001111111111111111";
+                  elsif (NUM_DQ_PINS = 8) then
+                     hdata <= "00000000111111110000000011111111";               -- NUM_DQ_PINS == 4    
+                  elsif (NUM_DQ_PINS = 4) then
+                     hdata <= "00001111000011110000111100001111";
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+               hdata <= (others => '0');
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
+                  if (NUM_DQ_PINS = 16) then
+                  hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
+                  elsif (NUM_DQ_PINS = 8) then
+                  hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
+                  elsif (NUM_DQ_PINS = 4) then
+                     
+                  hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (rst_i = '1') then
+               hdata <= (others => '0');
+               elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
+                  if (NUM_DQ_PINS = 16) then
+                  hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
+                  elsif (NUM_DQ_PINS = 8) then
+                  hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
+                  elsif (NUM_DQ_PINS = 4) then
+                     
+                  hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
+                  end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      process (w1data, hdata)
+      begin
+         for i in 0 to  DWIDTH - 1 loop
+            
+            ndata(i) <= hdata(i) xor w1data(i);
+         end loop;
+      end process;
+      
+      
+      -- HAMMER_PATTERN_MINUS: generate walking HAMMER  data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine 
+      -- the position of the pin driving oppsite polarity
+      --  addr_i[6:2] = 5'h0f ; 32 bit data port
+      --                 => the rsing data pattern will be    32'b11111111_11111111_01111111_11111111
+      --                 => the falling data pattern will be  32'b00000000_00000000_00000000_00000000
+      
+      -- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
+      -- Dataport 32 bit width with starting addr_i  = 30'h12345678, user burst length 4
+      --                 => the 1st data pattern :     32'h12345678
+      --                 => the 2nd data pattern :     32'h12345679
+      --                 => the 3rd data pattern :     32'h1234567a
+      --                 => the 4th data pattern :     32'h1234567b
+      
+      --data_rdy_i
+      
+      xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
+         --data_o logic
+         process (clk_i)
+         begin
+            if (clk_i'event and clk_i = '1') then
+               if (cmd_startD = '1') then
+                  adata <= addr_i;
+               elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
+                 if (DWIDTH = 128) then
+                    adata <= adata + "00000000000000000000000000010000";
+                 elsif (DWIDTH = 64) then
+                    adata <= adata + "00000000000000000000000000001000";               -- DWIDTH == 32   
+                 else
+                  adata <= adata + "00000000000000000000000000000100";
+                 end if;
+               end if;
+            end if;
+         end process;
+         
+      end generate;
+      
+      -- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
+      -- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
+      --                
+      
+      xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
+         
+         --   PRBS DATA GENERATION
+         -- xor all the tap positions before feedback to 1st stage.
+         
+--         data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
+           data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';         
+         
+         
+         data_prbs_gen_inst : data_prbs_gen
+            generic map (
+               prbs_width  => 32,
+               seed_width  => 32
+            )
+            port map (
+               clk_i           => clk_i,
+               clk_en          => data_clk_en,
+               rst_i           => rst_i,
+               prbs_fseed_i    => prbs_fseed_i,
+               prbs_seed_init  => cmd_startE,
+               prbs_seed_i     => addr_i(31 downto 0),
+               prbs_o          => prbs_data
+            );
+         
+      end generate;
+      
+      
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/tg_status.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/tg_status.vhd
new file mode 100755
index 0000000..ec3aa9d
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/tg_status.vhd
@@ -0,0 +1,142 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: tg_status.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:42 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:  This module compare the memory read data agaisnt compare data that generated from data_gen module.
+--          Error signal will be asserted if the comparsion is not equal.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+entity tg_status is
+   generic (
+      TCQ             : TIME   := 100 ps;
+      DWIDTH                         : integer := 32
+   );
+   port (
+      
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic;
+      manual_clear_error             : in std_logic;
+      data_error_i                   : in std_logic;
+      cmp_data_i                     : in std_logic_vector(DWIDTH - 1 downto 0);
+      rd_data_i                      : in std_logic_vector(DWIDTH - 1 downto 0);
+      cmp_addr_i                     : in std_logic_vector(31 downto 0);
+      cmp_bl_i                       : in std_logic_vector(5 downto 0);
+      mcb_cmd_full_i                 : in std_logic;
+      mcb_wr_full_i                  : in std_logic;
+      mcb_rd_empty_i                 : in std_logic;
+      error_status                   : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
+      error                          : out std_logic
+   );
+end entity tg_status;
+
+architecture trans of tg_status is
+   
+   signal data_error_r             : std_logic;
+   signal error_set                : std_logic;
+begin
+   error <= error_set;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         
+         data_error_r <= data_error_i;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         
+         if ((rst_i or manual_clear_error) = '1') then
+--            error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
+              error_status <= (others => '0');
+            error_set <= '0';
+         else
+            -- latch the first error only
+            if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
+               error_status(31 downto 0) <= cmp_addr_i;
+               error_status(37 downto 32) <= cmp_bl_i;
+               error_status(40) <= mcb_cmd_full_i;
+               error_status(41) <= mcb_wr_full_i;
+               error_status(42) <= mcb_rd_empty_i;
+               error_set <= '1';
+               error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
+               
+               error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
+            end if;
+            
+            error_status(39 downto 38) <= "00";		-- reserved
+            
+            error_status(63 downto 43) <= "000000000000000000000";		-- reserved
+         end if;
+      end if;
+   end process;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/v6_data_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/v6_data_gen.vhd
new file mode 100755
index 0000000..34b1766
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/v6_data_gen.vhd
@@ -0,0 +1,3276 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor             : Xilinx
+-- \   \   \/     Version            : %version
+--  \   \         Application        : MIG
+--  /   /         Filename           : v6_data_gen.vhd
+-- /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:43 $
+-- \   \  /  \    Date Created       : Jul 03 2009
+--  \___\/\___\
+--
+-- Device       : Virtex6
+-- Design Name  : DDR2/DDR3
+-- Purpose      : This module generates different data pattern as described in
+--                parameter DATA_PATTERN and is set up for Virtex 6 family.
+-- Reference    :
+-- Revision History:
+--*****************************************************************************
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity v6_data_gen is
+   generic (
+      EYE_TEST        : string := "FALSE";
+      ADDR_WIDTH      : integer := 32;
+      MEM_BURST_LEN   : integer := 8;
+      BL_WIDTH        : integer := 6;
+      DWIDTH          : integer := 288;
+      DATA_PATTERN    : string := "DGEN_ALL"; --"DGEN_HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
+      NUM_DQ_PINS     : integer := 72;
+      COLUMN_WIDTH    : integer := 10;
+      SEL_VICTIM_LINE : integer := 3 -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+   );
+   port (
+      clk_i           : in std_logic;
+      rst_i           : in std_logic;
+      prbs_fseed_i    : in std_logic_vector(31 downto 0);
+      data_mode_i     : in std_logic_vector(3 downto 0);
+      data_rdy_i      : in std_logic;
+      cmd_startA      : in std_logic;
+      cmd_startB      : in std_logic;
+      cmd_startC      : in std_logic;
+      cmd_startD      : in std_logic;
+      cmd_startE      : in std_logic;
+      m_addr_i        : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      fixed_data_i    : in std_logic_vector(DWIDTH-1 downto 0);
+      addr_i          : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      user_burst_cnt  : in std_logic_vector(6 downto 0);
+      fifo_rdy_i      : in std_logic;
+      data_o          : out std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0)
+   );
+end entity v6_data_gen;
+
+architecture trans of v6_data_gen is
+
+component data_prbs_gen is
+   generic (
+      EYE_TEST        : string := "FALSE";
+      PRBS_WIDTH      : integer := 32;
+      SEED_WIDTH      : integer := 32
+     );
+   port (
+      clk_i           : in std_logic;
+      clk_en          : in std_logic;
+      rst_i           : in std_logic;
+      prbs_fseed_i    : in std_logic_vector(31 downto 0);
+      prbs_seed_init  : in std_logic;
+      prbs_seed_i     : in std_logic_vector(PRBS_WIDTH - 1 downto 0);
+
+      prbs_o          : out std_logic_vector(PRBS_WIDTH - 1 downto 0)
+   );
+end component;
+
+   constant ALL_0               : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0) := (others => '0');
+   signal prbs_data             : std_logic_vector(31 downto 0);
+   signal acounts               : std_logic_vector(35 downto 0);
+   signal adata                 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal hdata                 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal ndata                 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal w1data                : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal w0data                : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal data                  : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal tstpts                : std_logic_vector(7 downto 0);
+   signal burst_count_reached2  : std_logic;
+   signal data_valid            : std_logic;
+   signal walk_cnt              : std_logic_vector(2 downto 0);
+   signal user_address          : std_logic_vector(ADDR_WIDTH - 1 downto 0);
+   signal sel_w1gen_logic       : std_logic;
+   --signal BLANK                 : std_logic_vector(7 downto 0);
+   --signal SHIFT_0               : std_logic_vector(7 downto 0);
+   --signal SHIFT_1               : std_logic_vector(7 downto 0);
+   --signal SHIFT_2               : std_logic_vector(7 downto 0);
+   --signal SHIFT_3               : std_logic_vector(7 downto 0);
+   --signal SHIFT_4               : std_logic_vector(7 downto 0);
+   --signal SHIFT_5               : std_logic_vector(7 downto 0);
+   --signal SHIFT_6               : std_logic_vector(7 downto 0);
+   --signal SHIFT_7               : std_logic_vector(7 downto 0);
+   signal sel_victimline_r      : std_logic_vector(4 * NUM_DQ_PINS - 1 downto 0);
+   signal data_clk_en           : std_logic;
+   signal full_prbs_data        : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal h_prbsdata            : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+   signal i                     : integer;
+   signal j                     : integer;
+
+   signal data_mode_rr_a        : std_logic_vector(3 downto 0);
+   signal data_mode_rr_b        : std_logic_vector(3 downto 0);
+   signal data_mode_rr_c        : std_logic_vector(3 downto 0);
+   signal prbs_seed_i           : std_logic_vector(31 downto 0);
+
+  function concat ( in1 : integer;
+                    in2 : std_logic_vector) return std_logic_vector is
+  variable rang : integer := in2'length;
+  variable temp : std_logic_vector(in1*rang-1 downto 0);
+  begin
+    for i in 0 to in1-1 loop
+      temp(rang*(i+1)-1 downto rang*i) := in2;
+    end loop;
+
+  return temp;
+  end function;
+
+
+  function Data_Gen ( int       : integer
+                     ) return std_logic_vector is
+
+    variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
+    variable j : integer;
+  begin
+    j := int/2;
+      if((int mod 2) = 1) then
+
+       data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00010000";
+       data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00100000";
+       data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "01000000";
+       data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "10000000";
+     else
+       data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "00000001";
+       data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "00000010";
+       data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "00000100";
+       data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "00001000";
+     end if;
+
+
+
+    return data_bus;
+  end function;
+
+  function Data_GenW0 ( int       : integer) return std_logic_vector is
+
+    variable data_bus : std_logic_vector(4*NUM_DQ_PINS-1 downto 0) := (others => '0');
+    variable j : integer;
+  begin
+    j := int/2;
+      if((int mod 2) = 1) then
+        data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11101111";
+        data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11011111";
+        data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "10111111";
+        data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "01111111";
+      else
+        data_bus((0*NUM_DQ_PINS+j*8)+7 downto (0*NUM_DQ_PINS+j*8)) := "11111110";
+        data_bus((1*NUM_DQ_PINS+j*8)+7 downto (1*NUM_DQ_PINS+j*8)) := "11111101";
+        data_bus((2*NUM_DQ_PINS+j*8)+7 downto (2*NUM_DQ_PINS+j*8)) := "11111011";
+        data_bus((3*NUM_DQ_PINS+j*8)+7 downto (3*NUM_DQ_PINS+j*8)) := "11110111";
+      end if;
+
+    return data_bus;
+  end function;
+
+  
+
+begin
+   data_o         <= data;
+   full_prbs_data <= concat(DWIDTH/32,prbs_data);
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         data_mode_rr_a <= data_mode_i;
+         data_mode_rr_b <= data_mode_i;
+         data_mode_rr_c <= data_mode_i;
+      end if;
+   end process;
+
+
+   process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
+   begin
+      case data_mode_rr_a is
+         when "0000" =>
+            data <= h_prbsdata;
+         when "0001" =>     --  "0001" = fixed data
+            data <= fixed_data_i;
+         when "0010" =>     --  "0010" = address as data
+            data <= adata;
+         when "0011" =>     --  "0011" = hammer
+            data <= hdata;
+         when "0100" =>     --  "0100" = neighbour
+            data <= ndata;
+         when "0101" =>     --  "0101" = walking 1's
+            data <= w1data;
+            
+         when "0110" =>     --  "0110" = walking 0's
+            data <= w1data;
+         when "0111" =>     --  "0111" = prbs
+            data <= full_prbs_data;
+         when others =>
+            data <= (others => '0');
+      end case;
+   end process;
+
+--   process (data_mode_rr_a, h_prbsdata, fixed_data_i, adata, hdata, ndata, w1data, full_prbs_data)
+--   begin
+--      case data_mode_rr_a is
+--         when "0000" =>
+--            data <= h_prbsdata;
+--         when "0001" =>     --  "0001" = fixed data
+--             data <= fixed_data_i;
+--         when "0010" =>     --  "0010" = address as data
+--            data <= adata;
+--         when "0011" =>     --  "0011" = hammer
+--            data <= hdata;
+--         when "0100" =>     --  "0100" = neighbour
+--            data <= ndata;
+--         when "0111" =>     --  "0111" = prbs
+--            data <= full_prbs_data;
+--         when others =>
+--            data <= w1data;
+--      end case;
+--   end process;
+
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (data_mode_rr_c(2 downto 0) = "101" or data_mode_rr_c(2 downto 0) = "100" or data_mode_rr_c(2 downto 0) = "110") then -- WALKING PATTERN
+            sel_w1gen_logic <= '1';
+         else
+            sel_w1gen_logic <= '0';
+         end if;
+      end if;
+   end process;
+
+   WALKING_ONE_8_PATTERN : if (NUM_DQ_PINS = 8 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if (fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(3) is
+
+                 when '0' =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                   else
+                       w1data <= Data_GenW0(0);
+                   end if;
+                 when '1' =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                   else
+                       w1data <= Data_GenW0(1);
+                   end if;
+                 when others =>
+                   w1data <= (others => '0');
+
+                 end case;
+               end if;
+             elsif (MEM_BURST_LEN = 8) then
+               w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+               w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+               w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+               w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+             end if;
+           end if;
+         end if;
+       end process;
+     end generate;
+
+   WALKING_ONE_16_PATTERN : if (NUM_DQ_PINS = 16 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(4 downto 3) is
+
+                 when "00" =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                   else
+                       w1data <= Data_GenW0(0);
+                   end if;
+
+                 when "01" =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                   else
+                       w1data <= Data_GenW0(1);
+                   end if;
+
+                 when "10" =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                   else
+                       w1data <= Data_GenW0(2);
+                   end if;
+
+                 when "11" =>
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                   else
+                       w1data <= Data_GenW0(3);
+                   end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_24_PATTERN : if (NUM_DQ_PINS = 24 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(7 downto 3) is
+
+                 when "00000" | "00110" | "01100" |
+                      "10010" | "11000" | "11110" =>
+            --       when  "10010" | "11000"=> 
+   
+                   if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                   else
+                       w1data <= Data_GenW0(0);
+                   end if;
+
+                when "00001" | "00111" | "01101" |
+                     "10011" | "11001" | "11111" =>
+                  if (data_mode_i = "0101") then
+                      w1data <= Data_Gen(1);
+                  else
+                      w1data <= Data_GenW0(1);
+                  end if;
+
+                 when "00010" | "01000" | "01110" |  --2,8,14,20,26  
+                      "10100" | "11010"           =>
+ 
+                   if (data_mode_i = "0101") then
+                         w1data <= Data_Gen(2);
+                   else
+                       w1data <= Data_GenW0(2);
+                   end if;
+
+                 when "00011" | "01001" | "01111" |  --3,9,15,21,27
+                    "10101" | "11011"           =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+
+               when "00100" | "01010" | "10000" |
+                    "10110" | "11100"           =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+               when "00101" | "01011" | "10001" |
+                    "10111" | "11101"           =>
+                  
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(5);
+                 end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;  -- cmd_startC
+         end if; --if ( fifo_rdy_i = '1' or cmd_startC = '1')
+       end if;  -- clk
+     end process;
+   end generate;
+
+   WALKING_ONE_32_PATTERN : if (NUM_DQ_PINS = 32 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(6 downto 4) is
+
+                 when "000" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                 else
+                     w1data <= Data_GenW0(0);
+                 end if;
+
+                 when "001" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                 else
+                     w1data <= Data_GenW0(1);
+                 end if;
+
+                 when "010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                 else
+                     w1data <= Data_GenW0(2);
+                 end if;
+
+                 when "011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+
+                 when "100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+                 when "101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(5);
+                 end if;
+
+                 when "110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(6);
+                 else
+                     w1data <= Data_GenW0(6);
+                 end if;
+
+                 when "111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(7);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+--
+   WALKING_ONE_40_PATTERN : if (NUM_DQ_PINS = 40 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(7 downto 4) is
+
+                 when "0000" | "1010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                 else
+                     w1data <= Data_GenW0(0);
+                 end if;
+
+                 when "0001" | "1011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                 else
+                     w1data <= Data_GenW0(1);
+                 end if;
+
+                 when "0010" | "1100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                 else
+                     w1data <= Data_GenW0(2);
+                 end if;
+
+                 when "0011" | "1101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+
+                 when "0100" | "1110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+                 when "0101" | "1111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when "0110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(6);
+                 else
+                     w1data <= Data_GenW0(6);
+                 end if;
+
+                 when "0111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(7);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when "1000" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(8);
+                 else
+                     w1data <= Data_GenW0(8);
+                 end if;
+
+                 when "1001" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(9);
+                 else
+                     w1data <= Data_GenW0(9);
+                 end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_48_PATTERN : 
+   if (NUM_DQ_PINS = 48 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(7 downto 4) is
+
+                 when "0000" | "1100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                 else
+                     w1data <= Data_GenW0(0);
+                 end if;
+
+                 when "0001" | "1101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                 else
+                     w1data <= Data_GenW0(1);
+                 end if;
+
+                 when "0010" | "1110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                 else
+                     w1data <= Data_GenW0(2);
+                 end if;
+
+                 when "0011" | "1111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+
+                 when "0100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+                 when "0101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(5);
+                 end if;
+
+                 when "0110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(6);
+                 else
+                     w1data <= Data_GenW0(6);
+                 end if;
+
+                 when "0111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(7);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when "1000" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(8);
+                 else
+                     w1data <= Data_GenW0(8);
+                 end if;
+
+                 when "1001" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(9);
+                 else
+                     w1data <= Data_GenW0(9);
+                 end if;
+
+                 when "1010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(10);
+                 else
+                     w1data <= Data_GenW0(10);
+                 end if;
+
+                 when "1011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(11);
+                 else
+                     w1data <= Data_GenW0(11);
+                 end if;
+--
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+
+WALKING_ONE_56_PATTERN:
+    if (NUM_DQ_PINS = 56 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(8 downto 5) is
+
+                 when "0000" | "1110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(0);
+                 else
+                     w1data <= Data_GenW0(0);
+                 end if;
+
+
+                 when "0001" | "1111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(1);
+                 else
+                     w1data <= Data_GenW0(1);
+                 end if;
+
+
+                 when "0010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(2);
+                 else
+                     w1data <= Data_GenW0(2);
+                 end if;
+
+
+                 when "0011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(3);
+                 else
+                     w1data <= Data_GenW0(3);
+                 end if;
+                 when "0100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(4);
+                 else 
+                     w1data <= Data_GenW0(4);
+                 end if;
+
+                 when "0101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(5);
+                 else
+                     w1data <= Data_GenW0(5);
+                 end if;
+
+                 when "0110" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(6);
+                 else 
+                     w1data <= Data_GenW0(6);
+                 end if;
+
+                 when "0111" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(7);
+                 else
+                     w1data <= Data_GenW0(7);
+                 end if;
+
+                 when "1000" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(8);
+                 else
+                     w1data <= Data_GenW0(8);
+                 end if;
+
+                 when "1001" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(9);
+                 else
+                     w1data <= Data_GenW0(9);
+                 end if;
+
+                 when "1010" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(10);
+                 else
+                     w1data <= Data_GenW0(10);
+                 end if;
+                 when "1011" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(11);
+                 else
+                     w1data <= Data_GenW0(11);
+                 end if;
+
+                 when "1100" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(12);
+                 else
+                     w1data <= Data_GenW0(12);
+                 end if;
+
+                 when "1101" =>
+                 if (data_mode_i = "0101") then
+                       w1data <= Data_Gen(13);
+                 else
+                     w1data <= Data_GenW0(13);
+                 end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+--
+WALKING_ONE_64_PATTERN :
+if (NUM_DQ_PINS = 64 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(8 downto 5) is
+
+                 when "0000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(0);
+                     else
+                         w1data <= Data_GenW0(0);
+                     end if;
+
+                 when "0001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(1);
+                     else
+                         w1data <= Data_GenW0(1);
+                     end if;
+
+                 when "0010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(2);
+                     else
+                         w1data <= Data_GenW0(2);
+                     end if;
+
+                 when "0011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(3);
+                     else
+                         w1data <= Data_GenW0(3);
+                     end if;
+
+                 when "0100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(4);
+                     else
+                         w1data <= Data_GenW0(4);
+                     end if;
+
+                 when "0101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(5);
+                     else
+                         w1data <= Data_GenW0(5);
+                     end if;
+
+                 when "0110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(6);
+                     else
+                         w1data <= Data_GenW0(6);
+                     end if;
+
+                 when "0111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(7);
+                     else
+                         w1data <= Data_GenW0(7);
+                     end if;
+
+                 when "1000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(8);
+                     else
+                         w1data <= Data_GenW0(8);
+                     end if;
+
+                 when "1001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(9);
+                     else
+                         w1data <= Data_GenW0(9);
+                     end if;
+
+                 when "1010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(10);
+                     else
+                         w1data <= Data_GenW0(10);
+                     end if;
+
+                 when "1011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(11);
+                     else
+                         w1data <= Data_GenW0(11);
+                     end if;
+
+                 when "1100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(12);
+                     else
+                         w1data <= Data_GenW0(12);
+                     end if;
+
+                 when "1101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(13);
+                     else
+                         w1data <= Data_GenW0(13);
+                     end if;
+
+                 when "1110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(14);
+                     else
+                         w1data <= Data_GenW0(14);
+                     end if;
+
+                 when "1111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(15);
+                     else
+                         w1data <= Data_GenW0(15);
+                     end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+WALKING_ONE_72_PATTERN :
+   if (NUM_DQ_PINS = 72 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "10010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(0);
+                     else
+                         w1data <= Data_GenW0(0);
+                     end if;
+
+                 when "00001" | "10011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(1);
+                     else
+                         w1data <= Data_GenW0(1);
+                     end if;
+
+                 when "00010" | "10100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(2);
+                     else
+                         w1data <= Data_GenW0(2);
+                     end if;
+
+                 when "00011" | "10101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(3);
+                     else
+                         w1data <= Data_GenW0(3);
+                     end if;
+
+                 when "00100" | "10110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(4);
+                     else
+                         w1data <= Data_GenW0(4);
+                     end if;
+
+                 when "00101" | "10111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(5);
+                     else
+                         w1data <= Data_GenW0(5);
+                     end if;
+
+                 when "00110" | "11000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(6);
+                     else
+                         w1data <= Data_GenW0(6);
+                     end if;
+
+                 when "00111" | "11001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(7);
+                     else
+                         w1data <= Data_GenW0(7);
+                     end if;
+
+                 when "01000" | "11010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(8);
+                     else
+                         w1data <= Data_GenW0(8);
+                     end if;
+
+                 when "01001" | "11011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(9);
+                     else
+                         w1data <= Data_GenW0(9);
+                     end if;
+
+                 when "01010" |  "11100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(10);
+                     else
+                         w1data <= Data_GenW0(10);
+                     end if;
+
+                 when "01011" | "11101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(11);
+                     else
+                         w1data <= Data_GenW0(11);
+                     end if;
+
+                 when "01100" | "11110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(12);
+                     else
+                         w1data <= Data_GenW0(12);
+                     end if;
+
+                 when "01101" | "11111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(13);
+                     else
+                         w1data <= Data_GenW0(13);
+                     end if;
+
+                 when "01110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(14);
+                     else
+                         w1data <= Data_GenW0(14);
+                     end if;
+
+                 when "01111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(15);
+                     else
+                         w1data <= Data_GenW0(15);
+                     end if;
+
+                 when "10000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(16);
+                     else
+                         w1data <= Data_GenW0(16);
+                     end if;
+
+                 when "10001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(17);
+                     else
+                         w1data <= Data_GenW0(17);
+                     end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+WALKING_ONE_80_PATTERN :
+
+   if (NUM_DQ_PINS = 80 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "10100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(0);
+                     else
+                         w1data <= Data_GenW0(0);
+                     end if;
+
+                 when "00001" | "10101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(1);
+                     else
+                         w1data <= Data_GenW0(1);
+                     end if;
+
+                 when "00010" | "10110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(2);
+                     else
+                         w1data <= Data_GenW0(2);
+                     end if;
+
+                 when "00011" | "10111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(3);
+                     else
+                         w1data <= Data_GenW0(3);
+                     end if;
+
+                 when "00100" | "11000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(4);
+                     else
+                         w1data <= Data_GenW0(4);
+                     end if;
+
+                 when "00101" | "11001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(5);
+                     else
+                         w1data <= Data_GenW0(5);
+                     end if;
+
+                 when "00110" | "11010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(6);
+                     else
+                         w1data <= Data_GenW0(6);
+                     end if;
+
+                 when "00111" | "11011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(7);
+                     else
+                         w1data <= Data_GenW0(7);
+                     end if;
+
+                 when "01000" | "11100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(8);
+                     else
+                         w1data <= Data_GenW0(8);
+                     end if;
+
+                 when "01001" | "11101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(9);
+                     else
+                         w1data <= Data_GenW0(9);
+                     end if;
+
+                 when "01010" |  "11110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(10);
+                     else
+                         w1data <= Data_GenW0(10);
+                     end if;
+
+                 when "01011" | "11111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(11);
+                     else
+                         w1data <= Data_GenW0(11);
+                     end if;
+
+                 when "01100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(12);
+                     else
+                         w1data <= Data_GenW0(12);
+                     end if;
+
+                 when "01101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(13);
+                     else
+                         w1data <= Data_GenW0(13);
+                     end if;
+
+                 when "01110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(14);
+                     else
+                         w1data <= Data_GenW0(14);
+                     end if;
+
+                 when "01111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(15);
+                     else
+                         w1data <= Data_GenW0(15);
+                     end if;
+
+                 when "10000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(16);
+                     else
+                         w1data <= Data_GenW0(16);
+                     end if;
+
+                 when "10001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(17);
+                     else
+                         w1data <= Data_GenW0(17);
+                     end if;
+
+                 when "10010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(18);
+                     else
+                         w1data <= Data_GenW0(18);
+                     end if;
+
+                 when "10011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(19);
+                     else
+                         w1data <= Data_GenW0(19);
+                     end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+WALKING_ONE_88_PATTERN:
+     if (NUM_DQ_PINS = 88 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" | "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" | "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" | "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" | "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" | "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" | "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+
+WALKING_ONE_96_PATTERN:
+     if (NUM_DQ_PINS = 96 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" | "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" | "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" | "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" | "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else 
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_104_PATTERN:
+     if (NUM_DQ_PINS = 104 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" | "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" | "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+
+                 when "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_112_PATTERN:
+      if (NUM_DQ_PINS = 112 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+
+                 when "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+
+                 when "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+
+                 when "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_120_PATTERN:
+      if (NUM_DQ_PINS = 120 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(9 downto 5) is
+
+                 when "00000" | "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" | "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if; 
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+
+                 when "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+
+                 when "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+
+                 when "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+
+                 when "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(28);
+                       else
+                           w1data <= Data_GenW0(28);
+                       end if;
+
+                 when "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(29);
+                       else
+                           w1data <= Data_GenW0(29);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_128_PATTERN:
+     if (NUM_DQ_PINS = 128 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(10 downto 6) is
+
+                 when "00000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "00001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "00010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "00011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "00100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "00101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "00110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+
+                 when "00111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+
+                 when "01000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+
+                 when "01001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+
+                 when "01010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+
+                 when "01011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+
+                 when "01100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+
+                 when "01101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+
+                 when "01110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+
+                 when "01111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+
+                 when "10000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(16);
+                       else
+                           w1data <= Data_GenW0(16);
+                       end if;
+
+                 when "10001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(17);
+                       else
+                           w1data <= Data_GenW0(17);
+                       end if;
+
+                 when "10010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(18);
+                       else
+                           w1data <= Data_GenW0(18);
+                       end if;
+
+                 when "10011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(19);
+                       else
+                           w1data <= Data_GenW0(19);
+                       end if;
+
+                 when "10100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(20);
+                       else
+                           w1data <= Data_GenW0(20);
+                       end if;
+
+                 when "10101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(21);
+                       else
+                           w1data <= Data_GenW0(21);
+                       end if;
+
+                 when "10110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(22);
+                       else
+                           w1data <= Data_GenW0(22);
+                       end if;
+
+                 when "10111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+
+                 when "11000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+
+                 when "11001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+
+                 when "11010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+
+                 when "11011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+
+                 when "11100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(28);
+                       else
+                           w1data <= Data_GenW0(28);
+                       end if;
+
+                 when "11101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(29);
+                       else
+                           w1data <= Data_GenW0(29);
+                       end if;
+
+                 when "11110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(30);
+                       else
+                           w1data <= Data_GenW0(30);
+                       end if;
+
+                 when "11111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(31);
+                       else
+                           w1data <= Data_GenW0(31);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_136_PATTERN:
+     if (NUM_DQ_PINS = 136 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(11 downto 6) is
+
+                 when "000000"  =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+               when "000001" | "100011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(1);
+                     else
+                         w1data <= Data_GenW0(1);
+                     end if;
+
+               when "000010" | "100100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(2);
+                     else
+                         w1data <= Data_GenW0(2);
+                     end if;
+           
+               when "000011" | "100101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(3);
+                     else
+                         w1data <= Data_GenW0(3);
+                     end if;
+           
+               when "000100" | "100110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(4);
+                     else 
+                         w1data <= Data_GenW0(4);
+                     end if;
+           
+               when "000101" | "100111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(5);
+                     else
+                         w1data <= Data_GenW0(5);
+                     end if;
+           
+               when "000110" | "101000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(6);
+                     else
+                         w1data <= Data_GenW0(6);
+                     end if;
+           
+               when "000111" | "101001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(7);
+                     else
+                         w1data <= Data_GenW0(7);
+                     end if;
+           
+               when "001000" | "101010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(8);
+                     else
+                         w1data <= Data_GenW0(8);
+                     end if;
+           
+                 when "001001" | "101011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+           
+                 when "001010" | "101100" =>
+                       if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(10);
+                     else
+                         w1data <= Data_GenW0(10);
+                     end if;
+           
+               when "001011" | "101101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(11);
+                     else
+                         w1data <= Data_GenW0(11);
+                     end if;
+           
+               when "001100" | "101110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(12);
+                     else
+                         w1data <= Data_GenW0(12);
+                     end if;
+           
+               when "001101" | "101111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(13);
+                     else
+                         w1data <= Data_GenW0(13);
+                     end if;
+           
+               when "001110" | "110000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(14);
+                     else
+                         w1data <= Data_GenW0(14);
+                     end if;
+           
+               when "001111" | "110001" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(15);
+                     else
+                         w1data <= Data_GenW0(15);
+                     end if;
+           
+               when "010000" | "110010" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(16);
+                     else
+                         w1data <= Data_GenW0(16);
+                     end if;
+           
+               when "010001" | "110011" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(17);
+                     else
+                         w1data <= Data_GenW0(17);
+                     end if;
+           
+               when "010010" | "110100" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(18);
+                     else
+                         w1data <= Data_GenW0(18);
+                     end if;
+           
+               when "010011" | "110101" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(19);
+                     else
+                         w1data <= Data_GenW0(19);
+                     end if;
+           
+               when "010100" | "110110" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(20);
+                     else
+                         w1data <= Data_GenW0(20);
+                     end if;
+           
+               when "010101" | "110111" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(21);
+                     else
+                         w1data <= Data_GenW0(21);
+                     end if;
+           
+               when "010110" | "111000" =>
+                     if (data_mode_i = "0101") then
+                           w1data <= Data_Gen(22);
+                     else
+                         w1data <= Data_GenW0(22);
+                     end if;
+           
+               when "010111" | "111001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(23);
+                       else
+                           w1data <= Data_GenW0(23);
+                       end if;
+        
+                 when "011000" | "111010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(24);
+                       else
+                           w1data <= Data_GenW0(24);
+                       end if;
+        
+                 when "011001" | "111011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+        
+                 when "011010" | "111100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+        
+                 when "011011" | "111101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+        
+                 when "011100" | "111110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(28);
+                       else
+                           w1data <= Data_GenW0(28);
+                       end if;
+        
+                 when "011101" | "111111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(29);
+                       else
+                           w1data <= Data_GenW0(29);
+                       end if;
+        
+                 when "011110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(30);
+                       else
+                           w1data <= Data_GenW0(30);
+                       end if;
+        
+                 when "011111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(31);
+                       else
+                           w1data <= Data_GenW0(31);
+                       end if;
+        
+                 when "100000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(32);
+                       else
+                           w1data <= Data_GenW0(32);
+                       end if;
+        
+                 when "100001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(33);
+                       else
+                           w1data <= Data_GenW0(33);
+                       end if;
+
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+   WALKING_ONE_144_PATTERN:
+      if (NUM_DQ_PINS = 144 and (DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_NEIGHBOR" or DATA_PATTERN = "DGEN_ALL")) generate
+
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if ( fifo_rdy_i = '1' or cmd_startC = '1') then
+           if (cmd_startC = '1') then
+             if (sel_w1gen_logic = '1') then
+               case addr_i(11 downto 6) is
+
+                 when "000000" | "100100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(0);
+                       else
+                           w1data <= Data_GenW0(0);
+                       end if;
+
+                 when "000001" | "100101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(1);
+                       else 
+                           w1data <= Data_GenW0(1);
+                       end if;
+
+                 when "000010" | "100110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(2);
+                       else
+                           w1data <= Data_GenW0(2);
+                       end if;
+
+                 when "000011" | "100111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(3);
+                       else
+                           w1data <= Data_GenW0(3);
+                       end if;
+
+                 when "000100" | "101000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(4);
+                       else
+                           w1data <= Data_GenW0(4);
+                       end if;
+
+                 when "000101" | "101001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(5);
+                       else
+                           w1data <= Data_GenW0(5);
+                       end if;
+
+                 when "000110" | "101010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(6);
+                       else
+                           w1data <= Data_GenW0(6);
+                       end if;
+                 when "000111" | "101011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(7);
+                       else
+                           w1data <= Data_GenW0(7);
+                       end if;
+         
+                 when "001000" | "101100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(8);
+                       else
+                           w1data <= Data_GenW0(8);
+                       end if;
+         
+                 when "001001" | "101101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(9);
+                       else
+                           w1data <= Data_GenW0(9);
+                       end if;
+         
+                 when "001010" | "101110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(10);
+                       else
+                           w1data <= Data_GenW0(10);
+                       end if;
+         
+                 when "001011" | "101111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(11);
+                       else
+                           w1data <= Data_GenW0(11);
+                       end if;
+         
+                 when "001100" | "110000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(12);
+                       else
+                           w1data <= Data_GenW0(12);
+                       end if;
+         
+                 when "001101" | "110001" =>
+                     if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(13);
+                       else
+                           w1data <= Data_GenW0(13);
+                       end if;
+         
+                 when "001110" | "110010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(14);
+                       else
+                           w1data <= Data_GenW0(14);
+                       end if;
+         
+                 when "001111" | "110011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(15);
+                       else
+                           w1data <= Data_GenW0(15);
+                       end if;
+         
+                when "010000" | "110100" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(16);
+                      else
+                          w1data <= Data_GenW0(16);
+                      end if;
+         
+                when "010001" | "110101" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(17);
+                      else
+                          w1data <= Data_GenW0(17);
+                      end if;
+         
+                when "010010" | "110110" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(18);
+                      else
+                          w1data <= Data_GenW0(18);
+                      end if;
+         
+                when "010011" | "110111" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(19);
+                      else
+                          w1data <= Data_GenW0(19);
+                      end if;
+         
+                when "010100" | "111000" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(20);
+                      else
+                          w1data <= Data_GenW0(20);
+                      end if;
+         
+                when "010101" | "111001" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(21);
+                      else
+                          w1data <= Data_GenW0(21);
+                      end if;
+         
+                when "010110" | "111010" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(22);
+                      else
+                          w1data <= Data_GenW0(22);
+                      end if;
+         
+                when "010111" | "111011" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(23);
+                      else
+                          w1data <= Data_GenW0(23);
+                      end if;
+         
+                when "011000" | "111100" =>
+                      if (data_mode_i = "0101") then
+                            w1data <= Data_Gen(24);
+                      else
+                          w1data <= Data_GenW0(24);
+                      end if;
+         
+                 when "011001" | "111101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(25);
+                       else
+                           w1data <= Data_GenW0(25);
+                       end if;
+         
+                 when "011010" | "111110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(26);
+                       else
+                           w1data <= Data_GenW0(26);
+                       end if;
+         
+                 when "011011" | "111111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(27);
+                       else
+                           w1data <= Data_GenW0(27);
+                       end if;
+         
+                 when "011100" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(28);
+                       else
+                           w1data <= Data_GenW0(28);
+                       end if;
+         
+                 when "011101" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(29);
+                       else
+                           w1data <= Data_GenW0(29);
+                       end if;
+         
+                 when "011110" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(30);
+                       else
+                           w1data <= Data_GenW0(30);
+                       end if;
+         
+                 when "011111" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(31);
+                       else
+                           w1data <= Data_GenW0(31);
+                       end if;
+         
+                 when "100000" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(32);
+                       else
+                           w1data <= Data_GenW0(32);
+                       end if;
+         
+                 when "100001" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(33);
+                       else
+                           w1data <= Data_GenW0(33);
+                       end if;
+         
+                 when "100010" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(34);
+                       else
+                           w1data <= Data_GenW0(34);
+                       end if;
+         
+                 when "100011" =>
+                       if (data_mode_i = "0101") then
+                             w1data <= Data_Gen(35);
+                       else
+                           w1data <= Data_GenW0(35);
+                       end if;
+         
+                 when others =>
+                   w1data <= (others => '0');
+
+               end case;
+             end if;
+           elsif (MEM_BURST_LEN = 8) then
+             w1data(4 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS) <= (w1data(4 * NUM_DQ_PINS - 5 downto 3 * NUM_DQ_PINS) & w1data(4 * NUM_DQ_PINS - 1 downto 4 * NUM_DQ_PINS - 4));
+             w1data(3 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS) <= (w1data(3 * NUM_DQ_PINS - 5 downto 2 * NUM_DQ_PINS) & w1data(3 * NUM_DQ_PINS - 1 downto 3 * NUM_DQ_PINS - 4));
+             w1data(2 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS) <= (w1data(2 * NUM_DQ_PINS - 5 downto 1 * NUM_DQ_PINS) & w1data(2 * NUM_DQ_PINS - 1 downto 2 * NUM_DQ_PINS - 4));
+             w1data(1 * NUM_DQ_PINS - 1 downto 0 * NUM_DQ_PINS) <= (w1data(1 * NUM_DQ_PINS - 5 downto 0 * NUM_DQ_PINS) & w1data(1 * NUM_DQ_PINS - 1 downto 1 * NUM_DQ_PINS - 4));
+           end if;
+         end if;
+       end if;
+     end process;
+   end generate;
+
+
+   process (clk_i)
+   begin
+     if (clk_i'event and clk_i = '1') then
+       for i in 0 to  4 * NUM_DQ_PINS - 1 loop
+         if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
+           hdata(i) <= '1';
+         elsif (i >= 0 and i <= 1 * NUM_DQ_PINS - 1) then
+           hdata(i) <= '1';
+         elsif (i >= 1 * NUM_DQ_PINS and i <= 2 * NUM_DQ_PINS - 1) then
+           hdata(i) <= '0';
+         elsif (i >= 2 * NUM_DQ_PINS and i <= 3 * NUM_DQ_PINS - 1) then
+           hdata(i) <= '1';
+         elsif (i >= 3 * NUM_DQ_PINS and i <= 4 * NUM_DQ_PINS - 1) then
+           hdata(i) <= '0';
+         else
+           hdata(i) <= '1';
+         end if;
+       end loop;
+     end if;
+   end process;
+
+   process (w1data, hdata)
+   begin
+      for i in 0 to 4 * NUM_DQ_PINS - 1 loop
+         ndata(i) <= hdata(i) xor w1data(i);
+      end loop;
+   end process;
+
+   process (full_prbs_data, hdata)
+   begin
+     for i in 0 to  4 * NUM_DQ_PINS - 1 loop
+       if (i = SEL_VICTIM_LINE or (i - NUM_DQ_PINS) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 2)) = SEL_VICTIM_LINE or (i - (NUM_DQ_PINS * 3)) = SEL_VICTIM_LINE) then
+         h_prbsdata(i) <= full_prbs_data(SEL_VICTIM_LINE);
+       else
+         h_prbsdata(i) <= hdata(i);
+       end if;
+     end loop;
+   end process;
+
+   addr_pattern : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
+     process (clk_i)
+     begin
+       if (clk_i'event and clk_i = '1') then
+         if (cmd_startD = '1') then
+           acounts <= ("0000" & addr_i);
+         elsif (fifo_rdy_i = '1' and data_rdy_i = '1' and MEM_BURST_LEN = 8 ) then
+           if (NUM_DQ_PINS = 8 ) then
+             acounts <= acounts + X"000000004";
+           elsif (NUM_DQ_PINS = 16 and NUM_DQ_PINS < 32) then
+             acounts <= acounts + X"000000008";
+           elsif (NUM_DQ_PINS >= 32 and NUM_DQ_PINS < 64) then
+             acounts <= acounts +  X"000000010";
+           elsif (NUM_DQ_PINS >= 64 and NUM_DQ_PINS < 128) then
+             acounts <= acounts + X"000000020";
+           elsif (NUM_DQ_PINS >= 128 and NUM_DQ_PINS < 256) then
+             acounts <= acounts + X"000000040";
+           end if;
+         end if;
+       end if;
+     end process;
+
+     adata <= concat(DWIDTH/32,acounts(31 downto 0)); -- DWIDTH = 4 * NUM_DQ_PINS
+
+     end generate;
+
+     -- When doing eye_test, traffic gen only does write and want to
+     -- keep the prbs random and address is fixed at a location.
+     d_clk_en1 : if (EYE_TEST = "TRUE") generate
+        data_clk_en <= '1'; --fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
+     end generate;
+
+     d_clk_en2 : if (EYE_TEST = "FALSE") generate
+        data_clk_en <= (fifo_rdy_i and data_rdy_i) when (user_burst_cnt > "0000001") else '0';
+     end generate;
+
+     prbs_pattern : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
+
+        -- PRBS DATA GENERATION
+        -- xor all the tap positions before feedback to 1st stage.
+        prbs_seed_i <= (m_addr_i(6) & m_addr_i(31) & m_addr_i(8) & m_addr_i(22) & m_addr_i(9) & m_addr_i(24) & m_addr_i(21) & m_addr_i(23) & m_addr_i(18) & m_addr_i(10) & m_addr_i(20) & m_addr_i(17) & m_addr_i(13) & m_addr_i(16) & m_addr_i(12) & m_addr_i(4) & m_addr_i(15 downto 0)); --(m_addr_i[31:0]),
+
+        data_prbs_gen_inst : data_prbs_gen
+           generic map (
+              PRBS_WIDTH  => 32,
+              SEED_WIDTH  => 32,
+              EYE_TEST    => EYE_TEST
+           )
+           port map (
+              clk_i           => clk_i,
+              rst_i           => rst_i,
+              clk_en          => data_clk_en,
+              prbs_fseed_i    => prbs_fseed_i,
+              prbs_seed_init  => cmd_startE,
+              prbs_seed_i     => prbs_seed_i,
+              prbs_o          => prbs_data
+           );
+
+     end generate;
+
+end architecture trans;
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/wr_data_gen.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/wr_data_gen.vhd
new file mode 100755
index 0000000..e2c40d2
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/wr_data_gen.vhd
@@ -0,0 +1,511 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: wr_data_gen.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose:
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+library ieee;
+   use ieee.std_logic_1164.all;
+   use ieee.std_logic_unsigned.all;
+   use ieee.numeric_std.all;
+
+entity wr_data_gen is
+   generic (
+      
+      TCQ                            : TIME   := 100 ps;
+      FAMILY                         : string := "SPARTAN6";            -- "SPARTAN6", "VIRTEX6"
+      MEM_BURST_LEN                  : integer := 8;
+      
+      MODE                           : string := "WR";          --"WR", "RD"
+      ADDR_WIDTH                     : integer := 32;
+      BL_WIDTH                       : integer := 6;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_PRBS";           --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      SEL_VICTIM_LINE                : integer := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+      
+      COLUMN_WIDTH                   : integer := 10;
+      EYE_TEST                       : string := "FALSE"
+   );
+   port (
+      
+      clk_i                          : in std_logic;            --
+      rst_i                          : in std_logic_vector(4 downto 0);
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      
+      data_mode_i                    : in std_logic_vector(3 downto 0);         -- "00" = bram; 
+      
+      cmd_rdy_o                      : out std_logic;           -- ready to receive command. It should assert when data_port is ready at the                                        // beginning and will be deasserted once see the cmd_valid_i is asserted. 
+      -- And then it should reasserted when 
+      -- it is generating the last_word.
+      cmd_valid_i                    : in std_logic;            -- when both cmd_valid_i and cmd_rdy_o is high, the command  is valid.
+      cmd_validB_i                   : in std_logic;
+      cmd_validC_i                   : in std_logic;
+      
+      last_word_o                    : out std_logic;
+      
+      --  input [5:0] port_data_counts_i,// connect to data port fifo counts
+--      m_addr_i                       : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+      fixed_data_i                   : in std_logic_vector(DWIDTH - 1 downto 0);  
+      addr_i                         : in std_logic_vector(ADDR_WIDTH - 1 downto 0);            -- generated address used to determine data pattern.
+      bl_i                           : in std_logic_vector(BL_WIDTH - 1 downto 0);              -- generated burst length for control the burst data
+      
+      data_rdy_i                     : in std_logic;            -- connect from mcb_wr_full when used as wr_data_gen
+      -- connect from mcb_rd_empty when used as rd_data_gen
+      -- When both data_rdy and data_valid is asserted, the ouput data is valid.
+      data_valid_o                   : out std_logic;           -- connect to wr_en or rd_en and is asserted whenever the 
+      -- pattern is available.
+      data_o                         : out std_logic_vector(DWIDTH - 1 downto 0);               -- generated data pattern   
+      data_wr_end_o                  : out std_logic
+   );
+end entity wr_data_gen;
+
+architecture trans of wr_data_gen is
+
+COMPONENT sp6_data_gen IS
+   GENERIC (
+      
+      ADDR_WIDTH      : INTEGER := 32;
+      BL_WIDTH        : INTEGER := 6;
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_PRBS";
+      NUM_DQ_PINS     : INTEGER := 8;
+      COLUMN_WIDTH    : INTEGER := 10
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      cmd_startA      : IN STD_LOGIC;
+      cmd_startB      : IN STD_LOGIC;
+      cmd_startC      : IN STD_LOGIC;
+      cmd_startD      : IN STD_LOGIC;
+      cmd_startE      : IN STD_LOGIC;
+      fixed_data_i    : IN std_logic_vector(DWIDTH - 1 downto 0);  
+      
+      addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      user_burst_cnt  : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
+      
+      fifo_rdy_i      : IN STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
+   );
+END COMPONENT;   
+
+COMPONENT v6_data_gen IS
+   GENERIC (
+      
+      ADDR_WIDTH      : INTEGER := 32;
+      BL_WIDTH        : INTEGER := 6;
+      MEM_BURST_LEN                  : integer := 8;
+
+      DWIDTH          : INTEGER := 32;
+      DATA_PATTERN    : STRING := "DGEN_PRBS";
+      NUM_DQ_PINS     : INTEGER := 8;
+      SEL_VICTIM_LINE : INTEGER := 3;
+      COLUMN_WIDTH    : INTEGER := 10;
+      EYE_TEST        : STRING  := "FALSE"
+   );
+   PORT (
+      
+      clk_i           : IN STD_LOGIC;
+      rst_i           : IN STD_LOGIC;
+      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      
+      data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      data_rdy_i      : IN STD_LOGIC;
+      cmd_startA      : IN STD_LOGIC;
+      cmd_startB      : IN STD_LOGIC;
+      cmd_startC      : IN STD_LOGIC;
+      cmd_startD      : IN STD_LOGIC;
+      fixed_data_i    : IN std_logic_vector(DWIDTH - 1 downto 0);  
+      cmd_startE      : IN STD_LOGIC;
+      m_addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+      user_burst_cnt  : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
+      
+      fifo_rdy_i      : IN STD_LOGIC;
+      data_o          : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
+   );
+END COMPONENT;      
+
+   signal data                          : std_logic_vector(DWIDTH - 1 downto 0);
+   
+   signal cmd_rdy                       : std_logic;
+   signal cmd_rdyB                      : std_logic;
+   signal cmd_rdyC                      : std_logic;
+   signal cmd_rdyD                      : std_logic;
+   signal cmd_rdyE                      : std_logic;
+   signal cmd_rdyF                      : std_logic;
+   signal cmd_start                     : std_logic;
+   signal cmd_startB                    : std_logic;
+   signal cmd_startC                    : std_logic;
+   signal cmd_startD                    : std_logic;
+   signal cmd_startE                    : std_logic;
+   signal cmd_startF                    : std_logic;
+   
+   signal burst_count_reached2          : std_logic;
+   
+   signal data_valid                    : std_logic;
+   signal user_burst_cnt                : std_logic_vector(6 downto 0);
+   signal walk_cnt                      : std_logic_vector(2 downto 0);
+   
+   signal fifo_not_full                 : std_logic;
+   signal i                             : integer;
+   signal j                             : integer;
+   signal w3data                        : std_logic_vector(31 downto 0);
+   
+   -- counter to count user burst length
+   
+   -- bl_i;
+   
+   signal u_bcount_2                    : std_logic;
+   signal last_word_t                   : std_logic;
+   
+   -- Declare intermediate signals for referenced outputs
+   signal last_word_o_xhdl1             : std_logic;
+   signal data_o_xhdl0                  : std_logic_vector(DWIDTH - 1 downto 0);
+   signal tpt_hdata_xhdl2               : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
+begin
+   -- Drive referenced outputs
+   last_word_o <= last_word_o_xhdl1;
+   data_o <= data_o_xhdl0;
+   fifo_not_full <= data_rdy_i;
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
+            data_wr_end_o <= '1';
+         else
+            data_wr_end_o <= '0';
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         cmd_start <= cmd_validC_i and cmd_rdyC;
+         cmd_startB <= cmd_valid_i and cmd_rdyB;
+         cmd_startC <= cmd_validB_i and cmd_rdyC;
+         cmd_startD <= cmd_validB_i and cmd_rdyD;
+         cmd_startE <= cmd_validB_i and cmd_rdyE;
+         cmd_startF <= cmd_validB_i and cmd_rdyF;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            user_burst_cnt <= "0000000" ;
+         elsif (cmd_start = '1') then
+            if (FAMILY = "SPARTAN6") then
+               if (bl_i = "000000") then
+                  user_burst_cnt <= "1000000" ;
+               else
+                  user_burst_cnt <= ('0' & bl_i) ;
+               end if;
+            else
+               user_burst_cnt <= ('0' & bl_i)  ;
+            end if;
+         elsif (fifo_not_full = '1') then
+            if (user_burst_cnt /= "0000000") then
+               user_burst_cnt <= user_burst_cnt - "0000001"  ;
+            else
+               user_burst_cnt <= "0000000"  ;
+            end if;
+         end if;
+      end if;
+   end process;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
+            u_bcount_2 <= '1' ;
+         elsif (last_word_o_xhdl1 = '1') then
+            u_bcount_2 <= '0' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
+   
+   -- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
+   -- is assert and reassert during the last data
+   
+   cmd_rdy_o <= cmd_rdy and fifo_not_full;
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdy <= '1' ;
+         elsif (cmd_start = '1') then
+            if (bl_i = "000001") then
+               cmd_rdy <= '1' ;
+            else
+               cmd_rdy <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdy <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyB <= '1' ;
+         elsif (cmd_startB = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyB <= '1' ;
+            else
+               cmd_rdyB <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyB <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyC <= '1' ;
+         elsif (cmd_startC = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyC <= '1' ;
+            else
+               cmd_rdyC <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyC <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyD <= '1' ;
+         elsif (cmd_startD = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyD <= '1' ;
+            else
+               cmd_rdyD <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyD <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyE <= '1' ;
+         elsif (cmd_startE = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyE <= '1' ;
+            else
+               cmd_rdyE <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyE <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(0)) = '1') then
+            cmd_rdyF <= '1' ;
+         elsif (cmd_startF = '1') then
+            if (bl_i = "000001") then
+               cmd_rdyF <= '1' ;
+            else
+               cmd_rdyF <= '0' ;
+            end if;
+         elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
+            
+            cmd_rdyF <= '1' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   process (clk_i)
+   begin
+      if (clk_i'event and clk_i = '1') then
+         if ((rst_i(1)) = '1') then
+            data_valid <= '0' ;
+         elsif (cmd_start = '1') then
+            data_valid <= '1' ;
+         elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
+            data_valid <= '0' ;
+         end if;
+      end if;
+   end process;
+   
+   
+   data_valid_o <= data_valid and fifo_not_full;
+   
+   s6_wdgen : if (FAMILY = "SPARTAN6") generate
+      
+      
+      
+      
+      sp6_data_gen_inst : sp6_data_gen
+         generic map (
+            ADDR_WIDTH    => 32,
+            BL_WIDTH      => BL_WIDTH,
+            DWIDTH        => DWIDTH,
+            DATA_PATTERN  => DATA_PATTERN,
+            NUM_DQ_PINS   => NUM_DQ_PINS,
+            COLUMN_WIDTH  => COLUMN_WIDTH
+         )
+         port map (
+            clk_i           => clk_i,
+            rst_i           => rst_i(1),
+            data_rdy_i      => data_rdy_i,
+            prbs_fseed_i    => prbs_fseed_i,
+            
+            data_mode_i     => data_mode_i,
+            cmd_startA      => cmd_start,
+            cmd_startB      => cmd_startB,
+            cmd_startC      => cmd_startC,
+            cmd_startD      => cmd_startD,
+            cmd_startE      => cmd_startE,
+            fixed_data_i    => fixed_data_i,
+            addr_i          => addr_i,
+            user_burst_cnt  => user_burst_cnt,
+            fifo_rdy_i      => fifo_not_full,
+            data_o          => data_o_xhdl0
+         );
+      
+   end generate;                                    
+                                                    
+   v6_wdgen : if (FAMILY = "VIRTEX6") generate         
+                                                    
+                                                    
+                                                    
+                                                    
+      v6_data_gen_inst : v6_data_gen                
+         generic map (                              
+            ADDR_WIDTH       => 32,
+            BL_WIDTH         => BL_WIDTH,
+            DWIDTH           => DWIDTH,
+            MEM_BURST_LEN    => MEM_BURST_LEN,
+            
+            DATA_PATTERN     => DATA_PATTERN,
+            NUM_DQ_PINS      => NUM_DQ_PINS,        
+            SEL_VICTIM_LINE  => SEL_VICTIM_LINE,    
+            COLUMN_WIDTH     => COLUMN_WIDTH,       
+            EYE_TEST         => EYE_TEST
+         )                                          
+         port map (                                 
+            clk_i           => clk_i,               
+            rst_i           => rst_i(1),               
+            data_rdy_i      => data_rdy_i,          
+            prbs_fseed_i    => prbs_fseed_i,        
+                                                    
+            data_mode_i     => data_mode_i,         
+            cmd_starta      => cmd_start,           
+            cmd_startb      => cmd_startB,          
+            cmd_startc      => cmd_startC,          
+            cmd_startd      => cmd_startD,          
+            cmd_starte      => cmd_startE,          
+            fixed_data_i    => fixed_data_i,        
+            m_addr_i        => addr_i,      --m_addr_i,            
+            addr_i          => addr_i,              
+            user_burst_cnt  => user_burst_cnt,      
+            fifo_rdy_i      => fifo_not_full,       
+            data_o          => data_o_xhdl0         
+         );                                         
+   end generate;
+   
+   
+end architecture trans;
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/write_data_path.vhd b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/write_data_path.vhd
new file mode 100755
index 0000000..37d0cf4
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/sim/write_data_path.vhd
@@ -0,0 +1,210 @@
+--*****************************************************************************
+-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--*****************************************************************************
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version: %version
+--  \   \         Application: MIG
+--  /   /         Filename: write_data_path.vhd
+-- /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:28 $
+-- \   \  /  \    Date Created: Jul 03 2009
+--  \___\/\___\
+--
+-- Device: Spartan6
+-- Design Name: DDR/DDR2/DDR3/LPDDR 
+-- Purpose: This is top level of write path.
+-- Reference:
+-- Revision History:
+
+--*****************************************************************************
+
+LIBRARY ieee;
+   USE ieee.std_logic_1164.all;
+   USE ieee.std_logic_unsigned.all;
+
+entity write_data_path is
+   generic (
+      TCQ                            : TIME   := 100 ps;
+      MEM_BURST_LEN                  : integer := 8;
+      FAMILY                         : string := "SPARTAN6";
+      ADDR_WIDTH                     : integer := 32;
+      DWIDTH                         : integer := 32;
+      DATA_PATTERN                   : string := "DGEN_ALL";            --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : integer := 8;
+      SEL_VICTIM_LINE                : integer := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+      
+      MEM_COL_WIDTH                  : integer := 10;
+      EYE_TEST                       : string := "FALSE"
+   );
+   port (
+      
+      clk_i                          : in std_logic;
+      rst_i                          : in std_logic_vector(9 downto 0);
+      cmd_rdy_o                      : out std_logic;
+      cmd_valid_i                    : in std_logic;
+      cmd_validB_i                   : in std_logic;
+      cmd_validC_i                   : in std_logic;
+      prbs_fseed_i                   : in std_logic_vector(31 downto 0);
+      data_mode_i                    : in std_logic_vector(3 downto 0);
+--      m_addr_i                       : in std_logic_vector(31 downto 0);
+      fixed_data_i                   : in std_logic_vector(DWIDTH-1 downto 0);
+      addr_i                         : in std_logic_vector(31 downto 0);
+      
+      bl_i                           : in std_logic_vector(5 downto 0);
+      
+      --   input [5:0]            port_data_counts_i,// connect to data port fifo counts
+      
+      data_rdy_i                     : in std_logic;
+      data_valid_o                   : out std_logic;
+      last_word_wr_o                 : out std_logic;
+      data_o                         : out std_logic_vector(DWIDTH - 1 downto 0);
+      data_mask_o                    : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
+      data_wr_end_o                  : out std_logic   );
+end entity write_data_path;
+
+architecture trans of write_data_path is
+
+   COMPONENT wr_data_gen IS
+      GENERIC (
+      TCQ                            : TIME   := 100 ps;
+      FAMILY                         : STRING  := "SPARTAN6";           -- "SPARTAN6", "VIRTEX6"      
+      MODE                           : STRING  := "WR";         --"WR", "RD"
+      MEM_BURST_LEN                  : integer := 8;      
+      ADDR_WIDTH                     : INTEGER := 32;
+      BL_WIDTH                       : INTEGER := 6;
+      DWIDTH                         : INTEGER := 32;
+      DATA_PATTERN                   : STRING  := "DGEN_PRBS";          --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+      NUM_DQ_PINS                    : INTEGER := 8;
+      SEL_VICTIM_LINE                : INTEGER := 3;            -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern      
+      COLUMN_WIDTH                   : INTEGER := 10;
+      EYE_TEST                       : STRING  := "FALSE"
+      );
+      PORT (
+         clk_i           : IN STD_LOGIC;
+         rst_i           : in STD_LOGIC_VECTOR(4 downto 0);
+         prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+         data_mode_i     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+         cmd_rdy_o       : OUT STD_LOGIC;
+         cmd_valid_i     : IN STD_LOGIC;
+         cmd_validB_i    : IN STD_LOGIC;
+         cmd_validC_i    : IN STD_LOGIC;
+         last_word_o     : OUT STD_LOGIC;
+         fixed_data_i    : IN std_logic_vector(DWIDTH-1 downto 0);
+         
+--         m_addr_i        : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+         addr_i          : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
+         bl_i            : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
+         data_rdy_i      : IN STD_LOGIC;
+         data_valid_o    : OUT STD_LOGIC;
+         data_o          : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
+         data_wr_end_o   : OUT STD_LOGIC
+      );
+   END COMPONENT;
+
+   signal data_valid                    : std_logic;
+   signal cmd_rdy                       : std_logic;
+   
+   -- Declare intermediate signals for referenced outputs
+   signal cmd_rdy_o_xhdl0               : std_logic;
+   signal last_word_wr_o_xhdl3          : std_logic;
+   signal data_o_xhdl1                  : std_logic_vector(DWIDTH - 1 downto 0);
+   signal data_wr_end_o_xhdl2           : std_logic;
+begin
+   -- Drive referenced outputs
+   cmd_rdy_o <= cmd_rdy_o_xhdl0;
+   last_word_wr_o <= last_word_wr_o_xhdl3;
+   data_o <= data_o_xhdl1;
+   data_wr_end_o <= data_wr_end_o_xhdl2;
+   
+   data_valid_o <= data_valid and data_rdy_i;
+--   data_mask_o <= "0000";             -- for now 
+   data_mask_o <= (others => '0');   
+   
+   
+   wr_data_gen_inst : wr_data_gen
+      generic map (
+         TCQ              => TCQ,
+         family           => FAMILY,
+         num_dq_pins      => NUM_DQ_PINS,
+         sel_victim_line  => SEL_VICTIM_LINE,
+         MEM_BURST_LEN    => MEM_BURST_LEN,
+         
+         data_pattern     => DATA_PATTERN,
+         dwidth           => DWIDTH,
+         column_width     => MEM_COL_WIDTH,
+         eye_test         => EYE_TEST
+      )
+      port map (
+         clk_i          => clk_i,
+         rst_i          => rst_i(9 downto 5),
+         prbs_fseed_i   => prbs_fseed_i,
+         
+         data_mode_i    => data_mode_i,
+         cmd_rdy_o      => cmd_rdy_o_xhdl0,
+         cmd_valid_i    => cmd_valid_i,
+         cmd_validb_i   => cmd_validB_i,
+         cmd_validc_i   => cmd_validC_i,
+         
+         last_word_o    => last_word_wr_o_xhdl3,
+         --     .port_data_counts_i (port_data_counts_i),
+--         m_addr_i       => m_addr_i,
+         fixed_data_i   => fixed_data_i,
+         addr_i         => addr_i,
+         bl_i           => bl_i,
+         data_rdy_i     => data_rdy_i,
+         data_valid_o   => data_valid,
+         data_o         => data_o_xhdl1,
+         data_wr_end_o  => data_wr_end_o_xhdl2
+      );
+   
+end architecture trans;
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/synth/mem_interface_top_synp.sdc b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/synth/mem_interface_top_synp.sdc
new file mode 100644
index 0000000..4c5ff93
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/synth/mem_interface_top_synp.sdc
@@ -0,0 +1,20 @@
+# Synplicity, Inc. constraint file
+# Written on Mon Jun 27 15:50:39 2005
+
+define_attribute          {v:work.ddr2} syn_hier {hard}
+define_attribute          {v:work.iodrp_controller} syn_hier {hard}
+define_attribute          {v:work.iodrp_mcb_controller} syn_hier {hard}
+define_attribute          {v:work.mcb_raw_wrapper} syn_hier {hard}
+define_attribute          {v:work.mcb_soft_calibration} syn_hier {hard}
+define_attribute          {v:work.mcb_soft_calibration_top} syn_hier {hard}
+define_attribute          {v:work.memc3_infrastructure} syn_hier {hard}
+define_attribute          {v:work.memc3_wrapper} syn_hier {hard}
+
+# clock Constraints
+define_clock -disable -name {memc3_infrastructure_inst} -period 3000 -clockgroup default_clkgroup_1
+define_clock          -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 3000 -clockgroup default_clkgroup_2
+define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 3000 -clockgroup default_clkgroup_3
+
+
+
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/synth/script_synp.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/synth/script_synp.tcl
new file mode 100644
index 0000000..36a58c2
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/synth/script_synp.tcl
@@ -0,0 +1,40 @@
+project -new 
+add_file -vhdl "../rtl/ddr2.vhd"
+add_file -vhdl "../rtl/iodrp_controller.vhd"
+add_file -vhdl "../rtl/iodrp_mcb_controller.vhd"
+add_file -vhdl "../rtl/mcb_raw_wrapper.vhd"
+add_file -vhdl "../rtl/mcb_soft_calibration.vhd"
+add_file -vhdl "../rtl/mcb_soft_calibration_top.vhd"
+add_file -vhdl "../rtl/memc3_infrastructure.vhd"
+add_file -vhdl "../rtl/memc3_wrapper.vhd"
+add_file -constraint "../synth/mem_interface_top_synp.sdc"
+impl -add rev_1
+set_option -technology spartan6
+set_option -part xc6slx45
+set_option -package csg324
+set_option -speed_grade -3
+set_option -default_enum_encoding default
+#AXI_ENABLE synp definition is not required for user_design
+set_option -symbolic_fsm_compiler 1
+set_option -resource_sharing 0
+set_option -use_fsm_explorer 0
+set_option -top_module "ddr2"
+set_option -frequency 333.333
+set_option -fanout_limit 1000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -fixgatedclocks 0
+set_option -retiming 0
+set_option -modular 0
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -write_apr_constraint 0
+project -result_file "../synth/rev_1/ddr2.edf"
+set_option -vlog_std v2001
+set_option -auto_constrain_io 0
+impl -active "../synth/rev_1"
+project -run
+project -save
+
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_flist.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_flist.txt
new file mode 100644
index 0000000..f6620fb
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_flist.txt
@@ -0,0 +1,112 @@
+# Output products list for <ddr2>
+ddr2/docs/ug388.pdf
+ddr2/docs/ug416.pdf
+ddr2/example_design/datasheet.txt
+ddr2/example_design/mig.prj
+ddr2/example_design/par/create_ise.sh
+ddr2/example_design/par/example_top.ucf
+ddr2/example_design/par/icon_coregen.xco
+ddr2/example_design/par/ila_coregen.xco
+ddr2/example_design/par/ise_flow.sh
+ddr2/example_design/par/ise_run.txt
+ddr2/example_design/par/makeproj.sh
+ddr2/example_design/par/mem_interface_top.ut
+ddr2/example_design/par/readme.txt
+ddr2/example_design/par/rem_files.sh
+ddr2/example_design/par/set_ise_prop.tcl
+ddr2/example_design/par/vio_coregen.xco
+ddr2/example_design/rtl/example_top.vhd
+ddr2/example_design/rtl/iodrp_controller.vhd
+ddr2/example_design/rtl/iodrp_mcb_controller.vhd
+ddr2/example_design/rtl/mcb_raw_wrapper.vhd
+ddr2/example_design/rtl/mcb_soft_calibration.vhd
+ddr2/example_design/rtl/mcb_soft_calibration_top.vhd
+ddr2/example_design/rtl/memc3_infrastructure.vhd
+ddr2/example_design/rtl/memc3_tb_top.vhd
+ddr2/example_design/rtl/memc3_wrapper.vhd
+ddr2/example_design/rtl/traffic_gen/afifo.vhd
+ddr2/example_design/rtl/traffic_gen/cmd_gen.vhd
+ddr2/example_design/rtl/traffic_gen/cmd_prbs_gen.vhd
+ddr2/example_design/rtl/traffic_gen/data_prbs_gen.vhd
+ddr2/example_design/rtl/traffic_gen/init_mem_pattern_ctr.vhd
+ddr2/example_design/rtl/traffic_gen/mcb_flow_control.vhd
+ddr2/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd
+ddr2/example_design/rtl/traffic_gen/rd_data_gen.vhd
+ddr2/example_design/rtl/traffic_gen/read_data_path.vhd
+ddr2/example_design/rtl/traffic_gen/read_posted_fifo.vhd
+ddr2/example_design/rtl/traffic_gen/sp6_data_gen.vhd
+ddr2/example_design/rtl/traffic_gen/tg_status.vhd
+ddr2/example_design/rtl/traffic_gen/v6_data_gen.vhd
+ddr2/example_design/rtl/traffic_gen/wr_data_gen.vhd
+ddr2/example_design/rtl/traffic_gen/write_data_path.vhd
+ddr2/example_design/sim/functional/ddr2.prj
+ddr2/example_design/sim/functional/ddr2_model_c3.v
+ddr2/example_design/sim/functional/ddr2_model_parameters_c3.vh
+ddr2/example_design/sim/functional/isim.sh
+ddr2/example_design/sim/functional/isim.tcl
+ddr2/example_design/sim/functional/readme.txt
+ddr2/example_design/sim/functional/sim.do
+ddr2/example_design/sim/functional/sim_tb_top.vhd
+ddr2/example_design/sim/functional/timing_sim.sh
+ddr2/example_design/synth/example_top.lso
+ddr2/example_design/synth/example_top.prj
+ddr2/example_design/synth/mem_interface_top_synp.sdc
+ddr2/example_design/synth/script_synp.tcl
+ddr2/user_design/datasheet.txt
+ddr2/user_design/mig.prj
+ddr2/user_design/par/create_ise.sh
+ddr2/user_design/par/ddr2.ucf
+ddr2/user_design/par/icon_coregen.xco
+ddr2/user_design/par/ila_coregen.xco
+ddr2/user_design/par/ise_flow.sh
+ddr2/user_design/par/ise_run.txt
+ddr2/user_design/par/makeproj.sh
+ddr2/user_design/par/mem_interface_top.ut
+ddr2/user_design/par/readme.txt
+ddr2/user_design/par/rem_files.sh
+ddr2/user_design/par/set_ise_prop.tcl
+ddr2/user_design/par/vio_coregen.xco
+ddr2/user_design/rtl/ddr2.vhd
+ddr2/user_design/rtl/iodrp_controller.vhd
+ddr2/user_design/rtl/iodrp_mcb_controller.vhd
+ddr2/user_design/rtl/mcb_raw_wrapper.vhd
+ddr2/user_design/rtl/mcb_soft_calibration.vhd
+ddr2/user_design/rtl/mcb_soft_calibration_top.vhd
+ddr2/user_design/rtl/memc3_infrastructure.vhd
+ddr2/user_design/rtl/memc3_wrapper.vhd
+ddr2/user_design/sim/afifo.vhd
+ddr2/user_design/sim/cmd_gen.vhd
+ddr2/user_design/sim/cmd_prbs_gen.vhd
+ddr2/user_design/sim/data_prbs_gen.vhd
+ddr2/user_design/sim/ddr2.prj
+ddr2/user_design/sim/ddr2_model_c3.v
+ddr2/user_design/sim/ddr2_model_parameters_c3.vh
+ddr2/user_design/sim/init_mem_pattern_ctr.vhd
+ddr2/user_design/sim/isim.sh
+ddr2/user_design/sim/isim.tcl
+ddr2/user_design/sim/mcb_flow_control.vhd
+ddr2/user_design/sim/mcb_traffic_gen.vhd
+ddr2/user_design/sim/memc3_tb_top.vhd
+ddr2/user_design/sim/rd_data_gen.vhd
+ddr2/user_design/sim/read_data_path.vhd
+ddr2/user_design/sim/read_posted_fifo.vhd
+ddr2/user_design/sim/readme.txt
+ddr2/user_design/sim/sim.do
+ddr2/user_design/sim/sim_tb_top.vhd
+ddr2/user_design/sim/sp6_data_gen.vhd
+ddr2/user_design/sim/tg_status.vhd
+ddr2/user_design/sim/v6_data_gen.vhd
+ddr2/user_design/sim/wr_data_gen.vhd
+ddr2/user_design/sim/write_data_path.vhd
+ddr2/user_design/synth/ddr2.lso
+ddr2/user_design/synth/ddr2.prj
+ddr2/user_design/synth/mem_interface_top_synp.sdc
+ddr2/user_design/synth/script_synp.tcl
+ddr2.gise
+ddr2.vho
+ddr2.xco
+ddr2.xise
+ddr2_flist.txt
+ddr2_readme.txt
+ddr2_xmdf.tcl
+mig.prj
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_readme.txt b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_readme.txt
new file mode 100644
index 0000000..07a089d
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_readme.txt
@@ -0,0 +1,45 @@
+
+The design files are located at
+/home/ben/sandbox/git/hmb.git/src/ddr2:
+
+   - ddr2.vho:
+        vho template file containing code that can be used as a model
+        for instantiating a CORE Generator module in a HDL design.
+
+   - ddr2.xco:
+       CORE Generator input file containing the parameters used to
+       regenerate a core.
+
+   - ddr2_flist.txt:
+        Text file listing all of the output files produced when a customized
+        core was generated in the CORE Generator.
+
+   - ddr2_readme.txt:
+        Text file indicating the files generated and how they are used.
+
+   - ddr2_xmdf.tcl:
+        ISE Project Navigator interface file. ISE uses this file to determine
+        how the files output by CORE Generator for the core can be integrated
+        into your ISE project.
+
+   - ddr2.gise and ddr2.xise:
+        ISE Project Navigator support files. These are generated files and
+        should not be edited directly.
+
+   - ddr2 directory.
+
+In the ddr2 directory, three folders are created:
+   - docs:
+        This folder contains Virtex-6 FPGA Memory Interface Solutions user guide
+        and data sheet.
+
+   - example_design:
+        This folder includes the design with synthesizable test bench.
+
+   - user_design:
+        This folder includes the design without test bench modules.
+
+The example_design and user_design folders contain several other folders
+and files. All these output folders are discussed in more detail in
+Spartan-6 FPGA Memory Controller user guide (ug388.pdf) located in docs folder.
+    
\ No newline at end of file
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_xmdf.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_xmdf.tcl
new file mode 100644
index 0000000..229175b
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/ddr2_xmdf.tcl
@@ -0,0 +1,78 @@
+# The package naming convention is <core_name>_xmdf
+package provide ddr2_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations 
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::ddr2_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::ddr2_xmdf::xmdfInit { instance } {
+	# Variable containing name of library into which module is compiled
+	# Recommendation: <module_name>
+	# Required
+	utilities_xmdf::xmdfSetData $instance Module Attributes Name ddr2
+}
+# ::ddr2_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::ddr2_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+	# Array containing libraries that are assumed to exist
+	# Examples include unisim and xilinxcorelib
+	# Optional
+	# In this example, we assume that the unisim library will
+	# be magically
+	# available to the simulation and synthesis tool
+	utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+	utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+	incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/rtl/ddr2.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/rtl/iodrp_controller.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/rtl/iodrp_mcb_controller.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/rtl/mcb_raw_wrapper.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/rtl/mcb_soft_calibration.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/rtl/mcb_soft_calibration_top.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/rtl/memc3_infrastructure.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/rtl/memc3_wrapper.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ddr2/user_design/par/ddr2.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf 
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ddr2
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/src/vendor/xilinx/atlys_ddr2/edit_ddr2.tcl b/fpga/src/vendor/xilinx/atlys_ddr2/edit_ddr2.tcl
new file mode 100644
index 0000000..4e7afa2
--- /dev/null
+++ b/fpga/src/vendor/xilinx/atlys_ddr2/edit_ddr2.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "ddr2" xc6slx45-3csg324 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/fpga/src/vendor/xilinx/px_fifo.ngc b/fpga/src/vendor/xilinx/px_fifo.ngc
new file mode 100644
index 0000000..74625df
--- /dev/null
+++ b/fpga/src/vendor/xilinx/px_fifo.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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\ No newline at end of file
diff --git a/fpga/src/vendor/xilinx/px_fifo.vhd b/fpga/src/vendor/xilinx/px_fifo.vhd
new file mode 100644
index 0000000..0647622
--- /dev/null
+++ b/fpga/src/vendor/xilinx/px_fifo.vhd
@@ -0,0 +1,286 @@
+--------------------------------------------------------------------------------
+--    This file is owned and controlled by Xilinx and must be used solely     --
+--    for design, simulation, implementation and creation of design files     --
+--    limited to Xilinx devices or technologies. Use with non-Xilinx          --
+--    devices or technologies is expressly prohibited and immediately         --
+--    terminates your license.                                                --
+--                                                                            --
+--    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
+--    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
+--    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
+--    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
+--    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
+--    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
+--    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
+--    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
+--    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
+--    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
+--    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
+--    PARTICULAR PURPOSE.                                                     --
+--                                                                            --
+--    Xilinx products are not intended for use in life support appliances,    --
+--    devices, or systems.  Use in such applications are expressly            --
+--    prohibited.                                                             --
+--                                                                            --
+--    (c) Copyright 1995-2013 Xilinx, Inc.                                    --
+--    All rights reserved.                                                    --
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file px_fifo.vhd when simulating
+-- the core, px_fifo. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+LIBRARY XilinxCoreLib;
+-- synthesis translate_on
+ENTITY px_fifo IS
+  PORT (
+    rst : IN STD_LOGIC;
+    wr_clk : IN STD_LOGIC;
+    rd_clk : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC;
+    rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
+  );
+END px_fifo;
+
+ARCHITECTURE px_fifo_a OF px_fifo IS
+-- synthesis translate_off
+COMPONENT wrapped_px_fifo
+  PORT (
+    rst : IN STD_LOGIC;
+    wr_clk : IN STD_LOGIC;
+    rd_clk : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC;
+    rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
+  );
+END COMPONENT;
+
+-- Configuration specification
+  FOR ALL : wrapped_px_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
+    GENERIC MAP (
+      c_add_ngc_constraint => 0,
+      c_application_type_axis => 0,
+      c_application_type_rach => 0,
+      c_application_type_rdch => 0,
+      c_application_type_wach => 0,
+      c_application_type_wdch => 0,
+      c_application_type_wrch => 0,
+      c_axi_addr_width => 32,
+      c_axi_aruser_width => 1,
+      c_axi_awuser_width => 1,
+      c_axi_buser_width => 1,
+      c_axi_data_width => 64,
+      c_axi_id_width => 4,
+      c_axi_ruser_width => 1,
+      c_axi_type => 0,
+      c_axi_wuser_width => 1,
+      c_axis_tdata_width => 64,
+      c_axis_tdest_width => 4,
+      c_axis_tid_width => 8,
+      c_axis_tkeep_width => 4,
+      c_axis_tstrb_width => 4,
+      c_axis_tuser_width => 4,
+      c_axis_type => 0,
+      c_common_clock => 0,
+      c_count_type => 0,
+      c_data_count_width => 11,
+      c_default_value => "BlankString",
+      c_din_width => 32,
+      c_din_width_axis => 1,
+      c_din_width_rach => 32,
+      c_din_width_rdch => 64,
+      c_din_width_wach => 32,
+      c_din_width_wdch => 64,
+      c_din_width_wrch => 2,
+      c_dout_rst_val => "0",
+      c_dout_width => 32,
+      c_enable_rlocs => 0,
+      c_enable_rst_sync => 1,
+      c_error_injection_type => 0,
+      c_error_injection_type_axis => 0,
+      c_error_injection_type_rach => 0,
+      c_error_injection_type_rdch => 0,
+      c_error_injection_type_wach => 0,
+      c_error_injection_type_wdch => 0,
+      c_error_injection_type_wrch => 0,
+      c_family => "spartan6",
+      c_full_flags_rst_val => 1,
+      c_has_almost_empty => 0,
+      c_has_almost_full => 0,
+      c_has_axi_aruser => 0,
+      c_has_axi_awuser => 0,
+      c_has_axi_buser => 0,
+      c_has_axi_rd_channel => 0,
+      c_has_axi_ruser => 0,
+      c_has_axi_wr_channel => 0,
+      c_has_axi_wuser => 0,
+      c_has_axis_tdata => 0,
+      c_has_axis_tdest => 0,
+      c_has_axis_tid => 0,
+      c_has_axis_tkeep => 0,
+      c_has_axis_tlast => 0,
+      c_has_axis_tready => 1,
+      c_has_axis_tstrb => 0,
+      c_has_axis_tuser => 0,
+      c_has_backup => 0,
+      c_has_data_count => 0,
+      c_has_data_counts_axis => 0,
+      c_has_data_counts_rach => 0,
+      c_has_data_counts_rdch => 0,
+      c_has_data_counts_wach => 0,
+      c_has_data_counts_wdch => 0,
+      c_has_data_counts_wrch => 0,
+      c_has_int_clk => 0,
+      c_has_master_ce => 0,
+      c_has_meminit_file => 0,
+      c_has_overflow => 0,
+      c_has_prog_flags_axis => 0,
+      c_has_prog_flags_rach => 0,
+      c_has_prog_flags_rdch => 0,
+      c_has_prog_flags_wach => 0,
+      c_has_prog_flags_wdch => 0,
+      c_has_prog_flags_wrch => 0,
+      c_has_rd_data_count => 1,
+      c_has_rd_rst => 0,
+      c_has_rst => 1,
+      c_has_slave_ce => 0,
+      c_has_srst => 0,
+      c_has_underflow => 0,
+      c_has_valid => 0,
+      c_has_wr_ack => 0,
+      c_has_wr_data_count => 0,
+      c_has_wr_rst => 0,
+      c_implementation_type => 2,
+      c_implementation_type_axis => 1,
+      c_implementation_type_rach => 1,
+      c_implementation_type_rdch => 1,
+      c_implementation_type_wach => 1,
+      c_implementation_type_wdch => 1,
+      c_implementation_type_wrch => 1,
+      c_init_wr_pntr_val => 0,
+      c_interface_type => 0,
+      c_memory_type => 1,
+      c_mif_file_name => "BlankString",
+      c_msgon_val => 1,
+      c_optimization_mode => 0,
+      c_overflow_low => 0,
+      c_preload_latency => 0,
+      c_preload_regs => 1,
+      c_prim_fifo_type => "2kx18",
+      c_prog_empty_thresh_assert_val => 4,
+      c_prog_empty_thresh_assert_val_axis => 1022,
+      c_prog_empty_thresh_assert_val_rach => 1022,
+      c_prog_empty_thresh_assert_val_rdch => 1022,
+      c_prog_empty_thresh_assert_val_wach => 1022,
+      c_prog_empty_thresh_assert_val_wdch => 1022,
+      c_prog_empty_thresh_assert_val_wrch => 1022,
+      c_prog_empty_thresh_negate_val => 5,
+      c_prog_empty_type => 0,
+      c_prog_empty_type_axis => 0,
+      c_prog_empty_type_rach => 0,
+      c_prog_empty_type_rdch => 0,
+      c_prog_empty_type_wach => 0,
+      c_prog_empty_type_wdch => 0,
+      c_prog_empty_type_wrch => 0,
+      c_prog_full_thresh_assert_val => 2047,
+      c_prog_full_thresh_assert_val_axis => 1023,
+      c_prog_full_thresh_assert_val_rach => 1023,
+      c_prog_full_thresh_assert_val_rdch => 1023,
+      c_prog_full_thresh_assert_val_wach => 1023,
+      c_prog_full_thresh_assert_val_wdch => 1023,
+      c_prog_full_thresh_assert_val_wrch => 1023,
+      c_prog_full_thresh_negate_val => 2046,
+      c_prog_full_type => 0,
+      c_prog_full_type_axis => 0,
+      c_prog_full_type_rach => 0,
+      c_prog_full_type_rdch => 0,
+      c_prog_full_type_wach => 0,
+      c_prog_full_type_wdch => 0,
+      c_prog_full_type_wrch => 0,
+      c_rach_type => 0,
+      c_rd_data_count_width => 11,
+      c_rd_depth => 2048,
+      c_rd_freq => 1,
+      c_rd_pntr_width => 11,
+      c_rdch_type => 0,
+      c_reg_slice_mode_axis => 0,
+      c_reg_slice_mode_rach => 0,
+      c_reg_slice_mode_rdch => 0,
+      c_reg_slice_mode_wach => 0,
+      c_reg_slice_mode_wdch => 0,
+      c_reg_slice_mode_wrch => 0,
+      c_synchronizer_stage => 2,
+      c_underflow_low => 0,
+      c_use_common_overflow => 0,
+      c_use_common_underflow => 0,
+      c_use_default_settings => 0,
+      c_use_dout_rst => 1,
+      c_use_ecc => 0,
+      c_use_ecc_axis => 0,
+      c_use_ecc_rach => 0,
+      c_use_ecc_rdch => 0,
+      c_use_ecc_wach => 0,
+      c_use_ecc_wdch => 0,
+      c_use_ecc_wrch => 0,
+      c_use_embedded_reg => 0,
+      c_use_fifo16_flags => 0,
+      c_use_fwft_data_count => 1,
+      c_valid_low => 0,
+      c_wach_type => 0,
+      c_wdch_type => 0,
+      c_wr_ack_low => 0,
+      c_wr_data_count_width => 12,
+      c_wr_depth => 2048,
+      c_wr_depth_axis => 1024,
+      c_wr_depth_rach => 16,
+      c_wr_depth_rdch => 1024,
+      c_wr_depth_wach => 16,
+      c_wr_depth_wdch => 1024,
+      c_wr_depth_wrch => 16,
+      c_wr_freq => 1,
+      c_wr_pntr_width => 11,
+      c_wr_pntr_width_axis => 10,
+      c_wr_pntr_width_rach => 4,
+      c_wr_pntr_width_rdch => 10,
+      c_wr_pntr_width_wach => 4,
+      c_wr_pntr_width_wdch => 10,
+      c_wr_pntr_width_wrch => 4,
+      c_wr_response_latency => 1,
+      c_wrch_type => 0
+    );
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_px_fifo
+  PORT MAP (
+    rst => rst,
+    wr_clk => wr_clk,
+    rd_clk => rd_clk,
+    din => din,
+    wr_en => wr_en,
+    rd_en => rd_en,
+    dout => dout,
+    full => full,
+    empty => empty,
+    rd_data_count => rd_data_count
+  );
+-- synthesis translate_on
+
+END px_fifo_a;
diff --git a/fpga/src/vendor/xilinx/px_fifo.xco b/fpga/src/vendor/xilinx/px_fifo.xco
new file mode 100644
index 0000000..e3d0aef
--- /dev/null
+++ b/fpga/src/vendor/xilinx/px_fifo.xco
@@ -0,0 +1,213 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Fri Aug 23 07:30:57 2013
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:fifo_generator:9.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=px_fifo
+CSET data_count=false
+CSET data_count_width=11
+CSET disable_timing_violations=false
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=5
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_read_channel=false
+CSET enable_read_pointer_increment_by2=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=2047
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=2046
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=32
+CSET input_depth=2048
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=32
+CSET output_depth=2048
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET programmable_full_type_axis=No_Programmable_Full_Threshold
+CSET programmable_full_type_rach=No_Programmable_Full_Threshold
+CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
+CSET programmable_full_type_wach=No_Programmable_Full_Threshold
+CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
+CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=11
+CSET register_slice_mode_axis=Fully_Registered
+CSET register_slice_mode_rach=Fully_Registered
+CSET register_slice_mode_rdch=Fully_Registered
+CSET register_slice_mode_wach=Fully_Registered
+CSET register_slice_mode_wdch=Fully_Registered
+CSET register_slice_mode_wrch=Fully_Registered
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET synchronization_stages=2
+CSET synchronization_stages_axi=2
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=12
+CSET wuser_width=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T12:39:56Z
+# END Extra information
+GENERATE
+# CRC: 3eb4d24e
diff --git a/fpga/syn/Makefile b/fpga/syn/Makefile
new file mode 100644
index 0000000..7590a1c
--- /dev/null
+++ b/fpga/syn/Makefile
@@ -0,0 +1,235 @@
+# #############################################################################
+# Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+# #############################################################################
+PROJECT_DEFAULT = atlys_sig
+PROJECT_NAME   ?= $(PROJECT_DEFAULT)
+PROJECT_DIR     = $(PROJECT_NAME)_build
+PROJECT_SRC     = ../src
+PROJECT_SRC_TOP = $(PROJECT_SRC)/top
+PROJECT_UCF     = $(PROJECT_SRC_TOP)/$(PROJECT_NAME).ucf
+
+##### BUILD FLAGS #############################
+FPGA_PART       = $(shell grep FPGA_PART $(PROJECT_UCF) | cut -d'=' -f2)
+XST_FLAGS       = -intstyle silent
+NGDBUILD_FLAGS  = -intstyle silent -dd _ngo
+NGDBUILD_FLAGS += $(if $(PROJECT_UCF),-uc ../,)$(PROJECT_UCF)
+MAP_FLAGS       = -intstyle silent -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 \
+                  -global_opt off -mt off -ir off -pr off -lc off -power off
+PAR_FLAGS       = -w -intstyle silent -ol high -mt off
+TRCE_FLAGS      = -intstyle silent -v 3 -s 3 -n 3 -fastpaths
+BITGEN_FLAGS    = -intstyle silent
+
+##### SOURCE FILES ############################
+COMMON_SRCS =  $(PROJECT_SRC)/snippets/vhdl/rrarbiter.vhd
+
+FX2_TOP_DIR = ../../fx2/fpga
+USB_NGCS = $(FX2_TOP_DIR)/vendor/xilinx/usb_fifo_tx.ngc $(FX2_TOP_DIR)/vendor/xilinx/usb_fifo_rx.ngc \
+           $(FX2_TOP_DIR)/vendor/xilinx/usb_fifo_tx_fin.ngc
+USB_SRCS = $(FX2_TOP_DIR)/f2p/strm_package.vhd $(FX2_TOP_DIR)/f2p/f2p_master.vhd \
+           $(FX2_TOP_DIR)/f2p/f2p_strm_top.vhd $(FX2_TOP_DIR)/strm_ddr2/strm_ddr2.vhd \
+	   $(FX2_TOP_DIR)/strm_regfile/strm_regfile.vhd
+
+DVI_TOP_DIR = $(PROJECT_SRC)/dvi
+DVI_SRCS = $(DVI_TOP_DIR)/dvi_package.vhd $(DVI_TOP_DIR)/serdes_1_to_5_diff_data.vhd $(DVI_TOP_DIR)/DRAM16XN.vhd \
+           $(DVI_TOP_DIR)/phsaligner.vhd $(DVI_TOP_DIR)/chnlbond.vhd $(DVI_TOP_DIR)/serdes_n_to_1.vhd \
+           $(DVI_TOP_DIR)/encoder.vhd $(DVI_TOP_DIR)/decoder.vhd $(DVI_TOP_DIR)/convert_30to15_fifo.vhd \
+           $(DVI_TOP_DIR)/dvi_encoder.vhd $(DVI_TOP_DIR)/dvi_decoder.vhd
+
+I2C_TOP_DIR = $(PROJECT_SRC)/i2c
+I2C_SRCS = $(I2C_TOP_DIR)/slave/i2c_slave.vhd $(I2C_TOP_DIR)/slave/i2c_rom.vhd
+
+DDR2_TOP_DIR = $(PROJECT_SRC)/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/
+DDR2_SRCS = $(DDR2_TOP_DIR)/iodrp_controller.vhd $(DDR2_TOP_DIR)/mcb_raw_wrapper.vhd \
+            $(DDR2_TOP_DIR)/iodrp_mcb_controller.vhd $(DDR2_TOP_DIR)/mcb_soft_calibration_top.vhd \
+            $(DDR2_TOP_DIR)/mcb_soft_calibration.vhd $(DDR2_TOP_DIR)/memc3_infrastructure.vhd \
+            $(DDR2_TOP_DIR)/memc3_wrapper.vhd $(DDR2_TOP_DIR)/ddr2.vhd
+
+SIG_TOP_DIR = $(PROJECT_SRC)/sig
+SIG_NGCS = $(PROJECT_SRC)/vendor/xilinx/px_fifo.ngc
+SIG_SRCS = $(SIG_TOP_DIR)/sig_read.vhd $(SIG_TOP_DIR)/sig_write.vhd $(SIG_TOP_DIR)/sig.vhd \
+           $(SIG_TOP_DIR)/ddr2dvi.vhd $(SIG_TOP_DIR)/dvi2ddr.vhd
+
+NGCS = $(USB_NGCS) $(SIG_NGCS)
+SRCS = $(NGCS:%.ngc=%.vhd) \
+       $(COMMON_SRCS) \
+       $(DVI_SRCS) \
+       $(I2C_SRCS) \
+       $(DDR2_SRCS) \
+       $(USB_SRCS) \
+       $(SIG_SRCS) \
+       $(PROJECT_SRC_TOP)/$(PROJECT_NAME).vhd
+
+##### RUN SCRIPTS #############################
+define XST_SCRIPT
+set -tmpdir "tmp"
+set -xsthdpdir "xst"
+run
+-ifn $(PROJECT_NAME).prj
+-ofn $(PROJECT_NAME)
+-ofmt NGC
+-p $(FPGA_PART)
+-top $(PROJECT_NAME)
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing NO
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
+endef
+export XST_SCRIPT
+
+define BITGEN_FILE
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
+endef
+export BITGEN_FILE
+
+##### PRINT ###################################
+PW=\033[1m\033[0m
+GR=\E[40;32m
+WH=\E[40;37m
+B=\033[1m
+pr_info = "$(B) $(GR)[$(1)]\t $(WH)$(2)$(PW)"
+
+TARGETS = build help prep syn ngd map par trce bit flash clean
+VAR_TARGETS = $(PROJECT_DIR)/tmp  $(PROJECT_DIR)/$(PROJECT_NAME).ngc $(PROJECT_DIR)/$(PROJECT_NAME).ngd \
+	       $(PROJECT_DIR)/$(PROJECT_NAME)_map.ncd $(PROJECT_DIR)/$(PROJECT_NAME).pcf \
+	       $(PROJECT_DIR)/$(PROJECT_NAME).ncd $(PROJECT_DIR)/$(PROJECT_NAME).twr \
+	       $(PROJECT_DIR)/$(PROJECT_NAME).bit
+##### BUILD RULES #############################
+.SILENT: help $(if $(V),,$(TARGETS) $(VAR_TARGETS))
+.PHONY: $(TARGETS)
+
+help:
+	echo -e "$$ make PROJECT_NAME=<top-file> <rule> [V=1]"
+	echo -e "\tprojects (*=default) .. : $(subst $(PROJECT_DEFAULT),*$(PROJECT_DEFAULT),$(subst $(PROJECT_SRC_TOP)/,,$(subst .ucf,,$(wildcard $(PROJECT_SRC_TOP)/*.ucf))))"
+	echo -e "\trule .................. : $(TARGETS)"
+	echo -e "\tV ..................... : verbose"
+
+prep $(PROJECT_DIR)/tmp: $(SRCS)
+	echo -e $(call pr_info,PREP,Build ENV for $(PROJECT_NAME))
+	mkdir -p $(PROJECT_DIR)/tmp
+	rm -f $(PROJECT_DIR)/$(PROJECT_NAME).prj
+	for s in $(SRCS); do \
+		if [ "$${s##*.}" = "vhd" ]; then echo "vhdl work \"../$$s\"" >> $(PROJECT_DIR)/$(PROJECT_NAME).prj; fi; \
+		if [ "$${s##*.}" = "v"   ]; then echo "verilog work \"../$$s\"" >> $(PROJECT_DIR)/$(PROJECT_NAME).prj; fi; \
+	done
+	echo "$$XST_SCRIPT" > $(PROJECT_DIR)/$(PROJECT_NAME).xst
+
+syn $(PROJECT_DIR)/$(PROJECT_NAME).ngc: $(PROJECT_DIR)/tmp
+	echo -e $(call pr_info,NGC,Link prebuild IP Cores)
+	for n in $(NGCS); do ln -sf ../$$n $(PROJECT_DIR)/${n##*/}; done
+	echo -e $(call pr_info,XST,Synthesis)
+	cd $(PROJECT_DIR) && xst $(XST_FLAGS) -ifn $(PROJECT_NAME).xst -ofn $(PROJECT_NAME).syr
+
+ngd $(PROJECT_DIR)/$(PROJECT_NAME).ngd: $(PROJECT_DIR)/$(PROJECT_NAME).ngc $(PROJECT_UCF)
+	echo -e $(call pr_info,NGD,Native Generic Database)
+	cd $(PROJECT_DIR) && ngdbuild $(NGDBUILD_FLAGS) -p $(FPGA_PART) $(PROJECT_NAME).ngc $(PROJECT_NAME).ngd
+
+map $(PROJECT_DIR)/$(PROJECT_NAME)_map.ncd $(PROJECT_DIR)/$(PROJECT_NAME).pcf: $(PROJECT_DIR)/$(PROJECT_NAME).ngd
+	echo -e $(call pr_info,MAP,Mapping Logic)
+	cd $(PROJECT_DIR) && map $(MAP_FLAGS) -p $(FPGA_PART) -o $(PROJECT_NAME)_map.ncd $(PROJECT_NAME).ngd $(PROJECT_NAME).pcf
+
+par $(PROJECT_DIR)/$(PROJECT_NAME).ncd: $(PROJECT_DIR)/$(PROJECT_NAME)_map.ncd $(PROJECT_DIR)/$(PROJECT_NAME).pcf
+	echo -e $(call pr_info,PAR,Place and Route)
+	cd $(PROJECT_DIR) && par $(PAR_FLAGS) $(PROJECT_NAME)_map.ncd $(PROJECT_NAME).ncd $(PROJECT_NAME).pcf
+
+trce $(PROJECT_DIR)/$(PROJECT_NAME).twr: $(PROJECT_DIR)/$(PROJECT_NAME).ncd
+	echo -e $(call pr_info,TRCE,Timing analyzes)
+	cd $(PROJECT_DIR) && trce $(TRCE_FLAGS) -xml $(PROJECT_NAME).twx $(PROJECT_NAME).ncd -o $(PROJECT_NAME).twr $(PROJECT_NAME).pcf
+
+bit build $(PROJECT_DIR)/$(PROJECT_NAME).bit: $(PROJECT_DIR)/$(PROJECT_NAME).ncd $(PROJECT_DIR)/$(PROJECT_NAME).twr
+	echo -e $(call pr_info,BITG,Bitfile Generation)
+	echo "$$BITGEN_FILE" > $(PROJECT_DIR)/$(PROJECT_NAME).ut
+	cd $(PROJECT_DIR) && bitgen $(BITGEN_FLAGS) -f $(PROJECT_NAME).ut $(PROJECT_NAME).ncd
+
+flash: $(PROJECT_DIR)/$(PROJECT_NAME).bit
+	echo -e "setmode -bs\nsetCable -p auto\nIdentify -inferir\nidentifyMPM\nassignFile -p 1 -file "$$PWD/$(PROJECT_DIR)/$(PROJECT_NAME).bit"\nprogram -p 1\nquit\n" | impact -batch
+
+clean:
+	echo -e $(call pr_info,RM,delete project directory)
+	rm -rf $(PROJECT_DIR)
diff --git a/fpga/syn/syn.gise b/fpga/syn/syn.gise
new file mode 100644
index 0000000..3e71169
--- /dev/null
+++ b/fpga/syn/syn.gise
@@ -0,0 +1,258 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="syn.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="../../fx2/fpga/vendor/xilinx/coregen.log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.ngc" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.vhd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.ngc" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.vhd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.vhd" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="../src/ddr2/coregen.log"/>
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="../src/vendor/xilinx/px_fifo.asy" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/px_fifo.ngc" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../src/vendor/xilinx/px_fifo.sym" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/px_fifo.vhd" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="../src/vendor/xilinx/px_fifo.vho" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/usb_fifo_rx.ngc" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/usb_fifo_rx.vhd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/usb_fifo_tx.ngc" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/usb_fifo_tx.vhd" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="atlys_sig.bgn" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="atlys_sig.bit" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="atlys_sig.bld"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="atlys_sig.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="atlys_sig.drc" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="atlys_sig.lso"/>
+    <file xil_pn:fileType="FILE_MSK" xil_pn:name="atlys_sig.msk"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig.ncd" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="atlys_sig.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="atlys_sig.ngd"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="atlys_sig.ngr"/>
+    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="atlys_sig.pad"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="atlys_sig.par" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="atlys_sig.pcf" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="atlys_sig.prj"/>
+    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="atlys_sig.ptwx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="atlys_sig.stx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="atlys_sig.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="atlys_sig.twr" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="atlys_sig.twx" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="atlys_sig.unroutes" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="atlys_sig.ut" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:fileType="FILE_XPI" xil_pn:name="atlys_sig.xpi"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="atlys_sig.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="atlys_sig_envsettings.html"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="atlys_sig_map.map" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="atlys_sig_map.mrp" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig_map.ncd" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="atlys_sig_map.ngm" xil_pn:subbranch="Map"/>
+    <file xil_pn:fileType="FILE_PSR" xil_pn:name="atlys_sig_map.psr"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_map.xrpt"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_ngdbuild.xrpt"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="atlys_sig_pad.csv" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="atlys_sig_pad.txt" xil_pn:subbranch="Par"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_par.xrpt"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="atlys_sig_summary.html"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="atlys_sig_summary.xml"/>
+    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="atlys_sig_usage.xml"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_xst.xrpt"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6498325036265346234" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1381750723" xil_pn:in_ck="-4990497755435147446" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8579041901420796151" xil_pn:start_ts="1381750722">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.ngc"/>
+      <outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.vhd"/>
+      <outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.ngc"/>
+      <outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.vhd"/>
+      <outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc"/>
+      <outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_controller.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_mcb_controller.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_raw_wrapper.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration_top.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_infrastructure.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_wrapper.vhd"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/px_fifo.ngc"/>
+      <outfile xil_pn:name="../src/vendor/xilinx/px_fifo.vhd"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:in_ck="-3266226745153874044" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7532054547514773688" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:in_ck="-3266226745153874044" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-616900325625012223" xil_pn:start_ts="1379695224">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1381750752" xil_pn:in_ck="-5754007203490239776" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3327302063185124304" xil_pn:start_ts="1381750723">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+      <outfile xil_pn:name="atlys_sig.lso"/>
+      <outfile xil_pn:name="atlys_sig.ngc"/>
+      <outfile xil_pn:name="atlys_sig.ngr"/>
+      <outfile xil_pn:name="atlys_sig.prj"/>
+      <outfile xil_pn:name="atlys_sig.stx"/>
+      <outfile xil_pn:name="atlys_sig.syr"/>
+      <outfile xil_pn:name="atlys_sig.xst"/>
+      <outfile xil_pn:name="atlys_sig_xst.xrpt"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+      <outfile xil_pn:name="xst"/>
+    </transform>
+    <transform xil_pn:end_ts="1379695258" xil_pn:in_ck="-2812728212376607396" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4408915874172682627" xil_pn:start_ts="1379695258">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1381750764" xil_pn:in_ck="-5271234473535174591" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7713896191513598818" xil_pn:start_ts="1381750752">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_ngo"/>
+      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+      <outfile xil_pn:name="atlys_sig.bld"/>
+      <outfile xil_pn:name="atlys_sig.ngd"/>
+      <outfile xil_pn:name="atlys_sig_ngdbuild.xrpt"/>
+    </transform>
+    <transform xil_pn:end_ts="1381750841" xil_pn:in_ck="-2821415870385197163" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-8360921270489510961" xil_pn:start_ts="1381750764">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
+      <outfile xil_pn:name="atlys_sig.pcf"/>
+      <outfile xil_pn:name="atlys_sig_map.map"/>
+      <outfile xil_pn:name="atlys_sig_map.mrp"/>
+      <outfile xil_pn:name="atlys_sig_map.ncd"/>
+      <outfile xil_pn:name="atlys_sig_map.ngm"/>
+      <outfile xil_pn:name="atlys_sig_map.psr"/>
+      <outfile xil_pn:name="atlys_sig_map.xrpt"/>
+      <outfile xil_pn:name="atlys_sig_summary.xml"/>
+      <outfile xil_pn:name="atlys_sig_usage.xml"/>
+    </transform>
+    <transform xil_pn:end_ts="1381750888" xil_pn:in_ck="4790132884118110510" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1381750841">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
+      <outfile xil_pn:name="atlys_sig.ncd"/>
+      <outfile xil_pn:name="atlys_sig.pad"/>
+      <outfile xil_pn:name="atlys_sig.par"/>
+      <outfile xil_pn:name="atlys_sig.ptwx"/>
+      <outfile xil_pn:name="atlys_sig.unroutes"/>
+      <outfile xil_pn:name="atlys_sig.xpi"/>
+      <outfile xil_pn:name="atlys_sig_pad.csv"/>
+      <outfile xil_pn:name="atlys_sig_pad.txt"/>
+      <outfile xil_pn:name="atlys_sig_par.xrpt"/>
+    </transform>
+    <transform xil_pn:end_ts="1379698920" xil_pn:in_ck="1798662901162223602" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-7216915341624083389" xil_pn:start_ts="1379698874">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="InputRemoved"/>
+      <status xil_pn:value="OutputRemoved"/>
+    </transform>
+    <transform xil_pn:end_ts="1379693527" xil_pn:in_ck="1798662901162210748" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1379693525">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="NotReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+      <status xil_pn:value="OutputRemoved"/>
+    </transform>
+    <transform xil_pn:end_ts="1375166772" xil_pn:in_ck="-2821415870385197295" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1375166762">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+    </transform>
+    <transform xil_pn:end_ts="1381750888" xil_pn:in_ck="-2821415870385197295" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381750879">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+      <outfile xil_pn:name="atlys_sig.twr"/>
+      <outfile xil_pn:name="atlys_sig.twx"/>
+    </transform>
+    <transform xil_pn:end_ts="1375175447" xil_pn:in_ck="4790132884118110510" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791353" xil_pn:start_ts="1375175447">
+      <status xil_pn:value="FailedRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+    </transform>
+    <transform xil_pn:end_ts="1377159094" xil_pn:in_ck="-2821415870385197163" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1377159094">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+    </transform>
+  </transforms>
+
+</generated_project>
diff --git a/fpga/syn/syn.xise b/fpga/syn/syn.xise
new file mode 100644
index 0000000..7b6a361
--- /dev/null
+++ b/fpga/syn/syn.xise
@@ -0,0 +1,513 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="../src/dvi/DRAM16XN.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="../src/i2c/slave/i2c_rom.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+    </file>
+    <file xil_pn:name="../src/i2c/slave/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+    </file>
+    <file xil_pn:name="../src/dvi/decoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+    </file>
+    <file xil_pn:name="../src/dvi/dvi_decoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+    </file>
+    <file xil_pn:name="../src/dvi/dvi_encoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+    </file>
+    <file xil_pn:name="../src/dvi/dvi_package.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="../src/dvi/encoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+    </file>
+    <file xil_pn:name="../src/dvi/phsaligner.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="../src/dvi/chnlbond.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
+    <file xil_pn:name="../src/dvi/serdes_n_to_1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+    </file>
+    <file xil_pn:name="../src/dvi/convert_30to15_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+    </file>
+    <file xil_pn:name="../src/dvi/serdes_1_to_5_diff_data.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+    </file>
+    <file xil_pn:name="../src/top/atlys_sig.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+    </file>
+    <file xil_pn:name="../src/sig/sig_write.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+    </file>
+    <file xil_pn:name="../src/sig/sig_read.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="127"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+    </file>
+    <file xil_pn:name="../src/vendor/xilinx/px_fifo.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    </file>
+    <file xil_pn:name="../src/top/atlys_sig.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../fx2/fpga/f2p/strm_package.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+    </file>
+    <file xil_pn:name="../src/sig/ddr2dvi.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+    </file>
+    <file xil_pn:name="../src/sig/dvi2ddr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+    </file>
+    <file xil_pn:name="../../fx2/fpga/strm_ddr2/strm_ddr2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+    </file>
+    <file xil_pn:name="../src/misc/rrarbiter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+    </file>
+    <file xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+    </file>
+    <file xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+    </file>
+    <file xil_pn:name="../../fx2/fpga/f2p/f2p_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+    </file>
+    <file xil_pn:name="../../fx2/fpga/f2p/f2p_strm_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+    </file>
+    <file xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|atlys_sig|top" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../src/top/atlys_sig.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/atlys_sig" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Auto" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked) ben;/home/dev/Xilinx/14.6/ISE_DS/ISE/data/Xilinx Default (unlocked) ben.xds" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="atlys_sig" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="atlys_sig_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="atlys_sig_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="atlys_sig_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="atlys_sig_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="atlys_sig" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/atlys_sig" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.atlys_sig" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.atlys_sig" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/dev/Xilinx/14.6/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="syn" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-04T13:17:55" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F14F3C952E4C1216E6919D07C5E9A997" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings>
+    <binding xil_pn:location="/atlys_sig" xil_pn:name="../src/top/atlys_sig.ucf"/>
+  </bindings>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
diff --git a/fpga/tools/edid2dat.sh b/fpga/tools/edid2dat.sh
new file mode 100755
index 0000000..8d04378
--- /dev/null
+++ b/fpga/tools/edid2dat.sh
@@ -0,0 +1,31 @@
+#!/bin/bash
+# #############################################################################
+# Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+# #############################################################################
+
+if [ $# != 1 ]; then
+	echo "$0 <ouput-file>"
+	exit -1;
+fi
+
+ofile=$1
+
+monitor-get-edid | xxd -i1 | sed 's/ //g' | sed 's/,$//' | sed 's/,/\n/g' | sed 's/0x//' > $ofile
diff --git a/fpga/tools/edid_extract_timing.sh b/fpga/tools/edid_extract_timing.sh
new file mode 100755
index 0000000..5b03d54
--- /dev/null
+++ b/fpga/tools/edid_extract_timing.sh
@@ -0,0 +1,61 @@
+#!/bin/bash
+# #############################################################################
+# Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+# #############################################################################
+
+if [ $# != 1 ]; then
+	echo "$0 <input-file>"
+	exit -1;
+fi
+
+ifile=$1
+
+c=0;
+for i in `cat $ifile`; do
+	if [ $[ c % 16 ] -eq 0 ]; then
+		echo
+		printf "%04x: " $c
+	fi
+	printf " %02x" 0x$i;
+	d[$c]=$i;
+	c=$[ $c + 1 ];
+done;
+echo; echo
+
+echo "Pixel Clock Freq: $[ 0x${d[0x37]}${d[0x36]} * 10000 ] Hz"
+tmp=$[ (0x${d[0x3a]} & 0xf0) << 4 | 0x${d[0x38]}]
+printf "Horizontal Active: %d | x\"%x\"\n" $tmp $tmp
+tmp=$[ (0x${d[0x3a]} & 0x0f) << 8 | 0x${d[0x39]}]
+printf "Horizontal Blanking: %d | x\"%x\"\n" $tmp $tmp
+tmp=$[ (0x${d[0x3d]} & 0xf0) << 4 | 0x${d[0x3b]}]
+printf "Vertical Active: %d | x\"%x\"\n" $tmp $tmp
+tmp=$[ (0x${d[0x3d]} & 0x0f) << 8 | 0x${d[0x3c]}]
+printf "Vertical Blanking: %d | x\"%x\"\n" $tmp $tmp
+
+tmp=$[ (0x${d[0x41]} & 0xc0) << 2 | 0x${d[0x3e]}]
+printf "Horizontal Sync. Offset: %d | x\"%x\"\n" $tmp $tmp
+tmp=$[ (0x${d[0x41]} & 0x30) << 4 | 0x${d[0x3f]}]
+printf "Horizontal Sync. Pulse Width: %d | x\"%x\"\n" $tmp $tmp
+
+tmp=$[ (0x${d[0x41]} & 0x0c) << 2 | (0x${d[0x40]} >> 4) ]
+printf "Vertical Sync. Offset: %d | x\"%x\"\n" $tmp $tmp
+tmp=$[ (0x${d[0x41]} & 0x03)      | (0x${d[0x40]} & 0x0f) ]
+printf "Vertical Sync. Pulse Width: %d | x\"%x\"\n" $tmp $tmp
diff --git a/fx2 b/fx2
new file mode 160000
index 0000000..4d59d22
--- /dev/null
+++ b/fx2
@@ -0,0 +1 @@
+Subproject commit 4d59d22c13478ba153f22b934d1eb4e4eafd3ab7