library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.dvi_package.all;

library UNISIM;
use UNISIM.Vcomponents.all;

entity dvi2ddr is
	port (
		clk                   : in  std_logic;
		rst                   : in  std_logic;

		ctrl_disable_wr       : in  std_logic;
		
		rx_tmds               : in  std_logic_vector(3 downto 0);
		rx_tmds_n             : in  std_logic_vector(3 downto 0);

		-- memory interface
		ddr2_cmd_en_o         : out std_logic;
		ddr2_cmd_instr_o      : out std_logic_vector( 2 downto 0);
		ddr2_cmd_bl_o         : out std_logic_vector( 5 downto 0);
		ddr2_cmd_byte_addr_o  : out std_logic_vector(29 downto 0);
		ddr2_cmd_empty_i      : in  std_logic;
		ddr2_cmd_full_i       : in  std_logic;
		ddr2_wr_en_o          : out std_logic;
		ddr2_wr_mask_o        : out std_logic_vector( 3 downto 0);
		ddr2_wr_data_o        : out std_logic_vector(31 downto 0);
		ddr2_wr_full_i        : in  std_logic;
		ddr2_wr_empty_i       : in  std_logic;
		ddr2_wr_count_i       : in  std_logic_vector( 6 downto 0);
		ddr2_wr_underrun_i    : in  std_logic;
		ddr2_wr_error_i       : in  std_logic
	);
end dvi2ddr;

architecture dvi2ddr of dvi2ddr is
	signal rx_tmds_s                : std_logic_vector(3 downto 0);
	signal rx_color                 : color_t(COLOR_CNT-1 downto 0);
	signal rx_color_en              : std_logic;
	signal rx_pll_lckd              : std_logic;
	signal rx_rst_n                 : std_logic;
	signal rx_pclk                  : std_logic;
	signal rx_hsync                 : std_logic;
	signal rx_vsync                 : std_logic;
begin
	-- ----------------------------------------------------------------------------
	-- HDMI to DDR2
	-- ----------------------------------------------------------------------------
	dvi_decoder_0: entity work.dvi_decoder
	port map (
		ext_rst        => rst,

		tmdsclk_p      => rx_tmds(3),
		tmdsclk_n      => rx_tmds_n(3),
		din_p          => rx_tmds(2 downto 0),
		din_n          => rx_tmds_n(2 downto 0),

		reset_n        => rx_rst_n,    -- rx reset
		pclk_o         => rx_pclk,     -- regenerated pixel clock
		pclkx2_o       => open,         -- double rate pixel clock
		pclkx10_o      => open,         -- 10x pixel as IOCLK

		pll_lckd_o     => rx_pll_lckd,     -- send pll_lckd out so it can be fed into a different BUFPLL
		serdesstrobe_o => open,         -- BUFPLL serdesstrobe output
		tmdsclk_o      => open,         -- TMDS cable clock

		hsync_o        => rx_hsync,    -- hsync data
		vsync_o        => rx_vsync,    -- vsync data
		valid_o        => open,
		ready_o        => open,
		psalgnerr_o    => open,
		sdout_o        => open,
		dat_en_o       => rx_color_en, -- data enable
		color_o        => rx_color
	);

	sig_write_0: entity work.sig_write
	generic map (MEM_START_ADR => "00" & x"0000000")
	port map (
		clk                   => rx_pclk,
		rst_n                 => rx_rst_n,
		ctrl_disable_wr       => ctrl_disable_wr,

		-- memory interface
		ddr2_clk              => clk,
		ddr2_cmd_en_o         => ddr2_cmd_en_o,
		ddr2_cmd_instr_o      => ddr2_cmd_instr_o,
		ddr2_cmd_bl_o         => ddr2_cmd_bl_o,
		ddr2_cmd_byte_addr_o  => ddr2_cmd_byte_addr_o,
		ddr2_cmd_empty_i      => ddr2_cmd_empty_i,
		ddr2_cmd_full_i       => ddr2_cmd_full_i,

		ddr2_wr_en_o          => ddr2_wr_en_o,
		ddr2_wr_mask_o        => ddr2_wr_mask_o,
		ddr2_wr_data_o        => ddr2_wr_data_o,
		ddr2_wr_full_i        => ddr2_wr_full_i,
		ddr2_wr_empty_i       => ddr2_wr_empty_i,
		ddr2_wr_count_i       => ddr2_wr_count_i,
		ddr2_wr_underrun_i    => ddr2_wr_underrun_i,
		ddr2_wr_error_i       => ddr2_wr_error_i,

		-- display output
		hsync_i               => rx_hsync,
		vsync_i               => rx_vsync,
		color_en_i            => rx_color_en,
		color_i               => rx_color
	);

end dvi2ddr;