-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;

ENTITY sig_tb IS
END sig_tb;

ARCHITECTURE rtl OF sig_tb IS
	constant CLK_PERIOD : time := 20 ns;
	signal clk          : std_logic;
	signal rst          : std_logic;
	signal rst_n        : std_logic;
                            
	signal en_stb_i     : std_logic;
	signal hsync_o      : std_logic;
	signal vsync_o      : std_logic;
	signal color_en_o   : std_logic;
	signal color_o      : color_t(COLOR_CNT-1 downto 0);

	signal en_stb_iq    : std_logic;
	signal hsync_oq     : std_logic;
	signal vsync_oq     : std_logic;
	signal color_en_oq  : std_logic;
	signal color_oq     : color_t(COLOR_CNT-1 downto 0);
BEGIN
	rst   <= transport '1', '0' after ( 4 * CLK_PERIOD);
	rst_n <= not rst;

	clock: process
	begin
		clk <= '1', '0' after CLK_PERIOD/2;
		wait for CLK_PERIOD;
	end process;

	reg: process begin
	wait until rising_edge(clk);
		en_stb_iq   <= en_stb_i;
		hsync_o     <= hsync_oq;
		vsync_o     <= vsync_oq;
		color_o     <= color_oq;
		color_en_o  <= color_en_oq;
	end process;

	dut: entity work.sig
	generic map (
		H_ACTIVE_PIXEL => x"500",
		H_BLANKING     => x"198",
		H_SYNC_WIDTH   => x"070",
		H_SYNC_OFFSET  => x"030",
		V_ACTIVE_LINES => x"400",
		V_BLANKING     => x"02a",
		V_SYNC_WIDTH   => x"01",
		V_SYNC_OFFSET  => x"03"
	)
	port map (  
		clk        => clk,
		rst_n      => rst_n,
                           
		en_stb_i   => en_stb_iq,
		hsync_o    => hsync_oq,
		vsync_o    => vsync_oq,
		color_en_o => color_en_oq,
		color_o    => color_oq
	);

	dut2: entity work.vga
	port map (
		pixelClock => clk,
		Red        => open,
		Green      => open,
		Blue       => open,
		hSync      => open,
		vSync      => open,
		blank      => open
	);

	beh: process begin
		en_stb_i <= '0';
		wait for 20*CLK_PERIOD;
		en_stb_i <= '1';
		--wait for CLK_PERIOD;
		--en_stb_i <= '0';
		wait;
	end process;
end rtl;

configuration sig_tb_rtl_cfg of sig_tb is
  for rtl
  end for;
end sig_tb_rtl_cfg;