#FPGA_PART=xc6slx45-3-csg324
CONFIG VCCAUX = 3.3;

##############################################################################
# SYSCLK Input
##############################################################################
NET "clk100" LOC = "L15" | IOSTANDARD = LVCMOS33 | TNM_NET = clk100;
TIMESPEC TS_clk100 = PERIOD "clk100" 100 MHz HIGH 50%;

# Constraint for RX0
NET "dvi2ddr_0/dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;

##############################################################################
# Mechanical Switches (SW)
##############################################################################
NET "switch<0>"         LOC = "A10" |IOSTANDARD = LVCMOS33 ;
#NET "switch<1>"         LOC = "D14" |IOSTANDARD = LVCMOS33 ;
#NET "switch<2>"         LOC = "C14" | IOSTANDARD = LVCMOS33 ;
#NET "switch<3>"         LOC = "P15" | IOSTANDARD = LVCMOS33 ;

#############################################
## TMDS pairs for Atlys top OUT: J2 - Bank 0
#############################################
NET "tx0_tmds(3)"   LOC = "B6" | IOSTANDARD = TMDS_33 ; # Clock
NET "tx0_tmds_n(3)" LOC = "A6" | IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(2)"   LOC = "B8" | IOSTANDARD = TMDS_33 ; # Red
NET "tx0_tmds_n(2)" LOC = "A8" | IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(1)"   LOC = "C7" | IOSTANDARD = TMDS_33 ; # Green
NET "tx0_tmds_n(1)" LOC = "A7" | IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(0)"   LOC = "D8" | IOSTANDARD = TMDS_33 ; # Blue
NET "tx0_tmds_n(0)" LOC = "C8" | IOSTANDARD = TMDS_33 ;

###############################################
## TMDS pairs for Atlys top OUT: JA - Bank 2
## Use TML_33 to add output series termination
###############################################
#NET "tx1_tmds(3)"   LOC = "T9" |IOSTANDARD = TML_33; #TMDS_33 ; ## Clock
#NET "tx1_tmds_n(3)" LOC = "V9" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(2)"   LOC = "N5" |IOSTANDARD = TML_33; #TMDS_33 ; ## Red
#NET "tx1_tmds_n(2)" LOC = "P6" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(1)"   LOC = "T4" |IOSTANDARD = TML_33; #TMDS_33 ; ## Green
#NET "tx1_tmds_n(1)" LOC = "V4" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(0)"   LOC = "R3" |IOSTANDARD = TML_33; #TMDS_33 ; ## Blue
#NET "tx1_tmds_n(0)" LOC = "T3" |IOSTANDARD = TML_33; #TMDS_33 ; #
#
###################################################
## TMDS pairs for Atlys IN (FPGA Bank 1): J3
###################################################
#NET "rx1_tmds(3)"   LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
#NET "rx1_tmds_n(3)" LOC = "H18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(2)"   LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
#NET "rx1_tmds_n(2)" LOC = "J18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(1)"   LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green
#NET "rx1_tmds_n(1)" LOC = "L18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(0)"   LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue
#NET "rx1_tmds_n(0)" LOC = "K18" |IOSTANDARD = TMDS_33 ;
#
###############################################
## TMDS pairs for Atlys IN (FPGA Bank 0): J1
###############################################
NET "rx0_tmds(3)"   LOC = "D11" |IOSTANDARD = TMDS_33 ; # CLK
NET "rx0_tmds_n(3)" LOC = "C11" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(2)"   LOC = "B12" |IOSTANDARD = TMDS_33 ; # Red
NET "rx0_tmds_n(2)" LOC = "A12" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(1)"   LOC = "B11" |IOSTANDARD = TMDS_33 ; # Green
NET "rx0_tmds_n(1)" LOC = "A11" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(0)"   LOC = "G9"  |IOSTANDARD = TMDS_33 ; # Blue
NET "rx0_tmds_n(0)" LOC = "F9"  |IOSTANDARD = TMDS_33 ;
NET "rx0_scl"       LOC = "C13" |IOSTANDARD = LVCMOS33 ;
NET "rx0_sda"       LOC = "A13" |IOSTANDARD = LVCMOS33 ;


########################################
# Reset button and LEDs and Mechanical Switches (SW)
########################################
NET "rstbtn_n" LOC = "T15" | IOSTANDARD = LVCMOS33;
NET "led<0>"   LOC = "U18" | IOSTANDARD = LVCMOS33;
NET "led<1>"   LOC = "M14" | IOSTANDARD = LVCMOS33;
NET "led<2>"   LOC = "N14" | IOSTANDARD = LVCMOS33;
NET "led<3>"   LOC = "L14" | IOSTANDARD = LVCMOS33;
NET "led<4>"   LOC = "M13" | IOSTANDARD = LVCMOS33;
NET "led<5>"   LOC = "D4"  | IOSTANDARD = LVCMOS33;
NET "led<6>"   LOC = "P16" | IOSTANDARD = LVCMOS33;
NET "led<7>"   LOC = "N12" | IOSTANDARD = LVCMOS33;

# Multi-cycle paths for TX0 / encoder_0
TIMEGRP "bramgrp_0" = RAMS(ddr2dvi_0/dvi_encoder_0/pixel2x/data_int<*>);
TIMEGRP "fddbgrp_0" = FFS(ddr2dvi_0/dvi_encoder_0/pixel2x/db<*>);
TIMEGRP "bramra_0"  = FFS(ddr2dvi_0/dvi_encoder_0/pixel2x/ra<*>);
TIMESPEC "TS_ramdo_0" = FROM "bramgrp_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
TIMESPEC "TS_ramra_0" = FROM "bramra_0"  TO "fddbgrp_0" TS_DVI_CLOCK0;

#######################################################################################
#### onBoard USB controller
#######################################################################################
####NET "UsbMode"     LOC = "A5";  # Bank = 0, Pin name = IO_L6N, Sch name = U1-INT0#
NET "usb_clk"     LOC = "C10" | IOSTANDARD = LVCMOS33 | TNM_NET = clk48; # Bank = 0, Pin name = IO_L37P_GCLK13, Sch name = U1-IFCLK
TIMESPEC TS_clk48 = PERIOD "clk48" 48 MHz HIGH 50%;
NET "usb_flag_a"  LOC = "B9"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L35P_GCLK17, Sch name = U1-FLAGA
NET "usb_flag_b"  LOC = "A9"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L35N_GCLK16, Sch name = U1-FLAGB
NET "usb_flag_c"  LOC = "C15" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L64P_SCP5, Sch name = U1-FLAGC
NET "usb_cs"      LOC = "B2"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L2P, Sch name = U1-SLCS
NET "usb_oe"      LOC = "A15" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L64N_SCP4, Sch name = U1-SLOE
NET "usb_rd"      LOC = "F13" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L63P_SCP7, Sch name = U1-SLRD
NET "usb_wr"      LOC = "E13" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L63N_SCP6, Sch name = U1-SLWR
NET "usb_pktend"  LOC = "C4"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L1N_VREF, Sch name = U1-PKTEND
NET "usb_adr<0>"  LOC = "A14" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L62N_VREF, Sch name = U1-FIFOAD0
NET "usb_adr<1>"  LOC = "B14" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L62P, Sch name = U1-FIFOAD1
NET "usb_dat<0>"  LOC = "A2"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L2N, Sch name = U1-FD0
NET "usb_dat<1>"  LOC = "D6"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L3P, Sch name = U1-FD1
NET "usb_dat<2>"  LOC = "C6"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L3N, Sch name = U1-FD2
NET "usb_dat<3>"  LOC = "B3"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L4P, Sch name = U1-FD3
NET "usb_dat<4>"  LOC = "A3"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L4N, Sch name = U1-FD4
NET "usb_dat<5>"  LOC = "B4"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L5P, Sch name = U1-FD5
NET "usb_dat<6>"  LOC = "A4"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L5N, Sch name = U1-FD6
NET "usb_dat<7>"  LOC = "C5"  | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L6P, Sch name = U1-FD7

#######################################################################################
#### SIG READ
#######################################################################################
# FIXME: for now just TIG between the FIFO clocks
TIMESPEC "TS_async_0" = FROM "ddr2dvi_0_pclk_buf" TO "ddr2_0_memc3_infrastructure_inst_clk0_bufg_in" TIG;
TIMESPEC "TS_async_1" = FROM "ddr2_0_memc3_infrastructure_inst_clk0_bufg_in" TO "ddr2dvi_0_pclk_buf" TIG;

#######################################################################################
#### DDR2
#######################################################################################
CONFIG MCB_PERFORMANCE= STANDARD;
NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
#NET "c?_pll_lock" TIG;
#INST "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;

#Please uncomment the below TIG if used in a design which enables self-refresh mode
#NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;

NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
NET "ddr2_dq[*]"  IN_TERM = NONE;
NET "ddr2_dqs"    IN_TERM = NONE;
NET "ddr2_dqs_n"  IN_TERM = NONE;
NET "ddr2_udqs"   IN_TERM = NONE;
NET "ddr2_udqs_n" IN_TERM = NONE;
NET "ddr2_clk"    LOC = "G3" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L46P_M3CLK, Sch name = DDR-CK_P
NET "ddr2_clk_n"  LOC = "G1" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L46N_M3CLKN, Sch name = DDR-CK_N
NET "ddr2_cke"    LOC = "H7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L53P_M3CKE, Sch name = DDR-CKE
NET "ddr2_ras_n"  LOC = "L5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN, Sch name = DDR-RAS
NET "ddr2_cas_n"  LOC = "K5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = DDR-CAS
NET "ddr2_we_n"   LOC = "E3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L50P_M3WE, Sch name = DDR-WE
NET "ddr2_rzq"	  LOC = "L6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L31P, Sch name = RZQ
NET "ddr2_zio"	  LOC = "C2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L83P, Sch name = ZIO

NET "ddr2_ba<0>"  LOC = "F2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L48P_M3BA0, Sch name = DDR-BA0
NET "ddr2_ba<1>"  LOC = "F1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L48N_M3BA1, Sch name = DDR-BA1
NET "ddr2_ba<2>"  LOC = "E1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L50N_M3BA2, Sch name = DDR-BA2

NET "ddr2_a<0>"   LOC = "J7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L47P_M3A0, Sch name = DDR-A0
NET "ddr2_a<1>"   LOC = "J6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L47N_M3A1, Sch name = DDR-A1
NET "ddr2_a<2>"   LOC = "H5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L49N_M3A2, Sch name = DDR-A2
NET "ddr2_a<3>"   LOC = "L7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L45P_M3A3, Sch name = DDR-A3
NET "ddr2_a<4>"   LOC = "F3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L51N_M3A4, Sch name = DDR-A4
NET "ddr2_a<5>"   LOC = "H4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L44P_GCLK21_M3A5, Sch name = DDR-A5
NET "ddr2_a<6>"   LOC = "H3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L44N_GCLK20_M3A6, Sch name = DDR-A6
NET "ddr2_a<7>"   LOC = "H6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L49P_M3A7, Sch name = DDR-A7
NET "ddr2_a<8>"   LOC = "D2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L52P_M3A8, Sch name = DDR-A8
NET "ddr2_a<9>"   LOC = "D1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L52N_M3A9, Sch name = DDR-A9
NET "ddr2_a<10>"  LOC = "F4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L51P_M3A10, Sch name = DDR-A10
NET "ddr2_a<11>"  LOC = "D3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L54N_M3A11, Sch name = DDR-A11
NET "ddr2_a<12>"  LOC = "G6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L53N_M3A12, Sch name = DDR-A12

NET "ddr2_dq<0>"  LOC = "L2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L37P_M3DQ0, Sch name = DDR-DQ0
NET "ddr2_dq<1>"  LOC = "L1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L37N_M3DQ1, Sch name = DDR-DQ1
NET "ddr2_dq<2>"  LOC = "K2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L38P_M3DQ2, Sch name = DDR-DQ2
NET "ddr2_dq<3>"  LOC = "K1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L38N_M3DQ3, Sch name = DDR-DQ3
NET "ddr2_dq<4>"  LOC = "H2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4, Sch name = DDR-DQ4
NET "ddr2_dq<5>"  LOC = "H1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = DDR-DQ5
NET "ddr2_dq<6>"  LOC = "J3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L40P_M3DQ6, Sch name = DDR-DQ6
NET "ddr2_dq<7>"  LOC = "J1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L40N_M3DQ7, Sch name = DDR-DQ7
NET "ddr2_dq<8>"  LOC = "M3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L36P_M3DQ8, Sch name = DDR-DQ8
NET "ddr2_dq<9>"  LOC = "M1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L36N_M3DQ9, Sch name = DDR-DQ9
NET "ddr2_dq<10>" LOC = "N2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L35P_M3DQ10, Sch name = DDR-DQ10
NET "ddr2_dq<11>" LOC = "N1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L35N_M3DQ11, Sch name = DDR-DQ11
NET "ddr2_dq<12>" LOC = "T2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L33P_M3DQ12, Sch name = DDR-DQ12
NET "ddr2_dq<13>" LOC = "T1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L33N_M3DQ13, Sch name = DDR-DQ13
NET "ddr2_dq<14>" LOC = "U2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L32P_M3DQ14, Sch name = DDR-DQ14
NET "ddr2_dq<15>" LOC = "U1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L32N_M3DQ15, Sch name = DDR-DQ15

NET "ddr2_udqs"   LOC="P2" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L34P_M3UDQS, Sch name = DDR-UDQS_P
NET "ddr2_udqs_n" LOC="P1" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L34N_M3UDQSN, Sch name = DDR-UDQS_N
NET "ddr2_dqs"    LOC="L4" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L39P_M3LDQS, Sch name = DDR-LDQS_P
NET "ddr2_dqs_n"  LOC="L3" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L39N_M3LDQSN, Sch name = DDR-LDQS_N
NET "ddr2_dm"     LOC="K3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM, Sch name = DDR-LDM
NET "ddr2_udm"    LOC="K4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM,	Sch name = DDR-UDM
NET "ddr2_odt"    LOC="K6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L45N_M3ODT, Sch name = DDR-ODT

NET "ddr2_zio"    LOC="C2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L83P, Sch name = DDR-ODT
# NET "ddr2_rzm"    LOC="L6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L31P, Sch name = DDR-ODT