259 lines
18 KiB
XML
259 lines
18 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="syn.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="../../fx2/fpga/vendor/xilinx/coregen.log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.ngc" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.vhd" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.ngc" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.vhd" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.vhd" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="../src/ddr2/coregen.log"/>
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<file xil_pn:fileType="FILE_ASY" xil_pn:name="../src/vendor/xilinx/px_fifo.asy" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/px_fifo.ngc" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="../src/vendor/xilinx/px_fifo.sym" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/px_fifo.vhd" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_VHO" xil_pn:name="../src/vendor/xilinx/px_fifo.vho" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/usb_fifo_rx.ngc" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/usb_fifo_rx.vhd" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="../src/vendor/xilinx/usb_fifo_tx.ngc" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VHDL" xil_pn:name="../src/vendor/xilinx/usb_fifo_tx.vhd" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="atlys_sig.bgn" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="atlys_sig.bit" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="atlys_sig.bld"/>
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<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="atlys_sig.cmd_log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="atlys_sig.drc" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="atlys_sig.lso"/>
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<file xil_pn:fileType="FILE_MSK" xil_pn:name="atlys_sig.msk"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig.ncd" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="atlys_sig.ngc"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="atlys_sig.ngd"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="atlys_sig.ngr"/>
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<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="atlys_sig.pad"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="atlys_sig.par" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="atlys_sig.pcf" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="atlys_sig.prj"/>
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<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="atlys_sig.ptwx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="atlys_sig.stx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="atlys_sig.syr"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="atlys_sig.twr" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="atlys_sig.twx" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="atlys_sig.unroutes" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="atlys_sig.ut" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:fileType="FILE_XPI" xil_pn:name="atlys_sig.xpi"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="atlys_sig.xst"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="atlys_sig_envsettings.html"/>
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<file xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig_guide.ncd" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="atlys_sig_map.map" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="atlys_sig_map.mrp" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="atlys_sig_map.ncd" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="atlys_sig_map.ngm" xil_pn:subbranch="Map"/>
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<file xil_pn:fileType="FILE_PSR" xil_pn:name="atlys_sig_map.psr"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_map.xrpt"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_ngdbuild.xrpt"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="atlys_sig_pad.csv" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="atlys_sig_pad.txt" xil_pn:subbranch="Par"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_par.xrpt"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="atlys_sig_summary.html"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="atlys_sig_summary.xml"/>
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<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="atlys_sig_usage.xml"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="atlys_sig_xst.xrpt"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1379695224">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-6498325036265346234" xil_pn:start_ts="1379695224">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1381750723" xil_pn:in_ck="-4990497755435147446" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8579041901420796151" xil_pn:start_ts="1381750722">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.ngc"/>
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<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_rx.vhd"/>
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<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.ngc"/>
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<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx.vhd"/>
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<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.ngc"/>
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<outfile xil_pn:name="../../fx2/fpga/vendor/xilinx/usb_fifo_tx_fin.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_controller.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_mcb_controller.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_raw_wrapper.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration_top.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_infrastructure.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/memc3_wrapper.vhd"/>
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<outfile xil_pn:name="../src/vendor/xilinx/px_fifo.ngc"/>
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<outfile xil_pn:name="../src/vendor/xilinx/px_fifo.vhd"/>
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<transform xil_pn:end_ts="1381750752" xil_pn:in_ck="-5754007203490239776" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3327302063185124304" xil_pn:start_ts="1381750723">
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<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
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<outfile xil_pn:name="atlys_sig.lso"/>
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<outfile xil_pn:name="atlys_sig.ngr"/>
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<outfile xil_pn:name="atlys_sig.stx"/>
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<outfile xil_pn:name="atlys_sig.syr"/>
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<outfile xil_pn:name="atlys_sig.xst"/>
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<outfile xil_pn:name="webtalk_pn.xml"/>
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<outfile xil_pn:name="xst"/>
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<transform xil_pn:end_ts="1379695258" xil_pn:in_ck="-2812728212376607396" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-4408915874172682627" xil_pn:start_ts="1379695258">
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<status xil_pn:value="SuccessfullyRun"/>
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<transform xil_pn:end_ts="1381750764" xil_pn:in_ck="-5271234473535174591" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7713896191513598818" xil_pn:start_ts="1381750752">
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<transform xil_pn:end_ts="1381750888" xil_pn:in_ck="4790132884118110510" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1381750841">
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<transform xil_pn:end_ts="1375166772" xil_pn:in_ck="-2821415870385197295" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1375166762">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputChanged"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1381750888" xil_pn:in_ck="-2821415870385197295" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1381750879">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
|
<outfile xil_pn:name="atlys_sig.twr"/>
|
|
<outfile xil_pn:name="atlys_sig.twx"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1375175447" xil_pn:in_ck="4790132884118110510" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791353" xil_pn:start_ts="1375175447">
|
|
<status xil_pn:value="FailedRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputChanged"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1377159094" xil_pn:in_ck="-2821415870385197163" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1377159094">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputChanged"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
</transform>
|
|
</transforms>
|
|
|
|
</generated_project>
|