372 lines
13 KiB
VHDL
372 lines
13 KiB
VHDL
---------------------------------------------------------------------
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---- ----
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---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
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---- ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2000 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- CVS Log
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--
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-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
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--
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-- $Date: 2004/02/18 11:41:48 $
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-- $Revision: 1.5 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: i2c_master_byte_ctrl.vhd,v $
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-- Revision 1.5 2004/02/18 11:41:48 rherveille
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-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
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--
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-- Revision 1.4 2003/08/09 07:01:13 rherveille
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-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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-- Fixed a potential bug in the byte controller's host-acknowledge generation.
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--
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-- Revision 1.3 2002/12/26 16:05:47 rherveille
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-- Core is now a Multimaster I2C controller.
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--
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-- Revision 1.2 2002/11/30 22:24:37 rherveille
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-- Cleaned up code
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--
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-- Revision 1.1 2001/11/05 12:02:33 rherveille
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-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
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-- Code updated, is now up-to-date to doc. rev.0.4.
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-- Added headers.
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--
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--
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------------------------------------------
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-- Byte controller section
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------------------------------------------
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_Logic_unsigned.all;
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use IEEE.numeric_std.all;
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entity i2c_master_byte_ctrl is
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port (
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clk : in std_logic;
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rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
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nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
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ena : in std_logic; -- core enable signal
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clk_cnt : in unsigned(15 downto 0); -- 4x SCL
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-- input signals
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start,
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stop,
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read,
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write,
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ack_in : std_logic;
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din : in std_logic_vector(7 downto 0);
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-- output signals
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cmd_ack : out std_logic; -- command done
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ack_out : out std_logic;
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i2c_busy : out std_logic; -- arbitration lost
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i2c_al : out std_logic; -- i2c bus busy
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dout : out std_logic_vector(7 downto 0);
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-- i2c lines
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scl_i : in std_logic; -- i2c clock line input
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scl_o : out std_logic; -- i2c clock line output
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scl_oen : out std_logic; -- i2c clock line output enable, active low
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sda_i : in std_logic; -- i2c data line input
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sda_o : out std_logic; -- i2c data line output
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sda_oen : out std_logic -- i2c data line output enable, active low
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);
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end entity i2c_master_byte_ctrl;
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architecture structural of i2c_master_byte_ctrl is
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component i2c_master_bit_ctrl is
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port (
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clk : in std_logic;
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rst : in std_logic;
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nReset : in std_logic;
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ena : in std_logic; -- core enable signal
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clk_cnt : in unsigned(15 downto 0); -- clock prescale value
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cmd : in std_logic_vector(3 downto 0);
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cmd_ack : out std_logic; -- command done
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busy : out std_logic; -- i2c bus busy
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al : out std_logic; -- arbitration lost
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din : in std_logic;
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dout : out std_logic;
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-- i2c lines
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scl_i : in std_logic; -- i2c clock line input
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scl_o : out std_logic; -- i2c clock line output
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scl_oen : out std_logic; -- i2c clock line output enable, active low
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sda_i : in std_logic; -- i2c data line input
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sda_o : out std_logic; -- i2c data line output
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sda_oen : out std_logic -- i2c data line output enable, active low
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);
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end component i2c_master_bit_ctrl;
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-- commands for bit_controller block
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constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
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constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
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constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
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constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
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constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
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-- signals for bit_controller
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signal core_cmd : std_logic_vector(3 downto 0);
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signal core_ack, core_txd, core_rxd : std_logic;
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signal al : std_logic;
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-- signals for shift register
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signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
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signal shift, ld : std_logic;
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-- signals for state machine
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signal go, host_ack : std_logic;
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signal dcnt : unsigned(2 downto 0); -- data counter
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signal cnt_done : std_logic;
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begin
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-- hookup bit_controller
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bit_ctrl: i2c_master_bit_ctrl port map(
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clk => clk,
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rst => rst,
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nReset => nReset,
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ena => ena,
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clk_cnt => clk_cnt,
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cmd => core_cmd,
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cmd_ack => core_ack,
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busy => i2c_busy,
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al => al,
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din => core_txd,
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dout => core_rxd,
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scl_i => scl_i,
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scl_o => scl_o,
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scl_oen => scl_oen,
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sda_i => sda_i,
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sda_o => sda_o,
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sda_oen => sda_oen
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);
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i2c_al <= al;
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-- generate host-command-acknowledge
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cmd_ack <= host_ack;
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-- generate go-signal
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go <= (read or write or stop) and not host_ack;
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-- assign Dout output to shift-register
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dout <= sr;
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-- generate shift register
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shift_register: process(clk, nReset)
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begin
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if (nReset = '0') then
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sr <= (others => '0');
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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sr <= (others => '0');
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elsif (ld = '1') then
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sr <= din;
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elsif (shift = '1') then
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sr <= (sr(6 downto 0) & core_rxd);
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end if;
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end if;
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end process shift_register;
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-- generate data-counter
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data_cnt: process(clk, nReset)
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begin
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if (nReset = '0') then
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dcnt <= (others => '0');
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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dcnt <= (others => '0');
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elsif (ld = '1') then
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dcnt <= (others => '1'); -- load counter with 7
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elsif (shift = '1') then
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dcnt <= dcnt -1;
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end if;
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end if;
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end process data_cnt;
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cnt_done <= '1' when (dcnt = 0) else '0';
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--
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-- state machine
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--
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statemachine : block
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type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
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signal c_state : states;
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begin
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--
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-- command interpreter, translate complex commands into simpler I2C commands
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--
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nxt_state_decoder: process(clk, nReset)
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begin
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if (nReset = '0') then
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core_cmd <= I2C_CMD_NOP;
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core_txd <= '0';
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shift <= '0';
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ld <= '0';
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host_ack <= '0';
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c_state <= st_idle;
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ack_out <= '0';
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elsif (clk'event and clk = '1') then
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if (rst = '1' or al = '1') then
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core_cmd <= I2C_CMD_NOP;
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core_txd <= '0';
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shift <= '0';
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ld <= '0';
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host_ack <= '0';
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c_state <= st_idle;
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ack_out <= '0';
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else
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-- initialy reset all signal
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core_txd <= sr(7);
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shift <= '0';
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ld <= '0';
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host_ack <= '0';
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case c_state is
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when st_idle =>
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if (go = '1') then
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if (start = '1') then
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c_state <= st_start;
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core_cmd <= I2C_CMD_START;
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elsif (read = '1') then
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c_state <= st_read;
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core_cmd <= I2C_CMD_READ;
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elsif (write = '1') then
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c_state <= st_write;
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core_cmd <= I2C_CMD_WRITE;
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else -- stop
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c_state <= st_stop;
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core_cmd <= I2C_CMD_STOP;
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end if;
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ld <= '1';
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end if;
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when st_start =>
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if (core_ack = '1') then
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if (read = '1') then
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c_state <= st_read;
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core_cmd <= I2C_CMD_READ;
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else
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c_state <= st_write;
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core_cmd <= I2C_CMD_WRITE;
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end if;
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ld <= '1';
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end if;
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when st_write =>
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if (core_ack = '1') then
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if (cnt_done = '1') then
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c_state <= st_ack;
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core_cmd <= I2C_CMD_READ;
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else
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c_state <= st_write; -- stay in same state
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core_cmd <= I2C_CMD_WRITE; -- write next bit
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shift <= '1';
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end if;
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end if;
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when st_read =>
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if (core_ack = '1') then
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if (cnt_done = '1') then
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c_state <= st_ack;
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core_cmd <= I2C_CMD_WRITE;
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else
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c_state <= st_read; -- stay in same state
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core_cmd <= I2C_CMD_READ; -- read next bit
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end if;
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shift <= '1';
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core_txd <= ack_in;
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end if;
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when st_ack =>
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if (core_ack = '1') then
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-- check for stop; Should a STOP command be generated ?
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if (stop = '1') then
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c_state <= st_stop;
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core_cmd <= I2C_CMD_STOP;
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else
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c_state <= st_idle;
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core_cmd <= I2C_CMD_NOP;
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-- generate command acknowledge signal
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host_ack <= '1';
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end if;
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-- assign ack_out output to core_rxd (contains last received bit)
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ack_out <= core_rxd;
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core_txd <= '1';
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else
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core_txd <= ack_in;
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end if;
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when st_stop =>
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if (core_ack = '1') then
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c_state <= st_idle;
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core_cmd <= I2C_CMD_NOP;
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-- generate command acknowledge signal
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host_ack <= '1';
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end if;
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when others => -- illegal states
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c_state <= st_idle;
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core_cmd <= I2C_CMD_NOP;
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report ("Byte controller entered illegal state.");
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end case;
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end if;
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end if;
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end process nxt_state_decoder;
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end block statemachine;
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end architecture structural;
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