367 lines
14 KiB
VHDL
367 lines
14 KiB
VHDL
---------------------------------------------------------------------
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---- ----
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---- WISHBONE revB2 compl. I2C Master Core; top level ----
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---- ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2000 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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-- CVS Log
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--
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-- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $
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--
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-- $Date: 2004/03/14 10:17:03 $
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-- $Revision: 1.7 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: i2c_master_top.vhd,v $
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-- Revision 1.7 2004/03/14 10:17:03 rherveille
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-- Fixed simulation issue when writing to CR register
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--
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-- Revision 1.6 2003/08/09 07:01:13 rherveille
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-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
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-- Fixed a potential bug in the byte controller's host-acknowledge generation.
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--
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-- Revision 1.5 2003/02/01 02:03:06 rherveille
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-- Fixed a few 'arbitration lost' bugs. VHDL version only.
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--
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-- Revision 1.4 2002/12/26 16:05:47 rherveille
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-- Core is now a Multimaster I2C controller.
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--
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-- Revision 1.3 2002/11/30 22:24:37 rherveille
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-- Cleaned up code
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--
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-- Revision 1.2 2001/11/10 10:52:44 rherveille
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-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
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--
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--library ieee;
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--use ieee.std_logic_1164.all;
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--use ieee.std_logic_arith.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_Logic_unsigned.all;
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use IEEE.numeric_std.all;
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entity i2c_master_top is
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generic(
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ARST_LVL : std_logic := '0' -- asynchronous reset level
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);
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port (
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-- wishbone signals
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wb_clk_i : in std_logic; -- master clock input
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wb_rst_i : in std_logic := '0'; -- synchronous active high reset
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arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
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-- wb_adr_i : in unsigned(2 downto 0); -- lower address bits
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wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
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wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
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wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
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wb_we_i : in std_logic; -- Write enable input
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wb_stb_i : in std_logic; -- Strobe signals / core select signal
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wb_cyc_i : in std_logic; -- Valid bus cycle input
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wb_ack_o : out std_logic; -- Bus cycle acknowledge output
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wb_inta_o : out std_logic; -- interrupt request output signal
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-- i2c lines
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scl_pad_i : in std_logic; -- i2c clock line input
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scl_pad_o : out std_logic; -- i2c clock line output
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scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
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sda_pad_i : in std_logic; -- i2c data line input
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sda_pad_o : out std_logic; -- i2c data line output
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sda_padoen_o : out std_logic -- i2c data line output enable, active low
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);
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end entity i2c_master_top;
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architecture structural of i2c_master_top is
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-- component i2c_master_byte_ctrl is
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-- port (
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-- clk : in std_logic;
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-- rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
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-- nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
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-- ena : in std_logic; -- core enable signal
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--
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-- clk_cnt : in unsigned(15 downto 0); -- 4x SCL
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--
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-- -- input signals
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-- start,
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-- stop,
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-- read,
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-- write,
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-- ack_in : std_logic;
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-- din : in std_logic_vector(7 downto 0);
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--
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-- -- output signals
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-- cmd_ack : out std_logic;
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-- ack_out : out std_logic;
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-- i2c_busy : out std_logic;
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-- i2c_al : out std_logic;
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-- dout : out std_logic_vector(7 downto 0);
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--
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-- -- i2c lines
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-- scl_i : in std_logic; -- i2c clock line input
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-- scl_o : out std_logic; -- i2c clock line output
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-- scl_oen : out std_logic; -- i2c clock line output enable, active low
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-- sda_i : in std_logic; -- i2c data line input
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-- sda_o : out std_logic; -- i2c data line output
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-- sda_oen : out std_logic -- i2c data line output enable, active low
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-- );
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-- end component i2c_master_byte_ctrl;
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-- registers
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signal prer : unsigned(15 downto 0); -- clock prescale register
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signal ctr : std_logic_vector(7 downto 0); -- control register
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signal txr : std_logic_vector(7 downto 0); -- transmit register
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signal rxr : std_logic_vector(7 downto 0); -- receive register
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signal cr : std_logic_vector(7 downto 0); -- command register
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signal sr : std_logic_vector(7 downto 0); -- status register
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-- internal reset signal
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signal rst_i : std_logic;
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-- wishbone write access
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signal wb_wacc : std_logic;
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-- internal acknowledge signal
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signal iack_o : std_logic;
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-- done signal: command completed, clear command register
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signal done : std_logic;
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-- command register signals
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signal sta, sto, rd, wr, ack, iack : std_logic;
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signal core_en : std_logic; -- core enable signal
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signal ien : std_logic; -- interrupt enable signal
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-- status register signals
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signal irxack, rxack : std_logic; -- received aknowledge from slave
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signal tip : std_logic; -- transfer in progress
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signal irq_flag : std_logic; -- interrupt pending flag
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signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
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signal i2c_al, al : std_logic; -- arbitration lost
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begin
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-- generate internal reset signal
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rst_i <= arst_i xor ARST_LVL;
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-- generate acknowledge output signal
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gen_ack_o : process(wb_clk_i)
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begin
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if (wb_clk_i'event and wb_clk_i = '1') then
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iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
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end if;
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end process gen_ack_o;
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wb_ack_o <= iack_o;
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-- generate wishbone write access signal
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wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
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-- assign wb_dat_o
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assign_dato : process(wb_clk_i)
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begin
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if (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_stb_i = '1' and wb_we_i = '0') then
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case wb_adr_i is
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when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
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when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
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when "010" => wb_dat_o <= ctr;
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when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
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when "100" => wb_dat_o <= sr; -- write is command register CR
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-- Debugging registers:
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-- These registers are not documented.
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-- Functionality could change in future releases
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when "101" => wb_dat_o <= txr;
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when "110" => wb_dat_o <= cr;
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when "111" => wb_dat_o <= x"23"; --(others => '0');
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when others => wb_dat_o <= (others => 'X'); -- for simulation only
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end case;
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else
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wb_dat_o <= (others => '0');
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end if;
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end if;
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end process assign_dato;
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-- generate registers (CR, SR see below)
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gen_regs: process(rst_i, wb_clk_i)
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begin
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if (rst_i = '0') then
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prer <= (others => '1');
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ctr <= (others => '0');
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txr <= (others => '0');
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_rst_i = '1') then
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prer <= (others => '1');
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ctr <= (others => '0');
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txr <= (others => '0');
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elsif (wb_wacc = '1') then
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case wb_adr_i is
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when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
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when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
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when "010" => ctr <= wb_dat_i;
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when "011" => txr <= wb_dat_i;
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when "100" => null; --write to CR, avoid executing the others clause
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-- illegal cases, for simulation only
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when others =>
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report ("Illegal write address, setting all registers to unknown.");
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prer <= (others => 'X');
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ctr <= (others => 'X');
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txr <= (others => 'X');
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end case;
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end if;
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end if;
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end process gen_regs;
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-- generate command register
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gen_cr: process(rst_i, wb_clk_i)
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begin
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if (rst_i = '0') then
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cr <= (others => '0');
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_rst_i = '1') then
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cr <= (others => '0');
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elsif (wb_wacc = '1') then
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if ( (core_en = '1') and (wb_adr_i = 4) ) then
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-- only take new commands when i2c core enabled
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-- pending commands are finished
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cr <= wb_dat_i;
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end if;
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else
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if (done = '1' or i2c_al = '1') then
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cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
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end if;
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cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
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cr(0) <= '0'; -- clear IRQ_ACK bit
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end if;
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end if;
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end process gen_cr;
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-- decode command register
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sta <= cr(7);
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sto <= cr(6);
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rd <= cr(5);
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wr <= cr(4);
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ack <= cr(3);
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iack <= cr(0);
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-- decode control register
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core_en <= ctr(7);
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ien <= ctr(6);
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-- hookup byte controller block
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byte_ctrl: entity work.i2c_master_byte_ctrl port map (
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clk => wb_clk_i,
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rst => wb_rst_i,
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nReset => rst_i,
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ena => core_en,
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clk_cnt => prer,
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start => sta,
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stop => sto,
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read => rd,
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write => wr,
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ack_in => ack,
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i2c_busy => i2c_busy,
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i2c_al => i2c_al,
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din => txr,
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cmd_ack => done,
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ack_out => irxack,
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dout => rxr,
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scl_i => scl_pad_i,
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scl_o => scl_pad_o,
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scl_oen => scl_padoen_o,
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sda_i => sda_pad_i,
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sda_o => sda_pad_o,
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sda_oen => sda_padoen_o
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);
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-- status register block + interrupt request signal
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st_irq_block : block
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begin
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-- generate status register bits
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gen_sr_bits: process (wb_clk_i, rst_i)
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begin
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if (rst_i = '0') then
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al <= '0';
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rxack <= '0';
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tip <= '0';
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irq_flag <= '0';
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_rst_i = '1') then
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al <= '0';
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rxack <= '0';
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tip <= '0';
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irq_flag <= '0';
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else
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al <= i2c_al or (al and not sta);
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rxack <= irxack;
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tip <= (rd or wr);
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-- interrupt request flag is always generated
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irq_flag <= (done or i2c_al or irq_flag) and not iack;
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end if;
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end if;
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end process gen_sr_bits;
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-- generate interrupt request signals
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gen_irq: process (wb_clk_i, rst_i)
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begin
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if (rst_i = '0') then
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wb_inta_o <= '0';
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elsif (wb_clk_i'event and wb_clk_i = '1') then
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if (wb_rst_i = '1') then
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wb_inta_o <= '0';
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else
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-- interrupt signal is only generated when IEN (interrupt enable bit) is set
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wb_inta_o <= irq_flag and ien;
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end if;
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end if;
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end process gen_irq;
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-- assign status register bits
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sr(7) <= rxack;
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sr(6) <= i2c_busy;
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sr(5) <= al;
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sr(4 downto 2) <= (others => '0'); -- reserved
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sr(1) <= tip;
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sr(0) <= irq_flag;
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end block;
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end architecture structural;
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