132 lines
3.8 KiB
VHDL
132 lines
3.8 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity sim_tb is
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end sim_tb;
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architecture rtl of sim_tb is
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constant CLK_PERIOD : time := 10 ns;
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signal clk : std_logic;
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signal rst : std_logic;
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signal rst_n : std_logic;
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component i2c_wrapper is
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generic ( prescale : std_logic_vector(15 downto 0) := x"00c8");
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port (
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wb_clk_i : in std_logic;
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wb_rst_i : in std_logic;
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wb_adr_i : in std_logic_vector(15 downto 0);
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wb_dat_i : in std_logic_vector(7 downto 0);
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wb_dat_o : out std_logic_vector(7 downto 0);
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wb_we_i : in std_logic;
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wb_stb_i : in std_logic;
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wb_ack_o : out std_logic;
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scl_i : in std_logic;
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scl_o : out std_logic;
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sda_i : in std_logic;
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sda_o : out std_logic;
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debug : out std_logic_vector(3 downto 0)
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);
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end component;
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component i2c_rom is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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sda_i : in std_logic;
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sda_o : out std_logic;
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scl_i : in std_logic
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);
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end component;
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signal wb_clk_i : std_logic;
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signal wb_rst_i : std_logic;
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signal wb_adr_i : std_logic_vector(15 downto 0);
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signal wb_dat_i : std_logic_vector(7 downto 0);
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signal wb_dat_o : std_logic_vector(7 downto 0);
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signal wb_we_i : std_logic;
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signal wb_stb_i : std_logic;
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signal wb_ack_o : std_logic;
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signal scl_wi : std_logic;
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signal scl_wo : std_logic;
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signal sda_wi : std_logic;
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signal sda_wo : std_logic;
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signal debug : std_logic_vector(3 downto 0);
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signal sda_ro : std_logic;
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begin
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rst <= transport '1', '0' after (4 * CLK_PERIOD);
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rst_n <= not rst;
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clock: process begin
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clk <= '1', '0' after CLK_PERIOD/2;
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wait for CLK_PERIOD;
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end process;
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wb_clk_i <= clk;
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wb_rst_i <= rst;
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beh_mst: process
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begin
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wb_dat_i <= x"00";
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wb_we_i <= '0';
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wb_adr_i <= x"6a08";
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wb_stb_i <= '0';
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wait for 20*CLK_PERIOD;
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wb_stb_i <= '1';
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wait until wb_ack_o = '1';
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wb_stb_i <= '0';
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wait;
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end process beh_mst;
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DUT_MST: i2c_wrapper
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port map (
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wb_clk_i => wb_clk_i,
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wb_rst_i => wb_rst_i,
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wb_adr_i => wb_adr_i,
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wb_dat_i => wb_dat_i,
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wb_dat_o => wb_dat_o,
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wb_we_i => wb_we_i,
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wb_stb_i => wb_stb_i,
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wb_ack_o => wb_ack_o,
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scl_i => scl_wi,
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scl_o => scl_wo,
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sda_i => sda_wi,
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sda_o => sda_wo
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);
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scl_wi <= scl_wo;
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sda_wi <= '1' when sda_ro = 'Z' else
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'0' when sda_ro = '0' else sda_wo;
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DUT: i2c_rom
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port map (
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clk => wb_clk_i,
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rst_n => rst_n,
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sda_i => sda_wo,
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sda_o => sda_ro,
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scl_i => scl_wo
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);
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end rtl;
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