195 lines
6.7 KiB
VHDL
195 lines
6.7 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.dvi_package.all;
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library UNISIM;
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use UNISIM.Vcomponents.all;
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entity ddr2dvi is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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rst_pll : in std_logic;
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tx_tmds : out std_logic_vector(3 downto 0);
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tx_tmds_n : out std_logic_vector(3 downto 0);
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tx_pll_locked_o : out std_logic;
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-- memory interface
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ddr2_cmd_en_o : out std_logic;
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ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0);
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ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0);
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ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0);
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ddr2_cmd_empty_i : in std_logic;
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ddr2_cmd_full_i : in std_logic;
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ddr2_rd_en_o : out std_logic;
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ddr2_rd_data_i : in std_logic_vector(31 downto 0);
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ddr2_rd_full_i : in std_logic;
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ddr2_rd_empty_i : in std_logic;
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ddr2_rd_count_i : in std_logic_vector( 6 downto 0);
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ddr2_rd_overflow_i : in std_logic;
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ddr2_rd_error_i : in std_logic
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);
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end ddr2dvi;
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architecture ddr2dvi of ddr2dvi is
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signal pclk : std_logic;
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signal pclk_buf : std_logic;
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signal tx_hsync : std_logic;
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signal tx_vsync : std_logic;
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signal tx_color_en : std_logic;
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signal tx_color : color_t(COLOR_CNT-1 downto 0);
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signal tx_pclkx2 : std_logic;
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signal tx_pclkx10 : std_logic;
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signal tx_reset_n : std_logic;
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signal tx_serdesstrobe : std_logic;
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signal tx_clkfbout : std_logic;
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signal tx_clkfbin : std_logic;
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signal tx_plllckd : std_logic;
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signal tx_pllclk0 : std_logic;
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signal tx_pllclk2 : std_logic;
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signal tx_bufpll_lock : std_logic;
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begin
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tx_pll_locked_o <= tx_plllckd;
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-- ----------------------------------------------------------------------------
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-- DDR2 READ Signal Generator
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-- ----------------------------------------------------------------------------
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sig_read_0: entity work.sig_read
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generic map (
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MEM_START_ADR => "00" & x"0000000",
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H_ACTIVE_PIXEL => x"500",
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H_BLANKING => x"198",
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H_SYNC_WIDTH => x"070",
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H_SYNC_OFFSET => x"030",
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V_ACTIVE_LINES => x"400",
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V_BLANKING => x"02a",
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V_SYNC_WIDTH => x"01",
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V_SYNC_OFFSET => x"03"
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)
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port map (
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clk => pclk,
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rst_n => rst_n,
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-- memory interface
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ddr2_clk => clk,
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ddr2_cmd_en_o => ddr2_cmd_en_o,
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ddr2_cmd_instr_o => ddr2_cmd_instr_o,
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ddr2_cmd_bl_o => ddr2_cmd_bl_o,
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ddr2_cmd_byte_addr_o => ddr2_cmd_byte_addr_o,
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ddr2_cmd_empty_i => ddr2_cmd_empty_i,
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ddr2_cmd_full_i => ddr2_cmd_full_i,
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ddr2_rd_en_o => ddr2_rd_en_o,
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ddr2_rd_data_i => ddr2_rd_data_i,
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ddr2_rd_full_i => ddr2_rd_full_i,
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ddr2_rd_empty_i => ddr2_rd_empty_i,
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ddr2_rd_count_i => ddr2_rd_count_i,
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ddr2_rd_overflow_i => ddr2_rd_overflow_i,
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ddr2_rd_error_i => ddr2_rd_error_i,
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en_stb_i => '1',
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hsync_o => tx_hsync,
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vsync_o => tx_vsync,
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color_en_o => tx_color_en,
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color_o => tx_color
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);
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-- ----------------------------------------------------------------------------
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-- Instantiate a dedicate PLL for output port
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-- ----------------------------------------------------------------------------
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--pclk <= ddr2_clk_out;
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pll_oserdes_0: PLL_BASE
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generic map (
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CLKIN_PERIOD => 9.0,
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CLKFBOUT_MULT => 29, --10 --set VCO to 10x of CLKIN
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DIVCLK_DIVIDE => 3,
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CLKOUT0_DIVIDE => 1,
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CLKOUT1_DIVIDE => 10,
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CLKOUT2_DIVIDE => 5,
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COMPENSATION => "SOURCE_SYNCHRONOUS"
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)
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port map (
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CLKFBOUT => tx_clkfbout,
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CLKOUT0 => tx_pllclk0,
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CLKOUT1 => pclk_buf,
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CLKOUT2 => tx_pllclk2,
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CLKOUT3 => open,
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CLKOUT4 => open,
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CLKOUT5 => open,
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LOCKED => tx_plllckd,
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CLKFBIN => tx_clkfbin,
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CLKIN => clk,
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RST => rst_pll
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);
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pclk_buf_0: BUFG port map(I => pclk_buf, O => pclk);
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-- ----------------------------------------------------------------------------
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-- This BUFG is needed in order to deskew between PLL clkin and clkout
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-- So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input
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-- ----------------------------------------------------------------------------
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tx_clkfb_buf: BUFG port map(I => tx_clkfbout, O => tx_clkfbin);
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-- --------------------------------
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-- regenerate pclkx2 for TX
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-- --------------------------------
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tx_pclkx2_buf: BUFG port map(I => tx_pllclk2, O => tx_pclkx2);
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-- --------------------------------
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-- regenerate pclkx10 for TX
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-- --------------------------------
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tx_ioclk_buf: BUFPLL
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generic map ( DIVIDE => 5 )
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port map (
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PLLIN => tx_pllclk0,
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GCLK => tx_pclkx2,
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LOCKED => tx_plllckd,
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IOCLK => tx_pclkx10,
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SERDESSTROBE => tx_serdesstrobe,
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LOCK => tx_bufpll_lock
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);
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tx_reset_n <= tx_bufpll_lock;
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dvi_encoder_0: entity work.dvi_encoder
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port map (
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rst_n => tx_reset_n,
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pclk => pclk,
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pclkx2 => tx_pclkx2,
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pclkx10 => tx_pclkx10,
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serdesstrobe_i => tx_serdesstrobe,
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color_i => tx_color,
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hsync_i => tx_hsync,
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vsync_i => tx_vsync,
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dat_en_i => tx_color_en,
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tmds_p => tx_tmds,
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tmds_n => tx_tmds_n
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);
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end ddr2dvi;
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