128 lines
4.6 KiB
VHDL
128 lines
4.6 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.dvi_package.all;
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entity sig is
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generic (
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H_ACTIVE_PIXEL : unsigned(11 downto 0) := x"5a0";
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H_BLANKING : unsigned(11 downto 0) := x"0dd";
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H_SYNC_WIDTH : unsigned(11 downto 0) := x"03c";
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H_SYNC_OFFSET : unsigned(11 downto 0) := x"050"; -- front porch
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V_ACTIVE_LINES : unsigned(11 downto 0) := x"21c";
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V_BLANKING : unsigned(11 downto 0) := x"022";
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V_SYNC_WIDTH : unsigned( 7 downto 0) := x"02";
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V_SYNC_OFFSET : unsigned( 7 downto 0) := x"18" -- front porch
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- memory interface
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--address_o : out std_logic_vector();
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-- display output
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en_stb_i : in std_logic;
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hsync_o : out std_logic;
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vsync_o : out std_logic;
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color_en_o : out std_logic;
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color_o : out color_t
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);
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end sig;
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architecture sig of sig is
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signal h_cnt : unsigned(11 downto 0);
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signal v_cnt : unsigned(11 downto 0);
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signal one_screen : std_logic;
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signal h_state : unsigned(1 downto 0);
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signal h_state_i : unsigned(1 downto 0);
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signal v_state : unsigned(1 downto 0);
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signal v_state_i : unsigned(1 downto 0);
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constant SYNC_OFF : unsigned(1 downto 0) := "00";
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constant SYNC : unsigned(1 downto 0) := "01";
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constant SYNC_BACK : unsigned(1 downto 0) := "10";
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constant ACTIVE_LINE : unsigned(1 downto 0) := "11";
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constant H_SYNC_BACK : unsigned(11 downto 0) := H_BLANKING - H_SYNC_OFFSET - H_SYNC_WIDTH;
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constant V_SYNC_BACK : unsigned(11 downto 0) := V_BLANKING - V_SYNC_OFFSET - V_SYNC_WIDTH;
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begin
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hsync_o <= '1' when h_state = SYNC and v_state = ACTIVE_LINE else '0';
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vsync_o <= '1' when v_state = SYNC else '0';
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color_en_o <= '1' when h_state = ACTIVE_LINE and v_state = ACTIVE_LINE else '0';
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color_o <= ((others => v_cnt(3)), (others => v_cnt(2)), (others => v_cnt(1)));
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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h_cnt <= x"000";
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v_cnt <= x"000";
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v_state <= "00";
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v_state_i <= "00";
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h_state <= "00";
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h_state_i <= "00";
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one_screen <= '0';
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elsif rising_edge(clk) then
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if v_state = ACTIVE_LINE and v_cnt = x"000" then
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one_screen <= '0';
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elsif en_stb_i = '1' then
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one_screen <= '1';
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end if;
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if one_screen = '1' and h_cnt = x"000" then
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h_state <= h_state_i;
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case h_state_i is
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when SYNC_OFF => h_cnt <= H_SYNC_OFFSET-1;
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when SYNC => h_cnt <= H_SYNC_WIDTH-1;
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when SYNC_BACK => h_cnt <= H_SYNC_BACK-1;
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when ACTIVE_LINE => h_cnt <= H_ACTIVE_PIXEL-1;
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when others => h_cnt <= x"000";
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end case;
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elsif h_cnt /= x"000" then
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h_cnt <= h_cnt - "1";
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end if;
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if one_screen = '1' and h_cnt = x"000" then
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h_state_i <= h_state_i + "01";
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end if;
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if one_screen = '1' and v_cnt = x"000" and h_state = SYNC_OFF then
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v_state <= v_state_i;
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case v_state_i is
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when SYNC_OFF => v_cnt <= x"0" & V_SYNC_OFFSET;
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when SYNC => v_cnt <= x"0" & V_SYNC_WIDTH;
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when SYNC_BACK => v_cnt <= V_SYNC_BACK;
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when ACTIVE_LINE => v_cnt <= V_ACTIVE_LINES;
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when others => v_cnt <= x"000";
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end case;
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elsif v_cnt /= x"000" and (h_state = ACTIVE_LINE and h_cnt = x"000") then
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v_cnt <= v_cnt - "1";
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end if;
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if one_screen = '1' and v_cnt = x"000" then
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v_state_i <= v_state_i + "01";
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end if;
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end if;
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end process;
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end sig;
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