hdet/fpga/src/sig/sig_write.vhd

-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;

entity sig_write is
	generic (
		MEM_START_ADR  : unsigned(29 downto 0) := "00" & x"0000000"
	);
	port (
		clk                   : in  std_logic;
		rst_n                 : in  std_logic;
		ctrl_disable_wr       : in  std_logic;

		-- memory interface
		ddr2_clk              : in  std_logic;
		ddr2_cmd_en_o         : out std_logic;
		ddr2_cmd_instr_o      : out std_logic_vector( 2 downto 0);
		ddr2_cmd_bl_o         : out std_logic_vector( 5 downto 0);
		ddr2_cmd_byte_addr_o  : out std_logic_vector(29 downto 0);
		ddr2_cmd_empty_i      : in  std_logic;
		ddr2_cmd_full_i       : in  std_logic;

		ddr2_wr_en_o          : out std_logic;
		ddr2_wr_mask_o        : out std_logic_vector( 3 downto 0);
		ddr2_wr_data_o        : out std_logic_vector(31 downto 0);
		ddr2_wr_full_i        : in  std_logic;
		ddr2_wr_empty_i       : in  std_logic;
		ddr2_wr_count_i       : in  std_logic_vector( 6 downto 0);
		ddr2_wr_underrun_i    : in  std_logic;
		ddr2_wr_error_i       : in  std_logic;

		-- display output
		hsync_i               : in  std_logic;
		vsync_i               : in  std_logic;
		color_en_i            : in  std_logic;
		color_i               : in  color_t(COLOR_CNT-1 downto 0)
	);
end sig_write;

architecture sig_write of sig_write is
	signal color_en_l       : std_logic;
	signal color_en_iq      : std_logic;
	signal rst              : std_logic;
	signal px_fifo_wr       : std_logic;
	signal px_fifo_full     : std_logic;
	signal px_fifo_empty    : std_logic;
	signal px_fifo_cnt      : std_logic_vector(10 downto 0);
	signal px_fifo_din      : std_logic_vector(31 downto 0);
	signal enabled          : std_logic;
	signal vsync            : std_logic;
	signal vsync_m          : std_logic;
	signal vsync_v          : std_logic;
	signal vsync_vq         : std_logic;
	signal vsync_sh         : std_logic_vector( 3 downto 0);

	-- memory
	signal mem_address      : unsigned(27 downto 0);
	signal mem_cmd_en       : std_logic;
	signal mem_wr_en        : std_logic;
	signal mem_wr_data      : std_logic_vector(31 downto 0);
	signal px_cnt           : unsigned( 7 downto 0);
begin
	rst <= not rst_n;

	-- -------------------------------------------------------------------------------
	-- MEMORY
	-- -------------------------------------------------------------------------------
	ddr2_cmd_byte_addr_o <= std_logic_vector(mem_address(27 downto 0) & "00");
	ddr2_cmd_bl_o        <= "111111";
	ddr2_cmd_instr_o     <= "000";
	ddr2_cmd_en_o        <= mem_cmd_en;
	ddr2_wr_data_o       <= mem_wr_data;
	ddr2_wr_en_o         <= mem_wr_en;
	ddr2_wr_mask_o       <= (others => '0');

	process (clk, rst_n)
	begin
	if rst_n = '0' then
		enabled <= '0';
		vsync <= '0';
	elsif rising_edge(clk) then
		-- eliminate glitches
		vsync_sh <= vsync_sh(2 downto 0) & vsync_i;
		if vsync_sh = "1111" then
			vsync <= '1';
		elsif vsync_sh = "0000" then
			vsync <= '0';
		end if;

		-- freeze frame switch
		if vsync = '1' then
			if ctrl_disable_wr = '1' then
				enabled <= '0';
			else
				enabled <= '1';
			end if;
		end if;
	end if;
	end process;

	px_fifo_wr  <= color_en_i and enabled;
	px_fifo_din <= (31 downto 24 => '0') & color_i(RED) & color_i(GREEN) & color_i(BLUE);
	px_fifo_0: entity work.px_fifo
	port map (
		wr_clk        => clk,
		rd_clk        => ddr2_clk,
		rst           => rst,
		din           => px_fifo_din,
		wr_en         => px_fifo_wr,
		rd_en         => mem_wr_en,
		dout          => mem_wr_data,
		full          => px_fifo_full,
		empty         => px_fifo_empty,
		rd_data_count => px_fifo_cnt
	);

	mem_wr_en  <= '1' when px_fifo_empty = '0' and ddr2_wr_full_i = '0' else '0';
	mem_cmd_en <= '1' when px_cnt = x"40" else '0';
	process (ddr2_clk, rst_n)
	begin
	if rst_n = '0' then
		px_cnt        <= (others => '0');
		mem_address   <= (others => '0');
		vsync_m       <= '0';
		vsync_v       <= '0';
		vsync_vq      <= '0';
	elsif rising_edge(ddr2_clk) then
		-- signal synchronizer
		vsync_m  <= vsync;
		vsync_v  <= vsync_m;
		vsync_vq <= vsync_v;

		if mem_cmd_en = '1' and mem_wr_en = '1' then
			px_cnt <= x"01";
		elsif mem_cmd_en = '1' then
			px_cnt <= (others => '0');
		elsif mem_wr_en = '1' then
			px_cnt <= px_cnt + "1";
		end if;

		if vsync_vq = '1' and vsync_v = '0' then
			mem_address <= MEM_START_ADR(29 downto 2);
		elsif mem_cmd_en = '1' then
			mem_address <= mem_address + x"040";
		end if;
	end if;
	end process;

end sig_write;