94 lines
4.5 KiB
Plaintext
94 lines
4.5 KiB
Plaintext
#FPGA_PART=xc6slx45-3-csg324
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CONFIG VCCAUX = 3.3;
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##############################################################################
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# SYSCLK Input
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##############################################################################
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NET "clk100" LOC = "L15" | IOSTANDARD = LVCMOS33 | TNM_NET = clk100;
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TIMESPEC TS_clk100 = PERIOD "clk100" 100 MHz HIGH 50%;
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# Constraint for RX0
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NET "dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
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TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;
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##############################################################################
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# Mechanical Switches (SW)
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##############################################################################
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#NET "switch<0>" LOC = "A10" |IOSTANDARD = LVCMOS33 ;
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#NET "switch<1>" LOC = "D14" |IOSTANDARD = LVCMOS33 ;
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#NET "switch<2>" LOC = "C14" | IOSTANDARD = LVCMOS33 ;
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#NET "switch<3>" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
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#############################################
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## TMDS pairs for Atlys top OUT: J2 - Bank 0
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#############################################
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NET "tx0_tmds(3)" LOC = "B6" |IOSTANDARD = TMDS_33 ; # Clock
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NET "tx0_tmds_n(3)" LOC = "A6" |IOSTANDARD = TMDS_33 ;
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NET "tx0_tmds(2)" LOC = "B8" |IOSTANDARD = TMDS_33 ; # Red
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NET "tx0_tmds_n(2)" LOC = "A8" |IOSTANDARD = TMDS_33 ;
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NET "tx0_tmds(1)" LOC = "C7" |IOSTANDARD = TMDS_33 ; # Green
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NET "tx0_tmds_n(1)" LOC = "A7" |IOSTANDARD = TMDS_33 ;
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NET "tx0_tmds(0)" LOC = "D8" |IOSTANDARD = TMDS_33 ; # Blue
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NET "tx0_tmds_n(0)" LOC = "C8" |IOSTANDARD = TMDS_33 ;
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#
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###############################################
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## TMDS pairs for Atlys top OUT: JA - Bank 2
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## Use TML_33 to add output series termination
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###############################################
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#NET "tx1_tmds(3)" LOC = "T9" |IOSTANDARD = TML_33; #TMDS_33 ; ## Clock
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#NET "tx1_tmds_n(3)" LOC = "V9" |IOSTANDARD = TML_33; #TMDS_33 ; #
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#NET "tx1_tmds(2)" LOC = "N5" |IOSTANDARD = TML_33; #TMDS_33 ; ## Red
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#NET "tx1_tmds_n(2)" LOC = "P6" |IOSTANDARD = TML_33; #TMDS_33 ; #
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#NET "tx1_tmds(1)" LOC = "T4" |IOSTANDARD = TML_33; #TMDS_33 ; ## Green
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#NET "tx1_tmds_n(1)" LOC = "V4" |IOSTANDARD = TML_33; #TMDS_33 ; #
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#NET "tx1_tmds(0)" LOC = "R3" |IOSTANDARD = TML_33; #TMDS_33 ; ## Blue
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#NET "tx1_tmds_n(0)" LOC = "T3" |IOSTANDARD = TML_33; #TMDS_33 ; #
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#
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###################################################
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## TMDS pairs for Atlys IN (FPGA Bank 1): J3
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###################################################
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#NET "rx1_tmds(3)" LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
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#NET "rx1_tmds_n(3)" LOC = "H18" |IOSTANDARD = TMDS_33 ;
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#NET "rx1_tmds(2)" LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
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#NET "rx1_tmds_n(2)" LOC = "J18" |IOSTANDARD = TMDS_33 ;
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#NET "rx1_tmds(1)" LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green
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#NET "rx1_tmds_n(1)" LOC = "L18" |IOSTANDARD = TMDS_33 ;
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#NET "rx1_tmds(0)" LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue
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#NET "rx1_tmds_n(0)" LOC = "K18" |IOSTANDARD = TMDS_33 ;
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#
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###############################################
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## TMDS pairs for Atlys IN (FPGA Bank 0): J1
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###############################################
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NET "rx0_tmds(3)" LOC = "D11" |IOSTANDARD = TMDS_33 ; # CLK
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NET "rx0_tmds_n(3)" LOC = "C11" |IOSTANDARD = TMDS_33 ;
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NET "rx0_tmds(2)" LOC = "B12" |IOSTANDARD = TMDS_33 ; # Red
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NET "rx0_tmds_n(2)" LOC = "A12" |IOSTANDARD = TMDS_33 ;
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NET "rx0_tmds(1)" LOC = "B11" |IOSTANDARD = TMDS_33 ; # Green
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NET "rx0_tmds_n(1)" LOC = "A11" |IOSTANDARD = TMDS_33 ;
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NET "rx0_tmds(0)" LOC = "G9" |IOSTANDARD = TMDS_33 ; # Blue
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NET "rx0_tmds_n(0)" LOC = "F9" |IOSTANDARD = TMDS_33 ;
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NET "rx0_scl" LOC = "C13" |IOSTANDARD = LVCMOS33 ;
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NET "rx0_sda" LOC = "A13" |IOSTANDARD = LVCMOS33 ;
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########################################
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# Reset button and LEDs and Mechanical Switches (SW)
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########################################
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NET "rstbtn_n" LOC = "T15" |IOSTANDARD = LVCMOS33;
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NET "led<0>" LOC = "U18" |IOSTANDARD = LVCMOS33;
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NET "led<1>" LOC = "M14" |IOSTANDARD = LVCMOS33;
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NET "led<2>" LOC = "N14" |IOSTANDARD = LVCMOS33;
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NET "led<3>" LOC = "L14" |IOSTANDARD = LVCMOS33;
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NET "led<4>" LOC = "M13" |IOSTANDARD = LVCMOS33;
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NET "led<5>" LOC = "D4" |IOSTANDARD = LVCMOS33;
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NET "led<6>" LOC = "P16" |IOSTANDARD = LVCMOS33;
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NET "led<7>" LOC = "N12" |IOSTANDARD = LVCMOS33;
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# Multi-cycle paths for TX0 / encoder_0
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#TIMEGRP "bramgrp_0" = RAMS(dvi_encoder_0/pixel2x/data_i<*>);
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#TIMEGRP "fddbgrp_0" = FFS(dvi_encoder_0/pixel2x/db<*>);
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#TIMEGRP "bramra_0" = FFS(dvi_encoder_0/pixel2x/ra<*>);
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#
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#TIMESPEC "TS_ramdo_0" = FROM "bramgrp_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
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#TIMESPEC "TS_ramra_0" = FROM "bramra_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
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