HDMI/DVI Encoder/Decoder
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8 years ago
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. use work.dvi_package.all;
  5. library UNISIM;
  6. use UNISIM.Vcomponents.all;
  7. ENTITY dvi_tb IS
  8. END dvi_tb;
  9. ARCHITECTURE rtl OF dvi_tb IS
  10. constant CLK_PERIOD : time := 20.0 ns;
  11. constant CLK1_PERIOD : time := 10.0 ns;
  12. constant CLK2_PERIOD : time := 2.0 ns;
  13. signal clk : std_logic;
  14. signal clk1 : std_logic;
  15. signal clk2 : std_logic;
  16. signal rst : std_logic;
  17. signal rst_n : std_logic;
  18. signal en_stb_i : std_logic;
  19. signal hsync_o : std_logic;
  20. signal vsync_o : std_logic;
  21. signal color_en_o : std_logic;
  22. signal color_o : color_t(COLOR_CNT-1 downto 0);
  23. signal en_stb_iq : std_logic;
  24. signal hsync_oq : std_logic;
  25. signal vsync_oq : std_logic;
  26. signal color_en_oq : std_logic;
  27. signal color_oq : color_t(COLOR_CNT-1 downto 0);
  28. -- dvi encoder
  29. signal pclk : std_logic;
  30. signal pclk_buf : std_logic;
  31. signal tx_pclkx2 : std_logic;
  32. signal tx_pclkx10 : std_logic;
  33. signal tx_reset_n : std_logic;
  34. signal tx_serdesstrobe : std_logic;
  35. signal tx_clkfbout : std_logic;
  36. signal tx_clkfbin : std_logic;
  37. signal tx_plllckd : std_logic;
  38. signal tx_pllclk0 : std_logic;
  39. signal tx_pllclk2 : std_logic;
  40. signal tx_bufpll_lock : std_logic;
  41. signal tx_tmds : std_logic_vector(3 downto 0);
  42. signal tx_tmds_n : std_logic_vector(3 downto 0);
  43. -- dvi decoder
  44. signal rx_pll_lckd : std_logic;
  45. signal rx_rst_n : std_logic;
  46. signal rx_pclk : std_logic;
  47. signal rx_hsync : std_logic;
  48. signal rx_vsync : std_logic;
  49. signal rx_color : color_t(COLOR_CNT-1 downto 0);
  50. signal rx_color_en : std_logic;
  51. BEGIN
  52. rst <= transport '1', '0' after (4 * CLK_PERIOD);
  53. rst_n <= not rst;
  54. clock: process
  55. begin
  56. clk <= '1', '0' after CLK_PERIOD/2;
  57. wait for CLK_PERIOD;
  58. end process;
  59. clock1: process
  60. begin
  61. clk1 <= '1', '0' after CLK1_PERIOD/2;
  62. wait for CLK1_PERIOD;
  63. end process;
  64. clock2: process
  65. begin
  66. clk2 <= '1', '0' after CLK2_PERIOD/2;
  67. wait for CLK2_PERIOD;
  68. end process;
  69. -- ----------------------------------------------------------------------------
  70. -- ----------------------------------------------------------------------------
  71. -- DVI ENCODER
  72. -- ----------------------------------------------------------------------------
  73. -- ----------------------------------------------------------------------------
  74. -- ----------------------------------------------------------------------------
  75. -- Instantiate a dedicate PLL for output port
  76. -- ----------------------------------------------------------------------------
  77. tx_plllckd <= rst_n;
  78. tx_pllclk0 <= clk2;
  79. pclk_buf <= clk;
  80. tx_pllclk2 <= clk1;
  81. pclk_buf_0: BUFG port map(I => pclk_buf, O => pclk);
  82. -- ----------------------------------------------------------------------------
  83. -- This BUFG is needed in order to deskew between PLL clkin and clkout
  84. -- So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input
  85. -- ----------------------------------------------------------------------------
  86. tx_clkfb_buf: BUFG port map(I => tx_clkfbout, O => tx_clkfbin);
  87. -- --------------------------------
  88. -- regenerate pclkx2 for TX
  89. -- --------------------------------
  90. tx_pclkx2_buf: BUFG port map(I => tx_pllclk2, O => tx_pclkx2);
  91. -- --------------------------------
  92. -- regenerate pclkx10 for TX
  93. -- --------------------------------
  94. tx_ioclk_buf: BUFPLL
  95. generic map ( DIVIDE => 5 )
  96. port map (
  97. PLLIN => tx_pllclk0,
  98. GCLK => tx_pclkx2,
  99. LOCKED => tx_plllckd,
  100. IOCLK => tx_pclkx10,
  101. SERDESSTROBE => tx_serdesstrobe,
  102. LOCK => tx_bufpll_lock
  103. );
  104. tx_reset_n <= tx_bufpll_lock;
  105. dvi_encoder_0: entity work.dvi_encoder
  106. port map (
  107. rst_n => tx_reset_n,
  108. pclk => pclk,
  109. pclkx2 => tx_pclkx2,
  110. pclkx10 => tx_pclkx10,
  111. serdesstrobe_i => tx_serdesstrobe,
  112. color_i => color_o,
  113. hsync_i => hsync_o,
  114. vsync_i => vsync_o,
  115. dat_en_i => color_en_o,
  116. tmds_p => tx_tmds,
  117. tmds_n => tx_tmds_n
  118. );
  119. reg: process begin
  120. wait until rising_edge(clk);
  121. en_stb_iq <= en_stb_i;
  122. hsync_o <= hsync_oq;
  123. vsync_o <= vsync_oq;
  124. color_o <= color_oq;
  125. color_en_o <= color_en_oq;
  126. end process;
  127. dut: entity work.sig
  128. generic map (
  129. H_ACTIVE_PIXEL => x"500",
  130. H_BLANKING => x"198",
  131. H_SYNC_WIDTH => x"070",
  132. H_SYNC_OFFSET => x"030",
  133. V_ACTIVE_LINES => x"400",
  134. V_BLANKING => x"02a",
  135. V_SYNC_WIDTH => x"01",
  136. V_SYNC_OFFSET => x"03"
  137. )
  138. port map (
  139. clk => clk,
  140. rst_n => rst_n,
  141. en_stb_i => en_stb_iq,
  142. hsync_o => hsync_oq,
  143. vsync_o => vsync_oq,
  144. color_en_o => color_en_oq,
  145. color_o => color_oq
  146. );
  147. beh: process begin
  148. en_stb_i <= '0';
  149. wait for 250000 ns;
  150. en_stb_i <= '1';
  151. wait;
  152. end process;
  153. -- ----------------------------------------------------------------------------
  154. -- ----------------------------------------------------------------------------
  155. -- DVI DECODER
  156. -- ----------------------------------------------------------------------------
  157. -- ----------------------------------------------------------------------------
  158. dvi_decoder_0: entity work.dvi_decoder
  159. port map (
  160. ext_rst => rst,
  161. tmdsclk_p => tx_tmds(3),
  162. tmdsclk_n => tx_tmds_n(3),
  163. din_p => tx_tmds(2 downto 0),
  164. din_n => tx_tmds_n(2 downto 0),
  165. reset_n => rx_rst_n, -- rx reset
  166. pclk_o => rx_pclk, -- regenerated pixel clock
  167. pclkx2_o => open, -- double rate pixel clock
  168. pclkx10_o => open, -- 10x pixel as IOCLK
  169. pll_lckd_o => rx_pll_lckd, -- send pll_lckd out so it can be fed into a different BUFPLL
  170. serdesstrobe_o => open, -- BUFPLL serdesstrobe output
  171. tmdsclk_o => open, -- TMDS cable clock
  172. hsync_o => rx_hsync, -- hsync data
  173. vsync_o => rx_vsync, -- vsync data
  174. valid_o => open,
  175. ready_o => open,
  176. psalgnerr_o => open,
  177. sdout_o => open,
  178. dat_en_o => rx_color_en, -- data enable
  179. color_o => rx_color
  180. );
  181. end rtl;
  182. configuration dvi_tb_rtl_cfg of dvi_tb is
  183. for rtl
  184. end for;
  185. end dvi_tb_rtl_cfg;