2013-10-07 09:07:08 +02:00
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-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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2013-09-23 10:20:49 +02:00
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.dvi_package.all;
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library UNISIM;
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use UNISIM.Vcomponents.all;
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entity chnlbond is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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rawdata_i : in std_logic_vector(9 downto 0);
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psaligned_i : in std_logic;
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other_valid_i : in std_logic_vector(1 downto 0);
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other_ready_i : in std_logic_vector(1 downto 0);
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ready_o : out std_logic;
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sdata_o : out std_logic_vector(9 downto 0)
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);
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end chnlbond;
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architecture chnlbond of chnlbond is
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signal rawdata_vld : std_logic;
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signal we : std_logic;
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signal wa, ra : unsigned(3 downto 0);
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signal dpfo_dout : std_logic_vector(9 downto 0);
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signal sdata : std_logic_vector(9 downto 0);
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signal rcvd_ctkn : std_logic;
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signal rcvd_ctkn_q : std_logic;
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signal blnkbgn : std_logic;
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signal skip_line : std_logic;
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signal next_blnkbgn : std_logic;
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signal ready : std_logic;
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signal rawdata_vld_q : std_logic;
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signal rawdata_vld_s : std_logic;
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signal ra_en : std_logic;
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begin
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sdata_o <= sdata;
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ready_o <= ready;
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rawdata_vld <= other_valid_i(0) and other_valid_i(1) and psaligned_i;
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-- ----------------------------------------------------------
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-- FIFO Write Control Logic
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-- ----------------------------------------------------------
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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we <= '0';
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sdata <= (others => '0');
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wa <= (others => '0');
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elsif rising_edge(clk) then
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we <= rawdata_vld;
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if rawdata_vld = '1' then
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wa <= wa + "1";
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else
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wa <= (others => '0');
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end if;
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sdata <= dpfo_dout;
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end if;
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end process;
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-- ----------------------------------------------------------
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-- FIFO
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-- ----------------------------------------------------------
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cbfifo_i: entity work.DRAM16XN
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generic map ( data_width => 10 )
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port map (
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DATA_IN => rawdata_i,
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ADDRESS => std_logic_vector(wa),
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ADDRESS_DP => std_logic_vector(ra),
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WRITE_EN => we,
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CLK => clk,
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O_DATA_OUT => open,
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O_DATA_OUT_DP => dpfo_dout
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);
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-- ----------------------------------------------------------
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-- FIFO read Control Logic
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-- ----------------------------------------------------------
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next_blnkbgn <= skip_line and blnkbgn;
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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rcvd_ctkn <= '0';
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rcvd_ctkn_q <= '0';
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ready <= '0';
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skip_line <= '0';
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rawdata_vld_q <= '0';
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rawdata_vld_s <= '0';
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elsif rising_edge(clk) then
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-- ---------------------------
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-- Use blank period beginning
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-- as a speical marker to
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-- align all channel together
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-- ---------------------------
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rcvd_ctkn <= '0';
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if sdata = CTRLTOKEN0 or sdata = CTRLTOKEN1
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or sdata = CTRLTOKEN2 or sdata = CTRLTOKEN3 then
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rcvd_ctkn <= '1';
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end if;
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rcvd_ctkn_q <= rcvd_ctkn;
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blnkbgn <= rcvd_ctkn and not rcvd_ctkn_q;
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-- ---------------------------
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-- skip the current line
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-- ---------------------------
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if rawdata_vld = '0' then
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skip_line <= '0';
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elsif blnkbgn = '1' then
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skip_line <= '1';
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end if;
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-- ---------------------------
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-- Declare my own readiness
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-- ---------------------------
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if rawdata_vld = '0' then
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ready <= '0';
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elsif next_blnkbgn = '1' then
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ready <= '1';
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end if;
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rawdata_vld_q <= rawdata_vld;
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rawdata_vld_s <= rawdata_vld and not rawdata_vld_q;
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end if;
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end process;
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-- ----------------------------------------------------------
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-- 1. FIFO flow through first when all channels are found valid(phase aligned)
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-- 2. When the speical marker on my channel is found, the fifo read is hold
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-- 3. Until the same markers are found across all three channels, the fifo read resumes
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-- ----------------------------------------------------------
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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ra_en <= '0';
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ra <= (others => '0');
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elsif rising_edge(clk) then
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if rawdata_vld_s = '1' or (other_ready_i(0) = '1' and other_ready_i(1) = '1' and ready = '1') then
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ra_en <= '1';
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elsif next_blnkbgn = '1' and not (other_ready_i(0) = '1' and other_ready_i(1) = '1' and ready = '1') then
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ra_en <= '0';
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end if;
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-- ---------------------------
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-- FIFO Read Address Counter
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-- ---------------------------
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if rawdata_vld = '0' then
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ra <= (others => '0');
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elsif ra_en = '1' then
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ra <= ra + "1";
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end if;
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end if;
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end process;
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end chnlbond;
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