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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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use work.dvi_package.all; |
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|
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library UNISIM; |
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use UNISIM.Vcomponents.all; |
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ENTITY dvi_tb IS |
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END dvi_tb; |
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ARCHITECTURE rtl OF dvi_tb IS |
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constant CLK_PERIOD : time := 20.0 ns; |
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constant CLK1_PERIOD : time := 10.0 ns; |
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constant CLK2_PERIOD : time := 2.0 ns; |
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signal clk : std_logic; |
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signal clk1 : std_logic; |
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signal clk2 : std_logic; |
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signal rst : std_logic; |
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signal rst_n : std_logic; |
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|
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signal en_stb_i : std_logic; |
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signal hsync_o : std_logic; |
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signal vsync_o : std_logic; |
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signal color_en_o : std_logic; |
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signal color_o : color_t(COLOR_CNT-1 downto 0); |
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signal en_stb_iq : std_logic; |
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signal hsync_oq : std_logic; |
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signal vsync_oq : std_logic; |
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signal color_en_oq : std_logic; |
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signal color_oq : color_t(COLOR_CNT-1 downto 0); |
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|
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-- dvi encoder |
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signal pclk : std_logic; |
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signal pclk_buf : std_logic; |
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signal tx_pclkx2 : std_logic; |
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signal tx_pclkx10 : std_logic; |
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signal tx_reset_n : std_logic; |
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signal tx_serdesstrobe : std_logic; |
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signal tx_clkfbout : std_logic; |
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signal tx_clkfbin : std_logic; |
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signal tx_plllckd : std_logic; |
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signal tx_pllclk0 : std_logic; |
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signal tx_pllclk2 : std_logic; |
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signal tx_bufpll_lock : std_logic; |
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signal tx_tmds : std_logic_vector(3 downto 0); |
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signal tx_tmds_n : std_logic_vector(3 downto 0); |
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|
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-- dvi decoder |
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signal rx_pll_lckd : std_logic; |
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signal rx_rst_n : std_logic; |
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signal rx_pclk : std_logic; |
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signal rx_hsync : std_logic; |
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signal rx_vsync : std_logic; |
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signal rx_color : color_t(COLOR_CNT-1 downto 0); |
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signal rx_color_en : std_logic; |
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BEGIN |
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rst <= transport '1', '0' after (4 * CLK_PERIOD); |
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rst_n <= not rst; |
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|
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clock: process |
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begin |
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clk <= '1', '0' after CLK_PERIOD/2; |
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wait for CLK_PERIOD; |
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end process; |
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clock1: process |
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begin |
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clk1 <= '1', '0' after CLK1_PERIOD/2; |
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wait for CLK1_PERIOD; |
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end process; |
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clock2: process |
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begin |
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clk2 <= '1', '0' after CLK2_PERIOD/2; |
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wait for CLK2_PERIOD; |
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end process; |
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|
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-- ---------------------------------------------------------------------------- |
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-- ---------------------------------------------------------------------------- |
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-- DVI ENCODER |
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-- ---------------------------------------------------------------------------- |
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-- ---------------------------------------------------------------------------- |
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-- ---------------------------------------------------------------------------- |
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-- Instantiate a dedicate PLL for output port |
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-- ---------------------------------------------------------------------------- |
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tx_plllckd <= rst_n; |
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tx_pllclk0 <= clk2; |
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pclk_buf <= clk; |
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tx_pllclk2 <= clk1; |
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pclk_buf_0: BUFG port map(I => pclk_buf, O => pclk); |
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|
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-- ---------------------------------------------------------------------------- |
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-- This BUFG is needed in order to deskew between PLL clkin and clkout |
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-- So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input |
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-- ---------------------------------------------------------------------------- |
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tx_clkfb_buf: BUFG port map(I => tx_clkfbout, O => tx_clkfbin); |
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-- -------------------------------- |
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-- regenerate pclkx2 for TX |
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-- -------------------------------- |
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tx_pclkx2_buf: BUFG port map(I => tx_pllclk2, O => tx_pclkx2); |
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|
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-- -------------------------------- |
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-- regenerate pclkx10 for TX |
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-- -------------------------------- |
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tx_ioclk_buf: BUFPLL |
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generic map ( DIVIDE => 5 ) |
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port map ( |
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PLLIN => tx_pllclk0, |
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GCLK => tx_pclkx2, |
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LOCKED => tx_plllckd, |
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IOCLK => tx_pclkx10, |
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SERDESSTROBE => tx_serdesstrobe, |
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LOCK => tx_bufpll_lock |
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); |
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tx_reset_n <= tx_bufpll_lock; |
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dvi_encoder_0: entity work.dvi_encoder |
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port map ( |
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rst_n => tx_reset_n, |
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pclk => pclk, |
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pclkx2 => tx_pclkx2, |
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pclkx10 => tx_pclkx10, |
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serdesstrobe_i => tx_serdesstrobe, |
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color_i => color_o, |
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hsync_i => hsync_o, |
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vsync_i => vsync_o, |
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dat_en_i => color_en_o, |
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tmds_p => tx_tmds, |
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tmds_n => tx_tmds_n |
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); |
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reg: process begin |
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wait until rising_edge(clk); |
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en_stb_iq <= en_stb_i; |
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hsync_o <= hsync_oq; |
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vsync_o <= vsync_oq; |
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color_o <= color_oq; |
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color_en_o <= color_en_oq; |
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end process; |
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|
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dut: entity work.sig |
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generic map ( |
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H_ACTIVE_PIXEL => x"500", |
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H_BLANKING => x"198", |
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H_SYNC_WIDTH => x"070", |
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H_SYNC_OFFSET => x"030", |
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V_ACTIVE_LINES => x"400", |
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V_BLANKING => x"02a", |
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V_SYNC_WIDTH => x"01", |
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V_SYNC_OFFSET => x"03" |
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) |
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port map ( |
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clk => clk, |
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rst_n => rst_n, |
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en_stb_i => en_stb_iq, |
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hsync_o => hsync_oq, |
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vsync_o => vsync_oq, |
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color_en_o => color_en_oq, |
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color_o => color_oq |
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); |
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beh: process begin |
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en_stb_i <= '0'; |
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wait for 250000 ns; |
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en_stb_i <= '1'; |
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wait; |
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end process; |
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|
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-- ---------------------------------------------------------------------------- |
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-- ---------------------------------------------------------------------------- |
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-- DVI DECODER |
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-- ---------------------------------------------------------------------------- |
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-- ---------------------------------------------------------------------------- |
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dvi_decoder_0: entity work.dvi_decoder |
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port map ( |
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ext_rst => rst, |
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tmdsclk_p => tx_tmds(3), |
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tmdsclk_n => tx_tmds_n(3), |
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din_p => tx_tmds(2 downto 0), |
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din_n => tx_tmds_n(2 downto 0), |
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reset_n => rx_rst_n, -- rx reset |
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pclk_o => rx_pclk, -- regenerated pixel clock |
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pclkx2_o => open, -- double rate pixel clock |
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pclkx10_o => open, -- 10x pixel as IOCLK |
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pll_lckd_o => rx_pll_lckd, -- send pll_lckd out so it can be fed into a different BUFPLL |
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serdesstrobe_o => open, -- BUFPLL serdesstrobe output |
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tmdsclk_o => open, -- TMDS cable clock |
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hsync_o => rx_hsync, -- hsync data |
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vsync_o => rx_vsync, -- vsync data |
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valid_o => open, |
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ready_o => open, |
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psalgnerr_o => open, |
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sdout_o => open, |
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dat_en_o => rx_color_en, -- data enable |
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color_o => rx_color |
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); |
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end rtl; |
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configuration dvi_tb_rtl_cfg of dvi_tb is |
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for rtl |
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end for; |
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end dvi_tb_rtl_cfg; |
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