-- ----------------------------------------------------------------------------- -- Copyright (c) 2013 Benjamin Krill -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. -- ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library UNISIM; use UNISIM.Vcomponents.all; entity DRAM16XN is generic (data_width : integer := 20); port ( DATA_IN : in std_logic_vector(data_width-1 downto 0); ADDRESS : in std_logic_vector(3 downto 0); ADDRESS_DP : in std_logic_vector(3 downto 0); WRITE_EN : in std_logic; CLK : in std_logic; O_DATA_OUT_DP : out std_logic_vector(data_width-1 downto 0); O_DATA_OUT : out std_logic_vector(data_width-1 downto 0) ); end DRAM16XN; architecture DRAM16XN of DRAM16XN is begin RAM: for I in 0 to data_width-1 generate I_RAM16X1D: RAM16X1D port map ( D => DATA_IN(I), --insert input signal WE => WRITE_EN, --insert Write Enable signal WCLK => CLK, --insert Write Clock signal A0 => ADDRESS(0), --insert Address 0 signal port SPO A1 => ADDRESS(1), --insert Address 1 signal port SPO A2 => ADDRESS(2), --insert Address 2 signal port SPO A3 => ADDRESS(3), --insert Address 3 signal port SPO DPRA0 => ADDRESS_DP(0), --insert Address 0 signal dual port DPO DPRA1 => ADDRESS_DP(1), --insert Address 1 signal dual port DPO DPRA2 => ADDRESS_DP(2), --insert Address 2 signal dual port DPO DPRA3 => ADDRESS_DP(3), --insert Address 3 signal dual port DPO SPO => O_DATA_OUT(I), --insert output signal SPO DPO => O_DATA_OUT_DP(I) --insert output signal DPO ); end generate; end DRAM16XN;