-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;

library UNISIM;
use UNISIM.Vcomponents.all;

entity serdes_n_to_1 is
	generic ( SF : integer := 0 );
	port (
		ioclk           : in   std_logic;
		gclk            : in   std_logic;
		rst             : in   std_logic;
		serdesstrobe_i  : in   std_logic;
		data_i          : in   std_logic_vector(SF-1 downto 0);
		data_o          : out  std_logic
	);
end serdes_n_to_1;

architecture serdes_n_to_1 of serdes_n_to_1 is
	signal cascade_di  : std_logic;
	signal cascade_do  : std_logic;
	signal cascade_ti  : std_logic;
	signal cascade_to  : std_logic;
	signal mdatain     : std_logic_vector(8 downto 0);
begin
	datir: for I in 0 to SF-1 generate
		mdatain(I) <= data_i(I);
	end generate;
	dati0: for I in SF to 8 generate
		mdatain(I) <= '0';
	end generate;

	oserdes_m: OSERDES2
	generic map (
		DATA_WIDTH   => SF,            -- SERDES word width.  This should match the setting is BUFPLL
		DATA_RATE_OQ => "SDR",         -- <SDR>, DDR
		DATA_RATE_OT => "SDR",         -- <SDR>, DDR
		SERDES_MODE  => "MASTER",      -- <DEFAULT>, MASTER, SLAVE
		OUTPUT_MODE  => "DIFFERENTIAL"
	)
	port map (
		OQ        => data_o,
		OCE       => '1',
		CLK0      => ioclk,
		CLK1      => '0',
		IOCE      => serdesstrobe_i,
		RST       => rst,
		CLKDIV    => gclk,
		D4        => mdatain(7),
		D3        => mdatain(6),
		D2        => mdatain(5),
		D1        => mdatain(4),
		TQ        => open,
		T1        => '0',
		T2        => '0',
		T3        => '0',
		T4        => '0',
		TRAIN     => '0',
		TCE       => '1',
		SHIFTIN1  => '1',         -- Dummy input in Master
		SHIFTIN2  => '1',         -- Dummy input in Master
		SHIFTIN3  => cascade_do,  -- Cascade output D data from slave
		SHIFTIN4  => cascade_to,  -- Cascade output T data from slave
		SHIFTOUT1 => cascade_di,  -- Cascade input D data to slave
		SHIFTOUT2 => cascade_ti,  -- Cascade input T data to slave
		SHIFTOUT3 => open,        -- Dummy output in Master
		SHIFTOUT4 => open         -- Dummy output in Master
	);

	oserdes_s: OSERDES2
	generic map (
		DATA_WIDTH   => SF,            -- SERDES word width.  This should match the setting is BUFPLL
		DATA_RATE_OQ => "SDR",         -- <SDR>, DDR
		DATA_RATE_OT => "SDR",         -- <SDR>, DDR
		SERDES_MODE  => "SLAVE",       -- <DEFAULT>, MASTER, SLAVE
		OUTPUT_MODE  => "DIFFERENTIAL"
	)
	port map (
		OQ        => open,
		OCE       => '1',
		CLK0      => ioclk,
		CLK1      => '0',
		IOCE      => serdesstrobe_i,
		RST       => rst,
		CLKDIV    => gclk,
		D4        => mdatain(3),
		D3        => mdatain(2),
		D2        => mdatain(1),
		D1        => mdatain(0),
		TQ        => open,
		T1        => '0',
		T2        => '0',
		T3        => '0',
		T4        => '0',
		TRAIN     => '0',
		TCE       => '1',
		SHIFTIN1  => cascade_di, -- Cascade input D from Master
		SHIFTIN2  => cascade_ti, -- Cascade input T from Master
		SHIFTIN3  => '1',        -- Dummy input in Slave
		SHIFTIN4  => '1',        -- Dummy input in Slave
		SHIFTOUT1 => open,       -- Dummy output in Slave
		SHIFTOUT2 => open,       -- Dummy output in Slave
		SHIFTOUT3 => cascade_do, -- Cascade output D data to Master
		SHIFTOUT4 => cascade_to  -- Cascade output T data to Master
	);
end serdes_n_to_1;