43 lines
1.5 KiB
VHDL
43 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library UNISIM;
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use UNISIM.Vcomponents.all;
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entity DRAM16XN is
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generic (data_width : integer := 20);
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port (
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DATA_IN : in std_logic_vector(data_width-1 downto 0);
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ADDRESS : in std_logic_vector(3 downto 0);
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ADDRESS_DP : in std_logic_vector(3 downto 0);
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WRITE_EN : in std_logic;
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CLK : in std_logic;
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O_DATA_OUT_DP : out std_logic_vector(data_width-1 downto 0);
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O_DATA_OUT : out std_logic_vector(data_width-1 downto 0)
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);
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end DRAM16XN;
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architecture DRAM16XN of DRAM16XN is
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begin
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RAM: for I in 0 to data_width-1 generate
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I_RAM16X1D: RAM16X1D
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port map (
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D => DATA_IN(I), --insert input signal
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WE => WRITE_EN, --insert Write Enable signal
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WCLK => CLK, --insert Write Clock signal
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A0 => ADDRESS(0), --insert Address 0 signal port SPO
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A1 => ADDRESS(1), --insert Address 1 signal port SPO
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A2 => ADDRESS(2), --insert Address 2 signal port SPO
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A3 => ADDRESS(3), --insert Address 3 signal port SPO
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DPRA0 => ADDRESS_DP(0), --insert Address 0 signal dual port DPO
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DPRA1 => ADDRESS_DP(1), --insert Address 1 signal dual port DPO
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DPRA2 => ADDRESS_DP(2), --insert Address 2 signal dual port DPO
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DPRA3 => ADDRESS_DP(3), --insert Address 3 signal dual port DPO
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SPO => O_DATA_OUT(I), --insert output signal SPO
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DPO => O_DATA_OUT_DP(I) --insert output signal DPO
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);
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end generate;
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end DRAM16XN;
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