201 lines
7.2 KiB
VHDL
201 lines
7.2 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.dvi_package.all;
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library UNISIM;
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use UNISIM.Vcomponents.all;
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entity encoder is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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data_i : in std_logic_vector(7 downto 0);
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c0 : in std_logic;
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c1 : in std_logic;
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de : in std_logic;
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data_o : out std_logic_vector(9 downto 0)
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);
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end encoder;
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architecture encoder of encoder is
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signal n1d : unsigned(3 downto 0);
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signal data_iq : std_logic_vector(7 downto 0);
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signal decision1 : std_logic;
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signal q_m : std_logic_vector(8 downto 0);
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signal n0q_m : unsigned(3 downto 0); -- number of 1s and 0s for q_m
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signal n1q_m : unsigned(3 downto 0); -- number of 1s and 0s for q_m
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signal n1q_i : unsigned(3 downto 0); -- number of 1s and 0s for q_m
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signal cnt : unsigned(4 downto 0); -- disparity counter, MSB is the sign bit
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signal decision2 : std_logic;
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signal decision3 : std_logic;
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type usigned_t is array(natural range <>) of unsigned(3 downto 0);
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signal data_iu : usigned_t(7 downto 0);
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signal q_mu : usigned_t(8 downto 0);
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signal de_q, de_reg : std_logic;
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signal c0_q, c1_q : std_logic;
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signal c0_reg, c1_reg : std_logic;
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signal c1c0 : std_logic_vector(1 downto 0);
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signal q_m_reg : std_logic_vector(8 downto 0);
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signal data_oq : std_logic_vector(9 downto 0);
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begin
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-- ----------------------------------------------------------
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-- Counting number of 1s and 0s for each incoming pixel
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-- component. Pipe line the result.
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-- Register Data Input so it matches the pipe lined adder
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-- output
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-- ----------------------------------------------------------
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tounsigned0: for I in 0 to 7 generate
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data_iu(I)(3 downto 1) <= "000";
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data_iu(I)(0 downto 0) <= unsigned(data_i(I downto I));
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end generate;
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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n1d <= (others => '0');
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data_iq <= (others => '0');
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elsif rising_edge(clk) then
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n1d <= data_iu(0) + data_iu(1) + data_iu(2) + data_iu(3)
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+ data_iu(4) + data_iu(5) + data_iu(6) + data_iu(7);
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data_iq <= data_i;
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end if;
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end process;
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-- ----------------------------------------------------------
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-- Stage 1: 8 bit -> 9 bit
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-- Refer to DVI 1.0 Specification, page 29, Figure 3-5
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-- ----------------------------------------------------------
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decision1 <= '1' when n1d > x"4" or (n1d = x"4" and data_iq(0) = '0') else '0';
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q_m(0) <= data_iq(0);
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q_m(1) <= (q_m(0) xnor data_iq(1)) when decision1 = '1' else q_m(0) xor data_iq(1);
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q_m(2) <= (q_m(1) xnor data_iq(2)) when decision1 = '1' else q_m(1) xor data_iq(2);
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q_m(3) <= (q_m(2) xnor data_iq(3)) when decision1 = '1' else q_m(2) xor data_iq(3);
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q_m(4) <= (q_m(3) xnor data_iq(4)) when decision1 = '1' else q_m(3) xor data_iq(4);
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q_m(5) <= (q_m(4) xnor data_iq(5)) when decision1 = '1' else q_m(4) xor data_iq(5);
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q_m(6) <= (q_m(5) xnor data_iq(6)) when decision1 = '1' else q_m(5) xor data_iq(6);
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q_m(7) <= (q_m(6) xnor data_iq(7)) when decision1 = '1' else q_m(6) xor data_iq(7);
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q_m(8) <= '0' when decision1 = '1' else '1';
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-- ----------------------------------------------------------
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-- Stage 2: 9 bit -> 10 bit
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-- Refer to DVI 1.0 Specification, page 29, Figure 3-5
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-- ----------------------------------------------------------
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tounsigned1: for I in 0 to 8 generate
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q_mu(I)(3 downto 1) <= "000";
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q_mu(I)(0 downto 0) <= unsigned(q_m(I downto I));
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end generate;
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n1q_i <= q_mu(0) + q_mu(1) + q_mu(2) + q_mu(3) + q_mu(4) + q_mu(5) + q_mu(6) + q_mu(7);
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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n1q_m <= (others => '0');
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n0q_m <= (others => '0');
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elsif rising_edge(clk) then
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n1q_m <= n1q_i;
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n0q_m <= x"8" - n1q_i;
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end if;
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end process;
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decision2 <= '1' when cnt = "00000" or n1q_m = n0q_m else '0';
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-- ----------------------------------------------------------
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-- [(cnt > 0) and (N1q_m > N0q_m)] or [(cnt < 0) and (N0q_m > N1q_m)]
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-- ----------------------------------------------------------
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decision3 <= '1' when (cnt(4) = '0' and n1q_m > n0q_m) or (cnt(4) = '1' and n0q_m > n1q_m) else '0';
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-- --------------------------
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-- pipe line alignment
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-- --------------------------
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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de_q <= '0';
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de_reg <= '0';
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c0_q <= '0';
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c0_reg <= '0';
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c1_q <= '0';
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c1_reg <= '0';
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q_m_reg <= (others => '0');
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elsif rising_edge(clk) then
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de_q <= de;
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de_reg <= de_q;
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c0_q <= c0;
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c0_reg <= c0_q;
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c1_q <= c1;
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c1_reg <= c1_q;
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q_m_reg <= q_m;
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end if;
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end process;
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-- --------------------------
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-- 10-bit out
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-- disparity counter
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-- --------------------------
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process (clk, rst_n)
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begin
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if rst_n = '0' then
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data_oq <= (others => '0');
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cnt <= (others => '0');
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elsif rising_edge(clk) then
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if de_reg = '1' then
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if decision2 = '1' then
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data_oq(9) <= not q_m_reg(8);
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data_oq(8) <= q_m_reg(8);
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if q_m_reg(8) = '1' then
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data_oq(7 downto 0) <= q_m_reg(7 downto 0);
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cnt <= cnt + n1q_m - n0q_m;
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else
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data_oq(7 downto 0) <= not q_m_reg(7 downto 0);
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cnt <= cnt + n0q_m - n1q_m;
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end if;
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elsif decision3 = '1' then
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data_oq(9) <= '1';
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data_oq(8) <= q_m_reg(8);
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data_oq(7 downto 0) <= not q_m_reg(7 downto 0);
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cnt <= cnt + (q_m_reg(8) & '0') + (n0q_m - n1q_m);
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else
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data_oq(9) <= '0';
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data_oq(8) <= q_m_reg(8);
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data_oq(7 downto 0) <= q_m_reg(7 downto 0);
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cnt <= cnt - (not q_m_reg(8) & '0') + (n1q_m - n0q_m);
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end if;
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else
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case c1c0 is
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when "00" => data_oq <= CTRLTOKEN0;
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when "01" => data_oq <= CTRLTOKEN1;
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when "10" => data_oq <= CTRLTOKEN2;
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when others => data_oq <= CTRLTOKEN3;
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end case;
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cnt <= (others => '0');
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end if;
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end if;
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end process;
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c1c0 <= c1_reg & c0_reg;
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data_o <= data_oq;
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end encoder;
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