133 lines
4.7 KiB
VHDL
133 lines
4.7 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.dvi_package.all;
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library UNISIM;
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use UNISIM.Vcomponents.all;
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entity dvi_encoder is
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port (
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rst_n : in std_logic; -- external reset input, e.g. reset button
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pclk : in std_logic; -- pixel clock
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pclkx2 : in std_logic; -- double pixel rate for gear box
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pclkx10 : in std_logic; -- IOCLK
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serdesstrobe_i : in std_logic; -- serdesstrobe for iserdes2
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color_i : in color_t(COLOR_CNT-1 downto 0); -- pixel data out
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hsync_i : in std_logic; -- hsync data
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vsync_i : in std_logic; -- vsync data
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dat_en_i : in std_logic; -- data enable
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tmds_p : out std_logic_vector(3 downto 0); -- tmds
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tmds_n : out std_logic_vector(3 downto 0) -- tmds
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);
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end dvi_encoder;
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architecture dvi_encoder of dvi_encoder is
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signal rst : std_logic;
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signal toggle : std_logic;
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signal tmdsclkint : std_logic_vector(4 downto 0);
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signal data : sdat_t(COLOR_CNT-1 downto 0);
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signal sdata : std_logic_vector(29 downto 0);
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type data_5bit_t is array(natural range <>) of std_logic_vector(4 downto 0);
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signal tmds_data : data_5bit_t(3 downto 0);
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signal tmdsint : std_logic_vector(3 downto 0);
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signal tmds_clk : std_logic;
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begin
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rst <= not rst_n;
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-- ----------------------------------------------------------
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-- Forward TMDS Clock Using OSERDES2 block
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-- ----------------------------------------------------------
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process (pclkx2, rst_n)
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begin
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if rst_n = '0' then
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toggle <= '0';
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tmdsclkint <= (others => '0');
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elsif rising_edge(pclkx2) then
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toggle <= not toggle;
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if toggle = '1' then
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tmdsclkint <= (others => '1');
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else
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tmdsclkint <= (others => '0');
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end if;
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end if;
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end process;
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clkout: entity work.serdes_n_to_1
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generic map (SF => 5)
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port map (
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ioclk => pclkx10,
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gclk => pclkx2,
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rst => rst,
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serdesstrobe_i => serdesstrobe_i,
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data_i => tmdsclkint,
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data_o => tmds_clk
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);
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TMDS3: OBUFDS port map (I => tmds_clk, O => tmds_p(3), OB => tmds_n(3)); -- clock
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-- ----------------------------------------------------------
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-- Forward TMDS Data: 3 channels
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-- ----------------------------------------------------------
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forward: for I in 0 to COLOR_CNT-1 generate
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oserdes_I: entity work.serdes_n_to_1
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generic map (SF => 5)
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port map (
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ioclk => pclkx10,
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gclk => pclkx2,
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rst => rst,
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serdesstrobe_i => serdesstrobe_i,
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data_i => tmds_data(I),
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data_o => tmdsint(I)
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);
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TMDS_I: OBUFDS port map (I => tmdsint(I), O => tmds_p(I), OB => tmds_n(I));
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enc_I: entity work.encoder
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port map (
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clk => pclk,
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rst_n => rst_n,
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data_i => color_i(I),
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c0 => hsync_i,
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c1 => vsync_i,
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de => dat_en_i,
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data_o => data(I)
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);
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end generate;
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sdata <= data(RED)(9 downto 5) & data(GREEN)(9 downto 5) & data(BLUE)(9 downto 5)
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& data(RED)(4 downto 0) & data(GREEN)(4 downto 0) & data(BLUE)(4 downto 0);
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pixel2x: entity work.convert_30to15_fifo
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port map (
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rst => rst,
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clk => pclk,
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clkx2 => pclkx2,
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data_i => sdata,
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data_o(14 downto 10) => tmds_data(2),
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data_o( 9 downto 5) => tmds_data(1),
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data_o( 4 downto 0) => tmds_data(0)
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);
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end dvi_encoder;
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