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rrarbiter.vhd 2.7KB

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  1. -- -----------------------------------------------------------------------------
  2. -- Copyright (c) 2009 Benjamin Krill <benjamin@krll.de>
  3. --
  4. -- Permission is hereby granted, free of charge, to any person obtaining a copy
  5. -- of this software and associated documentation files (the "Software"), to deal
  6. -- in the Software without restriction, including without limitation the rights
  7. -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  8. -- copies of the Software, and to permit persons to whom the Software is
  9. -- furnished to do so, subject to the following conditions:
  10. --
  11. -- The above copyright notice and this permission notice shall be included in
  12. -- all copies or substantial portions of the Software.
  13. --
  14. -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17. -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18. -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19. -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20. -- THE SOFTWARE.
  21. -- -----------------------------------------------------------------------------
  22. library ieee;
  23. use ieee.std_logic_1164.all;
  24. use ieee.numeric_std.all;
  25. entity rrarbiter is
  26. generic ( CNT : integer := 7 );
  27. port (
  28. clk : in std_logic;
  29. rst_n : in std_logic;
  30. req : in std_logic_vector(CNT-1 downto 0);
  31. ack : in std_logic;
  32. grant : out std_logic_vector(CNT-1 downto 0)
  33. );
  34. end;
  35. architecture rrarbiter of rrarbiter is
  36. signal grant_q : std_logic_vector(CNT-1 downto 0);
  37. signal pre_req : std_logic_vector(CNT-1 downto 0);
  38. signal sel_gnt : std_logic_vector(CNT-1 downto 0);
  39. signal isol_lsb : std_logic_vector(CNT-1 downto 0);
  40. signal mask_pre : std_logic_vector(CNT-1 downto 0);
  41. signal win : std_logic_vector(CNT-1 downto 0);
  42. begin
  43. grant <= grant_q;
  44. mask_pre <= req and not (std_logic_vector(unsigned(pre_req) - 1) or pre_req); -- Mask off previous winners
  45. sel_gnt <= mask_pre and std_logic_vector(unsigned(not(mask_pre)) + 1); -- Select new winner
  46. isol_lsb <= req and std_logic_vector(unsigned(not(req)) + 1); -- Isolate least significant set bit.
  47. win <= sel_gnt when mask_pre /= (CNT-1 downto 0 => '0') else isol_lsb;
  48. process (clk, rst_n)
  49. begin
  50. if rst_n = '0' then
  51. pre_req <= (others => '0');
  52. grant_q <= (others => '0');
  53. elsif rising_edge(clk) then
  54. grant_q <= grant_q;
  55. pre_req <= pre_req;
  56. if grant_q = (CNT-1 downto 0 => '0') or ack = '1' then
  57. if win /= (CNT-1 downto 0 => '0') then
  58. pre_req <= win;
  59. end if;
  60. grant_q <= win;
  61. end if;
  62. end if;
  63. end process;
  64. end rrarbiter;