175 lines
3.5 KiB
VHDL
175 lines
3.5 KiB
VHDL
-- ---------------------------------------------------------------------------
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-- (2009) Benjamin Krill <ben@codiert.org>
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--
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-- "THE BEER-WARE LICENSE" (Revision 42):
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-- ben@codiert.org wrote this file. As long as you retain this notice you can
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-- do whatever you want with this stuff. If we meet some day, and you think
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-- this stuff is worth it, you can buy me a beer in return Benjamin Krill
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-- ---------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_Logic_unsigned.all;
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use IEEE.numeric_std.all;
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entity rrarbiter_tb is
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end rrarbiter_tb;
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architecture rtl of rrarbiter_tb is
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constant CLK_PERIOD : time := 36 ns;
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signal clk : std_logic;
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signal rst : std_logic;
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signal rst_n : std_logic;
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signal req : std_logic_vector(6 downto 0);
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signal grant : std_logic_vector(6 downto 0);
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signal ack : std_logic;
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begin
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rst <= transport '1', '0' after ( 4 * CLK_PERIOD);
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rst_n <= not rst;
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clock: process
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begin
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clk <= '1', '0' after CLK_PERIOD/2;
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wait for Clk_PERIOD;
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end process;
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beh: process
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begin
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req <= "0000000";
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wait for 10*CLK_PERIOD;
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req <= "0000011";
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wait for 5*CLK_PERIOD;
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req <= "0000000";
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wait for 5*CLK_PERIOD;
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req <= "0001111";
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wait for 5*CLK_PERIOD;
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req <= "0001110";
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wait for 20*CLK_PERIOD;
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req <= "0000000";
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wait for 20*CLK_PERIOD;
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wait;
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end process beh;
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beh0: process
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begin
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ack <= '0';
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wait for 10*CLK_PERIOD;
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wait for 6*CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for 8*CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for 5*CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for 2*CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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ack <= '1';
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wait for CLK_PERIOD;
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ack <= '0';
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wait for CLK_PERIOD;
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wait for 20*CLK_PERIOD;
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wait;
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end process beh0;
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DUT: entity work.rrarbiter_reg
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port map (
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clk => clk,
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rst_n => rst_n,
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ack => ack,
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req => req,
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grant => grant
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);
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end rtl;
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configuration rrarbiter_tb_rtl_cfg of rrarbiter_tb is
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for rtl
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end for;
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end rrarbiter_tb_rtl_cfg;
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