fx2/fpga/f2p/strm_package.vhd

-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- GENERAL PKT FORMAT
-- --------------------------------------------------------
-- Type (4bit)
-- _Tag (4bit)
-- Plength (7bit) data length (0 = 0byte, 0x7f = 127 * 4byte)
--          31            16|15             0
-- header  |Type_Tag________|___PLenght______|
-- data    |... type defined data/fields ... |
--
-- --------------------------------------------------------
-- --------------------------------------------------------
-- DDR2 WRITE TYPE FORMAT
-- --------------------------------------------------------
-- header  |1   ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- data    | .... data ....                  |
--
-- DDR2 READ TYPE FORMAT
-- --------------------------------------------------------
-- header0 |0   ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- header1 |                |_______SIZE_____| -- SIZE in 4byte to read
-- --------------------------------------------------------
-- --------------------------------------------------------
-- --------------------------------------------------------
-- --------------------------------------------------------
-- REGFILE WRITE TYPE FORMAT
-- --------------------------------------------------------
-- header  |1   ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- data    |          32 bit data            |
--
-- REGFILE READ TYPE FORMAT
-- --------------------------------------------------------
-- header  |0TAG________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- --------------------------------------------------------
-- --------------------------------------------------------

package strm_package is
	constant STRM_TYPE_HIGH          : integer := 31;
	constant STRM_TYPE_LOW           : integer := 28;
	constant STRM_TAG_HIGH           : integer := 27;
	constant STRM_TAG_LOW            : integer := 24;
	constant STRM_LENGTH_HIGH        : integer := 23;
	constant STRM_LENGTH_LOW         : integer :=  0;

	-- SLAVE TYPE IDs
	constant STRM_TYPE_DDR2          : std_logic_vector(3 downto 0) := "0001";
	constant STRM_TYPE_REGFILE       : std_logic_vector(3 downto 0) := "0010";

	-- DDR2
	constant STRM_DDR2_ADR_HIGH      : integer   := 27;
	constant STRM_DDR2_ADR_LOW       : integer   :=  0;
	constant STRM_DDR2_ACCESS        : integer   := 31;
	constant STRM_DDR2_ACC_WRITE     : std_logic := '1';
	constant STRM_DDR2_ACC_READ      : std_logic := '0';
	constant STRM_DDR2_SIZE_HIGH     : integer   := 23;
	constant STRM_DDR2_SIZE_LOW      : integer   :=  0;

	-- bus types
	type strm_dat_bus_t is array(natural range <>) of std_logic_vector(31 downto 0);
end package;