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add stream output start of packet (SOP)

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This commit is contained in:
Benjamin Krill
2013-12-04 15:43:22 +01:00
parent 19caae41ef
commit 6f69d97683
6 changed files with 367 additions and 369 deletions
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20
fpga/strm_ddr2/strm_ddr2.vhd
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@@ -33,6 +33,7 @@ entity strm_ddr2 is
-- streaming bus
strm_in_data_i : in std_logic_vector(31 downto 0);
strm_in_eop_i : in std_logic;
strm_in_sop_i : in std_logic;
strm_in_en_i : in std_logic;
strm_in_busy_o : out std_logic;
strm_out_req_o : out std_logic;
@@ -72,9 +73,11 @@ architecture strm_ddr2 of strm_ddr2 is
signal rst : std_logic;
signal strm_in_data : std_logic_vector(31 downto 0);
signal strm_in_eop : std_logic;
signal strm_in_sop : std_logic;
signal strm_in_en : std_logic;
signal strm_in_busy : std_logic;
signal strm_type_vld : std_logic;
signal strm_tag : std_logic_vector( 3 downto 0);
signal strm_size : unsigned(23 downto 0);
signal ddr2_wr_en : std_logic;
signal ddr2_wr_mask : std_logic_vector( 3 downto 0);
@@ -90,7 +93,7 @@ architecture strm_ddr2 of strm_ddr2 is
signal strm_out_eop : std_logic;
signal strm_out_hdr_en : std_logic;
signal ddr2_rd_en : std_logic;
signal bla_cnt : unsigned(7 downto 0);
signal read_cnt : unsigned(7 downto 0);
begin
rst <= not rst_n;
ddr2_rd_en_o <= ddr2_rd_en;
@@ -101,15 +104,17 @@ begin
ddr2_wr_data_o <= ddr2_wr_data;
strm_in_data <= strm_in_data_i;
strm_in_eop <= strm_in_eop_i;
strm_in_sop <= strm_in_sop_i;
strm_in_en <= strm_in_en_i;
strm_in_busy_o <= strm_in_busy;
strm_in_busy <= ddr2_wr_full_i or ddr2_cmd_full_i;
strm_type_vld <= '1' when strm_in_data(STRM_TYPE_HIGH downto STRM_TYPE_LOW) = STRM_TYPE_DDR2 else '0';
strm_type_vld <= strm_in_sop when strm_in_data(STRM_TYPE_HIGH downto STRM_TYPE_LOW) = STRM_TYPE_DDR2 else '0';
process (clk, rst_n)
begin
if rst_n = '0' then
sm_strm <= IDLE;
strm_tag <= (others => '0');
strm_size <= (others => '0');
ddr2_cmd_instr <= (others => '0');
ddr2_wr_en <= '0';
@@ -120,11 +125,12 @@ begin
ddr2_size <= (others => '0');
ddr2_read_size <= (others => '0');
strm_out_size <= (others => '0');
bla_cnt <= (others => '0');
read_cnt <= (others => '0');
strm_out_hdr_en <= '0';
elsif rising_edge(clk) then
-- STRM SIZE
if sm_strm = IDLE and strm_in_en = '1' then
strm_tag <= strm_in_data(STRM_TAG_HIGH downto STRM_TAG_LOW);
strm_size <= unsigned(strm_in_data(STRM_LENGTH_HIGH downto STRM_LENGTH_LOW));
end if;
@@ -226,7 +232,7 @@ begin
sm_strm <= DDR2_READ;
end if;
when DDR2_READ =>
if ddr2_rd_empty_i = '1' and ddr2_size /= x"000000" and bla_cnt = dw_cnt(6 downto 0) then
if ddr2_rd_empty_i = '1' and ddr2_size /= x"000000" and read_cnt = dw_cnt(6 downto 0) then
sm_strm <= DDR2_RD_ADJ;
elsif strm_out_eop = '1' then
sm_strm <= IDLE;
@@ -248,9 +254,9 @@ begin
end if;
if ddr2_cmd_en = '1' then
bla_cnt <= (others => '0');
read_cnt <= (others => '0');
elsif ddr2_rd_en = '1' then
bla_cnt <= bla_cnt + "1";
read_cnt <= read_cnt + "1";
end if;
-- STRM OUT REGISTERS
@@ -272,7 +278,7 @@ begin
strm_out_en_o <= strm_out_hdr_en when sm_strm = DDR2_RD_WAIT and strm_out_busy_i = '0' else ddr2_rd_en;
strm_out_eop <= ddr2_rd_en when ddr2_read_size >= strm_out_size and sm_strm = DDR2_READ else '0';
strm_out_eop_o <= strm_out_eop;
strm_out_data_o <= STRM_TYPE_DDR2 & (27 downto 24 => '0') & std_logic_vector(strm_out_size)
strm_out_data_o <= STRM_TYPE_DDR2 & strm_tag & std_logic_vector(strm_out_size)
when strm_out_hdr_en = '1' else ddr2_rd_data_i;
end strm_ddr2;