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Benjamin Krill
2013-10-02 10:43:54 +02:00
commit f3e562f835
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-- ---------------------------------------------------------------
-- (2013) Benjamin Krill <benjamin@krll.de>
-- ---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity f2p_master is
port (
clk : in std_logic;
rst_n : in std_logic;
debug : out std_logic_vector(7 downto 0);
-- cypress interface
usb_clk : in std_logic;
usb_flag_a_i : in std_logic; -- programmable flag
usb_flag_b_i : in std_logic; -- full flag
usb_flag_c_i : in std_logic; -- empty flag
usb_cs_o : out std_logic; -- put to GND, not need for this application
usb_oe_o : out std_logic; -- active_low
usb_rd_o : out std_logic; -- active_low
usb_wr_o : out std_logic; -- active_low
usb_pktend_o : out std_logic; -- active_low
usb_adr_o : out std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8
usb_dat_io : inout std_logic_vector(7 downto 0);
-- write/read pipe
wp_wr_i : in std_logic;
wp_full_o : out std_logic;
wp_eop_i : in std_logic;
wp_dat_i : in std_logic_vector(31 downto 0);
rp_rd_i : in std_logic;
rp_empty_o : out std_logic;
rp_dat_o : out std_logic_vector(31 downto 0)
);
end f2p_master;
architecture f2p_master of f2p_master is
constant EP2 : std_logic_vector(1 downto 0) := "00";
constant EP4 : std_logic_vector(1 downto 0) := "01";
constant EP6 : std_logic_vector(1 downto 0) := "10";
constant EP8 : std_logic_vector(1 downto 0) := "11";
signal rst : std_logic;
type sm_usb_t is (IDLE, RD_ADDRESS, RD_READ, WR_ADDRESS, WR_WRITE);
signal sm_usb : sm_usb_t;
signal usb_oe : std_logic;
signal usb_rd : std_logic;
signal usb_wr : std_logic;
signal usb_wr_cnt : unsigned(25 downto 0);
signal usb_pktend : std_logic;
signal usb_dat_out : std_logic_vector(7 downto 0);
signal usb_dat_in : std_logic_vector(7 downto 0);
signal usb_adr : std_logic;
signal uftx_din : std_logic_vector(31 downto 0);
signal uftx_wren : std_logic;
signal uftx_rden : std_logic;
signal uftx_dout : std_logic_vector( 7 downto 0);
signal uftx_full : std_logic;
signal uftx_empty : std_logic;
signal ufrx_din : std_logic_vector( 7 downto 0);
signal ufrx_wren : std_logic;
signal ufrx_rden : std_logic;
signal ufrx_dout : std_logic_vector(31 downto 0);
signal ufrx_full : std_logic;
signal ufrx_empty : std_logic;
signal uftxfin_cnt : unsigned(23 downto 0);
signal uftxfin_din : std_logic_vector(23 downto 0);
signal uftxfin_wren : std_logic;
signal uftxfin_rden : std_logic;
signal uftxfin_dout : std_logic_vector(23 downto 0);
signal uftxfin_full : std_logic;
signal uftxfin_empty : std_logic;
begin
rst <= not rst_n;
-- EP2 from host, EP6 to host
-- during IDLE monitor EF and read data from fifo
usb_adr_o <= EP2 when (usb_adr = '0' or sm_usb = RD_ADDRESS) and sm_usb /= WR_ADDRESS else EP6;
usb_cs_o <= '0';
usb_oe_o <= not usb_oe;
usb_rd_o <= not usb_rd;
usb_wr_o <= not usb_wr;
usb_pktend_o <= not usb_pktend;
usb_dat_io <= (others => 'Z') when usb_oe = '1' else usb_dat_out;
usb_dat_in <= usb_dat_io when usb_oe = '1' else (others => '0');
usb_oe <= '1' when (usb_adr = '0' or sm_usb = RD_ADDRESS) and sm_usb /= WR_ADDRESS else '0';
usb_rd <= '1' when sm_usb = RD_READ and usb_flag_c_i = '1' else '0';
usb_wr <= '1' when sm_usb = WR_WRITE and usb_flag_b_i = '1' and uftx_empty = '0' else '0';
usb_pktend <= '1' when sm_usb = WR_WRITE and uftxfin_empty = '0'
and to_integer(usb_wr_cnt(25 downto 2)) = to_integer(unsigned(uftxfin_dout)) else '0';
process (usb_clk, rst_n)
begin
if rst_n = '0' then
sm_usb <= IDLE;
usb_adr <= '0';
usb_wr_cnt <= "00" & x"000001";
elsif rising_edge(usb_clk) then
if usb_pktend = '1' then
usb_wr_cnt <= "00" & x"000001";
elsif usb_wr = '1' then
usb_wr_cnt <= usb_wr_cnt + "1";
end if;
-- EP address switch
if sm_usb = RD_ADDRESS then
usb_adr <= '0';
elsif sm_usb = WR_ADDRESS then
usb_adr <= '1';
end if;
case sm_usb is
when IDLE =>
if uftx_empty = '0' then
sm_usb <= WR_ADDRESS;
elsif ufrx_full = '0' then
sm_usb <= RD_ADDRESS;
end if;
when RD_ADDRESS =>
sm_usb <= RD_READ;
when RD_READ =>
sm_usb <= IDLE;
if usb_flag_c_i = '1' and ufrx_full = '0' then -- fifo not empty
sm_usb <= RD_READ;
end if;
when WR_ADDRESS =>
sm_usb <= WR_WRITE;
when WR_WRITE =>
if usb_pktend = '1' then
sm_usb <= IDLE;
end if;
end case;
end if;
end process;
-- --------------------------------------------------------------------
-- USB RX FIFO
-- --------------------------------------------------------------------
rp_dat_o <= ufrx_dout(7 downto 0) & ufrx_dout(15 downto 8) & ufrx_dout(23 downto 16) & ufrx_dout(31 downto 24);
rp_empty_o <= ufrx_empty;
ufrx_rden <= rp_rd_i;
ufrx_din <= usb_dat_in;
ufrx_wren <= usb_rd;
usb_fifo_rx_0: entity work.usb_fifo_rx
port map (
rst => rst,
wr_clk => usb_clk,
wr_en => ufrx_wren,
din => ufrx_din,
full => ufrx_full,
rd_clk => clk,
rd_en => ufrx_rden,
dout => ufrx_dout,
empty => ufrx_empty
);
-- --------------------------------------------------------------------
-- USB TX FIFO
-- --------------------------------------------------------------------
uftx_din <= wp_dat_i;
uftx_wren <= wp_wr_i;
wp_full_o <= uftx_full;
uftx_rden <= usb_wr;
usb_dat_out <= uftx_dout;
usb_fifo_tx_0: entity work.usb_fifo_tx
port map (
rst => rst,
wr_clk => clk,
wr_en => uftx_wren,
din => uftx_din,
full => uftx_full,
rd_clk => usb_clk,
rd_en => uftx_rden,
dout => uftx_dout,
empty => uftx_empty
);
process (clk, rst_n)
begin
if rst_n = '0' then
uftxfin_cnt <= x"000001";
elsif rising_edge(clk) then
if uftxfin_wren = '1' then
uftxfin_cnt <= x"000001";
elsif wp_wr_i = '1' then
uftxfin_cnt <= uftxfin_cnt + "1";
end if;
end if;
end process;
uftxfin_wren <= wp_wr_i and wp_eop_i and not uftxfin_full;
uftxfin_din <= std_logic_vector(uftxfin_cnt);
uftxfin_rden <= usb_pktend and not uftxfin_empty;
usb_fifo_txfin_0: entity work.usb_fifo_tx_fin
port map (
rst => rst,
wr_clk => clk,
wr_en => uftxfin_wren,
din => uftxfin_din,
full => uftxfin_full,
rd_clk => usb_clk,
rd_en => uftxfin_rden,
dout => uftxfin_dout,
empty => uftxfin_empty
);
end f2p_master;

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-- ---------------------------------------------------------------
-- (2013) Benjamin Krill <benjamin@krll.de>
-- ---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.strm_package.all;
entity f2p_strm_top is
generic ( STRM_OUT_SLV_CNT : integer := 1 );
port (
clk : in std_logic;
rst_n : in std_logic;
debug : out std_logic_vector(7 downto 0);
-- cypress interface
usb_clk : in std_logic;
usb_flag_a_i : in std_logic; -- programmable flag
usb_flag_b_i : in std_logic; -- full flag
usb_flag_c_i : in std_logic; -- empty flag
usb_cs_o : out std_logic; -- put to GND, not need for this application
usb_oe_o : out std_logic; -- active_low
usb_rd_o : out std_logic; -- active_low
usb_wr_o : out std_logic; -- active_low
usb_pktend_o : out std_logic; -- active_low
usb_adr_o : out std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8
usb_dat_io : inout std_logic_vector(7 downto 0);
-- streaming bus
strm_in_data_o : out std_logic_vector(31 downto 0);
strm_in_eop_o : out std_logic;
strm_in_en_o : out std_logic;
strm_in_busy_i : in std_logic;
strm_out_slv_reqs_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
strm_out_slv_busy_o : out std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
strm_out_data_i : in strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
strm_out_eop_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
strm_out_en_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0)
);
end f2p_strm_top;
architecture f2p_strm_top of f2p_strm_top is
signal rp_read_cnt : unsigned(23 downto 0);
signal strm_data : std_logic_vector(31 downto 0);
signal strm_eop : std_logic;
signal strm_en : std_logic;
signal wp_wr : std_logic;
signal wp_full : std_logic;
signal wp_eop : std_logic;
signal wp_dat : std_logic_vector(31 downto 0);
signal rp_rd : std_logic;
signal rp_empty : std_logic;
signal rp_dat : std_logic_vector(31 downto 0);
signal rrarb_req : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
signal rrarb_ack : std_logic;
signal rrarb_grant : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_data_mux : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
begin
strm_in_data_o <= strm_data;
strm_in_eop_o <= strm_eop;
strm_in_en_o <= strm_en;
f2p_master_0: entity work.f2p_master
port map (
clk => clk,
rst_n => rst_n,
debug => debug,
-- cypress interface
usb_clk => usb_clk,
usb_flag_a_i => usb_flag_a_i,
usb_flag_b_i => usb_flag_b_i,
usb_flag_c_i => usb_flag_c_i,
usb_cs_o => usb_cs_o,
usb_oe_o => usb_oe_o,
usb_rd_o => usb_rd_o,
usb_wr_o => usb_wr_o,
usb_pktend_o => usb_pktend_o,
usb_adr_o => usb_adr_o,
usb_dat_io => usb_dat_io,
-- write/read pipe
wp_wr_i => wp_wr,
wp_full_o => wp_full,
wp_dat_i => wp_dat,
wp_eop_i => wp_eop,
rp_rd_i => rp_rd,
rp_empty_o => rp_empty,
rp_dat_o => rp_dat
);
-- ------------------------------------------------------------------
-- USB FIFO SLAVES
-- ------------------------------------------------------------------
-- FROM USB
rp_rd <= not rp_empty and not strm_in_busy_i;
process (clk, rst_n)
begin
if rst_n = '0' then
rp_read_cnt <= (others => '0');
strm_data <= (others => '0');
strm_en <= '0';
strm_eop <= '0';
elsif rising_edge(clk) then
-- get next packet and stream to slaves
if rp_rd = '1' then
if rp_read_cnt /= x"000000" then
rp_read_cnt <= rp_read_cnt - "1";
else
rp_read_cnt <= unsigned(rp_dat(STRM_LENGTH_HIGH downto STRM_LENGTH_LOW));
end if;
end if;
-- stream data
strm_en <= '0';
strm_eop <= '0';
if rp_rd = '1' then
strm_en <= '1';
strm_data <= rp_dat;
if rp_read_cnt = x"000001" then
strm_eop <= '1';
end if;
end if;
end if;
end process;
-- TO USB - strm arbiter
rrarb_req <= strm_out_slv_reqs_i and not rrarb_grant;
rrarb_ack <= '1' when (strm_out_eop_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0';
rrarb_strm_out_0: entity work.rrarbiter
generic map ( CNT => STRM_OUT_SLV_CNT )
port map (
clk => clk,
rst_n => rst_n,
req => rrarb_req,
ack => rrarb_ack,
grant => rrarb_grant
);
strm_out_slv_busy_o <= not rrarb_grant or (STRM_OUT_SLV_CNT-1 downto 0 => wp_full);
strm_out_data_mux(0) <= strm_out_data_i(0) and (31 downto 0 => rrarb_grant(0));
dc: for I in 1 to STRM_OUT_SLV_CNT-1 generate
strm_out_data_mux(I) <= strm_out_data_mux(I-1) or (strm_out_data_i(I) and (31 downto 0 => rrarb_grant(I)));
end generate dc;
wp_dat <= strm_out_data_mux(STRM_OUT_SLV_CNT-1);
wp_wr <= '1' when (strm_out_en_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0';
wp_eop <= '1' when (strm_out_eop_i and rrarb_grant) /= (STRM_OUT_SLV_CNT-1 downto 0 => '0') else '0';
end f2p_strm_top;

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-- ---------------------------------------------------------------
-- (2013) Benjamin Krill <benjamin@krll.de>
-- ---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- GENERAL PKT FORMAT
-- --------------------------------------------------------
-- Type (4bit)
-- Plength (7bit) data length (0 = 0byte, 0x7f = 127 * 4byte)
-- 31 16|15 0
-- header |Type ________|___PLenght______|
-- data |... type defined data/fields ... |
--
-- DDR2 WRITE TYPE FORMAT
-- --------------------------------------------------------
-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- data | .... data .... |
--
-- DDR2 READ TYPE FORMAT
-- --------------------------------------------------------
-- header0 |0 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- header1 | |_______SIZE_____| -- SIZE in 4byte to read
package strm_package is
constant STRM_TYPE_HIGH : integer := 31;
constant STRM_TYPE_LOW : integer := 28;
constant STRM_LENGTH_HIGH : integer := 23;
constant STRM_LENGTH_LOW : integer := 0;
-- SLAVE TYPE IDs
constant STRM_TYPE_DDR2 : std_logic_vector(3 downto 0) := "0001";
-- DDR2
constant STRM_DDR2_BUS : integer := 0;
constant STRM_DDR2_ADR_HIGH : integer := 27;
constant STRM_DDR2_ADR_LOW : integer := 0;
constant STRM_DDR2_ACCESS : integer := 31;
constant STRM_DDR2_ACC_WRITE : std_logic := '1';
constant STRM_DDR2_ACC_READ : std_logic := '0';
constant STRM_DDR2_SIZE_HIGH : integer := 23;
constant STRM_DDR2_SIZE_LOW : integer := 0;
-- bus types
type strm_dat_bus_t is array(natural range <>) of std_logic_vector(31 downto 0);
end package;

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-- ---------------------------------------------------------------------------
-- (2009) Benjamin Krill <ben@codiert.org>
--
-- "THE BEER-WARE LICENSE" (Revision 42):
-- ben@codiert.org wrote this file. As long as you retain this notice you can
-- do whatever you want with this stuff. If we meet some day, and you think
-- this stuff is worth it, you can buy me a beer in return Benjamin Krill
-- ---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rrarbiter is
generic ( CNT : integer := 7 );
port (
clk : in std_logic;
rst_n : in std_logic;
req : in std_logic_vector(CNT-1 downto 0);
ack : in std_logic;
grant : out std_logic_vector(CNT-1 downto 0)
);
end;
architecture rrarbiter of rrarbiter is
signal grant_q : std_logic_vector(CNT-1 downto 0);
signal pre_req : std_logic_vector(CNT-1 downto 0);
signal sel_gnt : std_logic_vector(CNT-1 downto 0);
signal isol_lsb : std_logic_vector(CNT-1 downto 0);
signal mask_pre : std_logic_vector(CNT-1 downto 0);
signal win : std_logic_vector(CNT-1 downto 0);
begin
grant <= grant_q;
mask_pre <= req and not (std_logic_vector(unsigned(pre_req) - 1) or pre_req); -- Mask off previous winners
sel_gnt <= mask_pre and std_logic_vector(unsigned(not(mask_pre)) + 1); -- Select new winner
isol_lsb <= req and std_logic_vector(unsigned(not(req)) + 1); -- Isolate least significant set bit.
win <= sel_gnt when mask_pre /= (CNT-1 downto 0 => '0') else isol_lsb;
process (clk,rst_n)
begin
if rst_n = '0' then
pre_req <= (others => '0');
grant_q <= (others => '0');
elsif rising_edge(clk) then
grant_q <= grant_q;
pre_req <= pre_req;
if grant_q = (CNT-1 downto 0 => '0') or ack = '1' then
if win /= (CNT-1 downto 0 => '0') then
pre_req <= win;
end if;
grant_q <= win;
end if;
end if;
end process;
end rrarbiter;

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-- ---------------------------------------------------------------
-- (2013) Benjamin Krill <benjamin@krll.de>
-- ---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.strm_package.all;
entity strm_ddr2 is
port (
clk : in std_logic;
rst_n : in std_logic;
debug : out std_logic_vector( 7 downto 0);
-- streaming bus
strm_in_data_i : in std_logic_vector(31 downto 0);
strm_in_eop_i : in std_logic;
strm_in_en_i : in std_logic;
strm_in_busy_o : out std_logic;
strm_out_req_o : out std_logic;
strm_out_busy_i : in std_logic;
strm_out_data_o : out std_logic_vector(31 downto 0);
strm_out_eop_o : out std_logic;
strm_out_en_o : out std_logic;
-- memory interface
ddr2_cmd_en_o : out std_logic;
ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0);
ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0);
ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0);
ddr2_cmd_empty_i : in std_logic;
ddr2_cmd_full_i : in std_logic;
ddr2_wr_en_o : out std_logic;
ddr2_wr_mask_o : out std_logic_vector( 3 downto 0);
ddr2_wr_data_o : out std_logic_vector(31 downto 0);
ddr2_wr_full_i : in std_logic;
ddr2_wr_empty_i : in std_logic;
ddr2_wr_count_i : in std_logic_vector( 6 downto 0);
ddr2_wr_underrun_i : in std_logic;
ddr2_wr_error_i : in std_logic;
ddr2_rd_en_o : out std_logic;
ddr2_rd_data_i : in std_logic_vector(31 downto 0);
ddr2_rd_full_i : in std_logic;
ddr2_rd_empty_i : in std_logic;
ddr2_rd_count_i : in std_logic_vector( 6 downto 0);
ddr2_rd_overflow_i : in std_logic;
ddr2_rd_error_i : in std_logic
);
end strm_ddr2;
architecture strm_ddr2 of strm_ddr2 is
type sm_strm_t is (IDLE, DDR2_ADDRESS, RECV, DDR2_READ, DDR2_RD_SIZE, DDR2_RD_WAIT, DDR2_RD_ADJ, DDR2_RD_REQ, IGNORE);
signal sm_strm : sm_strm_t;
signal rst : std_logic;
signal strm_in_data : std_logic_vector(31 downto 0);
signal strm_in_eop : std_logic;
signal strm_in_en : std_logic;
signal strm_in_busy : std_logic;
signal strm_type_vld : std_logic;
signal strm_size : unsigned(23 downto 0);
signal ddr2_wr_en : std_logic;
signal ddr2_wr_mask : std_logic_vector( 3 downto 0);
signal ddr2_wr_data : std_logic_vector(31 downto 0);
signal dw_cnt : unsigned( 7 downto 0);
signal dw_cnt_dec : unsigned( 7 downto 0);
signal ddr2_adr : unsigned(27 downto 0);
signal ddr2_size : unsigned(23 downto 0);
signal ddr2_read_size : unsigned(23 downto 0);
signal ddr2_cmd_en : std_logic;
signal ddr2_cmd_instr : std_logic_vector( 2 downto 0);
signal strm_out_size : unsigned(23 downto 0);
signal strm_out_eop : std_logic;
signal strm_out_hdr_en : std_logic;
signal ddr2_rd_en : std_logic;
signal bla_cnt : unsigned(7 downto 0);
begin
rst <= not rst_n;
ddr2_rd_en_o <= ddr2_rd_en;
ddr2_cmd_en_o <= ddr2_cmd_en;
ddr2_cmd_instr_o <= ddr2_cmd_instr;
ddr2_wr_en_o <= ddr2_wr_en;
ddr2_wr_mask_o <= ddr2_wr_mask;
ddr2_wr_data_o <= ddr2_wr_data;
strm_in_data <= strm_in_data_i;
strm_in_eop <= strm_in_eop_i;
strm_in_en <= strm_in_en_i;
strm_in_busy_o <= strm_in_busy;
strm_in_busy <= ddr2_wr_full_i or ddr2_cmd_full_i;
strm_type_vld <= '1' when strm_in_data(STRM_TYPE_HIGH downto STRM_TYPE_LOW) = STRM_TYPE_DDR2 else '0';
process (clk, rst_n)
begin
if rst_n = '0' then
sm_strm <= IDLE;
strm_size <= (others => '0');
ddr2_cmd_instr <= (others => '0');
ddr2_wr_en <= '0';
ddr2_wr_mask <= (others => '0');
ddr2_wr_data <= (others => '0');
dw_cnt <= (others => '0');
ddr2_adr <= (others => '0');
ddr2_size <= (others => '0');
ddr2_read_size <= (others => '0');
strm_out_size <= (others => '0');
bla_cnt <= (others => '0');
strm_out_hdr_en <= '0';
elsif rising_edge(clk) then
-- STRM SIZE
if sm_strm = IDLE and strm_in_en = '1' then
strm_size <= unsigned(strm_in_data(STRM_LENGTH_HIGH downto STRM_LENGTH_LOW));
end if;
-- SAVE DDR2 ADDRESS
if sm_strm = DDR2_ADDRESS and strm_in_en = '1' then
ddr2_adr <= unsigned(strm_in_data(STRM_DDR2_ADR_HIGH downto STRM_DDR2_ADR_LOW));
elsif ddr2_cmd_en = '1' then
ddr2_adr <= ddr2_adr + x"040";
end if;
-- SAVE DDR2 READ SIZE
if sm_strm = DDR2_RD_SIZE and strm_in_en = '1' then
ddr2_size <= unsigned(strm_in_data(STRM_DDR2_SIZE_HIGH downto STRM_DDR2_SIZE_LOW));
strm_out_size <= unsigned(strm_in_data(STRM_DDR2_SIZE_HIGH downto STRM_DDR2_SIZE_LOW));
elsif sm_strm = DDR2_RD_REQ and ddr2_cmd_full_i = '0' then
if ddr2_size > x"000040" then
ddr2_size <= ddr2_size - x"40";
else
ddr2_size <= (others => '0');
end if;
end if;
-- DDR2 DW COUNT
if sm_strm = RECV or sm_strm = IDLE then
if strm_in_en = '1' and ddr2_cmd_en = '1' then
dw_cnt <= x"01";
elsif ddr2_cmd_en = '1' then
dw_cnt <= (others => '0');
elsif strm_in_en = '1' then
dw_cnt <= dw_cnt + "1";
end if;
elsif sm_strm = DDR2_RD_ADJ and ddr2_cmd_full_i = '0' then
if ddr2_size > x"000040" then
dw_cnt <= x"40";
else
dw_cnt <= ddr2_size(7 downto 0);
end if;
elsif strm_out_eop = '1' then
dw_cnt <= (others => '0');
end if;
-- DDR2 instruction
if sm_strm = DDR2_ADDRESS and strm_in_en = '1' then
if strm_in_data(STRM_DDR2_ACCESS) = STRM_DDR2_ACC_WRITE then
ddr2_cmd_instr <= "000";
else
ddr2_cmd_instr <= "001";
end if;
end if;
if sm_strm = IDLE then
strm_out_hdr_en <= '1';
elsif sm_strm = DDR2_RD_WAIT and strm_out_busy_i = '0' then
strm_out_hdr_en <= '0';
end if;
-- RECV STATES
case sm_strm is
when IDLE =>
if strm_in_en = '1' then
if strm_type_vld = '1' then
sm_strm <= DDR2_ADDRESS;
else
sm_strm <= IGNORE;
end if;
end if;
when DDR2_ADDRESS =>
if strm_in_en = '1' then
if strm_in_data(STRM_DDR2_ACCESS) = STRM_DDR2_ACC_WRITE then
sm_strm <= RECV;
else
sm_strm <= DDR2_RD_SIZE;
end if;
end if;
-- DDR WRITE
when RECV =>
if strm_in_eop = '1' and strm_in_en = '1' then
sm_strm <= IDLE;
end if;
-- DDR READ
when DDR2_RD_SIZE =>
if strm_in_en = '1' then
if strm_in_eop = '1' then
sm_strm <= DDR2_RD_ADJ;
else
sm_strm <= IGNORE;
end if;
end if;
when DDR2_RD_ADJ =>
if ddr2_cmd_full_i = '0' then
sm_strm <= DDR2_RD_REQ;
end if;
when DDR2_RD_REQ =>
sm_strm <= DDR2_RD_WAIT;
when DDR2_RD_WAIT =>
if ddr2_rd_empty_i = '0' and strm_out_busy_i = '0' then
sm_strm <= DDR2_READ;
end if;
when DDR2_READ =>
if ddr2_rd_empty_i = '1' and ddr2_size /= x"000000" and bla_cnt = dw_cnt(6 downto 0) then
sm_strm <= DDR2_RD_ADJ;
elsif strm_out_eop = '1' then
sm_strm <= IDLE;
end if;
-- COMMON IGNORE
when IGNORE =>
if strm_in_eop = '1' and strm_in_en = '1' then
sm_strm <= IDLE;
end if;
end case;
-- DDR REGISTERS
ddr2_wr_en <= '0';
if strm_in_en = '1' and sm_strm = RECV then
ddr2_wr_en <= '1';
ddr2_wr_mask <= (others => '0');
ddr2_wr_data <= strm_in_data;
end if;
if ddr2_cmd_en = '1' then
bla_cnt <= (others => '0');
elsif ddr2_rd_en = '1' then
bla_cnt <= bla_cnt + "1";
end if;
-- STRM OUT REGISTERS
if sm_strm = DDR2_RD_SIZE then
ddr2_read_size <= x"000001";
elsif ddr2_rd_en = '1' then
ddr2_read_size <= ddr2_read_size + "1";
end if;
end if;
end process;
ddr2_cmd_en <= '1' when (sm_strm = RECV and dw_cnt = x"40") or ((sm_strm = DDR2_RD_REQ or sm_strm = IDLE) and dw_cnt /= x"00") else '0';
dw_cnt_dec <= dw_cnt - "1";
ddr2_cmd_bl_o <= std_logic_vector(dw_cnt_dec(5 downto 0));
ddr2_cmd_byte_addr_o <= std_logic_vector(ddr2_adr) & "00";
ddr2_rd_en <= not ddr2_rd_empty_i when sm_strm = DDR2_READ else '0';
strm_out_req_o <= not ddr2_rd_empty_i and strm_out_busy_i when sm_strm = DDR2_RD_WAIT else '0';
strm_out_en_o <= strm_out_hdr_en when sm_strm = DDR2_RD_WAIT and strm_out_busy_i = '0' else ddr2_rd_en;
strm_out_eop <= ddr2_rd_en when ddr2_read_size >= strm_out_size and sm_strm = DDR2_READ else '0';
strm_out_eop_o <= strm_out_eop;
strm_out_data_o <= STRM_TYPE_DDR2 & (27 downto 24 => '0') & std_logic_vector(strm_out_size)
when strm_out_hdr_en = '1' else ddr2_rd_data_i;
end strm_ddr2;

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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file usb_fifo_rx.vhd when simulating
-- the core, usb_fifo_rx. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY usb_fifo_rx IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END usb_fifo_rx;
ARCHITECTURE usb_fifo_rx_a OF usb_fifo_rx IS
-- synthesis translate_off
COMPONENT wrapped_usb_fifo_rx
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_usb_fifo_rx USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 12,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 0,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "4kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 4095,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 4094,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 12,
c_wr_depth => 4096,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 12,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_usb_fifo_rx
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END usb_fifo_rx_a;

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##############################################################
#
# Xilinx Core Generator version 14.6
# Date: Thu Sep 5 11:31:02 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=usb_fifo_rx
CSET data_count=false
CSET data_count_width=12
CSET disable_timing_violations=true
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=4095
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=4094
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=8
CSET input_depth=4096
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=32
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=12
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: cfe320cf

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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file usb_fifo_tx.vhd when simulating
-- the core, usb_fifo_tx. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY usb_fifo_tx IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END usb_fifo_tx;
ARCHITECTURE usb_fifo_tx_a OF usb_fifo_tx IS
-- synthesis translate_off
COMPONENT wrapped_usb_fifo_tx
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_usb_fifo_tx USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1021,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1020,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 12,
c_rd_depth => 4096,
c_rd_freq => 1,
c_rd_pntr_width => 12,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_usb_fifo_tx
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END usb_fifo_tx_a;

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##############################################################
#
# Xilinx Core Generator version 14.6
# Date: Wed Sep 4 11:25:04 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=usb_fifo_tx
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1021
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=1020
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=32
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=8
CSET output_depth=4096
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=12
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: e2514423

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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file usb_fifo_tx_fin.vhd when simulating
-- the core, usb_fifo_tx_fin. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY usb_fifo_tx_fin IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END usb_fifo_tx_fin;
ARCHITECTURE usb_fifo_tx_fin_a OF usb_fifo_tx_fin IS
-- synthesis translate_off
COMPONENT wrapped_usb_fifo_tx_fin
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_usb_fifo_tx_fin USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 24,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 24,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_usb_fifo_tx_fin
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END usb_fifo_tx_fin_a;

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##############################################################
#
# Xilinx Core Generator version 14.6
# Date: Wed Sep 25 12:38:10 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=usb_fifo_tx_fin
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1023
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=1022
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=24
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=24
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 7bd756aa