hdet/fpga/src/vendor/xilinx/atlys_ddr2/coregen.cgp

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2014-02-17 13:33:46 +01:00
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true