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hdet/fpga/src/vendor/xilinx/atlys_ddr2
History
Benjamin Krill d94a97b112 initial HDET design 2014-02-17 13:33:46 +01:00
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ddr2 initial HDET design 2014-02-17 13:33:46 +01:00
coregen.cgp initial HDET design 2014-02-17 13:33:46 +01:00
create_ddr2.tcl initial HDET design 2014-02-17 13:33:46 +01:00
ddr2.gise initial HDET design 2014-02-17 13:33:46 +01:00
ddr2.ncf initial HDET design 2014-02-17 13:33:46 +01:00
ddr2.vho initial HDET design 2014-02-17 13:33:46 +01:00
ddr2.xco initial HDET design 2014-02-17 13:33:46 +01:00
ddr2.xise initial HDET design 2014-02-17 13:33:46 +01:00
ddr2_flist.txt initial HDET design 2014-02-17 13:33:46 +01:00
ddr2_readme.txt initial HDET design 2014-02-17 13:33:46 +01:00
ddr2_xmdf.tcl initial HDET design 2014-02-17 13:33:46 +01:00
edit_ddr2.tcl initial HDET design 2014-02-17 13:33:46 +01:00