113 lines
3.7 KiB
VHDL
113 lines
3.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.dvi_package.all;
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library UNISIM;
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use UNISIM.Vcomponents.all;
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entity dvi2ddr is
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port (
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clk : in std_logic;
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rst : in std_logic;
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ctrl_disable_wr : in std_logic;
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rx_tmds : in std_logic_vector(3 downto 0);
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rx_tmds_n : in std_logic_vector(3 downto 0);
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-- memory interface
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ddr2_cmd_en_o : out std_logic;
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ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0);
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ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0);
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ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0);
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ddr2_cmd_empty_i : in std_logic;
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ddr2_cmd_full_i : in std_logic;
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ddr2_wr_en_o : out std_logic;
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ddr2_wr_mask_o : out std_logic_vector( 3 downto 0);
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ddr2_wr_data_o : out std_logic_vector(31 downto 0);
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ddr2_wr_full_i : in std_logic;
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ddr2_wr_empty_i : in std_logic;
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ddr2_wr_count_i : in std_logic_vector( 6 downto 0);
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ddr2_wr_underrun_i : in std_logic;
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ddr2_wr_error_i : in std_logic
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);
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end dvi2ddr;
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architecture dvi2ddr of dvi2ddr is
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signal rx_tmds_s : std_logic_vector(3 downto 0);
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signal rx_color : color_t(COLOR_CNT-1 downto 0);
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signal rx_color_en : std_logic;
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signal rx_pll_lckd : std_logic;
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signal rx_rst_n : std_logic;
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signal rx_pclk : std_logic;
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signal rx_hsync : std_logic;
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signal rx_vsync : std_logic;
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begin
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-- ----------------------------------------------------------------------------
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-- HDMI to DDR2
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-- ----------------------------------------------------------------------------
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dvi_decoder_0: entity work.dvi_decoder
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port map (
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ext_rst => rst,
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tmdsclk_p => rx_tmds(3),
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tmdsclk_n => rx_tmds_n(3),
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din_p => rx_tmds(2 downto 0),
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din_n => rx_tmds_n(2 downto 0),
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reset_n => rx_rst_n, -- rx reset
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pclk_o => rx_pclk, -- regenerated pixel clock
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pclkx2_o => open, -- double rate pixel clock
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pclkx10_o => open, -- 10x pixel as IOCLK
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pll_lckd_o => rx_pll_lckd, -- send pll_lckd out so it can be fed into a different BUFPLL
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serdesstrobe_o => open, -- BUFPLL serdesstrobe output
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tmdsclk_o => open, -- TMDS cable clock
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hsync_o => rx_hsync, -- hsync data
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vsync_o => rx_vsync, -- vsync data
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valid_o => open,
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ready_o => open,
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psalgnerr_o => open,
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sdout_o => open,
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dat_en_o => rx_color_en, -- data enable
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color_o => rx_color
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);
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sig_write_0: entity work.sig_write
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generic map (MEM_START_ADR => "00" & x"0000000")
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port map (
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clk => rx_pclk,
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rst_n => rx_rst_n,
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ctrl_disable_wr => ctrl_disable_wr,
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-- memory interface
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ddr2_clk => clk,
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ddr2_cmd_en_o => ddr2_cmd_en_o,
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ddr2_cmd_instr_o => ddr2_cmd_instr_o,
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ddr2_cmd_bl_o => ddr2_cmd_bl_o,
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ddr2_cmd_byte_addr_o => ddr2_cmd_byte_addr_o,
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ddr2_cmd_empty_i => ddr2_cmd_empty_i,
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ddr2_cmd_full_i => ddr2_cmd_full_i,
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ddr2_wr_en_o => ddr2_wr_en_o,
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ddr2_wr_mask_o => ddr2_wr_mask_o,
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ddr2_wr_data_o => ddr2_wr_data_o,
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ddr2_wr_full_i => ddr2_wr_full_i,
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ddr2_wr_empty_i => ddr2_wr_empty_i,
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ddr2_wr_count_i => ddr2_wr_count_i,
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ddr2_wr_underrun_i => ddr2_wr_underrun_i,
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ddr2_wr_error_i => ddr2_wr_error_i,
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-- display output
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hsync_i => rx_hsync,
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vsync_i => rx_vsync,
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color_en_i => rx_color_en,
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color_i => rx_color
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);
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end dvi2ddr;
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