113 lines
3.2 KiB
VHDL
113 lines
3.2 KiB
VHDL
-- -----------------------------------------------------------------------------
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-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
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--
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
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-- of this software and associated documentation files (the "Software"), to deal
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-- in the Software without restriction, including without limitation the rights
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-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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-- copies of the Software, and to permit persons to whom the Software is
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-- furnished to do so, subject to the following conditions:
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--
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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-- THE SOFTWARE.
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-- -----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.dvi_package.all;
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ENTITY sig_tb IS
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END sig_tb;
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ARCHITECTURE rtl OF sig_tb IS
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constant CLK_PERIOD : time := 20 ns;
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signal clk : std_logic;
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signal rst : std_logic;
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signal rst_n : std_logic;
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signal en_stb_i : std_logic;
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signal hsync_o : std_logic;
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signal vsync_o : std_logic;
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signal color_en_o : std_logic;
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signal color_o : color_t(COLOR_CNT-1 downto 0);
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signal en_stb_iq : std_logic;
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signal hsync_oq : std_logic;
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signal vsync_oq : std_logic;
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signal color_en_oq : std_logic;
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signal color_oq : color_t(COLOR_CNT-1 downto 0);
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BEGIN
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rst <= transport '1', '0' after ( 4 * CLK_PERIOD);
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rst_n <= not rst;
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clock: process
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begin
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clk <= '1', '0' after CLK_PERIOD/2;
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wait for CLK_PERIOD;
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end process;
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reg: process begin
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wait until rising_edge(clk);
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en_stb_iq <= en_stb_i;
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hsync_o <= hsync_oq;
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vsync_o <= vsync_oq;
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color_o <= color_oq;
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color_en_o <= color_en_oq;
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end process;
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dut: entity work.sig
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generic map (
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H_ACTIVE_PIXEL => x"500",
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H_BLANKING => x"198",
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H_SYNC_WIDTH => x"070",
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H_SYNC_OFFSET => x"030",
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V_ACTIVE_LINES => x"400",
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V_BLANKING => x"02a",
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V_SYNC_WIDTH => x"01",
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V_SYNC_OFFSET => x"03"
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)
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port map (
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clk => clk,
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rst_n => rst_n,
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en_stb_i => en_stb_iq,
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hsync_o => hsync_oq,
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vsync_o => vsync_oq,
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color_en_o => color_en_oq,
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color_o => color_oq
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);
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dut2: entity work.vga
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port map (
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pixelClock => clk,
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Red => open,
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Green => open,
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Blue => open,
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hSync => open,
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vSync => open,
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blank => open
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);
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beh: process begin
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en_stb_i <= '0';
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wait for 20*CLK_PERIOD;
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en_stb_i <= '1';
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--wait for CLK_PERIOD;
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--en_stb_i <= '0';
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wait;
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end process;
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end rtl;
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configuration sig_tb_rtl_cfg of sig_tb is
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for rtl
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end for;
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end sig_tb_rtl_cfg;
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