50 lines
1.4 KiB
Plaintext
50 lines
1.4 KiB
Plaintext
##############################################################
|
|
#
|
|
# Xilinx Core Generator version 14.6
|
|
# Date: Sun Jul 28 10:10:27 2013
|
|
#
|
|
##############################################################
|
|
#
|
|
# This file contains the customisation parameters for a
|
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
|
# that you do not manually alter this file as it may cause
|
|
# unexpected and unsupported behavior.
|
|
#
|
|
##############################################################
|
|
#
|
|
# Generated from component: xilinx.com:ip:mig:3.92
|
|
#
|
|
##############################################################
|
|
#
|
|
# BEGIN Project Options
|
|
SET addpads = false
|
|
SET asysymbol = true
|
|
SET busformat = BusFormatAngleBracketNotRipped
|
|
SET createndf = false
|
|
SET designentry = VHDL
|
|
SET device = xc6slx45
|
|
SET devicefamily = spartan6
|
|
SET flowvendor = Other
|
|
SET formalverification = false
|
|
SET foundationsym = false
|
|
SET implementationfiletype = Ngc
|
|
SET package = csg324
|
|
SET removerpms = false
|
|
SET simulationfiles = Behavioral
|
|
SET speedgrade = -3
|
|
SET verilogsim = false
|
|
SET vhdlsim = true
|
|
# END Project Options
|
|
# BEGIN Select
|
|
SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92
|
|
# END Select
|
|
# BEGIN Parameters
|
|
CSET component_name=ddr2
|
|
CSET xml_input_file=./ddr2/user_design/mig.prj
|
|
# END Parameters
|
|
# BEGIN Extra information
|
|
MISC pkg_timestamp=2013-06-08T23:00:50Z
|
|
# END Extra information
|
|
GENERATE
|
|
# CRC: ede738a9
|