124 lines
8.0 KiB
XML
124 lines
8.0 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="ddr2/user_design/rtl/ddr2.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="ddr2/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="ddr2/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="ddr2/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
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</file>
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<file xil_pn:name="ddr2/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
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</file>
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<file xil_pn:name="ddr2/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
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</file>
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<file xil_pn:name="ddr2/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
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</file>
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<file xil_pn:name="ddr2/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
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</file>
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<file xil_pn:name="ddr2/user_design/par/ddr2.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ddr2|arc" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="ddr2/user_design/rtl/ddr2.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ddr2" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="ddr2" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-07-28T12:10:31" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1E4028521BF14C180A8024C9024AB5B9" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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<bindings>
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<binding xil_pn:location="/ddr2" xil_pn:name="ddr2/user_design/par/ddr2.ucf"/>
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</bindings>
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<libraries/>
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<autoManagedFiles>
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<!-- The following files are identified by `include statements in verilog -->
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<!-- source files and are automatically managed by Project Navigator. -->
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<!-- -->
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<!-- Do not hand-edit this section, as it will be overwritten when the -->
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<!-- project is analyzed based on files automatically identified as -->
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<!-- include files. -->
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</autoManagedFiles>
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</project>
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