72 lines
2.3 KiB
Plaintext
72 lines
2.3 KiB
Plaintext
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CORE Generator Options:
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Target Device : xc6slx45-csg324
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Speed Grade : -3
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HDL : vhdl
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Synthesis Tool : Foundation_ISE
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MIG Output Options:
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Component Name : ddr2
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No of Controllers : 1
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Hardware Test Bench : enabled
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/*******************************************************/
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/* Controller 3 */
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/*******************************************************/
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Controller Options :
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Memory : DDR2_SDRAM
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Interface : NATIVE
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Design Clock Frequency : 3000 ps (333.33 MHz)
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Memory Type : Components
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Memory Part : MT47H64M16XX-25E
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Equivalent Part(s) : MT47H64M16HR-25E
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Row Address : 13
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Column Address : 10
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Bank Address : 3
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Data Mask : enabled
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Memory Options :
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Burst Length : 4(010)
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CAS Latency : 5
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DQS# Enable : Enable
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DLL Enable : Enable-Normal
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OCD Operation : OCD Exit
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Output Drive Strength : Fullstrength
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Outputs : Enable
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Additive Latency (AL) : 0
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RDQS Enable : Disable
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RTT (nominal) - ODT : 50ohms
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High Temparature Self Refresh Rate : Disable
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User Interface Parameters :
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Configuration Type : Four 32-bit bi-directional ports
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Ports Selected : Port0, Port1, Port2, Port3
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Memory Address Mapping : BANK_ROW_COLUMN
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Arbitration Algorithm : Round Robin
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Arbitration :
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Time Slot0 : 0123
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Time Slot1 : 1230
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Time Slot2 : 2301
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Time Slot3 : 3012
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Time Slot4 : 0123
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Time Slot5 : 1230
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Time Slot6 : 2301
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Time Slot7 : 3012
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Time Slot8 : 0123
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Time Slot9 : 1230
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Time Slot10: 2301
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Time Slot11: 3012
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FPGA Options :
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Class for Address and Control : II
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Class for Data : II
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Memory Interface Pin Termination : CALIB_TERM
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DQ/DQS : 25 Ohms
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Bypass Calibration : enabled
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Debug Signals for Memory Controller : Disable
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Input Clock Type : Single-Ended
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