173 lines
10 KiB
Plaintext
173 lines
10 KiB
Plaintext
############################################################################
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##
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## Xilinx, Inc. 2006 www.xilinx.com
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## Sun Jul 28 12:10:23 2013
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## Generated by MIG Version 3.92
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##
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############################################################################
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## File name : example_top.ucf
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##
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## Details : Constraints file
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## FPGA family: spartan6
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## FPGA: xc6slx45-csg324
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## Speedgrade: -3
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## Design Entry: VHDL
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## Design: with Test bench
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## DCM Used: Enable
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## No.Of Memory Controllers: 1
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##
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############################################################################
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############################################################################
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# VCC AUX VOLTAGE
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############################################################################
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CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
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############################################################################
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# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
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# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
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# follows the corresponding GUI option setting. However, DDR3 can operate at higher
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# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
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# remove/edit the below constraint to avoid false errors.
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############################################################################
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CONFIG MCB_PERFORMANCE= STANDARD;
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##################################################################################
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# Timing Ignore constraints for paths crossing the clock domain
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##################################################################################
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NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
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NET "c?_pll_lock" TIG;
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INST "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
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#Please uncomment the below TIG if used in a design which enables self-refresh mode
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#NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
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NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
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############################################################################
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## Memory Controller 3
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## Memory Device: DDR2_SDRAM->MT47H64M16XX-25E
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## Frequency: 333.333 MHz
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## Time Period: 3000 ps
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## Supported Part Numbers: MT47H64M16HR-25E
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############################################################################
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############################################################################
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## Clock constraints
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############################################################################
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NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
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TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3 ns HIGH 50 %;
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############################################################################
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############################################################################
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## I/O TERMINATION
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############################################################################
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NET "mcb3_dram_dq[*]" IN_TERM = NONE;
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NET "mcb3_dram_dqs" IN_TERM = NONE;
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NET "mcb3_dram_dqs_n" IN_TERM = NONE;
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NET "mcb3_dram_udqs" IN_TERM = NONE;
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NET "mcb3_dram_udqs_n" IN_TERM = NONE;
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############################################################################
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# Status Signals
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############################################################################
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NET "error" IOSTANDARD = LVCMOS18 ;
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NET "calib_done" IOSTANDARD = LVCMOS18 ;
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NET "calib_done" LOC = "B2" ;
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NET "error" LOC = "A2" ;
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############################################################################
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# I/O STANDARDS
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############################################################################
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NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II ;
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NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II ;
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NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II ;
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NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II ;
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NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II ;
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NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II ;
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NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II ;
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NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II ;
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NET "mcb3_rzq" IOSTANDARD = SSTL18_II ;
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NET "mcb3_zio" IOSTANDARD = SSTL18_II ;
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NET "c3_sys_clk" IOSTANDARD = LVCMOS25 ;
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NET "c3_sys_rst_i" IOSTANDARD = LVCMOS18 ;
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############################################################################
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# MCB 3
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# Pin Location Constraints for Clock, Masks, Address, and Controls
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############################################################################
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NET "mcb3_dram_a[0]" LOC = "J7" ;
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NET "mcb3_dram_a[10]" LOC = "F4" ;
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NET "mcb3_dram_a[11]" LOC = "D3" ;
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NET "mcb3_dram_a[12]" LOC = "G6" ;
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NET "mcb3_dram_a[1]" LOC = "J6" ;
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NET "mcb3_dram_a[2]" LOC = "H5" ;
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NET "mcb3_dram_a[3]" LOC = "L7" ;
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NET "mcb3_dram_a[4]" LOC = "F3" ;
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NET "mcb3_dram_a[5]" LOC = "H4" ;
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NET "mcb3_dram_a[6]" LOC = "H3" ;
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NET "mcb3_dram_a[7]" LOC = "H6" ;
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NET "mcb3_dram_a[8]" LOC = "D2" ;
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NET "mcb3_dram_a[9]" LOC = "D1" ;
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NET "mcb3_dram_ba[0]" LOC = "F2" ;
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NET "mcb3_dram_ba[1]" LOC = "F1" ;
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NET "mcb3_dram_ba[2]" LOC = "E1" ;
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NET "mcb3_dram_cas_n" LOC = "K5" ;
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NET "mcb3_dram_ck" LOC = "G3" ;
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NET "mcb3_dram_ck_n" LOC = "G1" ;
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NET "mcb3_dram_cke" LOC = "H7" ;
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NET "mcb3_dram_dm" LOC = "K3" ;
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NET "mcb3_dram_dq[0]" LOC = "L2" ;
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NET "mcb3_dram_dq[10]" LOC = "N2" ;
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NET "mcb3_dram_dq[11]" LOC = "N1" ;
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NET "mcb3_dram_dq[12]" LOC = "T2" ;
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NET "mcb3_dram_dq[13]" LOC = "T1" ;
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NET "mcb3_dram_dq[14]" LOC = "U2" ;
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NET "mcb3_dram_dq[15]" LOC = "U1" ;
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NET "mcb3_dram_dq[1]" LOC = "L1" ;
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NET "mcb3_dram_dq[2]" LOC = "K2" ;
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NET "mcb3_dram_dq[3]" LOC = "K1" ;
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NET "mcb3_dram_dq[4]" LOC = "H2" ;
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NET "mcb3_dram_dq[5]" LOC = "H1" ;
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NET "mcb3_dram_dq[6]" LOC = "J3" ;
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NET "mcb3_dram_dq[7]" LOC = "J1" ;
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NET "mcb3_dram_dq[8]" LOC = "M3" ;
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NET "mcb3_dram_dq[9]" LOC = "M1" ;
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NET "mcb3_dram_dqs" LOC = "L4" ;
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NET "mcb3_dram_dqs_n" LOC = "L3" ;
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NET "mcb3_dram_odt" LOC = "K6" ;
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NET "mcb3_dram_ras_n" LOC = "L5" ;
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NET "c3_sys_clk" LOC = "R10" ;
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NET "c3_sys_rst_i" LOC = "M8" ;
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NET "mcb3_dram_udm" LOC = "K4" ;
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NET "mcb3_dram_udqs" LOC = "P2" ;
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NET "mcb3_dram_udqs_n" LOC = "P1" ;
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NET "mcb3_dram_we_n" LOC = "E3" ;
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##################################################################################
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#RZQ is required for all MCB designs. Do not move the location #
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#of this pin for ES devices.For production devices, RZQ can be moved to any #
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#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
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#a 2R resistor should be connected between RZQand ground, where R is the desired#
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#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
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##################################################################################
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NET "mcb3_rzq" LOC = "N4" ;
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##################################################################################
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#ZIO is only required for MCB designs using Calibrated Input Termination.#
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#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
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#MCB bank but must be left as a no-connect (NC) pin.#
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##################################################################################
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NET "mcb3_zio" LOC = "P4" ;
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