52 lines
1.5 KiB
Plaintext
52 lines
1.5 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 11.2
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# Date: Fri Jun 12 05:42:56 2009
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = False
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SET asysymbol = False
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = vhdl
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SET device = xc6slx45
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SET devicefamily = spartan6
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SET flowvendor = Foundation_ISE
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = csg324
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SET removerpms = False
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SET simulationfiles = Structural
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SET speedgrade = -3
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SET verilogsim = False
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SET vhdlsim = False
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# END Project Options
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# BEGIN Select
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SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
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# END Select
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# BEGIN Parameters
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CSET asynchronous_input_port_width=8
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CSET asynchronous_output_port_width=7
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CSET component_name=vio
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CSET enable_asynchronous_input_port=false
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CSET enable_asynchronous_output_port=true
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CSET enable_synchronous_input_port=false
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CSET enable_synchronous_output_port=false
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CSET invert_clock_input=false
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CSET synchronous_input_port_width=8
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CSET synchronous_output_port_width=8
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# END Parameters
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GENERATE
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# CRC: 66fe39ed
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